Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application discloses a preparation method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a semiconductor substrate; the semiconductor substrate comprises a first region and a second region; forming a power device structure in the first region and forming a BCD device structure in the second region; a buried layer is formed under the power device structure; a deep trench is formed in the semiconductor substrate; the bottom of the deep trench is located in the buried layer; and a conductive material is filled in the deep trench to lead out a drain of the power device structure to the surface of the semiconductor substrate. The scheme provided by the application can lead out the drain of the power device from the surface of the semiconductor substrate, so that the specific on-resistance of the power device is reduced.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In the process of integrating power devices such as SGT (Shielded Gate Transistor), trench MOS (Trench Metal-Oxide-Semiconductor Field-Effect Transistor), SJ (Super Junction MOSFET), and IGBT (Insulated Gate Bipolar Transistor) with BCD devices, the drain current path of the power device is relatively long, resulting in a large Rsp (Specific On-Resistance) of the power device. Summary of the Invention

[0003] This application provides a method for fabricating a semiconductor structure and the semiconductor structure itself, which enables the drain of a power device to be led out from the surface of a semiconductor substrate, thereby reducing the specific on-resistance of the power device. The specific solution is as follows: In a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, the method comprising: A semiconductor substrate is provided; the semiconductor substrate includes a first region; A power device structure is formed in the first region; a buried layer is formed beneath the power device structure; A conductive structure is formed in the semiconductor substrate, extending from one side of the device layer to the buried layer; the conductive structure is used to lead the drain of the power device structure to the surface of the semiconductor substrate.

[0004] Optionally, forming a conductive structure in the semiconductor substrate that extends from one side of the device layer to the buried layer includes: A deep trench is formed in the semiconductor substrate, extending from one side of the device layer to the buried layer; The deep trench is filled with conductive material to form a conductive structure.

[0005] Optionally, forming a deep trench in the semiconductor substrate that extends from one side of the device layer to the buried layer includes: An interlayer dielectric layer is formed on the surface of the semiconductor substrate; A deep trench is formed in the semiconductor substrate by photolithography, penetrating the interlayer dielectric layer and with its bottom located in the buried layer.

[0006] Optionally, prior to forming a deep trench in the semiconductor substrate through the interlayer dielectric layer and with its bottom located in the buried layer using a photolithography process, the method further includes: A first contact hole is formed above the power device structure, penetrating the interlayer dielectric layer.

[0007] Optionally, the semiconductor substrate further includes a second region in which a BCD device structure is formed; the method further includes: While forming a first contact hole penetrating the interlayer dielectric layer above the power device structure, a second contact hole penetrating the interlayer dielectric layer is formed above the BCD device structure.

[0008] Optionally, forming an interlayer dielectric layer on the surface of the semiconductor substrate includes: A nitride layer is formed on the surface of the semiconductor substrate, and an interlayer dielectric layer is formed on the surface of the nitride layer; A first contact hole penetrating the interlayer dielectric layer is formed above the power device structure, and a second contact hole penetrating the interlayer dielectric layer is formed above the BCD device structure, including: Using the nitride layer as a stop layer, a contact hole etching process is performed on the semiconductor substrate to form a first contact hole penetrating the interlayer dielectric layer above the power device structure, and a second contact hole penetrating the interlayer dielectric layer above the BCD device structure.

[0009] Optionally, after forming a deep trench penetrating the interlayer dielectric layer in the semiconductor substrate using a photolithography process, the method further includes: The first contact hole and the second contact hole are etched again so that the first contact hole penetrates the nitride layer and its bottom is located in the conductive region of the power device structure, and the second contact hole penetrates the nitride layer and its bottom is located in the conductive region of the BCD device structure.

[0010] Optionally, filling the deep trench with a conductive material includes: Conductive material is filled into the deep trench, the first contact hole, and the second contact hole.

[0011] Optionally, if no first contact hole is formed above the power device structure, after filling the deep trench with conductive material, the method further includes: A first contact hole is formed above the power device structure, penetrating the interlayer dielectric layer.

[0012] Optionally, before forming a first contact hole penetrating the interlayer dielectric layer above the power device structure, the method further includes: A first oxide layer is formed on the surface of the interlayer dielectric layer and on the surface of the conductive material filling the deep trench.

[0013] Optionally, the semiconductor substrate further includes a second region in which a BCD device structure is formed; the formation of a first contact hole penetrating the interlayer dielectric layer above the power device structure includes: A first contact hole penetrating the first oxide layer and the interlayer dielectric layer is formed above the power device structure, and a second contact hole penetrating the first oxide layer and the interlayer dielectric layer is formed above the BCD device structure.

[0014] Optionally, forming a first contact hole penetrating the interlayer dielectric layer above the power device structure includes: A first contact hole is formed above the power device structure, penetrating the first oxide layer and the interlayer dielectric layer, and a third contact hole is formed above the deep trench, penetrating the first oxide layer; the bottom of the third contact hole is located in the conductive material filled in the deep trench.

[0015] Secondly, embodiments of this application provide a semiconductor structure, the structure including a power device structure and a conductive structure that connects from one side of the device layer to a buried layer located below the power device structure; The conductive structure is used to lead the drain of the power device structure to the surface of the semiconductor substrate.

[0016] Compared with the prior art, this application has the following advantages: The method for fabricating a semiconductor structure provided in this application includes the following steps: providing a semiconductor substrate; the semiconductor substrate includes a first region; forming a power device structure in the first region; forming a buried layer below the power device structure; forming a conductive structure in the semiconductor substrate that connects from one side of the device layer to the buried layer; the conductive structure is used to lead the drain of the power device structure to the surface of the semiconductor substrate.

[0017] As can be seen, the semiconductor structure fabrication method provided in this application can form a buried layer beneath the power device structure during the fabrication of any power device such as SGT (Shielded Gate Transistor), trench MOS (Trench Metal-Oxide-Semiconductor Field-Effect Transistor), SJ (Super Junction MOSFET), and IGBT (Insulated Gate Bipolar Transistor). This buried layer allows for the effective drain current to flow into the power device structure. Thus, after forming a conductive structure connecting the device layer to the buried layer, the drain current of the power device structure can flow from the buried layer to the conductive structure, thereby leading the drain current to the surface of the semiconductor substrate through the conductive structure. Compared to the prior art where the drain current is led out using a back-substrate drain, requiring the drain current to pass through a high-resistivity substrate, the drain current of the power device in this embodiment does not need to pass through the high-resistivity substrate, effectively reducing the specific on-resistance of the power device. Attached Figure Description

[0018] Figure 1 This is a flowchart of a method for preparing a semiconductor structure provided in an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of an example of a power device structure formed in the semiconductor structure fabrication method provided in the embodiments of this application.

[0020] Figure 3 This is a schematic diagram of the formation of a power device structure in the first region in the semiconductor structure fabrication method provided in the embodiments of this application.

[0021] Figure 4 This is a schematic diagram of the formation of a BCD device structure in the second region in the semiconductor structure fabrication method provided in the embodiments of this application.

[0022] Figure 5 This is a schematic diagram of an example of forming a deep trench in a semiconductor substrate in the semiconductor structure fabrication method provided in this application embodiment.

[0023] Figure 6 This is a schematic diagram of filling a deep trench with conductive material in the semiconductor structure fabrication method provided in the embodiments of this application.

[0024] Figure 7This is a schematic diagram of an example of forming a contact hole in the semiconductor structure fabrication method provided in this application embodiment.

[0025] Figure 8 This is a schematic diagram illustrating an example of filling a contact hole with conductive material in a semiconductor structure fabrication method provided in this application.

[0026] Figure 9 This is a schematic diagram of an example of forming a metal interconnect layer in the semiconductor structure fabrication method provided in this application embodiment.

[0027] Figure 10 This is a schematic diagram of the formation of the first oxide layer in the semiconductor structure fabrication method provided in the embodiments of this application.

[0028] Figure 11 This is another schematic diagram illustrating the formation of contact holes in the semiconductor structure fabrication method provided in this application embodiment.

[0029] Figure 12 This is another schematic diagram illustrating the filling of conductive material into the contact hole in the semiconductor structure fabrication method provided in this application embodiment.

[0030] Figure 13 This is a schematic diagram of the formation of a nitride layer in the semiconductor structure fabrication method provided in the embodiments of this application.

[0031] Figure 14 This is a schematic diagram of the formation of an interlayer dielectric layer in the semiconductor structure fabrication method provided in the embodiments of this application.

[0032] Figure 15 This is another schematic diagram illustrating the formation of contact holes in the semiconductor structure fabrication method provided in this application embodiment.

[0033] Figure 16 This is another schematic diagram illustrating the formation of deep trenches in a semiconductor substrate in the semiconductor structure fabrication method provided in this application embodiment.

[0034] Figure 17 This is a schematic diagram of the removal of photoresist in the semiconductor structure fabrication method provided in the embodiments of this application.

[0035] Figure 18 This is a schematic diagram of the re-etching of contact holes in the semiconductor structure fabrication method provided in the embodiments of this application.

[0036] Figure 19 This is a schematic diagram of filling conductive material in deep trenches and contact holes in the semiconductor structure fabrication method provided in the embodiments of this application.

[0037] Figure 20This is another schematic diagram illustrating the formation of a metal interconnect layer in the semiconductor structure fabrication method provided in this application.

[0038] Figure 21 This is a schematic diagram of the formation of a first contact hole, a second contact hole, and a third contact hole in the semiconductor structure fabrication method provided in the embodiments of this application.

[0039] Figure 22 This is another schematic diagram illustrating the filling of conductive material into the contact hole in the semiconductor structure fabrication method provided in this application embodiment.

[0040] Figure 23 This is another schematic diagram illustrating the formation of a metal interconnect layer in the semiconductor structure fabrication method provided in this application.

[0041] Figure 24 This is a schematic diagram of the integration of a trench-type metal-oxide-semiconductor field-effect transistor and a BCD device in the semiconductor structure fabrication method provided in the embodiments of this application.

[0042] Figure 25 This is a schematic diagram of the conductive structure formed multiple times in the semiconductor structure fabrication method provided in the embodiments of this application. Detailed Implementation

[0043] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0044] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0045] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0046] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0047] Based on the reasons mentioned in the background art, the first embodiment of this application provides a method for fabricating a semiconductor structure, which can lead the drain of a power device out from the surface of a semiconductor substrate, thereby reducing the specific on-resistance of the power device.

[0048] like Figure 1 The diagram shows a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application, including the following steps S101 to S103: Step S101: Provide a semiconductor substrate; the semiconductor substrate includes a first region; The semiconductor substrate refers to the basic material used to construct semiconductor devices. The semiconductor substrate can be any of the following: pure single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0049] The semiconductor substrate includes a first region, which is the region where a power device structure is to be formed. The power device structure may include, but is not limited to, any one of SGT (Shielded Gate Transistor), trench MOS (Trench Metal-Oxide-Semiconductor Field-Effect Transistor), SJ (Super Junction MOSFET), and IGBT (Insulated Gate Bipolar Transistor).

[0050] Step S102: A power device structure is formed in the first region; a buried layer is formed below the power device structure.

[0051] In one optional embodiment, the semiconductor substrate can be a P-type semiconductor substrate (such as the commonly used SGT, which is NMOS, in which case the semiconductor substrate can be a P-type semiconductor substrate). The P-type semiconductor substrate is formed by doping single-crystal silicon with trivalent elements (such as boron, aluminum, or gallium). In the P-type semiconductor substrate, the silicon lattice lacks free electrons, and the conductive charge carriers are mainly holes, exhibiting P-type conductivity characteristics.

[0052] When the semiconductor substrate is a P-type semiconductor substrate, the buried layer is an N-type buried layer (NBL), which is located between the deep N-well (DNW) and the P-type semiconductor substrate.

[0053] If no N-type buried layer is formed below the power device structure, the DNW directly contacts the P-type semiconductor substrate. The DNW carries a high positive voltage, while the potential of the P-type semiconductor substrate below is close to 0V. This PN junction is reverse biased, and the depletion layer blocks the longitudinal flow of electrons, preventing the formation of an effective drain current and causing the device to fail to conduct. In this embodiment, both the DNW and NBL are N-type silicon, without a PN junction, and there is no reverse blocking effect. Furthermore, the DNW is a lightly doped drift region. The low doping allows the depletion layer to fully expand during turn-off, uniformly dispersing the high-voltage electric field, thereby increasing the breakdown voltage (BV) of the power device structure. The NBL is heavily doped as the drain terminal (similar to the source and drain ion doping of a planar MOS), reducing contact resistance. Electrons can flow freely vertically downward from the DNW into the NBL, forming an effective drain current.

[0054] In another optional embodiment, the semiconductor substrate can be an N-type semiconductor substrate (e.g., if the SGT is a PMOS, then the semiconductor substrate can be an N-type semiconductor substrate). An N-type semiconductor substrate is formed by doping single-crystal silicon with pentavalent elements (such as phosphorus, arsenic, or antimony). In an N-type semiconductor substrate, the silicon lattice has a large number of surplus free electrons, and the conductive carriers are mainly free electrons, exhibiting N-type conductivity characteristics. When the semiconductor substrate is an N-type semiconductor substrate, the buried layer is a P-type buried layer (PBL).

[0055] For ease of explanation, the following description will use a P-type semiconductor substrate and an N-type buried layer as an example, and this application does not make any specific limitations in this regard.

[0056] Step S103: A conductive structure is formed in the semiconductor substrate that extends from one side of the device layer to the buried layer; the conductive structure is used to lead the drain of the power device structure to the surface of the semiconductor substrate.

[0057] This step forms a conductive structure for leading the drain of the power device structure to the surface of the semiconductor substrate. This conductive structure is the drain current path of the power device structure. Here, "one side of the device layer" refers to the side of the semiconductor substrate used to form the functional area of ​​the device, which can be understood as the front side of the semiconductor substrate (i.e., one side of the surface of the semiconductor substrate, not the back side of the semiconductor substrate).

[0058] In the embodiments of this application, the conductive structure can be a one-piece structure or a structure formed by multiple process steps, and this application does not impose any restrictions on it.

[0059] In one alternative embodiment, forming a conductive structure in the semiconductor substrate that connects from one side of the device layer to the buried layer can be achieved through the following steps: A deep trench is formed in the semiconductor substrate, extending from one side of the device layer to the buried layer; The deep trench is filled with conductive material to form a conductive structure.

[0060] In this embodiment, an etching process can be performed on the semiconductor substrate to form a deep trench with its bottom located in the buried layer. This deep trench will subsequently serve as a current path corresponding to the drain of the power device structure, forming a path in the semiconductor substrate to lead the drain of the power device structure to the surface of the semiconductor substrate.

[0061] In some optional examples, the width (Critical Dimension, CD) of the deep trench can be within the range of 0.5um to 1.5um, for example, it can be any value such as 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1.0um, 1.1um, 1.2um, 1.3um, 1.4um, or 1.5um. The depth of the deep trench can be specifically set based on the actual device requirements, and this application does not limit it.

[0062] Then, conductive material can be filled into the deep trench to bring the drain of the power device structure to the surface of the semiconductor substrate.

[0063] The conductive material may include any one of the following: a metallic material, polycrystalline silicon, etc. The metallic material may include, for example, any one of the following: tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), etc.

[0064] like Figure 2 The diagram shown is a schematic representation of an example of a power device structure formed in the semiconductor structure fabrication method provided in this application embodiment. The semiconductor substrate may include a substrate layer 101 and an epitaxial layer 102. The substrate layer 101 may be a P-type substrate layer (P-Sub), and the epitaxial layer 102 may be a P-type epitaxial layer (P-EPI). The semiconductor substrate includes a first region 10. Subsequently, high-energy N-type ion implantation can be performed on the epitaxial layer portion corresponding to the first region 10 in the epitaxial layer 102 to form a DNW (Deep N Well) 105. Then, power device structures 201-203 and an N-type buried layer 103 can be formed in the deep N well 105 formed in the first region 10. For ease of explanation, this application embodiment uses a shielded gate trench power transistor (SGT) as an example of a power device. Then, a deep trench 123 connecting from one side of the device layer to the buried layer 103 can be formed, and conductive material can be filled in the deep trench 123 to form a conductive structure. This conductive structure enables the drain of power device structures 201-203 to be led out to the substrate surface.

[0065] In existing technologies, power device structures such as SGT (Shielded Gate Transistor), Trenchmos (Trench Metal-Oxide-Semiconductor Field-Effect Transistor), SJ (Super Junction MOSFET), and IGBT (Insulated Gate Bipolar Transistor) often use a back-side substrate drain to draw out the drain current. In this way, the drain current needs to pass through the high-resistivity substrate at the bottom to be drawn out, resulting in a large on-resistance Rsp of the power device. In contrast, in this embodiment, since a conductive structure (such as a deep trench with the bottom located in the buried layer and filled with conductive material) is formed from one side of the device layer to the buried layer, the drain current of the power device structure can flow from the buried layer to the conductive structure, thereby leading the drain current of the power device structure to the surface of the semiconductor substrate through the conductive structure. It can be seen that in the semiconductor structure formed in this embodiment, the drain current of the power device does not need to pass through the high-resistivity substrate at the bottom, which can effectively reduce the specific on-resistance of the power device.

[0066] Optional, such as Figure 2As shown, forming a deep trench in the semiconductor substrate that extends from one side of the device layer to the buried layer may include the following steps: forming an interlayer dielectric layer 105 on the surface of the semiconductor substrate (a semiconductor substrate having a deep N-well 105); and forming a deep trench 123 in the semiconductor substrate through the interlayer dielectric layer 105 and with its bottom located in the buried layer 102 by photolithography.

[0067] In some examples, a first contact hole (such as a first contact hole 125 and another first contact hole 126) through the interlayer dielectric layer 105 may be formed above the power device structure before the deep trench 123 is formed, or the first contact hole through the interlayer dielectric layer 105 may be formed above the power device structure after the deep trench 123 is formed.

[0068] In one specific implementation, after forming the deep trench 123, if a first contact hole penetrating the interlayer dielectric layer 105 is formed above the power device structure, a nitride layer can be formed on the surface of the semiconductor substrate, and an interlayer dielectric layer can be formed on the surface of the nitride layer. Thus, the nitride layer can be used as a stop layer to perform a contact hole etching process on the semiconductor substrate, forming a first contact hole penetrating the interlayer dielectric layer above the power device structure. Then, photoresist is filled into the first contact hole, and photoresist is formed on the surface of the interlayer dielectric layer. The location of the deep trench to be formed is defined on the photoresist using a photolithography process, forming a deep trench penetrating the interlayer dielectric layer in the semiconductor substrate. Afterwards, an etching process is performed again on the first contact hole so that the first contact hole penetrates the nitride layer and its bottom is located in the conductive region of the power device structure.

[0069] In this specific implementation, when etching to form the first contact hole, the etching stops at the silicon nitride layer. In this way, when performing deep trench etching later, the photoresist filled in the first contact hole directly contacts the silicon nitride, which can avoid surface contamination or oxidation caused by direct contact between the photoresist filled in the first contact hole and the underlying polysilicon or silicon material.

[0070] Then, conductive material can be filled into the deep trench and the first contact hole.

[0071] In another specific implementation, if a first contact hole penetrating the interlayer dielectric layer 105 is formed above the power device structure before forming the deep trench 123, the first contact hole penetrating the interlayer dielectric layer can be formed above the power device structure after the deep trench is filled with conductive material.

[0072] Optionally, a first contact hole penetrating the interlayer dielectric layer can be formed directly above the power device structure; then, the first contact hole is filled with conductive material.

[0073] Optionally, before forming the first contact hole, a first oxide layer can be formed on the surface of the interlayer dielectric layer and the surface of the conductive material filled in the deep trench. This first oxide layer can protect the conductive material filled in the deep trench, preventing it from being exposed to air and contaminated. Then, a first contact hole penetrating the first oxide layer and the interlayer dielectric layer can be formed above the power device structure. Simultaneously with forming the first contact hole penetrating the first oxide layer and the interlayer dielectric layer above the power device structure, a third contact hole penetrating the first oxide layer can be formed above the deep trench; the bottom of the third contact hole is located within the conductive material filled in the deep trench. Then, conductive material can be filled into the first and third contact holes to lead the drain of the power device structure to the substrate surface through the conductive material-filled deep trench and the conductive material-filled third contact hole.

[0074] Furthermore, the semiconductor substrate may also include a second region, which is the region where the BCD device is to be formed. BCD (Bipolar-CMOS-DMOS) is a special semiconductor manufacturing process that can integrate bipolar transistors, complementary metal-oxide-semiconductor (CMOS), and diffused metal-oxide-semiconductor (DMOS) onto the same chip to achieve a combination of high-performance analog circuits, digital control, and high-voltage, high-current drive capabilities.

[0075] In this embodiment, a BCD device structure can be formed in the second region. In some examples, when the conductive structure is a one-piece structure, the BCD device structure can be formed before the conductive structure; in other examples, when the conductive structure is a multi-part structure, the BCD device structure can be formed after a portion of the conductive structure. This application does not specifically limit the formation order of the BCD device structure. Figure 3 The diagram illustrates the formation of a power device structure in the first region during the fabrication of a semiconductor structure according to an embodiment of this application. The semiconductor substrate may include a substrate layer 101 and an epitaxial layer 102. The substrate layer 101 may be a P-type substrate (P-Sub), and the epitaxial layer 102 may be a P-type epitaxial layer (P-EPI). The semiconductor substrate includes a first region 10 and a second region 20. The epitaxial layer refers to a new material layer with a specific doping concentration and crystal structure grown on the original semiconductor substrate through a process called epitaxy (EPI). This process allows control over the composition, thickness, doping type, and concentration of the new layer, thereby achieving specific electrical properties. The epitaxial layer can perfectly match the substrate at the atomic level, forming a continuous crystal structure.

[0076] Subsequently, high-energy N-type ion implantation can be performed on the epitaxial layer portion corresponding to the first region 10 in epitaxial layer 102 to form a DNW (Deep N Well) 105, and high-energy P-type ion implantation can be performed on the epitaxial layer portion corresponding to the second region 20 in epitaxial layer 102 to form a DPW (Deep P Well) 104. Then, power device structures 201-203 and an N-type buried layer 103 can be formed in the deep N well 105 formed in the first region 10. For ease of explanation, this embodiment uses a shielded gate trench power transistor (SGT) as an example for illustration.

[0077] The power device 201 includes a control gate 107 and a shielding gate 108. A second oxide layer 106 can be formed on the surface of the semiconductor substrate. The control gate and the shielding gate are made of polysilicon, and the oxide layer is made of silicon oxide. A P-type body region (P-Body Diffusion, abbreviated as PBD) 118 can be formed in the deep N-well 105. Multiple heavily doped N-type regions (N+ regions) can be formed in the deep N-well 105, including a heavily doped N-type region 109 located in the P-type body region 118 and a heavily doped N-type region 110 located in the deep N-well 105.

[0078] like Figure 4 The diagram shown is a schematic of the formation of a BCD device structure in the second region during the semiconductor structure fabrication method provided in this application embodiment. A BCD device structure, including a low-voltage CMOS logic device structure 204 and a high-voltage LDMOS power device structure 205, can be formed in the deep P-well 104 formed in the second region 20. Specifically, the deep P-well 104 formed in the second region 20 includes: shallow trenches 111, 145, and 149 for device isolation. The shallow trenches are filled with silicon oxide. A P-well (PW) 119 and an N-type drift field (NDF) 104 are also formed. Multiple heavily doped N-type regions (N+ regions) are formed in the P-well 119, including heavily doped N-type regions 112 and 114. A heavily doped N-type region 148 is formed in the N-type drift field 104. A heavily doped N-type region 147 and a heavily doped P-type region 146 are also formed in the deep P-well 104 formed in the second region 20. A field plate structure 121, a gate polysilicon 113, gate sidewalls 114 and 115 located on both sides of the gate polysilicon 113, and gate sidewalls 116 located on both sides of the gate polysilicon 115 are also formed.

[0079] The following combination Figures 5-23 The specific implementation methods of the semiconductor structure in the embodiments of this application are described in detail: Implementation Method 1 The formation of a deep trench in the semiconductor substrate that connects from one side of the device layer to the buried layer can be achieved by the following steps: forming an inter-layer dielectric (ILD) on the surface of the semiconductor substrate; and forming a deep trench in the semiconductor substrate through the inter-layer dielectric and with its bottom located in the buried layer by photolithography.

[0080] In some examples, such as Figure 5 The diagram shown is an example of forming a deep trench in a semiconductor substrate in a semiconductor structure fabrication method provided in this application. First, an interlayer dielectric layer 117 can be formed on the surface of the semiconductor substrate (on which a second oxide layer 106 is formed). The material of the interlayer dielectric layer 117 can be silicon oxide. Then, photoresist 122 is coated on the surface of the interlayer dielectric layer 117, and exposure, development, and etching processes are performed on the semiconductor substrate to form a deep trench 123 on the semiconductor substrate. The bottom of the deep trench 123 is located in an N-type buried layer 103.

[0081] like Figure 6 The diagram shown is a schematic of filling a deep trench with conductive material in the semiconductor structure fabrication method provided in this application embodiment. After forming the deep trench 123, a conductive material (such as tungsten (W)) can be deposited in the deep trench 123, and then the semiconductor substrate is polished to ensure that there is no conductive material residue on the surface of the interlayer dielectric layer 117 and that the surface is smooth.

[0082] In this implementation, a deep trench is formed first, followed by the formation of contact holes corresponding to the power device structure and the BCD device structure. That is, after filling the deep trench with conductive material, the first contact hole is not yet formed above the power device structure, and the second contact hole is not yet formed above the BCD device structure. At this time, as... Figure 7 The diagram shown is a schematic of an example of forming contact holes in the semiconductor structure fabrication method provided in this application embodiment. After depositing conductive material in the deep trench 123 and grinding it, a first contact hole penetrating the interlayer dielectric layer 117 can be formed above the power device structure formed in the first region 10, including a first contact hole 125 and another first contact hole 126. A second contact hole penetrating the interlayer dielectric layer can be formed above the BCD device structure formed in the second region 20, including a second contact hole 127, another second contact hole 128 and another second contact hole 129.

[0083] In a specific implementation, a first contact hole region to be formed in a first region and a second contact hole region to be formed in a second region can be defined using photolithography. Then, an etching step is performed to form a first contact hole penetrating the interlayer dielectric layer in the first contact hole region and a second contact hole penetrating the interlayer dielectric layer in the second contact hole region. The first contact hole is used to bring out the electrodes of the power device structure; the second contact hole is used to bring out the electrodes of the BCD device structure. The first and second contact holes are formed simultaneously in the same process step, saving process steps.

[0084] After forming the first and second contact holes, titanium / titanium nitride (Ti / TiN) stacks can be formed on the sidewall and bottom wall surfaces of the first and second contact holes (as shown in the attached figure). Figure 7 As shown, a Ti / TiN stack is provided on the sidewall of the contact hole. This can enhance the adhesion of the metal (such as tungsten) that is subsequently filled in the first and second contact holes, and effectively block the diffusion of metal atoms into the semiconductor material, preventing short circuits or performance degradation of the device.

[0085] After that, as Figure 8 The diagram shown is an example of filling conductive material into contact holes in a semiconductor structure fabrication method provided in this application embodiment. Figure 7 After the first contact hole 125, first contact hole 126, second contact hole 127, second contact hole 128, and second contact hole 129 are shown, conductive material (such as tungsten) can be filled into the first contact hole 125, first contact hole 126, second contact hole 127, second contact hole 128, and second contact hole 129. Then, the semiconductor substrate is polished to ensure that there is no conductive material residue on the surface of the interlayer dielectric layer 117 and that the surface is smooth.

[0086] After that, as Figure 9 The diagram illustrates an example of forming a metal interconnect layer in a semiconductor structure fabrication method provided in this application. After filling the first contact hole 125, first contact hole 126, second contact hole 127, second contact hole 128, and second contact hole 129 with conductive material, a metal interconnect layer can be formed above the deep trench, the first contact hole, and the second contact hole. Specifically, a metal interconnect layer 130 is formed above the deep trench 123, a metal interconnect layer 131 is formed above the first contact hole 125, a metal interconnect layer 132 is formed above the first contact hole 126, a metal interconnect layer 133 is formed above the second contact hole 127, a metal interconnect layer 134 is formed above the second contact hole 128, and a metal interconnect layer 135 is formed above the second contact hole 129. This enables the transmission of electrical signals.

[0087] The above is a detailed description of one implementation method of the semiconductor structure fabrication method in the embodiments of this application.

[0088] Implementation Method Two In this implementation, firstly, a deep trench can be formed according to the method provided in Implementation Method 1, and then a conductive material can be filled into the deep trench. That is, an interlayer dielectric layer can be formed on the surface of the semiconductor substrate first, and then a deep trench penetrating the interlayer dielectric layer can be formed in the semiconductor substrate by photolithography.

[0089] The difference from the first implementation is that, in this implementation, after the conductive material is filled in the deep trench, and before the first contact hole penetrating the interlayer dielectric layer is formed above the power device structure and the second contact hole penetrating the interlayer dielectric layer is formed above the BCD device structure, a first oxide layer can be formed on the surface of the interlayer dielectric layer and the surface of the conductive material filled in the deep trench.

[0090] like Figure 10 The diagram shown is a schematic representation of the formation of the first oxide layer in the semiconductor structure fabrication method provided in this application embodiment. Figure 6 After the conductive material is deposited in the deep trench 123 and polished, a first oxide layer 136 can be formed on the surface of the conductive material deposited in the interlayer dielectric layer 117 and the deep trench 123. In some examples, the thickness of the first oxide layer 136 can be in the range of 200 Å to 500 Å, for example, 200 Å, 250 Å, 300 Å, 350 Å, 400 Å, 450 Å, 500 Å, etc.

[0091] After that, as Figure 11 The diagram shown is another example of forming contact holes in a semiconductor structure fabrication method provided in this application. A first contact hole penetrating the first oxide layer 136 and the interlayer dielectric layer 117 can be formed above the power device structure formed in the first region 10, including a first contact hole 125 and another first contact hole 126. A second contact hole penetrating the first oxide layer 136 and the interlayer dielectric layer 117 can be formed above the BCD device structure formed in the second region 20. A first contact hole penetrating the interlayer dielectric layer 117 can be formed above the power device structure formed in the first region 10, including a first contact hole 125 and another first contact hole 126. A second contact hole can be formed above the BCD device structure formed in the second region 20, including a second contact hole 127, another second contact hole 128, and another second contact hole 129.

[0092] After that, as Figure 12The diagram shown is another example of filling conductive material into contact holes in the semiconductor structure fabrication method provided in this application embodiment. Figure 12 After the first contact hole 125, the first contact hole 126, the second contact hole 127, the second contact hole 128 and the second contact hole 129 shown, a conductive material (such as tungsten) can be filled into the first contact hole 125, the first contact hole 126, the second contact hole 127, the second contact hole 128 and the second contact hole 129.

[0093] Subsequently, the first oxide layer and a portion of the conductive material filling the first and second contact holes can be removed to ensure that the height difference between the remaining conductive material in the first and second contact holes and the interlayer dielectric layer is within a preset range (approximately flush). In a specific implementation, the first oxide layer and a portion of the conductive material filling the first and second contact holes can be removed by grinding or etching.

[0094] Subsequently, a metal interconnect layer can be formed over the first contact hole and the second contact hole.

[0095] In this implementation, after filling the deep trench with conductive material and before forming the first contact hole and the second contact hole, a first oxide layer is formed on the surface of the interlayer dielectric layer and the conductive material filled in the deep trench. On the one hand, this can avoid contamination caused by the conductive material filled in the deep trench being exposed to the air. On the other hand, when forming the first contact hole and the second contact hole, a layer of photoresist needs to be applied, which can avoid contact contamination caused by direct contact between the photoresist and the conductive material filled in the deep trench.

[0096] The above is a detailed description of the second implementation method of the semiconductor structure fabrication method in the embodiments of this application.

[0097] Implementation Method 3 In this implementation, before forming a deep trench penetrating the interlayer dielectric layer in the semiconductor substrate by photolithography, the following steps can be performed first: forming a first contact hole penetrating the interlayer dielectric layer above the power device structure, and forming a second contact hole penetrating the interlayer dielectric layer above the BCD device structure.

[0098] In other words, this implementation first forms the first contact hole of the power device structure and the second contact hole of the BCD device structure, and then forms a deep trench for leading the drain of the power device structure to the surface of the semiconductor substrate.

[0099] The following combination Figures 13-18 This implementation method will be described in detail: like Figure 13The diagram shown is a schematic of the formation of a nitride layer in the semiconductor structure fabrication method provided in this application embodiment. A nitride layer 137 can be formed on the surface of a semiconductor substrate (on which a second oxide layer 106 is formed). This nitride layer 137 can be used as a stop layer for subsequent contact hole etching.

[0100] After that, as Figure 14 The diagram shown is a schematic diagram of the formation of an interlayer dielectric layer in the semiconductor structure fabrication method provided in this application embodiment. After forming a nitride layer 137 on the surface of a semiconductor substrate, an interlayer dielectric layer 117 can be formed on the surface of the nitride layer 137.

[0101] After that, as Figure 15 The diagram shown is another example of forming contact holes in the semiconductor structure fabrication method provided in this application embodiment. After forming the interlayer dielectric layer 117, a photolithography process can be performed to form a first contact hole penetrating the interlayer dielectric layer 117 above the power device structure formed in the first region 10, including a first contact hole 138 and another first contact hole 139, and a second contact hole penetrating the interlayer dielectric layer 117 above the BCD device structure formed in the second region 20, including a second contact hole 140, another second contact hole 141, and another second contact hole 142. In a specific implementation, a contact hole etching process can be performed on the semiconductor substrate using a nitride layer as a stop layer to form a first contact hole penetrating the interlayer dielectric layer above the power device structure formed in the first region 10, and a second contact hole penetrating the interlayer dielectric layer above the BCD device structure formed in the second region 20.

[0102] In this implementation, the etching process stops at the silicon nitride layer when forming the first and second contact holes. This way, during subsequent deep trench etching, the photoresist filling the first and second contact holes directly contacts the silicon nitride, avoiding surface contamination or oxidation caused by direct contact between the photoresist filling the first and second contact holes and the underlying polysilicon or silicon material.

[0103] After that, as Figure 16 The diagram shown is another example of forming a deep trench in a semiconductor substrate in the semiconductor structure fabrication method provided in this application embodiment. After forming the first contact hole 138, the first contact hole 139, the second contact hole 140, the second contact hole 141, and the second contact hole 142, photoresist can be filled into the first contact hole 138, the first contact hole 139, the second contact hole 140, the second contact hole 141, and the second contact hole 142, and photoresist can be coated on the surface of the interlayer dielectric layer 117. Then, exposure, development, and etching processes are performed to form a deep trench 144 with its bottom located in the N-type buried layer 103 in the semiconductor substrate.

[0104] After that, as Figure 17 As shown, the photoresist filling the first contact hole 138, the first contact hole 139, the second contact hole 140, the second contact hole 141 and the second contact hole 142 can be removed by dry or wet methods, and the photoresist on the surface of the interlayer dielectric layer 117 can also be removed.

[0105] After that, as Figure 18 The diagram shown is a schematic of the re-etching of contact holes in the semiconductor structure fabrication method provided in this application embodiment. After forming the deep trench 144, the first contact hole (first contact hole 138 and another first contact hole 139) and the second contact hole (second contact hole 140, another second contact hole 141 and another second contact hole 142) can be etched again so that the first contact hole penetrates the nitride layer 137 and its bottom is located in the conductive region of the power device structure formed in the first region 10, and the second contact hole penetrates the nitride layer 137 and its bottom is located in the conductive region of the BCD device structure formed in the second region 20.

[0106] After that, as Figure 19 The diagram illustrates the filling of conductive material into deep trenches and contact holes in the semiconductor structure fabrication method provided in this application embodiment. After forming deep trench 144, first contact holes 138 and 139 located in the conductive region of the power device structure, and second contact holes 140, 141, and 142 located in the conductive region of the BCD device structure, conductive material (such as tungsten) can be filled into deep trench 144, first contact holes 138, 139, 140, 141, and 142. Subsequently, the semiconductor substrate is polished to ensure that the surface of the interlayer dielectric layer 117 is free of conductive material residue and has a smooth surface.

[0107] like Figure 20 As shown, a metal interconnect layer 150 can be formed above a deep trench 144 filled with conductive material, a metal interconnect layer 151 can be formed above a first contact hole 138 filled with conductive material, a metal interconnect layer 152 can be formed above a first contact hole 139 filled with conductive material, a metal interconnect layer 153 can be formed above a second contact hole 140 filled with conductive material, a metal interconnect layer 154 can be formed above a second contact hole 141 filled with conductive material, and a metal interconnect layer 155 can be formed above a second contact hole 142 filled with conductive material.

[0108] In this implementation, a first contact hole for the power device structure and a second contact hole for the BCD device structure are first formed, and then a deep trench is formed to lead the drain of the power device structure to the surface of the semiconductor substrate. In this way, the filling of conductive material in the deep trench and the contact hole can be achieved simultaneously in one process step, saving process steps.

[0109] The above is a detailed description of the third implementation method of the semiconductor structure fabrication method in the embodiments of this application.

[0110] Implementation Method 4 In this implementation, firstly, a deep trench can be formed according to the method provided in Implementation Method 1, and then a conductive material can be filled into the deep trench. That is, an interlayer dielectric layer can be formed on the surface of the semiconductor substrate first, and then a deep trench penetrating the interlayer dielectric layer can be formed in the semiconductor substrate by photolithography.

[0111] After the deep trench is filled with conductive material, and before the first contact hole penetrating the interlayer dielectric layer is formed above the power device structure and the second contact hole penetrating the interlayer dielectric layer is formed above the BCD device structure, a first oxide layer may be formed on the surface of the interlayer dielectric layer and the surface of the conductive material filled in the deep trench.

[0112] Subsequently, a first contact hole penetrating the first oxide layer and the interlayer dielectric layer is formed above the power device structure, and a second contact hole penetrating the first oxide layer and the interlayer dielectric layer is formed above the BCD device structure. In this implementation, a third contact hole penetrating the first oxide layer can also be formed above the deep trench. The bottom of the third contact hole is located in the conductive material filled in the deep trench.

[0113] like Figure 21 The diagram shown illustrates the formation of a first contact hole, a second contact hole, and a third contact hole in the semiconductor structure fabrication method provided in this application embodiment. A first contact hole, including a first contact hole 125 and another first contact hole 126, can be formed above the power device structure formed in the first region 10, penetrating the first oxide layer 136 and the interlayer dielectric layer 117. A second contact hole, including a second contact hole 127, another second contact hole 128, and another second contact hole 129, can be formed above the BCD device structure formed in the second region 20, penetrating the first oxide layer 136 and with its bottom located in the conductive material filled in the deep trench 123. A third contact hole 156, penetrating the first oxide layer 136, is formed above the deep trench 123 and its bottom is located in the conductive material filled in the deep trench 123.

[0114] After that, as Figure 22The diagram shown illustrates another example of filling contact holes with conductive material in the semiconductor structure fabrication method provided in this application. Conductive material (such as tungsten) can be filled into the first contact hole 125, first contact hole 126, second contact hole 127, second contact hole 128, second contact hole 129, and third contact hole 156. Afterwards, the semiconductor substrate can be polished to ensure that the surface of the first oxide layer 136 is free of conductive material residue and has a smooth surface.

[0115] After that, as Figure 23 The diagram shown is another example of forming a metal interconnect layer in the semiconductor structure fabrication method provided in this application embodiment. A metal interconnect layer 158 can be formed above a first contact hole 125 filled with conductive material, a metal interconnect layer 159 can be formed above a first contact hole 126 filled with conductive material, a metal interconnect layer 160 can be formed above a second contact hole 127 filled with conductive material, a metal interconnect layer 161 can be formed above a second contact hole 128 filled with conductive material, a metal interconnect layer 162 can be formed above a second contact hole 129 filled with conductive material, and a metal interconnect layer 157 can be formed above a third contact hole 156 filled with conductive material.

[0116] In this implementation, a third contact hole is formed above the deep trench, its bottom located within the conductive material filling the deep trench, and... Figure 12 Compared to the method shown where a third contact hole is not formed above the deep trench, in this implementation, the material above the deep trench and above the contact hole is the same. Subsequently, when the semiconductor substrate is polished after filling the contact hole with conductive material, Figure 12 In the illustrated method, the different materials above the deep trench and above the contact hole lead to inconsistent grinding rates. Taking tungsten as an example, the tungsten filling the contact hole and the first oxide layer (made of silicon oxide) covering the deep trench have different hardness. The first oxide layer is harder and has a slower grinding rate, while tungsten is softer and has a faster grinding rate. This results in tungsten grinding faster under the same grinding conditions. In contrast, in this implementation, the materials above the deep trench and above the contact hole are the same, allowing for consistent grinding rates and synchronized grinding. This improves grinding uniformity and results in a smoother surface after grinding. The above is a detailed description of the fourth implementation method of the semiconductor structure fabrication method in the embodiments of this application.

[0117] In the appendix Figure 2 ~Appendix Figure 23 This application uses a shielded gate trench power transistor (SGT) as an example to illustrate its application. However, this application is not limited to this, and may include other examples. Figure 24The diagram shown is a schematic of the integration of trench metal-oxide-semiconductor field-effect transistors and BCD devices in the semiconductor structure fabrication method provided in this application embodiment. The power device structure formed in the first region 10 is a trench metal-oxide-semiconductor field-effect transistor, namely trench metal-oxide-semiconductor field-effect transistor 163, trench metal-oxide-semiconductor field-effect transistor 164, trench metal-oxide-semiconductor field-effect transistor 165 and trench metal-oxide-semiconductor field-effect transistor 166.

[0118] In another alternative embodiment, the conductive structure can be formed in multiple stages. For example, the conductive structure may include a trench structure and a fourth contact hole communicating with the trench structure. Figure 25 The diagram shown is a schematic of a conductive structure formed multiple times in the semiconductor structure fabrication method provided in this application embodiment. A trench structure 123-1 can be formed before forming the interlayer dielectric layer 117, and a conductive material can be filled into the trench structure 123-1. After forming the interlayer dielectric layer 117, while forming first contact holes 125 and 126 and second contact holes 127, 128, and 129 in the first and second regions respectively, a fourth contact hole 123-2 communicating with the trench structure 123-1 is formed above the trench structure 123-1, and a conductive material is filled into the fourth contact hole 123-2. The trench structure 123-1 filled with conductive material and the fourth contact hole 123-2 filled with conductive material constitute the conductive structure.

[0119] In some embodiments, the trench structure 123-1 can be formed and filled with conductive material before forming the BCD device. In this way, when removing the excess conductive material formed when filling the trench structure 123-1 with conductive material, it is possible to avoid affecting the BCD device.

[0120] In this embodiment of the application, by jointly fabricating the BCD device structure and the power device structure, process steps can be saved. For example, the second contact hole of the BCD device structure can be fabricated simultaneously with the first contact hole of the power device structure, thereby improving the fabrication efficiency of the device.

[0121] The method for fabricating a semiconductor structure provided in this application includes the following steps: providing a semiconductor substrate; the semiconductor substrate includes a first region; forming a power device structure in the first region; forming a buried layer below the power device structure; forming a conductive structure in the semiconductor substrate that connects from one side of the device layer to the buried layer; the conductive structure is used to lead the drain of the power device structure to the surface of the semiconductor substrate.

[0122] As can be seen, the semiconductor structure fabrication method provided in this application can form a buried layer beneath the power device structure during the fabrication of any power device such as SGT (Shielded Gate Transistor), trench MOS (Trench Metal-Oxide-Semiconductor Field-Effect Transistor), SJ (Super Junction MOSFET), and IGBT (Insulated Gate Bipolar Transistor). This buried layer allows for the effective drain current to flow into the power device structure. Thus, after forming a conductive structure connecting the device layer to the buried layer, the drain current of the power device structure can flow from the buried layer to the conductive structure, thereby leading the drain current to the surface of the semiconductor substrate through the conductive structure. Compared to the prior art where the drain current is led out using a back-substrate drain, requiring the drain current to pass through a high-resistivity substrate, the drain current of the power device in this embodiment does not need to pass through the high-resistivity substrate, effectively reducing the specific on-resistance of the power device.

[0123] A second embodiment of this application provides a semiconductor structure including a power device structure and a conductive structure extending from one side of the device layer to a buried layer located below the power device structure; wherein the conductive structure is used to lead the drain of the power device structure to the surface of the semiconductor substrate.

[0124] The semiconductor structure may also include a BCD device structure.

[0125] The semiconductor structure provided in the second embodiment of this application can be obtained by the preparation method of the semiconductor structure provided in the first embodiment of this application. For details, please refer to the detailed description of the preparation method of the semiconductor structure provided in the first embodiment of this application, which will not be repeated here.

[0126] As can be seen, in the semiconductor structure provided in the second embodiment of this application, in a power device structure or a semiconductor structure integrating a power device structure and a BCD device structure, since the conductive structure connects from one side of the device layer to the buried layer located below the power device structure, the drain current of the power device structure can flow from the buried layer to the conductive structure, thereby leading the drain current of the power device structure to the surface of the semiconductor substrate through the conductive structure. It is evident that, compared to the prior art where the drain current is led out using a back substrate drain, requiring the drain current to pass through the bottom high-resistivity substrate, the drain current of the power device structure in the semiconductor device provided in this embodiment does not need to pass through the bottom high-resistivity substrate, effectively reducing the specific on-resistance of the power device.

[0127] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A semiconductor substrate is provided; the semiconductor substrate includes a first region; A power device structure is formed in the first region; a buried layer is formed beneath the power device structure; A conductive structure is formed in the semiconductor substrate, extending from one side of the device layer to the buried layer; the conductive structure is used to lead the drain of the power device structure to the surface of the semiconductor substrate.

2. The method according to claim 1, characterized in that, The formation of a conductive structure in the semiconductor substrate that extends from one side of the device layer to the buried layer includes: A deep trench is formed in the semiconductor substrate, extending from one side of the device layer to the buried layer; The deep trench is filled with conductive material to form a conductive structure.

3. The method according to claim 1, characterized in that, The process of forming a deep trench in the semiconductor substrate that extends from one side of the device layer to the buried layer includes: An interlayer dielectric layer is formed on the surface of the semiconductor substrate; A deep trench is formed in the semiconductor substrate by photolithography, penetrating the interlayer dielectric layer and with its bottom located in the buried layer.

4. The method according to claim 3, characterized in that, Prior to forming a deep trench in the semiconductor substrate through the interlayer dielectric layer and with its bottom located in the buried layer using a photolithography process, the method further includes: A first contact hole is formed above the power device structure, penetrating the interlayer dielectric layer.

5. The method according to claim 4, characterized in that, The semiconductor substrate further includes a second region in which a BCD device structure is formed; the method further includes: While forming a first contact hole penetrating the interlayer dielectric layer above the power device structure, a second contact hole penetrating the interlayer dielectric layer is formed above the BCD device structure.

6. The method according to claim 4, characterized in that, The process of forming an interlayer dielectric layer on the surface of the semiconductor substrate includes: A nitride layer is formed on the surface of the semiconductor substrate, and an interlayer dielectric layer is formed on the surface of the nitride layer; A first contact hole penetrating the interlayer dielectric layer is formed above the power device structure, and a second contact hole penetrating the interlayer dielectric layer is formed above the BCD device structure, including: Using the nitride layer as a stop layer, a contact hole etching process is performed on the semiconductor substrate to form a first contact hole penetrating the interlayer dielectric layer above the power device structure, and a second contact hole penetrating the interlayer dielectric layer above the BCD device structure.

7. The method according to claim 6, characterized in that, After forming a deep trench penetrating the interlayer dielectric layer in the semiconductor substrate using a photolithography process, the method further includes: The first contact hole and the second contact hole are etched again so that the first contact hole penetrates the nitride layer and its bottom is located in the conductive region of the power device structure, and the second contact hole penetrates the nitride layer and its bottom is located in the conductive region of the BCD device structure.

8. The method according to claim 5, characterized in that, The process of filling the deep trench with conductive material includes: Conductive material is filled into the deep trench, the first contact hole, and the second contact hole.

9. The method according to claim 3, characterized in that, In the absence of a first contact hole formed above the power device structure, after filling the deep trench with conductive material, the method further includes: A first contact hole is formed above the power device structure, penetrating the interlayer dielectric layer.

10. The method according to claim 9, characterized in that, Before forming a first contact hole penetrating the interlayer dielectric layer above the power device structure, the method further includes: A first oxide layer is formed on the surface of the interlayer dielectric layer and on the surface of the conductive material filling the deep trench.

11. The method according to claim 10, characterized in that, The semiconductor substrate further includes a second region in which a BCD device structure is formed; the first contact hole formed above the power device structure, penetrating the interlayer dielectric layer, includes: A first contact hole penetrating the first oxide layer and the interlayer dielectric layer is formed above the power device structure, and a second contact hole penetrating the first oxide layer and the interlayer dielectric layer is formed above the BCD device structure.

12. The method according to claim 9, characterized in that, The first contact hole, which penetrates the interlayer dielectric layer, is formed above the power device structure, including: A first contact hole is formed above the power device structure, penetrating the first oxide layer and the interlayer dielectric layer, and a third contact hole is formed above the deep trench, penetrating the first oxide layer; the bottom of the third contact hole is located in the conductive material filled in the deep trench.

13. A semiconductor structure, characterized in that, The structure includes a power device structure and a conductive structure that extends from one side of the device layer to a buried layer located below the power device structure. The conductive structure is used to lead the drain of the power device structure to the surface of the semiconductor substrate.

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