A package structure of a current-sensing power MOSFET and a manufacturing method thereof

Abstract

The application discloses a packaging structure of a current-sensing power MOSFET and a manufacturing method thereof. The packaging structure comprises at least one first power MOS and at least one first sensing MOS, the first power MOS and the first sensing MOS are integrated on a first substrate and share a first gate driving signal; at least one second power MOS and at least one second sensing MOS, the second power MOS and the second sensing MOS are integrated on a second substrate and share a second gate driving signal; a first chip integrated with the first power MOS and the first sensing MOS and a second chip integrated with the second power MOS and the second sensing MOS are stacked in a back-to-back manner and connected through conductive glue; and a bottom electrode of the stacked structure is rewired to a top layer to realize integration of current monitoring and bidirectional switching power MOS.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power devices and advanced packaging technology, and particularly relates to a three-dimensional stacked packaging structure that integrates a current sensing unit with a power metal-oxide-semiconductor (MOS) device and its manufacturing method. Background Technology

[0002] With the rapid development of consumer electronics (such as mobile phones, laptops, and wearable devices), higher requirements have been placed on the safety, energy efficiency, and system integration of lithium batteries. In related applications, a lithium battery charge / discharge management system is typically required to protect the battery from overcharge, over-discharge, overcurrent, and short circuits. This type of charge / discharge management system generally includes a control integrated circuit (IC), a power metal-oxide-semiconductor field-effect transistor (MOSFET), and current sensing elements, and is usually implemented as a protection circuit module.

[0003] In existing technologies, power MOSFETs are typically connected in series between the battery pack and the load, and a dedicated control IC controls the on / off state of the power MOSFETs to manage battery charging and discharging. To achieve bidirectional current control, the charge / discharge management system usually includes at least two power MOSFETs, one for the charging path and the other for the discharging path. Furthermore, to monitor the battery's charging and discharging current in real time, existing solutions typically require a separate current sensing element in the circuit, such as a shunt resistor or a dedicated current sensing device.

[0004] However, in the aforementioned traditional solutions, power MOSFETs, current sensing elements, and control ICs are mostly implemented as discrete devices or multi-chip packages, resulting in a large number of components in the protection circuit module. This not only increases the footprint of the printed circuit board (PCB) but also makes it difficult to meet the high integration requirements of miniaturized and thinner systems. Furthermore, discrete current sensing resistors introduce additional power consumption and heat loss, which is detrimental to improving the overall system efficiency. In addition, the interconnection structure between multiple components may increase parasitic parameters, thereby affecting the system's reliability and response speed.

[0005] Therefore, how to reduce the number of discrete components, reduce PCB footprint, increase power density, and achieve a higher degree of system integration while ensuring lithium battery charge / discharge management and current detection functions has become a pressing technical problem in the field of semiconductor power devices and packaging technology. Summary of the Invention

[0006] To address the issues of large PCB area occupation and hindering miniaturization in existing lithium battery protection circuit modules, as described in the background, this invention provides a packaging structure for a current-sensing power MOSFET. The core of this packaging structure lies in the high integration of current sensing functionality with the power MOSFET, employing an innovative three-dimensional stacked packaging method. This significantly reduces module size, increases power density, and simplifies circuit design.

[0007] This invention provides a package structure for a current-sensing power MOSFET, comprising: at least one first power MOSFET and at least one first sensing MOSFET, wherein the first power MOSFET and the first sensing MOSFET are integrated on a first substrate and share a first gate drive signal; at least one second power MOSFET and at least one second sensing MOSFET, wherein the second power MOSFET and the second sensing MOSFET are integrated on a second substrate and share a second gate drive signal; a first chip integrating the first power MOSFET and the first sensing MOSFET and a second chip integrating the second power MOSFET and the second sensing MOSFET are stacked back-to-back and connected by conductive adhesive; the bottom electrode of the package structure is rearranged and wired to the top layer to achieve the integration of current monitoring and bidirectional switching power MOSFET.

[0008] In some embodiments, the substrate of the first substrate and the second substrate is a silicon-based, carbon-based, gallium nitride, or gallium arsenide substrate.

[0009] In some embodiments, the first power MOS, the first sensing MOS, the second power MOS, and the second sensing MOS are trench MOS or planar MOS.

[0010] In some embodiments, the first sensing MOS and the second sensing MOS are located on the sides of the first power MOS and the second power MOS, or the first power MOS and the second power MOS surround the first sensing MOS and the second sensing MOS.

[0011] In some embodiments, the packaging structure further includes a packaging shell, and the bottom electrode is connected to the top layer via lead-out metal pillars.

[0012] In some embodiments, the metal pillars include a first sensing electrode leading metal pillar, a first power MOS source leading metal pillar, a second sensing electrode leading metal pillar, a second power MOS source leading metal pillar, a first power MOS gate leading metal pillar, and a second power MOS gate leading metal pillar.

[0013] In some embodiments, the first sensing electrode lead-out metal post and the second sensing electrode lead-out metal post are square or round electrodes.

[0014] In some embodiments, the locations of the first sensing electrode lead-out metal post and the second sensing electrode lead-out metal post are not limited to the chip edge.

[0015] The present invention also provides a method for manufacturing a package structure of a current sensing power MOSFET, comprising the following steps: designing the area ratio of the sensing MOSFET to the power MOSFET; performing monolithic wafer manufacturing to integrate the sensing MOSFET and the power MOSFET into a single chip; performing back-side thinning on the chip; stacking the two chips back-to-back; re-layouting the wiring of the package structure and completing the overall packaging.

[0016] In some embodiments, during the monolithic wafer fabrication, the sensing MOS and the power MOS share a gate drive signal.

[0017] The present invention has the following beneficial effects:

[0018] 1. Significantly reduced PCB footprint: By integrating power MOSFETs and sensing MOSFETs on the same substrate and using 3D stacked packaging, the independent sensing resistors and discrete MOSFETs in traditional solutions are eliminated, resulting in a significant reduction in the size of the entire protection circuit module, meeting the miniaturization and thinning requirements of consumer electronics products.

[0019] 2. Increased power density: The highly integrated design and compact 3D layout enable higher power handling capacity per unit volume, improving the overall performance of the system.

[0020] 3. Simplified Design and Manufacturing: The power MOSFET and sensing MOSFET share the same gate drive signal, reducing the complexity of the control circuit. Simultaneously, the re-layout wiring technique avoids redundant design and leads, simplifying the packaging process.

[0021] 4. Optimized electrical performance: The compact layout and optimized lead design help reduce parasitic resistance and inductance, improve switching speed and efficiency, and enhance circuit performance. Attached Figure Description

[0022] Embodiments of the present invention will be described with reference to the accompanying drawings, which are briefly described below.

[0023] Figure 1 This is a schematic diagram of the package structure of a current-sensing power MOSFET.

[0024] Figure 2 Re-layout wiring for the package structure, top view after packaging.

[0025] Figure 3 for Figure 2 A cross-sectional view taken along line A-A'.

[0026] Figure 4 for Figure 2 A cross-sectional view taken along line B-B'.

[0027] Figure 5 This is a flowchart illustrating the manufacturing method of the package structure for a current-sensing power MOSFET.

[0028] In the accompanying drawings, the same reference numerals generally denote the same, functionally similar and / or structurally similar components.

[0029] Explanation of reference numerals in the attached figures: Package structure 1; First power MOS 10; First power MOS source 101; First power MOS gate 102; First power MOS trench 103; First sensing MOS 11; First sensing MOS electrode 111; First sensing MOS trench 112; Second power MOS 20; Second power MOS trench 201; Second sensing MOS 21; Second sensing MOS trench 211; Package housing 30; First source electrode 310; First sensing electrode 311; First gate electrode 312; Second source electrode 320; Second sensing electrode 321; Second gate electrode 322; Conductive adhesive 40; First sensing electrode lead-out metal pillar 511; First power MOS source lead-out metal pillar 512; First power MOS gate lead-out metal pillar 513; Second sensing electrode lead-out metal pillar 521; Second power MOS source lead-out metal pillar 522; Second power MOS gate lead-out metal pillar 523. Detailed Implementation

[0030] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0032] Embodiments of this application are described herein with reference to cross-sectional views, which are preferred embodiments of this application. Variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of embodiments of this application.

[0033] Please see Figure 1 , Figure 1 This is a schematic diagram of the package structure of a current-sensing power MOSFET.

[0034] like Figure 1 As shown, this invention provides a package structure 1 for a current-sensing power MOSFET, comprising: at least one first power MOSFET 10 and at least one first sensing MOSFET 11, the first power MOSFET 10 and the first sensing MOSFET 11 being integrated on a first substrate and sharing a first gate drive signal; at least one second power MOSFET 20 and at least one second sensing MOSFET 21, the second power MOSFET 20 and the second sensing MOSFET 21 being integrated on a second substrate and sharing a second gate drive signal; a first chip integrating the first power MOSFET 10 and the first sensing MOSFET 11 and a second chip integrating the second power MOSFET 20 and the second sensing MOSFET 21 are stacked back-to-back and connected by conductive adhesive 40; the bottom electrode of the package structure 1 is rearranged and routed to the top layer to achieve the integration of current monitoring and bidirectional switching power MOSFETs. The substrate of the first and second substrates is silicon-based, carbon-based, gallium nitride, or gallium arsenide substrate, but this invention is not limited to these.

[0035] Figure 1 In the first chip, the first power MOS 10 is the main power element carrying current, adopting a trench MOS structure (shown as a vertical trench in the figure). The source 101 of the first power MOS serves as the main current input or output terminal of the first power MOS 10, electrically connected to external circuits or redistribution layers. In the bidirectional switching architecture, it forms a corresponding node with the source or drain of the second power MOS to achieve high current carrying capacity and reduce internal package resistance and power loss. The gate 102 of the first power MOS receives the gate drive signal, controls the on and off states of the first power MOS 10, and shares the same gate signal with the first sensing MOS 11 to ensure synchronous operation of the power MOS and the sensing MOS, improving current sensing accuracy. The trench 103 of the first power MOS is a vertical conductive channel in the trench MOS structure, effectively increasing the channel width per unit area and significantly reducing the on-resistance (Rds(on)), making it suitable for high-current, high-power applications. The first sensing MOS electrode 111 outputs a sensing current or a sensing voltage, which is connected to a current detection circuit or a control IC to avoid external shunt resistors, reduce power consumption and temperature rise, and provide a high-precision current feedback signal. The first sensing MOS trench 112 forms the current path of the sensing MOS and uses the same or similar process conditions as the first power MOS 10 to ensure a stable ratio between the sensing current and the actual power current, and to improve process consistency and measurement reliability.

[0036] Secondly, on the second chip, the second power MOS 20 and the first power MOS 10 are configured back-to-back for current control in the other conduction direction to block the unidirectional conduction problem caused by the body diode, realizing a true bidirectional power switch suitable for applications such as battery protection and load switching. The second power MOS trench 201 provides a vertical conduction channel for the second power MOS 20, with a structure symmetrical to the first power MOS 10, maintaining consistent electrical characteristics during bidirectional conduction and reducing reverse conduction losses. The second sensing MOS trench 211 corresponds to the current sensing channel of the second power MOS 20, used to detect the magnitude of current in the reverse or other direction, and can simultaneously monitor forward and reverse currents, providing complete current protection and control information. The conductive adhesive 40 is used to electrically connect the first chip and the second chip, while providing mechanical fixation and heat conduction paths, simplifying the three-dimensional stacking process, reducing parasitic resistance and parasitic inductance between chips, and improving overall package reliability.

[0037] like Figure 1 As shown, the first power MOS 10, the first sensing MOS 11, the second power MOS 20, and the second sensing MOS 21 are trench MOS or planar MOS; Figure 1 As shown, the first power MOS 10, the first sensing MOS 11, the second power MOS 20, and the second sensing MOS 21 are trench MOS devices, specifically the first power MOS trench 103, the first sensing MOS trench 112, the second power MOS trench 201, and the second sensing MOS trench 211, respectively. In some embodiments, the first sensing MOS 11 and the second sensing MOS 21 are located on the sides of the first power MOS 10 and the second power MOS 20; or, the first power MOS 10 and the second power MOS 20 surround the first sensing MOS 11 and the second sensing MOS 21.

[0038] Please see Figures 2 to 4 , Figure 2 Re-layout wiring for the package structure, and a top view after packaging; Figure 3 for Figure 2 A cross-sectional view taken along line A-A'; and Figure 4 for Figure 2 A cross-sectional view taken along line B-B'.

[0039] like Figures 2 to 4 As shown, the packaging structure 1 also includes a packaging shell 30, and the bottom electrode is connected to the top layer through lead-out metal pillars, thereby realizing the integration of current monitoring and bidirectional switching power MOS. Figure 2The MOS electrodes stacked on the top and bottom layers are led out and re-routed, with the bottom layer electrode led out to the top layer. After the two layers of chips are stacked in three dimensions, the electrodes that were originally located at different heights or positions are led out to the package surface through rerouting to facilitate external electrical connections and measurements.

[0040] like Figure 2 The package 30 shown encapsulates the three-dimensionally stacked first and second chips, providing mechanical protection, moisture resistance, and contamination prevention, and serving as a carrier for rewiring and electrode lead-out. The first source electrode 310 of the lead-out electrode corresponding to the first power MOS 10 is the main current terminal of the first power MOS 10. Through rewiring, it is led out from inside the stacked structure to the package surface and can serve as a current input or output terminal, providing a low-impedance, high-current external connection path, facilitating system-level wiring and heat dissipation design. The first gate electrode 312 corresponds to the common gate of the first power MOS 10 and the first sensing MOS 11, used to input the gate drive control signal, ensuring synchronous turn-on and turn-off of the power MOS and the sensing MOS, improving current sensing accuracy and dynamic consistency. The first sensing electrode 311 of the lead-out electrode corresponding to the first sensing MOS 11 is the sensing output terminal of the first sensing MOS 11, outputting a sensing current or voltage proportional to the current of the first power MOS 10, for external control ICs to perform current monitoring, overcurrent protection, or power control, eliminating the need for external shunt resistors and reducing power consumption and package area.

[0041] Furthermore, the second source electrode 320 of the lead-out electrode corresponding to the second power MOS 20 is the main current terminal of the second power MOS 20, symmetrically configured with the first source electrode 310. This, combined with the back-to-back MOS structure, enables current conduction in the other direction, suitable for bidirectional current applications. The second gate electrode 322, corresponding to the shared gate of the second power MOS 20 and the second sensing MOS 21, receives the second set of gate drive signals, independently controlling the conduction state in the second direction, providing control flexibility for bidirectional switching. The second sensing electrode 321 of the lead-out electrode corresponding to the second sensing MOS 21 is the sensing output terminal of the second sensing MOS 21, used to detect the magnitude of current in the reverse or second direction. Simultaneous forward and reverse current monitoring can be achieved, enhancing the system's protection and control capabilities.

[0042] Through Figure 2 The redesigned layout achieves the following key effects: it overcomes the electrode height limitations caused by three-dimensional stacking, effectively brings the electrodes of the underlying chip to the package surface, clearly separates the power electrodes from the sensing electrodes, avoids interference, and improves package integration and electrical reliability.

[0043] like Figure 3As shown, the metal pillars leading out include a first sensing electrode leading-out metal pillar 511, a first power MOS source leading-out metal pillar 512, a second sensing electrode leading-out metal pillar 521, a second power MOS source leading-out metal pillar 522, a first power MOS gate leading-out metal pillar 513, and a second power MOS gate leading-out metal pillar 523. In some embodiments, the first sensing electrode leading-out metal pillar 511 and the second sensing electrode leading-out metal pillar 521 are square or circular electrodes. In some embodiments, the positions of the first sensing electrode leading-out metal pillar 511 and the second sensing electrode leading-out metal pillar 521 are not limited to the chip edge.

[0044] Figure 3 For along Figure 2 The vertical cross-sectional diagram obtained by the A-A' section line is mainly used to illustrate the three-dimensional back-to-back stacking relationship of the upper and lower chips, the configuration of the power MOS and the sensing MOS at different height layers, and the redistribution of the internal electrodes to the outside of the package through the metal pillars, as well as the separation design of the power current path and the sensing current path. In the cross-sectional structure of the first chip, the first power MOS 10 is the main power element that carries current. It is located in the upper chip and is fabricated on the same layer as the first sensing MOS 11. Its conduction state is controlled by the corresponding gate. The first sensing MOS 11 and the first power MOS 10 share a gate to generate a sensing current proportional to the current of the first power MOS 10. It has a small area and reflects the magnitude of the main current in a proportional manner. The metal pillar 512 of the first power MOS source leads the source of the first power MOS 10 vertically from the inside of the chip to the package surface, providing a low-impedance high-current conduction path, reducing on-resistance and parasitic inductance, which is beneficial for high-current operation and heat dissipation. The first sensing electrode is led out by the metal post 511, which leads out the sensing electrode of the first sensing MOS 11 for external current sensing or control circuit to read the signal. The sensing path is independent of the power path, reducing noise coupling and improving measurement accuracy.

[0045] In the cross-sectional structure of the second chip, the second power MOS 20 is configured back-to-back with the first power MOS 10 for conduction control in the other current direction, forming a bidirectional switching structure together with the first power MOS 10. The second sensing MOS 21 corresponds to the current sensing element of the second power MOS 20 and is used to detect current in the reverse or second direction. The source lead-out metal pillar 522 of the second power MOS leads the source of the second power MOS 20 to the outside of the package via a vertical metal pillar, symmetrically configured with the source 101 of the first power MOS, so that the bidirectional current path impedance is consistent. The second sensing electrode lead-out metal pillar 521 leads out the sensing signal of the second sensing MOS 21 and corresponds to the first sensing electrode 311, which can simultaneously monitor forward and reverse current, enhancing the protection and control functions of the system.

[0046] like Figure 4 As shown, two power MOS chips are vertically stacked, with metal pillars used to lead out electrodes for efficient electrical connection and thermal management. The first power MOS 10 of the first chip and the second power MOS 20 of the second chip are vertically stacked and connected through the conductive adhesive 40. For electrical connection, a dedicated metal pillar structure is used, including metal pillars 512 and 513 leading out the source and gate of the first power MOS, and metal pillars 522 and 523 leading out the source and gate of the second power MOS. The gate pillars 513 and 523 lead out the gates of the first and second power MOS, respectively, and are responsible for transmitting control signals to control the switching state of the MOS chips. The source pillars 512 and 522 lead out the source of the first and second power MOS, respectively, and are responsible for transmitting the main current.

[0047] Finally, the entire structure is completely enclosed by the package housing 30 to provide necessary mechanical support, environmental isolation, and protection. This package uses metal pillars as electrode leads, replacing the traditional wire bonding connection method. Using metal pillars reduces resistance and inductance; the metal pillars have a larger cross-sectional area and shorter connection length, significantly reducing resistance (R_DS(on)) and parasitic inductance. The metal pillars connect to the top and bottom of the package, allowing heat to be conducted away from both sides of the chip simultaneously, achieving double-sided heat dissipation. This provides higher heat dissipation than traditional single-sided heat dissipation packages, thereby improving the module's continuous operating current and reliability.

[0048] Please see Figure 5 , Figure 5 This is a flowchart illustrating the manufacturing method of the package structure for a current-sensing power MOSFET.

[0049] like Figure 5 As shown, the present invention also provides a method for manufacturing a package structure of a current-sensing power MOSFET, comprising the following steps: designing the area ratio of the sensing MOSFET to the power MOSFET; performing monolithic wafer manufacturing to integrate the sensing MOSFET and the power MOSFET into a single chip; performing back-side thinning on the chip; stacking the two chips back-to-back; re-layouting the wiring of the package structure, and completing the overall packaging. In the monolithic wafer manufacturing, the sensing MOSFET and the power MOSFET share a gate drive signal.

[0050] While various embodiments of the invention have been described above, it should be understood that these are presented by way of example only and not as limiting. Therefore, the scope of the invention should not be limited to the above embodiments, but should be defined solely by the claims and their equivalents.

Claims

1. A package structure for a current-sensing power MOSFET, characterized in that, include: At least one first power MOS and at least one first sensing MOS, wherein the first power MOS and the first sensing MOS are integrated on a first substrate and share a first gate drive signal; At least one second power MOS and at least one second sensing MOS, wherein the second power MOS and the second sensing MOS are integrated on a second substrate and share a second gate drive signal; A first chip integrating the first power MOS and the first sensing MOS and a second chip integrating the second power MOS and the second sensing MOS are stacked back to back and connected by conductive adhesive. The bottom electrode of the package structure is rewired to the top layer to achieve the integration of current monitoring and bidirectional switching power MOS.

2. The packaging structure according to claim 1, characterized in that, The substrate of the first substrate and the second substrate is a silicon-based, carbon-based, gallium nitride, or gallium arsenide substrate.

3. The packaging structure according to claim 1, characterized in that, The first power MOS, the first sensing MOS, the second power MOS and the second sensing MOS are trench MOS or planar MOS.

4. The packaging structure according to claim 1, characterized in that, The first sensing MOS and the second sensing MOS are located on the side of the first power MOS and the second power MOS, or the first power MOS and the second power MOS surround the first sensing MOS and the second sensing MOS.

5. The packaging structure according to claim 1, characterized in that, The packaging structure also includes a packaging shell, and the bottom electrode is connected to the top layer through lead-out metal pillars.

6. The packaging structure according to claim 5, characterized in that, The metal pillars include a first sensing electrode lead-out metal pillar, a first power MOS source lead-out metal pillar, a second sensing electrode lead-out metal pillar, a second power MOS source lead-out metal pillar, a first power MOS gate lead-out metal pillar, and a second power MOS gate lead-out metal pillar.

7. The packaging structure according to claim 6, characterized in that, The first sensing electrode lead-out metal post and the second sensing electrode lead-out metal post are square or round electrodes.

8. The packaging structure according to claim 6, characterized in that, The locations of the metal pillars leading out from the first sensing electrode and the metal pillars leading out from the second sensing electrode are not limited to the chip edge.

9. A method for manufacturing a package structure of a current-sensing power MOSFET, characterized in that, Includes the following steps: Design the area ratio of the sensing MOSFET to the power MOSFET; Monolithic wafer fabrication integrates sensing MOS and power MOS into a single chip; The chip undergoes a back-side thinning process; The two chips are stacked back-to-back, one on top of the other. The packaging structure is re-laid out and the wiring is rearranged to complete the overall packaging.

10. The manufacturing method according to claim 9, characterized in that, In the monolithic wafer manufacturing process, the sensing MOS and the power MOS share the same gate drive signal.

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