Semiconductor device and manufacturing method thereof, electronic device

Abstract

The application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof and an electronic device, which comprises a semiconductor substrate, a plurality of channels vertically stacked above the semiconductor substrate, a gate stack structure arranged around the channels, source / drain regions arranged on both sides of the channels, and a first interlayer arranged between the channels and the source / drain regions, wherein the first interlayer and the channels are made of different types of semiconductor materials, and the mobility of the semiconductor material of the first interlayer is higher than that of the semiconductor material of the channels. The first interlayer made of high-mobility material is arranged between the channels and the source / drain regions, which effectively improves the carrier mobility of the extension region, reduces the series resistance, and optimizes the carrier transport effect. In addition, by adjusting the strain characteristics of the first interlayer, the stress can be effectively transmitted to the nanosheet or nanowire channel, the carrier mobility of the channel is improved, and the driving performance of the transistor is significantly enhanced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] As integrated circuit manufacturing processes continue to evolve towards advanced technology nodes of 3nm and below, traditional dual-gate or triple-gate FinFET transistors, limited by physical size and gate control capabilities, can no longer meet the requirements for device miniaturization. Nano-gate-around-the-ring (GAAFET) transistors and three-dimensional complementary field-effect transistors (CFETs), highly compatible with mainstream high-k metal-gate FinFET processes, have become the core device structures for next-generation integrated circuits thanks to their horizontally stacked nanosheet (NS) channel structures.

[0003] In the horizontal Si-NS channel fabrication process, SiGe, acting as a sacrificial layer, exerts biaxial tensile stress on the channel. Simultaneously, the inner sidewall structure results in numerous defects in the source / drain epitaxial SiGe structure. This significantly weakens the compressive stress effect of the source / drain on the channel. Furthermore, as the NS channel is released, the tensile stress within the channel is also released, making it difficult to effectively improve the driving performance of the gate-all-around transistor (GAW). Therefore, developing novel GAW structures and device performance enhancement technologies is of great significance in advanced technology nodes and CFET device structures.

[0004] To address the aforementioned technical problem of insufficient channel stress, existing technologies propose two solutions: The first approach involves continuously optimizing the epitaxial quality of the source / drain to obtain greater channel compressive or tensile stress. However, due to the difference in growth location, dislocation lines still exist, and the source / drain and channel have stresses of the same polarity.

[0005] The second approach involves thinning the NS channel thickness after channel release and epitaxially forming an extremely thin SiGe layer to create a channel structure where SiGe encapsulates Si NS. This approach utilizes lattice mismatch characteristics to increase channel stress, but the SiGe layer also introduces severe interface state problems.

[0006] It is evident that existing improvement schemes either cause serious interface state problems or are limited by the difference in growth location, resulting in the continued existence of dislocation lines. Furthermore, the source / drain and channel have stresses of the same polarity, making it impossible to simultaneously achieve efficient and stable channel stress enhancement and excellent device electrical performance.

[0007] In view of this, the present invention is proposed. Summary of the Invention

[0008] The purpose of this invention is to provide a semiconductor device in which a first intercalation layer made of a high mobility material is disposed between the channel and the source / drain region, which effectively improves the carrier mobility in the extended region, reduces the series resistance, and optimizes the carrier transport effect.

[0009] In a first aspect, the present invention provides a semiconductor device, including a semiconductor substrate; Multiple channels are vertically stacked above the semiconductor substrate; A gate stack structure is disposed around the channel; Source / drain areas are located on both sides of the channel; A first intercalation layer is provided between the channel and the source / drain region. Both the first intercalation layer and the channel are semiconductor materials, and the mobility of the semiconductor material in the first intercalation layer is higher than that in the channel semiconductor material.

[0010] As a preferred embodiment of this technical solution, the first intercalation layer and the channel are made of different types of semiconductor materials, and there is a heterogeneous material interface between the first intercalation layer and the channel and the source / drain regions.

[0011] As a preferred embodiment of this technical solution, the width of the first intercalation layer is 1-10 nm along the length of the channel.

[0012] As a preferred embodiment of this technical solution, the material of the first intercalation layer includes any one of the following: multi-component silicon-germanium material, silicon carbide, strained silicon, strained silicon-germanium, strained germanium, gallium arsenide, indium arsenide, diamond, silicene, and graphene.

[0013] In a preferred embodiment of this technical solution, the source / drain regions are made of heavily doped semiconductor materials, and the channel is made of lightly doped semiconductor materials; The doping elements in the source / drain regions are group III or group V elements.

[0014] As a preferred embodiment of this technical solution, the material of the source / drain region includes any one of silicon, silicon-germanium, germanium, and silicon carbide; The channel is made of any one of silicon, silicon germanium, and germanium.

[0015] In a preferred embodiment of this technical solution, an inner wall is provided between the gate stack structure and the source / drain region, and the outer surface of the inner wall is flush with the outer surface of the first intercalation layer.

[0016] In a second aspect, the present invention provides a stacked semiconductor device, the stacked semiconductor device including a first transistor and a second transistor stacked together, the first transistor including the aforementioned semiconductor device, the second transistor including the aforementioned semiconductor device, and an isolation structure provided between the first transistor and the second transistor.

[0017] As a preferred embodiment of this technical solution, the first transistor is an N-type transistor and the second transistor is a P-type transistor; or the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0018] Thirdly, the present invention also provides a method for manufacturing the above-mentioned semiconductor device, comprising the following steps: Provide semiconductor substrates; Fin stacks consisting of a channel layer and a channel sacrificial layer are epitaxially grown on a semiconductor substrate. A false gate and outer wall are formed on the exposed surface of the fin stack. Using the false gate and outer wall as a mask, the fin stack is patterned to form multiple nanosheets or nanowire channels. The two ends of the nanosheet or the nanowire channel are etched back. High-mobility semiconductor materials are epitaxially or deposited at both ends of the nanosheet or nanowire channel after the etch-back process to form a first intercalation layer; A source / drain region is formed on the side of the first intercalation layer away from the nanosheet or the nanowire channel; Remove the dummy gate and release the nanosheet / nanowire channel to form a gate trench; An alternative gate stack structure is formed in the gate trench.

[0019] As a preferred embodiment of this technical solution, the back-etching process at both ends of the nanosheet or the nanowire channel includes: A selective etching process is used to etch back the two ends of the channel and the semiconductor substrate in a directional manner, forming a first concave structure at the two ends of the channel and a second concave structure on the semiconductor substrate.

[0020] As a preferred embodiment of this technical solution, the epitaxial or deposition of high-mobility semiconductor material at both ends of the nanosheet or nanowire channel after etch-back includes: The surfaces of the first and second concave structures are pretreated to remove the oxide layer and surface impurities. High-mobility semiconductor materials are grown in the first and second concave structures using selective epitaxy or thin film deposition processes. Annealing process is performed to form the first intercalation layer and the second intercalation layer.

[0021] As a preferred embodiment of this technical solution, forming a source / drain region on the side of the first intercalation layer opposite to the nanosheet or the nanowire channel includes: Semiconductor material is grown on the outside of the first intercalation layer using epitaxial or thin film deposition processes to form a source / drain precursor layer that is in close contact with the first intercalation layer. Heavy doping is achieved by incorporating group III or group V elements into the source / drain precursor layer using ion implantation or in-situ doping processes. Annealing activates the doped impurities, completing the source / drain region preparation.

[0022] Fourthly, the present invention also discloses the above-mentioned semiconductor device, or an electronic device including the above-mentioned stacked semiconductor device; the electronic device includes a smartphone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank.

[0023] The semiconductor device of the present invention has at least the following beneficial effects: 1. The present invention sets a first intercalation layer made of high mobility material between the channel and the source / drain region, which can significantly reduce the series resistance of the connection region between the source / drain region and the channel, reduce the scattering and loss of charge carriers in the transition region, improve the carrier transport efficiency from the path level, and improve the core electrical parameters such as device on resistance and switching characteristics. 2. This invention precisely controls the tensile / compressive strain of the first intercalation layer by adjusting the lattice mismatch, growth process, and annealing conditions of the high-mobility material. The stress is then stably transferred to the nanosheet / nanowire channel through interfacial interactions. Under stress, the channel lattice structure is optimized, significantly improving channel carrier mobility, effectively increasing transistor drive current, enhancing device driving capability, and effectively compensating for performance degradation caused by short-channel effects and interfacial scattering in advanced processes. Furthermore, this strain control method is flexible and controllable, allowing for matching corresponding strain types to different PMOS and NMOS device requirements, thus adapting to diverse device designs. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a top view of the semiconductor device of the present invention; Figure 2 These are two cutting methods for the semiconductor device of the present invention in the X-X' direction; Figure 3 This is a schematic cross-sectional view of the semiconductor device of the present invention along the Y1-Y1' direction; Figure 4 This is a schematic cross-sectional view of the semiconductor device of the present invention in the Y2-Y2' direction; Figure 5This is a schematic X-X' cross-sectional view of the stacked structure formed on the semiconductor substrate according to the present invention; Figure 6 This is a schematic diagram of the X-X' cross-section of the sidewall transfer process of the present invention; Figure 7 This is a Y-Y' cross-sectional schematic diagram of the sidewall transfer process of the present invention; Figure 8 This is a schematic diagram of the Y-Y' cross-section of the fin stacking structure formed in this invention; Figure 9 This is a schematic diagram of the Y-Y' cross-section of the shallow trench isolation zone formed in this invention; Figure 10 This is a schematic diagram of the X-X' cross-section after the dummy gate stack deposition and patterning of the present invention; Figure 11 This is a schematic diagram of the Y-Y' cross-section after the dummy gate stack deposition and patterning of the present invention; Figure 12 This is a schematic diagram of the X-X' section after the outer wall of the present invention has been formed; Figure 13 This is a schematic diagram of the X-X' cross-section after etching the fin stack of the source / drain region according to the present invention; Figure 14 This is a schematic diagram of the X-X' cross-section after etching the transverse grooves on the inner wall in this invention; Figure 15 This is a schematic diagram of the X-X' section after the inner wall of the present invention has been formed; Figure 16 This is a schematic X-X' cross-sectional view of the present invention after the formation of the first concave structure and the second concave structure. Figure 17 This is a schematic X-X' cross-sectional view of the present invention after the formation of the first and second intercalation layers; Figure 18 This is a schematic diagram of the X-X' cross-section after the epitaxial growth of the source / drain region in this invention; Figure 19 This is a schematic diagram of the X-X' cross-section after the isolation layer medium is deposited on the source / drain region and planarized according to the present invention; Figure 20 This is a schematic diagram of the X-X' cross-section after removing the dummy gate in this invention; Figure 21 This is a schematic diagram of the Y-Y' cross-section after removing the dummy gate in this invention; Figure 22 This is a schematic diagram of the X-X' cross-section after the formation of the gate trench through nanosheet channel release in this invention; Figure 23 This is a schematic diagram of the Y-Y' cross-section after the formation of the gate trench through nanosheet channel release in this invention; Figure 24This is a schematic diagram of the X-X' cross-section after the metal grid has been formed according to the present invention; Figure 25 This is a schematic diagram of the X-X' cross-section after the metal grid has been planarized according to the present invention; Figure 26 This is a schematic diagram of the X-X' cross-section after the deposition and planarization of the isolation medium of the present invention. Figure 27 This is a schematic diagram of the X-X' cross-section after the frontal contact and interconnection of the present invention; Figure 28 This is a schematic diagram of the X-X' cross-section after back-side contact and interconnection of the present invention.

[0026] Explanation of reference numerals in the attached figures: 1: Semiconductor substrate; 2: Channel; 3: Gate; 4: Source / drain region; 5: First intercalation layer; 6: Second intercalation layer; 7: Channel layer; 8: Channel sacrificial layer; 9: Shallow trench isolation region; 10: Dummy gate layer; 11: Outer wall; 12: Inner wall. Detailed Implementation

[0027] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0028] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0029] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0031] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0032] Existing gate-all-around transistor devices generally suffer from insufficient channel stress. Existing improvement schemes either cause serious interface state problems or are limited by the difference in growth location, resulting in the continued existence of dislocation lines. Furthermore, the source / drain and the channel have stresses of the same polarity, making it impossible to simultaneously achieve efficient and stable channel stress enhancement and excellent device electrical performance.

[0033] To solve the above problems, such as Figure 1-4 As shown, this invention proposes a semiconductor device in which a first intercalation layer is disposed between the channel and the source / drain regions. The semiconductor material in the first intercalation layer has a higher mobility than the semiconductor material in the channel. By placing a high-mobility semiconductor material between the channel and the source / drain regions, this invention significantly reduces the series resistance of the source / drain-channel junction region, reduces carrier scattering and loss in the transition region, improves carrier transport efficiency at the path level, and enhances core electrical parameters such as on-resistance and switching characteristics. Therefore, this invention achieves efficient and stable channel stress enhancement without introducing new interface defects, significantly improving the device's electrical performance.

[0034] Furthermore, by controlling the lattice mismatch, growth process, and annealing conditions of the first intercalated high-mobility material, this invention can precisely control the tensile / compressive strain of the first intercalation layer and stably transfer stress to the nanosheet / nanowire channel through interfacial interactions. Under stress, the channel lattice structure is optimized, significantly improving channel carrier mobility, effectively increasing transistor drive current, enhancing device driving capability, and effectively compensating for performance degradation caused by short-channel effects and interfacial scattering in advanced processes.

[0035] Meanwhile, the strain control method of the first intercalation layer in this invention is flexible and controllable, and can match the corresponding strain type according to the different device requirements of PMOS and NMOS, adapting to diverse device designs. For example, for NMOS devices, materials with low lattice constants such as SiC, silicon-doped carbon, and III-V group materials (gallium arsenide, indium arsenide) can be selected to prepare the first intercalation layer, transferring tensile stress to the channel, reducing the effective electron mass and improving electron mobility; for PMOS devices, materials with high lattice constants such as silicon-germanium alloys are selected, and the compressive stress intensity is precisely controlled by adjusting the germanium composition to improve hole mobility. At the same time, auxiliary methods such as film thickness, annealing, and crystal plane are combined to achieve fine control of stress magnitude and transfer efficiency. The strain control method of this invention breaks away from the limitations of traditional strain structures, is flexible in design and compatible with processes, and can be fully adapted to single transistors and stacked CMOS devices.

[0036] In a first aspect, embodiments of the present invention provide a semiconductor device, including a semiconductor substrate 1, a plurality of nanosheets or nanowire channels 2, a gate stack structure, and source / drain regions 4, wherein the plurality of nanosheets or nanowire channels 2 are vertically stacked above the semiconductor substrate 1; and the gate stack structure is disposed around the channels 2, and the source / drain regions 4 are disposed on both sides of the channels 2.

[0037] Specifically, such as Figure 1-4 As shown, a first intercalation layer 5 is disposed between multiple nanosheets or nanowire channels 2 and the source / drain region 4. Both the first intercalation layer 5 and the channel 2 are semiconductor materials, and the mobility of the semiconductor material in the first intercalation layer 5 is higher than that in the channel 2. That is, the two ends of the multiple nanosheets or nanowire channels 2 of the present invention are not in direct contact with the source / drain region 4, but are provided with a first intercalation layer 5 formed by deposition or epitaxy of a high-mobility semiconductor. By forming the first intercalation layer 5 with a high-mobility material, the carrier mobility of the extended region between the channel 2 and the source / drain region 4 is effectively enhanced without causing serious interface state problems, thereby improving the core electrical parameters such as device on-resistance and switching characteristics.

[0038] Based on the above technical solution, it should be noted that the first intercalation layer 5 of this invention can be formed between the channel 2 and the source / drain region 4 by epitaxy or deposition. Therefore, the first intercalation layer 5 and the channel 2 can be on the same crystal plane or on different crystal planes. When epitaxial growth is used, the first intercalation layer 5 and the channel 2 have the same crystal plane orientation, and their atomic arrangement crystal orientation and crystal plane are completely consistent. In this case, the difference in lattice constant between the epitaxial layer of the first intercalation layer 5 and the substrate of the channel 2 can be used to output stable tensile or compressive stress, thereby matching the requirements of NMOS and PMOS devices and improving electron mobility or hole mobility. When deposition growth is used, the first intercalation layer 5 and the channel 2 have different crystal plane orientations. In this case, the difference in lattice constant between the epitaxial layer of the first intercalation layer 5 and the substrate of the channel 2, as well as the difference in atomic density of different crystal planes, can be used to generate stress. The synergistic effect of these two variables can significantly improve the stress control dimension and utilization efficiency, meeting the customized needs of ultra-high performance devices. Both modes can be flexibly selected to fully adapt to different levels of advanced gate-to-ring semiconductor devices.

[0039] The present invention does not strictly limit the width of the first intercalation layer 5. For example, the width of the first intercalation layer 5 along the length direction of the channel 2 can be any value between 1 and 10 nm.

[0040] Regarding the material of the first intercalation layer 5, the material of the first intercalation layer of the present invention is a semiconductor material of a different type from that of the channel, preferably a semiconductor material with a higher mobility than the channel 2 material, for example, including but not limited to any one of multi-component silicon germanium material, silicon carbide, strained silicon, strained silicon germanium, strained germanium, gallium arsenide, indium arsenide, diamond, silicene and graphene.

[0041] Based on the above, it should be noted that because the material of the first intercalation layer of the present invention is a semiconductor material of a different type than that of the channel, there is a heterogeneous material interface between the first intercalation layer and the channel, source / drain regions.

[0042] In some embodiments of the present invention, for NMOS devices, the first intercalation layer 5 can be prepared using materials with low lattice constants such as SiC, silicon doped carbon, or III-V group materials (gallium arsenide, indium arsenide) to transfer tensile stress to the channel 2, thereby reducing the effective electron mass and improving electron mobility; for PMOS devices, the first intercalation layer 5 can be prepared using materials with high lattice constants such as silicon-germanium alloys, and the compressive stress intensity can be precisely controlled by adjusting the germanium composition to improve hole mobility.

[0043] Regarding the source / drain region 4, the material of the source / drain region 4 of the present invention includes any one of silicon, silicon-germanium, germanium, and silicon carbide, and is preferably heavily doped, for example, the doping concentration can be 1e17~1e22 cm⁻¹. -3 Any value between.

[0044] The specific doping elements of the source / drain region 4 are either group III or group V elements. Group III elements include boron (B), aluminum (Al), gallium (Ga), indium (In), etc., while group V elements include phosphorus (P), arsenic (As), antimony (Sb), etc.

[0045] In some embodiments of the present invention, for PMOS devices, the source / drain region 4 is mainly doped with group III elements, such as boron (B), aluminum (Al), gallium (Ga), indium (In), etc.; for NOMS devices, the source / drain region 4 is mainly doped with group V elements, such as phosphorus (P), arsenic (As), antimony (Sb), etc.

[0046] Regarding the channel 2, the material of the channel 2 in this invention includes any one of silicon, silicon-germanium, and germanium, and is preferably lightly doped, for example, the doping concentration can be 1e17~1e22 cm⁻¹. -3 Any value between.

[0047] Similarly, the specific doping elements of channel 2 are either group III elements or group V elements. Among them, group III elements include boron (B), aluminum (Al), gallium (Ga), indium (In), etc., and group V elements include phosphorus (P), arsenic (As), antimony (Sb), etc.

[0048] In some embodiments of the present invention, for PMOS devices, channel 2 is mainly doped with group III elements, such as boron (B), aluminum (Al), gallium (Ga), indium (In), etc.; for NOMS devices, channel 2 is mainly doped with group V elements, such as phosphorus (P), arsenic (As), antimony (Sb), etc.

[0049] Based on the above technical solution, an inner wall 12 is also provided between the gate 3 stack structure and the source / drain region 4, and the outer surface of the inner wall 12 is flush with the outer surface of the first intercalation layer 5.

[0050] Secondly, this embodiment provides a stacked semiconductor device, including a first transistor and a second transistor stacked together. Both the first transistor and the second transistor include the semiconductor device of the first aspect of the present invention, and an isolation structure is provided between the first transistor and the second transistor.

[0051] In this configuration, the first transistor is an N-type transistor and the second transistor is a P-type transistor; or the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0052] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0053] Thirdly, this embodiment provides a method for fabricating a semiconductor device. The structure of the semiconductor device formed by the fabrication method provided in the third aspect of this embodiment is the same as the structure of the semiconductor device provided in the first aspect. Therefore, the beneficial effects of the third aspect and its various implementations in this embodiment can be analyzed with reference to the beneficial effects in the first aspect and its various implementations, and will not be repeated here.

[0054] The following will be based on Figure 5-28 The cross-sectional view shown illustrates the manufacturing process. Specifically, the method for fabricating this semiconductor device includes the following steps: First, such as Figure 5 As shown, a stacked structure consisting of a channel layer 7 and a channel sacrificial layer 8 is epitaxially grown on a semiconductor substrate 1.

[0055] Specifically, the semiconductor substrate 1 can be a substrate made of any semiconductor material such as silicon, germanium silicon, or germanium, or a substrate made of insulating material such as silicon oxide or ceramic. The embodiments of the present invention do not specifically limit the structure and material of the semiconductor substrate 1, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention. The channel sacrificial layer 8 is generally made of SiGe, and the channel layer 7 is generally made of Si. Both the channel sacrificial layer 8 and the channel layer 7 are superlattice structures. The Si layer determines the number of subsequent nanowires. The number of Si layers is ≥1, and each layer is less than 30nm. The final thickness directly determines the height of the nanosheet / nanowire channel and the electrical performance.

[0056] Next, as Figure 6-9 As shown, the stacked structure is selectively etched back through the sidewall transfer process to form a fin stacked structure; then a shallow groove isolation area 9 is formed between two adjacent fins.

[0057] Specifically, firstly, a hard mask layer is deposited above the topmost channel layer 7. After patterning, the epitaxially grown superlattice stack is etched into multiple periodically distributed fins. The etching stops at or below the substrate. Then, an insulating dielectric material is deposited and planarized to expose the hard mask layer. The hard mask layer is then removed by wet or dry etching. The insulating dielectric material is then selectively etched back to expose the three-dimensional fin stack structure. Shallow trench isolation regions 9 are formed between adjacent fin stacks.

[0058] Next, as Figure 10-15 As shown, a dummy gate 10 is formed on the exposed fin surface. Sidewall media are deposited on both sides of the dummy gate 10 and anisotropic etching is performed to form an outer wall 11. Using the dummy gate 10 and the outer wall 11 as a mask, the fin stack structure is etched to form a channel stack. The sacrificial layer 8 of the channel is laterally etched to form a groove, and an inner sidewall 12 is formed in the groove.

[0059] Specifically, such as Figure 10-11 As shown, a gate dielectric oxide layer and a dummy gate layer 10 are sequentially deposited above the shallow trench isolation region 9, and CMP is performed. Then, a dummy gate hard mask layer is deposited. The material of the dummy gate layer 10 is polycrystalline silicon or amorphous silicon. The material of the dummy gate hard mask layer can be oxide, carbide, organic matter, etc., and the present invention does not strictly limit it. Furthermore, anisotropic etching of amorphous or polycrystalline dummy gates is performed and stopped at the top of the fin stack. After etching, the dummy gate hard mask layer above the dummy gate structure is retained. Furthermore, such as Figure 12 As shown, outer wall dielectrics are deposited on both sides of the dummy gate structure, and then the horizontal outer wall dielectrics are etched to retain only the dielectrics of the dummy gate and the hard mask layer sidewalls, forming outer wall 11. The material of the outer wall 11 dielectric can be silicon nitride, nitrogen-doped silicon oxide, nitrogen-doped silicon carbide, etc., and the present invention does not strictly limit it. Furthermore, such as Figure 13 As shown, the fin stack in source / drain region 4 is etched to form a channel stack; Furthermore, such as Figure 14 As shown, the channel sacrificial layer 8 of the fin is selectively etched isotropically and precisely in the center direction of the source / drain region 4 to form a groove; Furthermore, such as Figure 15 As shown, an inner sidewall medium is deposited and etched to form an inner sidewall 12. The material of the inner sidewall medium can be silicon nitride, nitrogen-doped silicon oxide, nitrogen-doped silicon carbide, etc., and the present invention does not strictly limit it. Next, as Figure 16 As shown, a selective etching process is used to etch back the two ends of the channel 2 and the semiconductor substrate 1 in a directional manner, forming a first concave structure with a certain depth at the two ends of the channel 2, and forming a second concave structure with a certain height on the semiconductor substrate 1. The height of the second concave structure is the same as the depth of the first concave structure, for example, it can be any value between 1-10nm.

[0060] Next, as Figure 17 As shown, a high-mobility semiconductor material is epitaxially or deposited at both ends of the nanosheet or nanowire channel 2 after the etch is performed to form the first intercalation layer 5.

[0061] Specifically, the surfaces of the first concave structure and the second concave structure are pretreated to remove the oxide layer and surface impurities; Furthermore, a high-mobility semiconductor material is grown in the first and second concave structures using selective epitaxy or thin film deposition processes. It should be noted that the first intercalation layer 5 and the second intercalation layer 6 are made of the same material, which is a high-mobility semiconductor material. The second intercalation layer 6 will be further etched away after the wafer is flipped.

[0062] Next, as Figure 18 As shown, a source / drain region 4 is formed on the side of the first intercalation layer 5 away from the nanosheet or nanowire channel 2.

[0063] Specifically, an epitaxial or thin film deposition process is used to grow a semiconductor material on the outside of the first intercalation layer 5 to form a source / drain precursor layer that is in close contact with the first intercalation layer 5. Heavy doping is achieved by incorporating group III or group V elements into the source / drain precursor layer using ion implantation or in-situ doping processes. Annealing activates doped impurities, completing the preparation of source / drain regions 4. At the same time, it increases the strain characteristics of locally high-mobility semiconductor materials and transfers stress to the channel.

[0064] This invention uses a high-mobility semiconductor material as the first intercalation layer, and then epitaxially extends a bulk source / drain region. The bulk source / drain region is used to apply stress to the first intercalation layer, and further promotes the transmission of the first intercalation stress into the channel, which can significantly enhance the driving characteristics of advanced logic devices such as GAA / CFET.

[0065] Next, as Figure 19-23 As shown, an isolation dielectric layer is deposited and planarized; the dummy gate layer 10 is removed, and the nanosheet / nanowire channel 2 is released to form the gate 3 trench.

[0066] Specifically, such as Figure 19 As shown, a layer of isolation medium is deposited and planarized. Furthermore, such as Figure 20-21 As shown, the aforementioned dummy gate layer 10 and dummy gate oxide layer formed by polycrystalline silicon or amorphous silicon are removed by selective etching or etching processes. Furthermore, such as Figure 22-23 As shown, selective etching is used to release the channel sacrificial layer 8 in the superlattice stack, thereby releasing the nanosheet / nanowire channel 2 and forming a gate trench between the channel layers 7.

[0067] Next, a high-k dielectric layer (not shown in the figure) is deposited on the surface of the nanosheet / nanowire channel 2; further, a work function layer (not shown in the figure) is deposited on the high-k dielectric layer; further, a metal gate layer is filled and CMP is performed to form a metal gate surrounding the channel layer 7, as shown in the figure. Figure 25 As shown.

[0068] For P-type transistors, the work function layer is P-WFL, and for N-type transistors, the work function layer is N-WFL.

[0069] In addition, a barrier layer (not shown in the figure) is deposited between the high-k dielectric layer and the work function layer to prevent the metal gate and the work function layer from diffusing into each other and to stabilize the interface.

[0070] Therefore, it can be seen that after the inner sidewall process of the GAA device is formed, the present invention adopts the technical solution of back etching and selective epitaxial first intercalation, which is fully compatible with the mainstream gate-around transistor integration technology and can apply channel stress, which is beneficial to the mass production of the application industry.

[0071] Finally, as Figure 26-28 As shown, further processes such as metal gate planarization, dielectric deposition, front contact and interconnection, and back contact and interconnection are carried out to realize the electrical connection between various parts inside the device and between the device and external circuits, so as to transmit the electrical signals of the device to the required places and build a complete integrated circuit system. This part of the process can refer to the existing technology and will not be described in detail here.

[0072] Fourthly, this embodiment provides an electronic device including the above-mentioned semiconductor devices, including smartphones, personal computers, tablet computers, artificial intelligence devices, wearable devices, or power banks.

[0073] The beneficial effects of the fourth aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0074] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that layers and regions of desired shapes can be formed using various technical means. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, Including semiconductor substrates; Multiple channels are vertically stacked above the semiconductor substrate; A gate stack structure is disposed around the channel; Source / drain areas are located on both sides of the channel; A first intercalation layer is provided between the channel and the source / drain region. Both the first intercalation layer and the channel are semiconductor materials, and the mobility of the semiconductor material in the first intercalation layer is higher than that in the channel semiconductor material.

2. The semiconductor device according to claim 1, characterized in that, The first intercalation layer and the channel are made of different types of semiconductor materials, and there is a heterogeneous material interface between the first intercalation layer and the channel and the source / drain regions.

3. The semiconductor device according to claim 1, characterized in that, The width of the first intercalation layer is 1-10 nm along the length of the channel.

4. The semiconductor device according to claim 1, characterized in that, The material of the first intercalation layer includes any one of the following: multi-component silicon-germanium material, silicon carbide, strained silicon, strained silicon-germanium, strained germanium, gallium arsenide, indium arsenide, diamond, silicene, and graphene.

5. The semiconductor device according to claim 1, characterized in that, The source / drain regions are made of heavily doped semiconductor material, and the channel is made of lightly doped semiconductor material; The doping elements in the source / drain regions are group III or group V elements.

6. The semiconductor device according to claim 1, characterized in that, The source / drain region is made of any one of silicon, silicon germanium, germanium, and silicon carbide; The channel is made of any one of silicon, silicon germanium, and germanium.

7. The semiconductor device according to claim 1, characterized in that, An inner wall is provided between the gate stack structure and the source / drain region, and the outer surface of the inner wall is flush with the outer surface of the first intercalation layer.

8. A stacked semiconductor device, characterized in that, The device includes a first transistor and a second transistor stacked together, the first transistor comprising a semiconductor device according to any one of claims 1-7, the second transistor comprising a semiconductor device according to any one of claims 1-7, and an isolation structure provided between the first transistor and the second transistor.

9. The stacked semiconductor device according to claim 8, characterized in that, The first transistor is an N-type transistor, and the second transistor is a P-type transistor; Alternatively, the first transistor may be a P-type transistor and the second transistor may be an N-type transistor.

10. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: Provide semiconductor substrates; Fin stacks consisting of a channel layer and a channel sacrificial layer are epitaxially grown on a semiconductor substrate. A false gate and outer wall are formed on the exposed surface of the fin stack. Using the false gate and outer wall as a mask, the fin stack is patterned to form multiple nanosheets or nanowire channels. The two ends of the nanosheet or the nanowire channel are etched back. High-mobility semiconductor materials are epitaxially or deposited at both ends of the nanosheet or nanowire channel after the etch-back process to form a first intercalation layer; A source / drain region is formed on the side of the first intercalation layer away from the nanosheet or the nanowire channel; Remove the dummy gate and release the nanosheet / nanowire channel to form a gate trench; An alternative gate stack structure is formed in the gate trench.

11. The manufacturing method according to claim 10, characterized in that, The step of etching back the two ends of the nanosheet or the nanowire channel includes: A selective etching process is used to etch back the two ends of the channel and the semiconductor substrate in a directional manner, forming a first concave structure at the two ends of the channel and a second concave structure on the semiconductor substrate.

12. The manufacturing method according to claim 11, characterized in that, The epitaxial or deposition of high-mobility semiconductor material at both ends of the nanosheet or nanowire channel after etch-back includes: The surfaces of the first and second concave structures are pretreated to remove the oxide layer and surface impurities. High-mobility semiconductor materials are grown in the first and second concave structures using selective epitaxy or thin film deposition processes. Annealing process is performed to form the first intercalation layer and the second intercalation layer.

13. The manufacturing method according to claim 10, characterized in that, The step of forming a source / drain region on the side of the first intercalation layer opposite to the nanosheet or the nanowire channel includes: Semiconductor material is grown on the outside of the first intercalation layer using epitaxial or thin film deposition processes to form a source / drain precursor layer that is in close contact with the first intercalation layer. Heavy doping is achieved by incorporating group III or group V elements into the source / drain precursor layer using ion implantation or in-situ doping processes. Annealing activates the doped impurities, completing the source / drain region preparation.

14. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 1-7, or includes the stacked semiconductor device according to claim 8 or 9; The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

Images