Thin film transistor substrate and display device comprising the same

Abstract

A thin film transistor substrate is provided, which includes a substrate, a first thin film transistor over the substrate, and a second thin film transistor over the substrate, wherein the first thin film transistor includes a first active layer including a first channel region, a first gate insulating layer over the first active layer, a first gate over the first gate insulating layer, a first source connected to the first active layer, and a first drain spaced apart from the first source and connected to the first active layer, the second thin film transistor includes a layer of a conductive material over the substrate, a first buffer layer over the layer of the conductive material, a second active layer including a second channel region over the first buffer layer, a second gate insulating layer over the second active layer, a second gate over the second gate insulating layer, a second source connected to the second active layer, and a second drain spaced apart from the second source and connected to the second active layer, and the layer of the conductive material is connected to the second source and overlaps with the second channel region. Further, a display device including the thin film transistor substrate is provided.

Description

[0001] Cross-references to related applications

[0002] This application is a divisional application of Chinese Patent Application No. 202210607527.5, filed on May 31, 2022, entitled "Thin Film Transistor Substrate and Display Device Including the Thin Film Transistor Substrate".

[0003] The original application claims the benefit of Korean Patent Application No. 10-2021-0075690, filed on June 10, 2021, which is incorporated herein by reference as fully set forth herein. Technical Field

[0004] This disclosure relates to a thin-film transistor substrate and a display device comprising the thin-film transistor substrate. Background Technology

[0005] Transistors are widely used as switching or driving devices in the field of electronic devices. Specifically, because thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching devices in display devices such as liquid crystal displays or organic light-emitting diodes.

[0006] For example, a display device may include a switching thin-film transistor (TFT) and a driving TFT. Typically, it is advantageous for the switching TFT to have a smaller s-factor to improve switching characteristics, while the driving TFT has a larger s-factor to represent grayscale.

[0007] However, because thin-film transistors typically have a small s-factor to ensure switching characteristics, they are difficult to represent grayscale when used as driving thin-film transistors in display devices.

[0008] Therefore, thin-film transistors with large s-factors are needed to easily represent grayscale by driving thin-film transistors applied to display devices. Summary of the Invention

[0009] This disclosure is made in view of the above-mentioned problems, and one object of this disclosure is to provide a thin-film transistor substrate including a thin-film transistor having a large s-factor.

[0010] Another object of this disclosure is to provide a thin-film transistor designed to have a large s-factor by including a conductive material layer disposed between a substrate and an active layer and connected to a source, and a thin-film transistor substrate containing the thin-film transistor.

[0011] Another object of this disclosure is to provide a thin-film transistor substrate comprising a first thin-film transistor having a relatively small s-factor and a second thin-film transistor having a relatively large s-factor.

[0012] Another object of this disclosure is to provide a display device that has excellent grayscale performance by including a driving thin-film transistor with a large s-factor.

[0013] In addition to the purposes of this disclosure as stated above, those skilled in the art will clearly understand other purposes and features of this disclosure through the following description.

[0014] According to one aspect of this disclosure, the above and other objectives can be achieved by providing a thin-film transistor substrate comprising: a substrate; a first thin-film transistor on the substrate; and a second thin-film transistor on the substrate, wherein the first thin-film transistor includes a first active layer having a first channel portion, a first gate insulating layer on the first active layer, a first gate on the first gate insulating layer, a first source connected to the first active layer, and a first drain spaced apart from and connected to the first active layer; the second thin-film transistor includes a conductive material layer on the substrate, a first buffer layer on the conductive material layer, a second active layer having a second channel portion on the first buffer layer, a second gate insulating layer on the second active layer, a second gate on the second gate insulating layer, a second source connected to the second active layer, and a second drain spaced apart from and connected to the second active layer, wherein the conductive material layer is connected to the second source and overlaps with the second channel portion.

[0015] The s-factor of the second thin-film transistor is greater than that of the first thin-film transistor.

[0016] The conductive material layer can have light-shielding properties.

[0017] The conductive material layer does not overlap with the first channel portion.

[0018] The first buffer layer can be disposed between the substrate and the first active layer, and between the substrate and the second active layer.

[0019] The first buffer layer can have a thickness of 50 nm to 300 nm.

[0020] The thickness of the second gate insulating layer can be 0.75 to 5 times the thickness of the first buffer layer.

[0021] The first buffer layer may include a hydrogen barrier layer on a conductive material layer and a buffer insulating layer on the hydrogen barrier layer.

[0022] The hydrogen barrier layer may contain silicon nitride (SiN) x ).

[0023] The hydrogen barrier layer can have a thickness of 10 nm to 100 nm.

[0024] The first gate insulating layer and the second gate insulating layer have the same thickness.

[0025] The first gate insulating layer and the second gate insulating layer can be formed integrally.

[0026] At least one of the first gate insulating layer or the second gate insulating layer may include a gate insulating portion and an interface layer on the gate insulating portion, and the interface layer may be configured to be closer to either the first channel portion or the second channel portion than the gate insulating portion.

[0027] The interface layer can be formed by metal-organic chemical vapor deposition (MOCVD).

[0028] The interface layer may contain silicon oxide (SiO2). x ), silicon nitride (SiN) x ( ) or at least one of metal oxides.

[0029] The interface layer may contain SiO2.

[0030] The interface layer can have a thickness of 1 nm to 10 nm.

[0031] The thin-film transistor substrate may further include a first pad layer disposed between the substrate and the first buffer layer and overlapping the first channel portion.

[0032] The first pad layer does not overlap with the second channel.

[0033] The first pad layer can have both electrical conductivity and light-shielding properties.

[0034] The first pad layer can be connected to the first gate.

[0035] The thin-film transistor substrate may further include a second buffer layer disposed between the substrate and the first buffer layer.

[0036] A conductive material layer is disposed between the first buffer layer and the second buffer layer.

[0037] The first pad layer can be disposed between the substrate and the second buffer layer.

[0038] The first pad layer can be connected to the first source.

[0039] The first pad layer can be connected to the first gate.

[0040] The first pad layer can be set between the first buffer layer and the second buffer layer.

[0041] The first pad layer can be connected to the first gate.

[0042] At least one of the first active layer or the second active layer may contain an oxide semiconductor material.

[0043] The oxide semiconductor material may include at least one of the following: IZO (InZnO) based, IGO (InGaO) based, ITO (InSnO) based, IGZO (InGaZnO) based, IGZTO (InGaZnSnO) based, GZTO (GaZnSnO) based, GZO (GaZnO) based, ITZO (InSnZnO) based, or FIZO (FeInZnO) based oxide semiconductor materials.

[0044] At least one of the first active layer or the second active layer may include a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0045] At least one of the first active layer or the second active layer may further include a third oxide semiconductor layer on the second oxide semiconductor layer.

[0046] According to another aspect of this disclosure, the above and other objectives can be achieved by providing a display device comprising a thin-film transistor substrate and a display element connected to a second thin-film transistor on the thin-film transistor substrate.

[0047] Display elements may include organic light-emitting diodes (OLEDs). Attached Figure Description

[0048] The above and other objects, features, and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A and Figure 1B This shows a cross-sectional view of a thin-film transistor substrate according to an embodiment of the present disclosure; Figure 2A and Figure 2B This shows a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure; Figure 3A and Figure 3B This is a cross-sectional view of a thin-film transistor substrate according to yet another embodiment of the present disclosure; Figure 4 This is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure; Figure 5 This is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure; Figure 6 This is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure; Figure 7 This is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure; Figures 8A to 8E It is a graph showing the threshold voltage of a thin-film transistor; Figure 9A and Figure 9B It is a graph showing the threshold voltage of a thin-film transistor; Figure 10 This is a graph showing the relationship between the S-factor and the thickness ratio of the first buffer layer and the gate insulating layer; Figure 11A and Figure 11B This is a schematic diagram illustrating the effective gate voltage of a first thin-film transistor according to an embodiment of the present disclosure; Figure 12A and Figure 12B This is a schematic diagram illustrating the effective gate voltage of a second thin-film transistor according to an embodiment of the present disclosure; Figure 13A and Figure 13B This is a schematic diagram illustrating the effective gate voltage of a first thin-film transistor according to another embodiment of the present disclosure; Figure 14 This is a schematic diagram illustrating a display device according to another embodiment of the present disclosure; Figure 15 It shows Figure 14 The circuit diagram of any one pixel; Figure 16 It shows Figure 15 A planar image of pixels; Figure 17 It is along Figure 16 A cross-sectional view taken from line I-I'; Figure 18 This is a plan view showing any pixel of a display device according to another embodiment of the present disclosure; Figure 19 It is along Figure 18 A cross-sectional view taken from line II-II'; Figure 20 It is along Figure 18 A cross-sectional view taken from line III-III'; Figure 21 This is a plan view showing any pixel of a display device according to yet another embodiment of the present disclosure; Figure 22 It is along Figure 21 A cross-sectional view taken from line IV-IV'; Figure 23 It is along Figure 21 A cross-sectional view of the line V-V'; Figure 24 This is a plan view showing any pixel of a display device according to another embodiment of the present disclosure; Figure 25 It is along Figure 24 A cross-sectional view taken from line VI-VI'; Figure 26 It is along Figure 24 A cross-sectional view taken from line VII-VII'; Figure 27 This is a circuit diagram showing any pixel of a display device according to another embodiment of the present disclosure; and Figure 28 This is a circuit diagram showing any pixel of a display device according to another embodiment of the present disclosure. Detailed Implementation

[0049] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be complete and fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0050] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details illustrated. Throughout the specification, similar reference numerals refer to similar elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions unnecessarily obscure the essential points of this disclosure.

[0051] When using the terms "including," "having," and "comprising" as described in this specification, another component may be added unless "only..." is used. Singular terms may include plural forms unless the opposite is mentioned.

[0052] When interpreting a component, even without an explicit description, the component is interpreted as including a range of error.

[0053] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "next to," one or more parts can be set between two parts, unless "only" or "directly" is used.

[0054] This document uses spatially related terms such as “below,” “under,” “below,” “above,” and “on top” to readily describe the relationship between one or more elements and another element or other elements as shown in the accompanying drawings. It should be understood that these terms are intended to encompass different orientations of the device, in addition to those shown in the drawings. For example, if the device shown in the drawings is flipped, a device described as being “below” or “below” another device may be being “on top” of that other device. Thus, the exemplary term “below” or “below” can include both “below” and “on top” orientations. Similarly, the exemplary term “on top” or “above” can include both “on top” and “below” orientations.

[0055] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases can be included unless “only” or “directly” is used.

[0056] It should be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the invention.

[0057] The term "at least one" should be understood to include any or all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third items" means a combination of two or more of the first, second, and third items, as well as all items derived from the first, second, or third item.

[0058] Features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interact and be technically driven differently from each other, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other, or may be performed together in a mutually dependent manner.

[0059] In the accompanying drawings, the same or similar elements are indicated by the same reference numerals, even if they are shown in different drawings.

[0060] In the embodiments of this disclosure, for ease of description, the source and drain are distinguished from each other. However, the source and drain can be used interchangeably. A source can be a drain, and a drain can be a source. Furthermore, a source in any embodiment of this disclosure can be a drain in another embodiment of this disclosure, and a drain in any embodiment of this disclosure can be a source in another embodiment of this disclosure.

[0061] In the embodiments of this disclosure, the source and drain are not limited as described above. In any embodiment of this disclosure, the source region can be a source, and in any embodiment of this disclosure, the drain region can be a drain. In any embodiment of this disclosure, the source region can be a drain, and in any embodiment of this disclosure, the drain region can be a source.

[0062] Figure 1A and Figure 1B This is a cross-sectional view of a thin-film transistor substrate 100 according to an embodiment of the present disclosure.

[0063] According to one embodiment of the present disclosure, a thin-film transistor substrate 100 includes a substrate 110, a first thin-film transistor TR1 on the substrate 110, and a second thin-film transistor TR2 on the substrate 110.

[0064] The first thin-film transistor TR1 includes a first active layer A1 having a first channel portion 131, a first gate insulating layer GI1 on the first active layer A1, a first gate G1 on the first gate insulating layer GI1, a first source S1 connected to the first active layer A1, and a first drain D1 spaced apart from the first source S1 and connected to the first active layer A1.

[0065] The second thin-film transistor TR2 includes a conductive material layer 215 on a substrate 110, a first buffer layer 120 on the conductive material layer 215, a second active layer A2 having a second channel portion 231 on the first buffer layer 120, a second gate insulating layer GI2 on the second active layer A2, a second gate G2 on the second gate insulating layer GI2, a second source S2 connected to the second active layer A2, and a second drain D2 spaced apart from the second source S2 and connected to the second active layer A2.

[0066] In the second thin-film transistor TR2, the conductive material layer 215 is connected to the second source S2 and overlaps with the second channel portion 231.

[0067] The second thin-film transistor TR2, having a conductive material layer 215 overlapping with the second channel portion 231 and connected to the second source S2, has a greater s-factor than the first thin-film transistor TR1. The second thin-film transistor TR2 can be used as a driving thin-film transistor for a display device.

[0068] In the following text, reference will be made to Figure 1A and Figure 1B A thin-film transistor substrate 100 according to an embodiment of the present disclosure will be described in more detail.

[0069] The substrate 110 can be formed using glass or plastic. A transparent plastic with flexible properties (e.g., polyimide) can be used to form the substrate 110. When polyimide is used as the substrate 110, a heat-resistant polyimide capable of withstanding high temperatures can be used.

[0070] A conductive material layer 215 is disposed on the substrate 110. The conductive material layer 215 overlaps with the second channel portion 231.

[0071] The conductive material layer 215 is conductive. The conductive material layer 215 may contain at least one of the following: aluminum-based metals such as aluminum (Al) or aluminum alloys; silver-based metals such as silver (Ag) or silver alloys; copper-based metals such as copper (Cu) or copper alloys; molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); titanium (Ti); or iron (Fe). The conductive material layer 215 may have a multilayer structure comprising at least two conductive material layers with different physical properties from each other.

[0072] According to one embodiment of this disclosure, the conductive material layer 215 is connected to the second source S2. Therefore, the voltage applied to the conductive material layer 215 can be the same as that applied to the second source S2.

[0073] According to one embodiment of this disclosure, the conductive material layer 215 overlaps with the second channel portion 231. When the same voltage as the second source S2 is applied to the conductive material layer 215, the conductive material layer 215 can influence the electrical characteristics of the second channel portion 231. Due to the influence of the conductive material layer 215 on the electrical characteristics, the influence of the electric field applied to the second channel portion 231 by the second gate G2 can be reduced.

[0074] According to one embodiment of this disclosure, the conductive material layer 215 does not overlap with the first channel portion 131. Therefore, the voltage applied to the conductive material layer 215 will not directly affect the first channel portion 131 and the first active layer A1.

[0075] According to one embodiment of this disclosure, the conductive material layer 215 may have light-shielding properties. Therefore, the conductive material layer 215 can be used as a light-shielding layer. The conductive material layer 215 can block light incident on the substrate 110 to protect the second channel portion 231 and the second active layer A2.

[0076] A first buffer layer 120 is disposed on the conductive material layer 215. The first buffer layer 120 may contain at least one of silicon oxide, silicon nitride, or metal-based oxide. According to one embodiment of the present disclosure, the first buffer layer 120 may contain at least one of silicon oxide or silicon nitride. The first buffer layer 120 may have a single-layer structure or may have a multi-layer structure.

[0077] The first buffer layer 120 protects the first active layer A1 and the second active layer A2. In addition, the first buffer layer 120 can keep the surface of the upper part of the substrate 110 uniform.

[0078] The first buffer layer 120 separates the conductive material layer 215 and the second channel portion 231 from each other.

[0079] According to one embodiment of this disclosure, a first buffer layer 120 may be disposed between the substrate 110 and the first active layer A1, and between the substrate 110 and the second active layer A2. (See reference...) Figure 1A and Figure 1B The first buffer layer 120 can be disposed on the entire surface of the substrate 110. The conductive material layer 215 and the second channel portion 231 are spaced apart from each other and insulated from each other by the first buffer layer 120.

[0080] According to one embodiment of the present disclosure, the first buffer layer 120 may have a thickness t1 of 50 nm to 300 nm. According to one embodiment of the present disclosure, the thickness t1 of the first buffer layer 120 is defined as the distance between the upper surface of the conductive material layer 215 and the lower surface of the second channel portion 231.

[0081] When the thickness t1 of the first buffer layer 120 is less than 50 nm, the first buffer layer 120 may not be able to prevent hydrogen (H) or oxygen (O) from penetrating into the first thin-film transistor TR1 and the second thin-film transistor TR2, thereby potentially degrading the function of the first thin-film transistor TR1 and the second thin-film transistor TR2. For example, when the thickness t1 of the first buffer layer 120 is less than 50 nm, the first channel portion 131 and the second channel portion 231 become conductive due to hydrogen (H) penetrating from the outside of the first thin-film transistor TR1 and the second thin-film transistor TR2, thereby potentially causing the transistor function of the first thin-film transistor TR1 and the second thin-film transistor TR2 to be lost.

[0082] When the thickness t1 of the first buffer layer 120 exceeds 300 nm, the distance between the conductive material layer 215 and the second channel portion 231 may increase, thereby making the capacitance Cap between the conductive material layer 215 and the second channel portion 231 very small. Therefore, even if the same voltage as the second source S2 is applied to the conductive material layer 215, the influence of the conductive material layer 215 on the electrical characteristics of the second channel portion 231 may be very small. When the influence of the conductive material layer 215 on the electrical characteristics of the second channel portion 231 decreases, the effect of reducing the electric field applied to the second channel portion 231 by the second gate G2 is almost negligible.

[0083] The first active layer A1 and the second active layer A2 are disposed on the first buffer layer 120.

[0084] The first active layer A1 and the second active layer A2 can be formed of semiconductor materials. The first active layer A1 of the first thin-film transistor TR1 can have the same or different composition as the second active layer A2 of the second thin-film transistor TR2. For example, the first active layer A1 and the second active layer A2 can contain one of amorphous silicon semiconductor materials, polycrystalline silicon semiconductor materials, and oxide semiconductor materials.

[0085] According to one embodiment of this disclosure, at least one of the first active layer A1 or the second active layer A2 may comprise an oxide semiconductor material. For example, the oxide semiconductor material may include at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, or FIZO (FeInZnO)-based oxide semiconductor materials, but one embodiment of this disclosure is not limited thereto. The first active layer A1 and the second active layer A2 may be made of other oxide semiconductor materials known in the art.

[0086] The first active layer A1 may include a first channel portion 131, a first conductor portion 132, and a second conductor portion 133. The first channel portion 131 overlaps with the first gate G1. The first conductor portion 132 and the second conductor portion 133 of the first active layer A1 do not overlap with the first gate G1. The first conductor portion 132 and the second conductor portion 133 may be formed by selectively conductiveizing a semiconductor material.

[0087] According to one embodiment of this disclosure, the first conductor portion 132 of the first active layer A1 can be a source region, and the second conductor portion 133 can be a drain region. According to one embodiment of this disclosure, the first conductor portion 132 can be called the source, and the second conductor portion 133 can be called the drain, but this is not a limitation of one embodiment of this disclosure. The first conductor portion 132 can be a drain region, and the second conductor portion 133 can be a source region. Furthermore, the first conductor portion 132 can be called the drain, and the second conductor portion 133 can be called the source.

[0088] The second active layer A2 may include a second channel portion 231, a first conductor portion 232, and a second conductor portion 233. The second channel portion 231 overlaps with the second gate G2. The first conductor portion 232 and the second conductor portion 233 of the second active layer A2 do not overlap with the second gate G2. The first conductor portion 232 and the second conductor portion 233 may be formed by selectively conductiveizing a semiconductor material.

[0089] According to one embodiment of this disclosure, the first conductor portion 232 of the second active layer A2 can be a source region, and the second conductor portion 233 can be a drain region. According to one embodiment of this disclosure, the first conductor portion 232 can be called the source, and the second conductor portion 233 can be called the drain, but this is not a limitation of one embodiment of this disclosure. The first conductor portion 232 can be a drain region, and the second conductor portion 233 can be a source region. Furthermore, the first conductor portion 232 can be called the drain, and the second conductor portion 233 can be called the source.

[0090] A first gate insulating layer GI1 is disposed on a first active layer A1, and a second gate insulating layer GI2 is disposed on a second active layer A2. More specifically, the first gate insulating layer GI1 is disposed on a first channel portion 131, and the second gate insulating layer GI2 is disposed on a second channel portion 231. The first gate insulating layer GI1 and the second gate insulating layer GI2 can be formed with separate patterns to distinguish them from each other. Figure 1B ), and can be formed as one entity without being distinguishable from each other ( Figure 1A ).

[0091] Each of the first gate insulating layer GI1 and the second gate insulating layer GI2 may comprise at least one of silicon oxide, silicon nitride, or metal-based oxide. Each of the first gate insulating layer GI1 and the second gate insulating layer GI2 may have a single-layer structure or a multi-layer structure.

[0092] The first gate insulating layer GI1 of the first thin-film transistor TR1 and the second gate insulating layer GI2 of the second thin-film transistor TR2 can have the same composition and can be formed by the same process. According to one embodiment of this disclosure, the thickness t21 of the first gate insulating layer GI1 and the thickness t22 of the second gate insulating layer GI2 can be the same as each other.

[0093] refer to Figure 1A The first gate insulating layer GI1 and the second gate insulating layer GI2 can be integrally formed on the entire surface of the substrate 110 without patterning. Because Figure 1A The first gate insulating layer GI1 and the second gate insulating layer GI2 are integrally formed, so the first gate insulating layer GI1 and the second gate insulating layer GI2 can be collectively referred to as gate insulating layer 140.

[0094] refer to Figure 1B The first gate insulating layer GI1 and the second gate insulating layer GI2 can be formed separately through patterning. Figure 1B In the thin-film transistor shown, the thickness t21 of the first gate insulating layer GI1 and the thickness t22 of the second gate insulating layer GI2 can be the same as each other (t21 = t22).

[0095] The first gate insulating layer GI1 and the second gate insulating layer GI2 respectively protect the first channel portion 131 and the second channel portion 231.

[0096] The first gate G1 of the first thin-film transistor TR1 is disposed on the first gate insulating layer GI1. The first gate G1 overlaps with the first channel portion 131 of the first active layer A1.

[0097] The second gate G2 of the second thin-film transistor TR2 is disposed on the second gate insulating layer GI2. The second gate G2 overlaps with the second channel portion 231 of the second active layer A2.

[0098] Each of the first gate G1 and the second gate G2 may contain at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), or titanium (Ti). The first gate G1 and the second gate G2 may have a multilayer structure comprising at least two conductive material layers with different physical properties from each other.

[0099] An interlayer insulating layer 160 is disposed on the first gate G1 and the second gate G2. The interlayer insulating layer 160 is an insulating layer made of insulating material. The interlayer insulating layer 160 can be made of organic material, or it can be made of inorganic material, or it can be made of a stacked structure of organic and inorganic layers.

[0100] The first source S1, the first drain D1, the second source S2, and the second drain D2 are disposed on the interlayer insulating layer 160.

[0101] The first source electrode S1 is connected to the first active layer A1 through a contact hole. The first drain electrode D1 is spaced apart from the first source electrode S1 and is connected to the first active layer A1 through a contact hole.

[0102] The second source electrode S2 is connected to the second active layer A2 through a contact hole. The second drain electrode D2 is spaced apart from the second source electrode S2 and is connected to the second active layer A2 through a contact hole.

[0103] Each of the first source S1, the first drain D1, the second source S2, and the second drain D2 may contain at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Each of the first source S1, the first drain D1, the second source S2, and the second drain D2 may be formed as a single layer of metal or alloy thereof, or may be formed as a multilayer of two or more layers.

[0104] refer to Figure 1A and Figure 1BThe bridging portion 171 may be disposed on the interlayer insulating layer 160. The bridging portion 171 is connected to the second source S2. The bridging portion 171 may extend from the second source S2, and a portion of the second source S2 may be the bridging portion 171.

[0105] The bridging portion 171 is connected to the conductive material layer 215 through the contact hole H21. The contact hole H21 is formed to pass through the interlayer insulating layer 160 and the first buffer layer 120.

[0106] The second source S2 of the second thin-film transistor TR2 and the conductive material layer 215 can be connected to each other through the bridging part 171.

[0107] When the first conductor portion 132 of the first active layer A1 is used as the first source and the second conductor portion 133 is used as the first drain, the first source S1 and the first drain D1 on the interlayer insulating layer 160 can be omitted.

[0108] Furthermore, when the first conductor portion 232 of the second active layer A2 is used as the second drain and the second conductor portion 233 is used as the second source, the second source S2 and the second drain D2 on the interlayer insulating layer 160 can be omitted. In this case, the second source S2 on the interlayer insulating layer 160 can be part of the bridging portion 171.

[0109] refer to Figure 1A and Figure 1B The bridging portion 171 can connect the second conductor portion 233 of the second active layer A2 to the conductive material layer 215 through the two contact holes H21 and H22. When the second conductor portion 233 of the second active layer A2 is used as the second drain, the bridging portion 171 can connect the conductive material layer 215 to the second drain through the two contact holes H21 and H22.

[0110] According to one embodiment of this disclosure, the s-factor of a second thin-film transistor TR2 having a conductive material layer 215 connected to a second source S2 is greater than the s-factor of a first thin-film transistor TR1.

[0111] The s factor will be described in detail below.

[0112] The s-factor (subthreshold swing) is defined as the inverse of the slope of the drain-source current curve relative to the gate voltage in the drain-source current curves of thin-film transistors TR1 and TR2 near the threshold voltage Vth. For example, the s-factor can be an indicator of the magnitude of the change in drain-source current relative to the gate voltage near the threshold voltage Vth of thin-film transistors TR1 and TR2.

[0113] As the s-factor increases, the drain-source current I relative to the gate voltage near the threshold voltage Vth increases. DS The rate of change slows down.

[0114] For example, the s-factor can be obtained through Figures 8A to 8E The current variation diagram shown is used to describe this. Figures 8A to 8E These are graphs showing the threshold voltage of the thin-film transistor. Specifically, Figures 8A to 8E It shows the relationship with gate voltage V GS Drain-source current I DS .exist Figures 8A to 8E The curve shown is near the threshold voltage Vth, relative to the gate voltage V. GS Drain-source current I DS The reciprocal of the curve is the s-factor. A steeper slope results in a smaller s-factor, while a gentler slope results in a larger s-factor. A larger s-factor corresponds to a larger drain-source current I relative to the gate voltage near the threshold voltage Vth. DS The rate of change is relatively slow.

[0115] As the s-factor increases, the drain-source current I relative to the gate voltage increases near the threshold voltage Vth. DS The rate of change slows down, making it easier to adjust the gate voltage V. GS Adjusting the drain-source current I DS Size.

[0116] In current-driven display devices, such as organic light-emitting display devices, the drain-source current I of the driving thin-film transistor can be adjusted. DS The size of the pixel controls its grayscale. The drain-source current Id of the thin-film transistor is driven by this. DS The value of s is determined by the gate voltage. Therefore, in an organic light-emitting display device driven by current, as the s-factor of the driving TFT increases, it becomes easier to adjust the grayscale of the pixel.

[0117] According to one embodiment of this disclosure, since the conductive material layer 215 overlaps with the second channel portion 231, when the same voltage as the second source S2 is applied to the conductive material layer 215, the conductive material layer 215 can influence the electrical characteristics of the second channel portion 231. Due to the influence of the conductive material layer 215 on the electrical characteristics, the influence of the electric field applied to the second channel portion 231 by the second gate G2 can be reduced. Therefore, the s-factor of the second thin-film transistor TR2, which includes the conductive material layer 215, can be greater than the s-factor of the first thin-film transistor TR1, which does not include the conductive material layer 215.

[0118] The effect of the conductive material layer 215 on the s-factor of the second thin-film transistor TR2 can be achieved through... Figure 11A , Figure 11B , Figure 12A and Figure 12B To describe.

[0119] Figure 11A and Figure 11B This illustrates the effective gate voltage V of the first thin-film transistor TR1 according to an embodiment of the present disclosure. eff A schematic diagram.

[0120] Figure 11A This schematically illustrates the effect of gate voltage V GS The capacitance Cap that can be generated when applied to the first thin-film transistor TR1. Gate voltage V. GS It is the voltage between the first source S1 and the first gate G1. Figure 11A The diagram schematically illustrates the capacitance relationship Cap at a voltage near the threshold voltage Vth before the first thin-film transistor TR1 is fully turned on.

[0121] like Figure 11A As shown, when the gate voltage V GS When applied to the first thin-film transistor TR1, a capacitance C can be formed between the first channel portion 131 of the first active layer A1 and the first gate G1. GI1 Furthermore, a capacitor C can be formed between the first channel portion 131 and the first source S1. CH .

[0122] according to Figure 11A The relationship between voltage and capacitance can be expressed as follows: Figure 11B As shown. Reference Figure 11B Due to the capacitance C between the first channel portion 131 and the first source S1 CH The gate voltage V applied between the first source S1 and the first gate G1 GS It may not be applied between the first channel portion 131 and the first gate G1. Therefore, voltage loss may occur.

[0123] refer to Figure 11B The voltage applied between the first channel portion 131 and the first gate G1 during the driving of the first thin-film transistor TR1 is called the effective gate voltage V. eff At that time, the effective gate voltage V eff It can be obtained through Equation 1 below.

[0124] [Formula 1]

[0125] V eff = [C GI1 / (C GI1 + C CH )] × V GS

[0126] Figure 12A and Figure 12BThis illustrates the effective gate voltage V of the second thin-film transistor TR2 according to an embodiment of the present disclosure. eff A schematic diagram.

[0127] Figure 12A This schematically illustrates the effect of gate voltage V GS The capacitance Cap that can be generated when applied to the second thin-film transistor TR2. Figure 12A The diagram schematically illustrates the capacitance relationship Cap at a voltage near the threshold voltage Vth before the second thin-film transistor TR2 is fully turned on.

[0128] like Figure 12A As shown, when the gate voltage V GS When applied to the second thin-film transistor TR2, a capacitance C can be formed between the second channel portion 231 of the second active layer A2 and the second gate G2. GI2 A capacitor C can be formed between the second channel portion 231 and the second source S2. CH A capacitor C can also be formed between the second channel portion 231 and the conductive material layer 215. BUF .exist Figure 12A and Figure 12B In the figure, since the conductive material layer 215 can be used as a light-shielding layer, the reference numeral for the conductive material layer 215 can be LS (light-shielding layer).

[0129] according to Figure 12A The relationship between voltage and capacitance Cap can be expressed as follows: Figure 12B As shown. Reference Figure 12B Due to the capacitance C between the second channel portion 231 and the second source S2 CH and the capacitance C between the second channel portion 231 and the conductive material layer 215 BUF The gate voltage V applied between the second source S2 and the second gate G2 GS It may not be applied between the second channel portion 231 and the second gate G2. Therefore, voltage loss may occur.

[0130] According to one embodiment of this disclosure, the conductive material layer 215 and the second source S2 are electrically connected to each other. Therefore, an additional capacitance C is generated between the second channel portion 231 and the conductive material layer 215. BUF This results in an increase in the capacitance Cap at the lower part of the second channel section 231, which causes voltage loss (C). CH +C BUF Therefore, refer to Figure 12B The voltage applied between the second channel 231 and the second gate G2 during the driving of the second thin-film transistor TR2 is called the effective gate voltage V. eff At that time, the effective gate voltage V effIt can be obtained through Equation 2 below.

[0131] [Equation 2]

[0132] V eff = [C GI2 / (C GI2 + C CH + C BUF )] × V GS

[0133] Referring to Equation 2, the denominator of Equation 2 is due to the capacitance C between the second channel portion 231 and the conductive material layer 215. BUF And thus, the effective gate voltage V increases. eff The reduction is greater than the actual gate voltage V applied between the second source S2 and the second gate G2. GS The decrease in voltage. Therefore, when the same voltage is applied, the drain-source current I of the second thin-film transistor TR2 decreases. DS The drain-source current I of the first thin-film transistor TR1 is less than DS And the drain-source current I DS The changes were also relatively small.

[0134] Thus, due to the drain-source current I of the second thin-film transistor TR2 DS The change is less than that of the first thin-film transistor TR1, so the s-factor of the second thin-film transistor TR2 is greater than that of the first thin-film transistor TR1.

[0135] According to one embodiment of this disclosure, the second channel portion 231 and the conductive material layer 215 are spaced apart when the first buffer layer 120 is inserted between them. Therefore, as the thickness of the first buffer layer 120 increases, the distance between the conductive material layer 215 and the second channel portion 231 increases, thereby increasing the capacitance C between the second channel portion 231 and the conductive material layer 215. BUF The capacitance C between the second channel portion 231 and the conductive material layer 215 decreases. BUF When the value is reduced, the s-factor of the second thin-film transistor TR2 will decrease.

[0136] Therefore, in order to make the s-factor of the second thin-film transistor TR2 have a relatively large value, the first buffer layer 120 can have a thickness less than or equal to a predetermined value. According to one embodiment of this disclosure, the first buffer layer 120 can have a thickness t1 of less than 300 nm. When the thickness t1 of the first buffer layer 120 exceeds 300 nm, the distance between the conductive material layer 215 and the second channel portion 231 may increase, thereby increasing the capacitance C between the conductive material layer 215 and the second channel portion 231. BUFIt may become very small. Therefore, the s-factor of the second thin-film transistor TR2 may become small.

[0137] As described above, when the thickness t1 of the first buffer layer 120 is less than 50 nm, the function of the first buffer layer 120 in blocking hydrogen (H) or oxygen (O) may be degraded, thereby the first channel portion 131 and the second channel portion 231 may be damaged or become conductive.

[0138] Therefore, according to one embodiment of this disclosure, the first buffer layer 120 may have a thickness t1 of 50 nm to 300 nm. More specifically, the first buffer layer 120 may have a thickness t1 of 50 nm to 250 nm, a thickness t1 of 80 nm to 250 nm, a thickness t1 of 80 nm to 200 nm, a thickness t1 of 100 nm to 200 nm, or a thickness t1 of 120 nm to 300 nm.

[0139] Referring to Equation 2, when driving the second thin-film transistor TR2, the effective gate voltage V eff Capacitance C between the second channel portion 231 and the second gate G2 GI2 The impact of this. Furthermore, the capacitance C between the second channel portion 231 and the second gate G2. GI2 The thickness t22 of the second gate insulating layer GI2 is affected.

[0140] According to one embodiment of this disclosure, the thickness of the second gate insulating layer GI2 can be 0.75 to 5 times the thickness of the first buffer layer 120, so that the second thin-film transistor TR2 has a large s-factor, while simultaneously turning on and off current flow. For example, the thickness t1 of the first buffer layer 120 and the thickness t22 of the second gate insulating layer GI2 can satisfy the following Equation 3.

[0141] [Formula 3]

[0142] 0.75 ≤ t22 / t1 ≤ 5

[0143] When the thickness t22 of the second gate insulating layer GI2 is less than 0.75 times the thickness t1 of the first buffer layer 120 (0.75 > t22 / t1), most of the gate voltage V GS The effect of the conductive material layer 215 is reduced when the second channel portion 231 is applied between the second gate G2 and the second gate G2, thereby the slope of the threshold voltage map may increase and the s factor of the second thin film transistor TR2 may decrease.

[0144] On the other hand, when the thickness t22 of the second gate insulating layer GI2 exceeds 5 times the thickness t1 of the first buffer layer 120 (t22 / t1 > 5), the s-factor of the second thin-film transistor TR2 may become too large. When the s-factor of the second thin-film transistor TR2 becomes too large, it may consume too much power to drive the second thin-film transistor TR2.

[0145] According to one embodiment of this disclosure, the thickness of the second gate insulating layer GI2 may be 1 to 3.5 times or 1.5 to 3 times the thickness of the first buffer layer 120.

[0146] According to one embodiment of this disclosure, for example, the second thin-film transistor TR2 may have an s-factor of 0.28 or higher. When the second thin-film transistor TR2 has an s-factor of 0.28 or higher, the grayscale of the pixel can be easily adjusted.

[0147] According to one embodiment of this disclosure, considering the ease of grayscale adjustment, the second thin-film transistor TR2 can have an s-factor of 0.3 or higher. When the s-factor of the second thin-film transistor TR2 becomes too large, the power consumption required to drive the second thin-film transistor TR2 increases. Considering these characteristics, the s-factor of the second thin-film transistor TR2 according to one embodiment of this disclosure can be in the range of 0.3 to 0.7. Therefore, the second thin-film transistor TR2 can be used as a driving transistor in a display device.

[0148] On the other hand, the s-factor of the first thin-film transistor TR1 is smaller than that of the second thin-film transistor TR2. The first thin-film transistor TR1, with its smaller s-factor, exhibits excellent switching characteristics. Therefore, the first thin-film transistor TR1 can be used as a switching transistor in a display device.

[0149] Figure 2A and 2B This is a cross-sectional view of a thin-film transistor substrate 200 according to another embodiment of the present disclosure. In the following, descriptions of already described elements will be omitted to avoid redundancy.

[0150] refer to Figure 2A The first buffer layer 120 may have a multilayer structure. When the first buffer layer 120 is thin, the first channel portion 131 and the second channel portion 231 become conductive due to the influence of hydrogen (H) present in the insulating layer, etc., which may cause the first thin film transistor TR1 and the second thin film transistor TR2 to lose their transistor function.

[0151] To prevent the first channel portion 131 and the second channel portion 231 from becoming conductive, the first buffer layer 120 may include a hydrogen barrier layer 122. The hydrogen barrier layer 122 may be disposed on the conductive material layer 215.

[0152] Specifically, in a thin-film transistor substrate 200 according to another embodiment of the present disclosure, the first buffer layer 120 may include a hydrogen barrier layer 122 on the conductive material layer 215 and a buffer insulating layer 121 on the hydrogen barrier layer 122. Hydrogen (H) is blocked by the hydrogen barrier layer 122, thereby effectively preventing the first channel portion 131 and the second channel portion 231 from becoming conductive.

[0153] Hydrogen barrier layer 122 may contain silicon nitride (SiN) x Silicon nitride (SiN) x It is considered to be a material with excellent hydrogen (H) blocking ability.

[0154] Considering the film stability and electrical insulation properties of the first buffer layer 120, the hydrogen barrier layer 122 can have a thickness of 10 nm to 100 nm. When the thickness of the hydrogen barrier layer 122 is less than 10 nm, the hydrogen barrier capability may deteriorate. When the thickness of the hydrogen barrier layer 122 exceeds 100 nm, the thickness of the buffer insulation layer 121 becomes relatively small, thereby potentially deteriorating the film stability and electrical insulation properties of the first buffer layer 120.

[0155] The buffer insulating layer 121 can be used to improve the film stability and electrical insulation properties of the first buffer layer 120. The buffer insulating layer 121 may contain silicon oxide (SiO2). x The buffer insulating layer 121 can have a thickness of 40 nm to 250 nm. When the thickness of the buffer insulating layer 121 is less than 40 nm, the film stability and electrical insulation properties of the first buffer layer 120 may deteriorate; when the thickness of the buffer insulating layer 121 exceeds 250 nm, the thickness of the first buffer layer 120 may be greater than the necessary thickness. The buffer insulating layer 121 can have a thickness of 40 nm to 250 nm.

[0156] When the first buffer layer 120 includes a hydrogen barrier layer 122 and a buffer insulating layer 121, even if the first buffer layer 120 has a thickness t1 of about 50 nm, it can effectively prevent the first channel portion 131 and the second channel portion 231 from becoming conductive, and the first buffer layer 120 can have excellent film stability and electrical insulation properties.

[0157] refer to Figure 2AThe first gate insulating layer GI1 and the second gate insulating layer GI2 are integrally formed. According to another embodiment of this disclosure, the first gate insulating layer GI1 and the second gate insulating layer GI2 can be collectively referred to as gate insulating layer 140. According to another embodiment of this disclosure, the gate insulating layer 140 can be disposed on the entire surface of the substrate 110. In this case, the first gate insulating layer GI1 and the second gate insulating layer GI2 do not need to be distinguished from each other. For convenience, the gate insulating layer 140 between the first channel portion 131 and the first gate G1 is referred to as the first gate insulating layer GI1, and the gate insulating layer 140 between the second channel portion 231 and the second gate G2 is referred to as the second gate insulating layer GI2.

[0158] refer to Figure 2A Since the first gate insulating layer GI1 and the second gate insulating layer GI2 are integrally formed, the thickness t21 of the first gate insulating layer GI1 and the thickness t22 of the second gate insulating layer GI2 are the same (t21 = t22).

[0159] According to another embodiment of this disclosure, at least one of the first gate insulating layer GI1 or the second gate insulating layer GI2 may include an interface layer 141 and a gate insulating portion 142 on the interface layer 141. The interface layer 141 may be configured to be closer to one of the first channel portion 131 and the second channel portion 231 than the gate insulating portion 142. The interface layer 141 may be configured to contact the first channel portion 131 and the second channel portion 231.

[0160] refer to Figure 2B The gate insulating layer 140 includes an interface layer 141 and a gate insulating portion 142 on the interface layer 141. The interface layer 141 is configured to be closer to the first channel portion 131 and the second channel portion 231 than the gate insulating portion 142. According to another embodiment of this disclosure, such as Figure 2B As shown, the interface layer 141 is in contact with each of the first channel portion 131 and the second channel portion 231.

[0161] Interface layer 141 protects the first channel portion 131 and the second channel portion 231. According to another embodiment of this disclosure, interface layer 141 can be formed by metal-organic chemical vapor deposition (MOCVD). The interface layer 141 formed by MOCVD has a dense and uniform atomic arrangement structure, thereby effectively blocking hydrogen (H), oxygen (O), etc., that permeate from the outside of the gate insulating layer 140. Therefore, the first channel portion 131 and the second channel portion 231 can be effectively protected.

[0162] Interface layer 141 can be made of an insulating material. For example, interface layer 141 can contain a material with insulating properties that can be applied to MOCVD methods. According to one embodiment of this disclosure, interface layer 141 can contain silicon oxide (SiO2). x ), silicon nitride (SiN) x At least one of the following: (a) or a metal oxide. Specifically, the interface layer 141 may comprise SiO2, SiN... x Or at least one of Al2O3. More specifically, the interface layer 141 may contain SiO2 as a silicon oxide (SiO2). x However, one embodiment of this disclosure is not limited thereto. Interface layer 141 may be formed of other materials having insulating properties.

[0163] According to another embodiment of this disclosure, the interface layer 141 may have a thickness of 1 nm to 10 nm. When the thickness of the interface layer 141 is less than 1 nm, the effect of the interface layer 141 in blocking hydrogen (H) and oxygen (O) may be reduced. When the thickness of the interface layer 141 exceeds 10 nm, it may take a longer time to form the interface layer 141, and the overall thickness of the gate insulating layer 140 may be greater than the necessary thickness.

[0164] The gate insulating portion 142 is the main body of the gate insulating layer 140. Due to the gate insulating portion 142, the gate insulating layer 140 can have excellent mechanical stability and electrical insulation properties, and can have the dielectric properties required to drive thin-film transistors TR1 and TR2.

[0165] Figure 3A and Figure 3B This is a cross-sectional view of a thin-film transistor substrate 300 according to yet another embodiment of the present disclosure.

[0166] and Figure 2B Compared to the thin-film transistor substrate 200, Figure 3A The thin-film transistor substrate 300 includes a first active layer A1 and a second active layer A2 with a multilayer structure.

[0167] Specifically, at least one of the first active layer A1 or the second active layer A2 may include first oxide semiconductor layers 130a and 230a on the substrate 110, and second oxide semiconductor layers 130b and 230b on the first oxide semiconductor layers 130a and 230a. The first oxide semiconductor layers 130a and 230a and the second oxide semiconductor layers 130b and 230b may contain the same semiconductor material or may contain different semiconductor materials.

[0168] First oxide semiconductor layers 130a and 230a support second oxide semiconductor layers 130b and 230b. Therefore, the first oxide semiconductor layers 130a and 230a are referred to as "support layers". A first channel portion 131 and a second channel portion 231 may be formed in the second oxide semiconductor layers 130b and 230b, respectively. Therefore, the second oxide semiconductor layers 130b and 230b are referred to as "channel layers", but one embodiment of this disclosure is not limited thereto. The first channel portion 131 and the second channel portion 231 may be formed in the first oxide semiconductor layers 130a and 230a.

[0169] The first oxide semiconductor layers 130a and 230a and the second oxide semiconductor layers 130b and 230b can be formed by deposition, metal-organic chemical vapor deposition (MOCVD), etc. The first oxide semiconductor layers 130a and 230a and the second oxide semiconductor layers 130b and 230b can be formed by continuous processes.

[0170] The structure of the first active layer A1 and the second active layer A2, comprising first oxide semiconductor layers 130a and 230a and second oxide semiconductor layers 130b and 230b, is referred to as a two-layer structure, but another embodiment of this disclosure is not limited thereto. At least one of the first active layer A1 or the second active layer A2 may further include a third oxide semiconductor layer on the second oxide semiconductor layers 130b and 230b.

[0171] According to another embodiment of this disclosure, at least one of the first gate insulating layer GI1 or the second gate insulating layer GI2 may include a gate insulating portion 142 and a passivation layer 143 on the gate insulating portion 142. The passivation layer 143 may be configured to be closer to one of the first gate G1 and the second gate G2 than the gate insulating portion 142.

[0172] refer to Figure 3B The gate insulating layer 140 includes a gate insulating portion 142 and a passivation layer 143 on the gate insulating portion 142. The passivation layer 143 can contact the first gate G1 and the second gate G2, respectively.

[0173] The passivation layer 143 improves the surface properties of the gate insulating layer 140. According to another embodiment of this disclosure, the passivation layer 143 can be formed by an MOCVD method. The passivation layer 143 formed by the MOCVD method has a dense and uniform atomic arrangement structure, thereby effectively blocking hydrogen (H), oxygen (O), etc., that permeate from the outside of the gate insulating layer 140. Therefore, the channels 131 and 132 can be effectively protected.

[0174] The passivation layer 143 can be made of an insulating material. For example, the passivation layer 143 can contain a material with insulating properties that can be applied to MOCVD methods. According to one embodiment of this disclosure, the passivation layer 143 can contain silicon oxide (SiO2). x ), silicon nitride (SiN) x At least one of the following: (a) or a metal oxide. Specifically, the passivation layer 143 may comprise SiO2, SiN... x Or at least one of Al2O3.

[0175] According to another embodiment of this disclosure, the passivation layer 143 may have a thickness of 1 nm to 10 nm. When the thickness of the passivation layer 143 is less than 1 nm, the passivation layer 143 may not be effective in blocking hydrogen (H) and oxygen (O). When the thickness of the passivation layer 143 exceeds 10 nm, it may take a long time to form the passivation layer 143, and the overall thickness of the gate insulating layer 140 may be greater than the necessary thickness.

[0176] Figure 4 This is a cross-sectional view of a thin-film transistor substrate 400 according to another embodiment of the present disclosure.

[0177] and Figure 2B Compared to the TFT substrate 200, Figure 4 The thin-film transistor substrate 400 further includes a first pad layer 115 that overlaps with the first channel portion 131.

[0178] refer to Figure 4 The first pad layer 115 is disposed between the substrate 110 and the first buffer layer 120 and overlaps with the first channel portion 131. The first pad layer 115 does not overlap with the second channel portion 231.

[0179] The first pad layer 115 may have conductive and light-shielding properties. The first pad layer 115 may be a light-shielding layer.

[0180] According to another embodiment of this disclosure, a first buffer layer 120 is disposed on a first pad layer 115. The first pad layer 115 and the first channel portion 131 are spaced apart from each other by the first buffer layer 120. (See also...) Figure 4 The gap distance t3 between the first pad layer 115 and the first channel portion 131 is substantially the same as the thickness t1 of the first buffer layer 120. Therefore, the gap distance t3 between the first pad layer 115 and the first channel portion 131 can be equal to the gap distance t1 between the conductive material layer 215 and the second channel portion 231.

[0181] According to another embodiment of this disclosure, the first pad layer 115 is connected to the first gate G1. Specifically, refer to... Figure 4The bridging portion 172 is disposed on the interlayer insulating layer 160, and the first pad layer 115 and the first gate G1 are connected to each other through the bridging portion 172.

[0182] refer to Figure 4 The first conductor portion 132 of the first active layer A1 serves as the first source S1, and the second conductor portion 133 serves as the first drain D1. Furthermore, the first conductor portion 232 of the second active layer A2 serves as the second drain D2, and the second conductor portion 233 serves as the second source S2.

[0183] The bridging portion 172 connects the first gate G1 to the first pad layer 115 through contact holes H11 and H12. One of the contact holes H11 and H12, contact hole H11, is formed by passing through the interlayer insulating layer 160, and the other contact hole H21 is formed by passing through the interlayer insulating layer 160, the gate insulating layer 140, and the first buffer layer 120.

[0184] refer to Figure 4 Since the first pad layer 115 is connected to the first gate G1, Figure 4 The first thin-film transistor TR1 can have a dual-gate structure. Due to the dual-gate structure, Figure 4 The first thin-film transistor TR1 can have a very small s-factor.

[0185] The effective gate voltage V of the first pad layer 115 eff You can refer to Figure 13A and Figure 13B describe.

[0186] Figure 13A and 13B This illustrates the effective gate voltage V of a first thin-film transistor according to another embodiment of the present disclosure. eff A schematic diagram.

[0187] Figure 13A This schematically illustrates the effect of gate voltage V GS Applied to Figure 4 The first thin-film transistor TR1 can generate a capacitance Cap. Figure 13A The diagram schematically illustrates the capacitance relationship Cap at a voltage near the threshold voltage Vth before the first thin-film transistor TR1 is fully turned on.

[0188] like Figure 13A As shown, when the gate voltage V GS When applied to the second thin-film transistor TR2, a capacitance C can be formed between the first channel portion 131 and the first gate G1. GI1 A capacitor C can be formed between the first channel portion 131 and the first source S1. CHFurthermore, a capacitor C can be formed between the first channel portion 131 and the first pad layer 115. BUF .

[0189] according to Figure 13A The relationship between voltage and capacitance Cap can be expressed as follows: Figure 13B As shown.

[0190] According to one embodiment of this disclosure, the first pad layer 115 and the first gate G1 are electrically connected to each other. Therefore, a gate voltage is applied to the first channel portion through the first pad layer 115. Consequently, the capacitance C between the first channel portion 131 and the first pad layer 115... BUF The corresponding effective gate voltage V eff Increase.

[0191] refer to Figure 13B The voltage applied between the first channel portion 131 and the first gate G1 during the driving of the first thin-film transistor TR1 is called the effective gate voltage V. eff At that time, the effective gate voltage V eff It can be obtained through Equation 4 below.

[0192] [Formula 4]

[0193] V eff = [C GI1 + C BUF ) / (C GI1 + C CH + C BUF )] × V GS

[0194] Referring to Equation 4, due to the capacitance C between the first channel portion 131 and the first pad layer 115 BUF Compared to Equation 2, the numerator of Equation 4 is larger. Therefore, the gate voltage V actually applied between the first source S1 and the first gate G1... GS In comparison, the effective gate voltage V eff The decrease is negligible. Therefore, when the same voltage is applied, the drain-source current I of the first thin-film transistor TR1 remains constant. DS The drain-source current I of the second thin-film transistor TR2 is greater than that of the second thin-film transistor. DS And the drain-source current I DS The range of changes is also quite large.

[0195] As described above, due to the drain-source current I of the first thin-film transistor TR1 DS The change in s is greater than that of the second thin-film transistor TR2, so the s-factor of the first thin-film transistor TR1 is less than that of the second thin-film transistor TR2.

[0196] Therefore, in Figure 4 In the thin-film transistor substrate 400 shown, the first thin-film transistor TR1, which has a very small s-factor, can be used as a switching transistor, and the second thin-film transistor TR2, which has a relatively large s-factor, can be used as a driving transistor for a display device.

[0197] Figure 5 This is a cross-sectional view of a thin-film transistor substrate 500 according to another embodiment of the present disclosure.

[0198] refer to Figure 5 According to another embodiment of the present disclosure, the thin-film transistor substrate 500 further includes a second buffer layer 220 between the substrate 110 and the first buffer layer 120. The second buffer layer 220 has insulating properties and can prevent the penetration of moisture and oxygen.

[0199] The second buffer layer 220 may comprise at least one of silicon oxide, silicon nitride, or metal-based oxide. The second buffer layer 220 may have a single-layer structure or a multi-layer structure.

[0200] According to one embodiment of this disclosure, the second buffer layer 220 may have the same thickness as the first buffer layer 120, or it may have a thickness greater than that of the first buffer layer 120. For example, the thickness of the second buffer layer 220 may be more than 1.5 times the thickness of the first buffer layer 120. The thickness of the second buffer layer 220 may be at least 2 or 3 times the thickness of the first buffer layer 120.

[0201] refer to Figure 5 The conductive material layer 215 can be disposed between the first buffer layer 120 and the second buffer layer 220. The first pad layer 115 can also be disposed between the first buffer layer 120 and the second buffer layer 220.

[0202] exist Figure 5 In the thin-film transistor substrate 500 shown according to another embodiment of the present disclosure, the first pad layer 115 is connected to... Figure 4 The first gate G1 is electrically connected in the same manner. The first pad layer 115 is connected to the first gate G1 through the bridging portion 172 and contact holes H11 and H12.

[0203] Figure 6 This is a cross-sectional view of a thin-film transistor substrate 600 according to another embodiment of the present disclosure.

[0204] refer to Figure 6 The first pad layer 115 can be disposed between the substrate 110 and the second buffer layer 220. The first pad layer 115 is connected to the first source S1 of the first thin film transistor TR1.

[0205] refer to Figure 6 A bridging portion 173 is disposed on the interlayer insulating layer 160, so that the first pad layer 115 and the first source S1 are connected to each other through the bridging portion 173. The bridging portion 173 can extend from the first source S1, and a portion of the first source S1 can be used as the bridging portion 173.

[0206] The bridging portion 173 is connected to the first pad layer 115 through the contact hole H12. The contact hole H21 is formed by passing through the interlayer insulating layer 160, the gate insulating layer 140, the first buffer layer 120, and the second buffer layer 220.

[0207] When the first conductor portion 132 of the first active layer A1 is used as the first source S1 and the second conductor portion 133 is used as the first drain D1, the first source S1 and the first drain D1 on the interlayer insulating layer 160 can be omitted. In this case, the first source S1 on the interlayer insulating layer 160 can be part of the bridging portion 173.

[0208] refer to Figure 6 The bridging portion 173 can connect the first conductor portion 132 of the first active layer A1 to the first pad layer 115 through two contact holes H11 and H12.

[0209] exist Figure 6 In the thin-film transistor substrate 600, since the first pad layer 115 is connected to the first source S1, a capacitance Cap can be formed between the first pad layer 115 and the first channel portion 131. However, because the distance between the first pad layer 115 and the first channel portion 131 is relatively long, the capacitance between the first pad layer 115 and the first channel portion 131 is very small. Therefore, the capacitance Cap between the first pad layer 115 and the first channel portion 131 has almost no effect on the gate voltage V. GS and effective gate voltage V eff .

[0210] According to one embodiment of this disclosure, the distance t4 between the first pad layer 115 and the first channel portion 131 is greater than the distance t1 between the conductive material layer 215 and the second channel portion 231. For example, the distance t4 between the first pad layer 115 and the first channel portion 131 may be at least twice the distance t1 between the conductive material layer 215 and the second channel portion 231 (t4 ≥ 2 × t1). More specifically, the distance t4 between the first pad layer 115 and the first channel portion 131 may be at least 2.5 times the distance t1 between the conductive material layer 215 and the second channel portion 231.

[0211] As described above, even though the first pad layer 115 is disposed under the first channel portion 131 of the first thin-film transistor TR1 and the first pad layer 115 is connected to the first source S1, the s-factor of the first thin-film transistor TR1 hardly increases because the distance between the first pad layer 115 and the first channel portion 131 is relatively long. Therefore, the first thin-film transistor TR1 can maintain excellent switching characteristics.

[0212] Figure 7 This is a cross-sectional view of a thin-film transistor substrate 700 according to another embodiment of the present disclosure.

[0213] refer to Figure 7 The first pad layer 115 is connected to the first gate G1. Specifically, a bridging portion 174 is disposed on the interlayer insulating layer 160, and the first pad layer 115 and the first gate G1 are connected to each other through the bridging portion 174.

[0214] refer to Figure 7 The first conductor portion 132 of the first active layer A1 serves as the first source S1, and the second conductor portion 133 serves as the first drain D1. Furthermore, the first conductor portion 232 of the second active layer A2 serves as the second drain D2, and the second conductor portion 233 serves as the second source S2.

[0215] The bridging portion 174 connects the first gate G1 to the first pad layer 115 through contact holes H11 and H12. One of the contact holes H11 and H12, contact hole H11, is formed by passing through the interlayer insulating layer 160, and the other contact hole H21 is formed by passing through the interlayer insulating layer 160, the gate insulating layer 140, the first buffer layer 120, and the second buffer layer 220.

[0216] refer to Figure 7 Since the first pad layer 115 is connected to the first gate G1, Figure 7 The first thin-film transistor TR1 can have a dual-gate structure.

[0217] However, due to the long distance between the first pad layer 115 and the first channel portion 131, the capacitance Cap between them is very small. Therefore, the capacitance Cap between the first pad layer 115 and the first channel portion 131 has almost no effect on the gate voltage V. GS and effective gate voltage V eff .

[0218] Figures 8A to 8E This is a graph showing the threshold voltage of a thin-film transistor. (For example...) Figures 8A to 8E As shown, the thin-film transistor's voltage relative to the gate voltage V GS Drain-source current I DS The curve represents the threshold voltage of a thin-film transistor.

[0219] Specifically, Figures 8A to 8E The thin-film transistor being measured has the same characteristics as... Figure 1A It has the same structure as the thin-film transistor TR2 shown.

[0220] Figure 8A , Figure 8B , Figure 8C and Figure 8D The thin-film transistor being measured includes a gate insulating layer with a thickness of 250 nm and first buffer layers 120 with thicknesses of 82 nm, 120 nm, 182 nm and 232 nm, respectively. Figure 8E The thin-film transistor includes a gate insulating layer with a thickness of 150 nm and a first buffer layer 120 with a thickness of 400 nm.

[0221] Confirmation based on Figure 8A , Figure 8B , Figure 8C and Figure 8D The thin-film transistors, including a first buffer layer 120 that is thinner than the gate insulating layer, have s-factors of 0.38 V / dec, 0.36 V / dec, 0.31 V / dec, and 0.31 V / dec, respectively.

[0222] Confirmation based on Figure 8E The thin-film transistor, which includes a first buffer layer 120 that is thicker than the gate insulating layer, has an s-factor of 0.19 V / dec.

[0223] refer to Figures 8A to 8E When the thickness t1 of the first buffer layer 120 and the thickness t22 of the gate insulating layer (second gate insulating layer GI2) satisfy the relationship of Equation 3, it can be confirmed that the thin film transistor has an s factor of more than 0.3 V / dec.

[0224] [Formula 3]

[0225] 0.75 ≤ t22 / t1 ≤ 5

[0226] Figure 9A and Figure 9B This is a graph showing the threshold voltage of a thin-film transistor. It is plotted relative to the gate voltage V. GS Drain-source current I DS The curve represents the threshold voltage of a thin-film transistor.

[0227] Figure 9A and Figure 9B The thin-film transistor being measured has the same characteristics as... Figure 2A It has the same structure as the thin-film transistor TR2 shown. Figure 9A and Figure 9BThe thin-film transistor being measured includes a gate insulating layer 140 with a thickness of 350 nm, and first buffer layers 120 with thicknesses of 110 nm and 130 nm, respectively.

[0228] Specifically, Figure 9A The first buffer layer 120 of the thin-film transistor being measured includes a hydrogen barrier layer 122 with a thickness of 10 nm and a buffer insulating layer 121 with a thickness of 100 nm. Figure 9B The first buffer layer 120 of the thin-film transistor being measured includes a hydrogen barrier layer 122 with a thickness of 30 nm and a buffer insulating layer 121 with a thickness of 100 nm. The hydrogen barrier layer 122 is made of silicon nitride (SiN). x The buffer insulating layer 121 is made of silicon oxide (SiO2). x Made from ).

[0229] confirm Figure 9A The thin-film transistor shown has a s-factor of 0.51 V / dec, according to Figure 9B The thin-film transistor has an s-factor of 0.49 V / dec. Thus, according to one embodiment of this disclosure, the thin-film transistor can have an s-factor of 0.45 V / dec or higher.

[0230] Figure 10 This is a graph showing the relationship between the s-factor and the thickness ratio of the first buffer layer and the gate insulating layer.

[0231] Specifically, Figure 10 It shows that when having with Figure 2A The thin-film transistor TR2 shown has the same gate insulating layer GI in the same structure as the thin-film transistor shown. Figure 2A When the thicknesses of the second gate insulating layer are 150 nm, 250 nm and 350 nm, respectively, the s-factor is based on the thickness ratio (GI / first buffer layer) of the first buffer layer 120 and the gate insulating layer GI.

[0232] refer to Figure 10 When the thickness of the gate insulating layer GI is 250 nm or more, and when the thickness ratio of the gate insulating layer GI to the first buffer layer 120 (GI / first buffer layer) is 0.75 or more, the thin film transistor can have an s factor of 0.3 or more.

[0233] Another embodiment of this disclosure provides a display device 800, which includes thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700, and a display element 710 connected to a second thin-film transistor TR2 connected to the thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700. According to yet another embodiment of this disclosure, for example, the display element 710 may include an organic light-emitting diode.

[0234] Figure 14 This is a schematic diagram illustrating a display device 800 according to another embodiment of the present disclosure.

[0235] like Figure 14 As shown, a display device 800 according to another embodiment of the present disclosure includes a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0236] Gate lines GL and data lines DL are disposed in the display panel 310, and pixel P is disposed in the intersection area of ​​gate lines GL and data lines DL. An image is displayed by driving pixel P.

[0237] The controller 340 controls the gate driver 320 and the data driver 330.

[0238] The controller 340 uses signals supplied from an external system (not shown) to output a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330. Furthermore, the controller 340 samples input image data from the external system, rearranges the sampled input image data, and supplies the rearranged digital image data (RGB) to the data driver 330.

[0239] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Furthermore, control signals for controlling the shift register can be included within the gate control signal GCS.

[0240] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0241] The data driver 330 supplies data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage and supplies the data voltage to the data line DL.

[0242] Gate driver 320 may include shift register 350.

[0243] The shift register 350 uses a start signal and a gate clock transmitted from the controller 340 to sequentially supply gate pulses to the gate line GL during a frame. In this case, a frame refers to the time period during which an image is output through the display panel 310. The gate pulses have an on-state voltage that enables the switching elements (thin-film transistors) disposed in the pixel P to conduct.

[0244] Furthermore, during the remaining periods of a frame when no gate pulse is supplied, shift register 350 supplies a gate cutoff signal to the gate line GL, which enables the switching element to turn off. In the following text, the gate pulse and the gate cutoff signal will be collectively referred to as the scan signal SS or Scan.

[0245] According to one embodiment of this disclosure, the gate driver 320 can be packaged on the substrate 110. Thus, the structure in which the gate driver 320 is directly packaged on the substrate 110 is referred to as a gate-in-panel (GIP) structure.

[0246] Figure 15 yes Figure 14 The circuit diagram of any pixel P. Figure 16 It shows Figure 15 A planar image of pixel P. Figure 17 It is along Figure 16 A cross-sectional view taken from line I-I'.

[0247] Figure 15 The circuit diagram is an equivalent circuit diagram of the pixel P of the display device 800, which includes an organic light-emitting diode (OLED) as a display element 710.

[0248] Pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710.

[0249] Figure 15 The pixel driving circuit PDC includes a first thin-film transistor TR1 as a switching transistor and a second thin-film transistor TR2 as a driving transistor. The first thin-film transistor TR1 and the second thin-film transistor TR2 have been described in the descriptions of thin-film transistor substrates 100, 200, 300, 400, 500, 600 and 700.

[0250] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied via the gate line GL.

[0251] The data line DL provides the data voltage Vdata to the pixel driving circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0252] The driving power line PL provides a driving voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0253] When the first thin-film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata supplied via the data line DL is supplied to the gate G2 of the second thin-film transistor TR2 connected to the display element 710. The data voltage Vdata charges the first capacitor C1 formed between the gate G2 and the source S2 of the second thin-film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0254] The amount of current supplied to the organic light-emitting diode (OLED) that serves as the display element 710 is controlled by the second thin-film transistor TR2 based on the data voltage Vdata, thereby controlling the grayscale of the light output from the display element 710.

[0255] refer to Figure 16 and Figure 17 The first thin-film transistor TR1 and the second thin-film transistor TR2 are disposed on the substrate 110.

[0256] The substrate 110 can be made of glass or plastic. Plastics with flexible properties (e.g., polyimide (PI)) can be used as the substrate 110.

[0257] A second buffer layer 220 is disposed on the substrate 110, and a conductive material layer 215 is disposed on the second buffer layer 220. The conductive material layer 215 may have conductive and light-shielding properties. The conductive material layer 215 can protect the active layers A1 and A2 by blocking light incident from the outside.

[0258] A first buffer layer 120 is disposed on the conductive material layer 215. The first buffer layer 120 is made of an insulating material and protects the active layers A1 and A2 from moisture or oxygen introduced from the outside. The first buffer layer 120 may include a hydrogen barrier layer 122 and a buffer insulating layer 121.

[0259] The first active layer A1 of the first thin-film transistor TR1 and the second active layer A2 of the second thin-film transistor TR2 are disposed on the first buffer layer 120.

[0260] For example, the first active layer A1 and the second active layer A2 may comprise an oxide semiconductor material. The first active layer A1 and the second active layer A2 may be formed from oxide semiconductor layers made of oxide semiconductor material.

[0261] The first active layer A1 may include a first channel portion 131, a first conductor portion 132, and a second conductor portion 133. The first channel portion 131 overlaps with the first gate G1. According to another embodiment of the present disclosure, the first conductor portion 132 may be referred to as the first source S1, and the second conductor portion 133 may be referred to as the first drain D1.

[0262] The second active layer A2 may include a second channel portion 231, a first conductor portion 232, and a second conductor portion 233. The second channel portion 231 overlaps with the second gate G2. According to another embodiment of this disclosure, the first conductor portion 232 may be referred to as the second source S2, and the second conductor portion 233 may be referred to as the second drain D2.

[0263] refer to Figure 16 and Figure 17 A portion of the first active layer A1 can be made conductive, and thus can be the first capacitor electrode C11 of the first capacitor C1.

[0264] A gate insulating layer 140 is disposed on the first active layer A1 and the second active layer A2. The gate insulating layer 140 may cover the entire upper surface of the first active layer A1 and the second active layer A2, or it may only cover a portion of the first active layer A1 and the second active layer A2. The gate insulating layer 140 protects the first channel portion 131 and the second channel portion 231.

[0265] The gate insulating layer 140 may include an interface layer 141 and a gate insulating portion 142 on the interface layer 141. The interface layer 141 is configured to be closer to the first channel portion 131 and the second channel portion 231 than the gate insulating portion 142.

[0266] The first gate G1 of the first thin-film transistor TR1 and the second gate G2 of the second thin-film transistor TR2 are disposed on the gate insulating layer 140.

[0267] The first gate G1 of the first thin-film transistor TR1 overlaps with at least a portion of the first active layer A1 of the first thin-film transistor TR1. The second gate G2 of the second thin-film transistor TR2 overlaps with at least a portion of the second active layer A2 of the second thin-film transistor TR2.

[0268] An interlayer insulating layer 160 is disposed on the first gate G1 and the second gate G2.

[0269] The data cable DL and the drive power cable PL are mounted on the interlayer insulation layer 160.

[0270] The data line DL contacts the first source S1 formed in the first active layer A1 through the first contact hole H1. According to another embodiment of this disclosure, the portion of the data line DL that overlaps with the first active layer A1 can be referred to as the first source S1.

[0271] The drive power line PL contacts the second drain electrode D2 formed in the second active layer A2 through the fifth contact hole H5. According to another embodiment of this disclosure, the portion of the drive power line PL that overlaps with the second active layer A2 can be referred to as the second drain electrode D2.

[0272] refer to Figure 16 and Figure 17 The second capacitor electrode C12 of the first capacitor C1, as well as the first bridging portion BR1 and the second bridging portion BR2 are disposed on the interlayer insulating layer 160.

[0273] The second capacitor electrode C12 overlaps with the first capacitor electrode C11 to form the first capacitor C1.

[0274] The first bridging portion BR1 can be integrally formed with the second capacitor electrode C12. The first bridging portion BR1 is connected to the conductive material layer 215 through the second contact hole H2, and to the second source electrode S2 through the third contact hole H3. Therefore, the conductive material layer 215 can be connected to the second source electrode S2 of the second thin film transistor TR2.

[0275] The second bridging portion BR2 is connected to the second gate G2 of the second thin-film transistor TR2 through the fourth contact hole H4, and is connected to the first capacitor electrode C11 of the first capacitor C1 through the seventh contact hole H7.

[0276] A planarization layer 175 is disposed on the data line DL, the drive power line PL, the second capacitor electrode C12, the first bridge portion BR1, and the second bridge portion BR2. The planarization layer 175 planarizes the upper parts of the first thin-film transistor TR1 and the second thin-film transistor TR2, and protects the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0277] The first electrode 711 of the display element 710 is disposed on the planarization layer 175. The first electrode 711 of the display element 710 is in contact with the second capacitor electrode C12 through a sixth contact hole H6 formed in the planarization layer 175, wherein the second capacitor electrode C12 is integrally formed with the first bridging portion BR1. Therefore, the first electrode 711 can be connected to the second source S2 of the second thin film transistor TR2.

[0278] The embankment layer 750 is disposed at the edge of the first electrode 711. The embankment layer 750 defines the light-emitting area of ​​the display element 710.

[0279] An organic light-emitting layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic light-emitting layer 712. Thus, the display element 710 is completed. Figure 17The display element 710 shown is an organic light-emitting diode (OLED). Therefore, the display device 100 according to an embodiment of the present disclosure is an organic light-emitting display device.

[0280] According to another embodiment of this disclosure, the second thin-film transistor TR2 may have a relatively large s-factor. The second thin-film transistor TR2 can be used as a driving transistor to improve the grayscale performance of the display device 800.

[0281] The first thin-film transistor TR1 has a relatively small s-factor, thus exhibiting excellent switching characteristics. The first thin-film transistor TR1 can be used as a switching transistor to improve the display quality of the display device 800.

[0282] Figure 18 This is a plan view showing any pixel P of a display device 900 according to another embodiment of the present disclosure. Figure 19 It is along Figure 18 A cross-sectional view taken from line II-II'. Figure 20 It is along Figure 18 The cross-sectional view taken from line III-III'.

[0283] and Figures 14 to 17 Compared to the display device 800 shown, Figure 18 The display device 900 further includes a first pad layer 115 that overlaps with the first active layer A1.

[0284] refer to Figure 19 and Figure 20 The first pad layer 115 is disposed between the substrate 110 and the first buffer layer 120. More specifically, the first pad layer 115 is disposed between the first buffer layer 120 and the second buffer layer 220.

[0285] The first pad layer 115 overlaps with the first channel portion 131 of the first active layer A1, but does not overlap with the second channel portion 231 of the second active layer A2.

[0286] The first pad layer 115 may have conductive and light-shielding properties. The first pad layer 115 may be a light-shielding layer.

[0287] refer to Figure 18 and Figure 20 The third bridging portion BR3 is disposed on the interlayer insulating layer 160. The third bridging portion BR3 is connected to the gate line GL through the eighth contact hole H8 and to the first pad layer 115 through the ninth contact hole H9. Since the first gate G1 is part of the gate line GL, the first pad layer 115 can be connected to the first gate G1 of the first thin film transistor TR1 through the third bridging portion BR3.

[0288] Figure 21This is a plan view showing any pixel P of a display device 1000 according to yet another embodiment of the present disclosure. Figure 22 It is along Figure 21 A cross-sectional view taken from line IV-IV'. Figure 23 It is along Figure 21 A cross-sectional view taken from line V-V'.

[0289] and Figures 14 to 17 Compared to the display device 800 shown, Figure 21 The display device 1000 further includes a first pad layer 115 that overlaps with the first active layer A1.

[0290] refer to Figures 21 to 23 The first pad layer 115 is disposed between the substrate 110 and the first buffer layer 120. More specifically, the first pad layer 115 is disposed between the substrate 110 and the second buffer layer 220.

[0291] refer to Figures 21 to 23 The third bridging portion BR3 is disposed on the interlayer insulating layer 160. The third bridging portion BR3 is connected to the first source S1 of the first thin-film transistor TR1 through the eighth contact hole H8, and is connected to the first pad layer 115 through the ninth contact hole H9. Therefore, the first pad layer 115 can be connected to the first source S1 of the first thin-film transistor TR1 through the third bridging portion BR3.

[0292] Figure 24 This is a plan view showing any pixel P of a display device 1100 according to another embodiment of the present disclosure. Figure 25 It is along Figure 24 A cross-sectional view taken from line VI-VI'. Figure 26 It is along Figure 24 A cross-sectional view taken from line VII-VII'.

[0293] exist Figures 24 to 26 In the display device 1100, with Figures 18 to 20 Compared to the display device 900, the first pad layer 115 is disposed between the substrate 110 and the second buffer layer 220.

[0294] refer to Figures 24 to 26 The third bridging portion BR3 is disposed on the interlayer insulating layer 160. The third bridging portion BR3 is connected to the gate line GL through the eighth contact hole H8 and to the first pad layer 115 through the ninth contact hole H9. Since the first gate G1 is part of the gate line GL, the first pad layer 115 can be connected to the first gate G1 of the first thin film transistor TR1 through the third bridging portion BR3.

[0295] Figure 27This is a circuit diagram showing any pixel P of a display device 1200 according to another embodiment of the present disclosure.

[0296] Figure 27 This is an equivalent circuit diagram showing the pixel P of an organic light-emitting display device.

[0297] Figure 27 The pixel P of the display device 1200 shown includes an organic light-emitting diode (OLED) as a display element 710, and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0298] In pixel P, there are signal lines DL, GL, PL, RL and SCL for supplying signals to the pixel driving circuit PDC.

[0299] The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, the driving voltage Vdd used to drive the pixel is supplied to the driving power line PL, the reference voltage Vref is supplied to the reference line RL, and the sensing control signal SCS is supplied to the sensing control line SCL.

[0300] refer to Figure 27 Assume the gate line of the nth pixel P is "GL". n Then the gate line of the (n-1)th pixel P adjacent to the nth pixel P is "GL". n-1 ", and the gate line "GL" of the (n-1)th pixel P n-1 "Used as the sensing control line SCL for the nth pixel P."

[0301] For example, the pixel driving circuit PDC includes a first thin-film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, a second thin-film transistor TR2 (driving transistor) for controlling the magnitude of the current output to the display element 710 according to the data voltage Vdata transmitted through the first thin-film transistor TR1, and a third thin-film transistor TR3 (reference transistor) for sensing the characteristics of the second thin-film transistor TR2.

[0302] A first capacitor C1 is disposed between the gate G2 of the second thin-film transistor TR2 and the display element 710. The first capacitor C1 is referred to as the storage capacitor Cst.

[0303] The first thin-film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL to transmit the data voltage Vdata supplied to the data line DL to the gate G2 of the second thin-film transistor TR2.

[0304] The third thin-film transistor TR3 is connected to the first node n1 and the reference line RL between the second thin-film transistor TR2 and the display element 710, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the second thin-film transistor TR2 as a driving transistor during the sensing period.

[0305] A second node n2, connected to the gate G2 of the second thin-film transistor TR2, is connected to the first thin-film transistor TR1. A first capacitor C1 is formed between the second node n2 and the first node n1.

[0306] When the first thin-film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate G2 of the second thin-film transistor TR2. The data voltage Vdata charges the first capacitor C1 formed between the gate G2 and the source S2 of the second thin-film transistor TR2.

[0307] When the second thin-film transistor TR2 is turned on, current is supplied to the display element 710 via the second thin-film transistor TR2 according to the driving voltage Vdd used to drive the pixel, thereby outputting light from the display element 710.

[0308] Figure 28 This is a circuit diagram showing any pixel of a display device 1300 according to another embodiment of the present disclosure.

[0309] Figure 28 The pixel P of the display device 1300 shown includes an organic light-emitting diode (OLED) as a display element 710, and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0310] The pixel drive circuit PDC includes thin-film transistors TR1, TR2, TR3, and TR4.

[0311] In pixel P, there are signal lines DL, EL, GL, PL, SCL and RL for supplying driving signals to the pixel driving circuit PDC.

[0312] and Figure 27 Compared to the pixel P, Figure 28 The pixel P further includes an emission control line EL. An emission control signal EM is supplied to the emission control line EL.

[0313] In addition, with Figure 27 Compared to the pixel drive circuit PDC, Figure 28 The pixel driving circuit PDC further includes a fourth thin-film transistor TR4 as a light-emitting control transistor for controlling the light-emitting timing of the second thin-film transistor TR2.

[0314] refer to Figure 28 Assume the gate line of the nth pixel P is "GL". n Then the gate line of the (n-1)th pixel P adjacent to the nth pixel P is "GL". n-1 ", and the gate line "GL" of the (n-1)th pixel P n-1 "Used as the sensing control line SCL for the nth pixel P."

[0315] The first capacitor C1 is disposed between the gate G2 of the second thin-film transistor TR2 and the display element 710. The second capacitor C2 is disposed between a terminal of the fourth thin-film transistor TR4, which is supplied with a drive voltage Vdd, and an electrode of the display element 710.

[0316] The first thin-film transistor TR1 provides a scan signal SS to the gate line GL to conduct, so as to transfer the data voltage Vdata supplied to the data line DL to the gate G2 of the second thin-film transistor TR2.

[0317] The third thin-film transistor TR3 is connected to the reference line RL, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the second thin-film transistor TR2, which is the driving transistor, during the sensing period.

[0318] The fourth thin-film transistor TR4 transmits the driving voltage Vdd to the second thin-film transistor TR2 or disables the driving voltage Vdd according to the light emission control signal EM. When the fourth thin-film transistor is turned on, current is supplied to the second thin-film transistor TR2, thereby emitting light from the display element 710.

[0319] In addition to the structure described above, the pixel driving circuit PDC according to another embodiment of the present disclosure can be formed in various other structures. For example, the pixel driving circuit PDC may include five or more thin-film transistors.

[0320] According to this disclosure, the following beneficial effects can be achieved.

[0321] A thin-film transistor substrate according to an embodiment of the present disclosure includes a second thin-film transistor designed to have a large s-factor. Since the second thin-film transistor includes a conductive material layer disposed between the substrate and the active layer and connected to the source, the second thin-film transistor can have a large s-factor. The second thin-film transistor can be used as a driving thin-film transistor for a display device, enabling the display device to easily represent grayscale.

[0322] A thin-film transistor substrate according to an embodiment of the present disclosure includes a first thin-film transistor designed to have a small s-factor and a second thin-film transistor designed to have a large s-factor. The first thin-film transistor can be used as a switching transistor due to its excellent switching characteristics, and the second thin-film transistor can be used as a driving transistor due to its large s-factor. Therefore, a display device having both excellent switching and driving characteristics can be manufactured using a thin-film transistor substrate according to an embodiment of the present disclosure.

[0323] The display device according to another embodiment of the present disclosure includes a second thin-film transistor having a relatively large s-factor, thereby having excellent grayscale performance.

[0324] It will be apparent to those skilled in the art that this disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications, and variations can be made in this disclosure without departing from the spirit or scope thereof. Therefore, the scope of this disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of this disclosure.

Claims

1. A display device, comprising: substrate; At least one buffer layer on the substrate; as well as The substrate has a plurality of pixels, each of which includes a display element and a pixel driving circuit. The pixel driving circuit includes a driving thin-film transistor, which is located on the substrate and configured to drive the display element. The driving thin-film transistor includes: A first active layer is located on the at least one buffer layer and has a first channel portion, the first active layer comprising an oxide semiconductor material; A first gate insulating layer on the first active layer; The first gate on the first gate insulating layer; The first source electrode connected to the first active layer; and The first drain is spaced apart from the first source and connected to the first active layer. The first conductive light-shielding layer is disposed below the first active layer and overlaps with the first channel portion. The first conductive light-shielding layer is electrically connected to the first source electrode. Wherein, the thickness of the first gate insulating layer is 0.75 to 5 times the thickness of the portion of the at least one buffer layer between the first conductive light-shielding layer and the first channel portion.

2. The display device according to claim 1 further includes a switching thin-film transistor. in, The switching thin-film transistor includes: A second active layer is located on the at least one buffer layer and has a second channel portion, the second active layer comprising an oxide semiconductor material; A second gate insulating layer on the second active layer; The second gate on the second gate insulating layer; The second source electrode connected to the second active layer; and The second drain, spaced apart from the second source and connected to the second active layer, The second conductive light-shielding layer is disposed below the second active layer and overlaps with the second channel portion, and the second conductive light-shielding layer is electrically connected to the second gate. In the thickness direction of the substrate, the distance between the first conductive light-shielding layer and the first channel portion is smaller than the distance between the second conductive light-shielding layer and the second channel portion.

3. The display device according to claim 2, wherein, The first active layer and the second active layer are disposed on the same layer.

4. The display device according to claim 2, wherein, The at least one buffer layer includes a first buffer layer and a second buffer layer between the substrate and the first buffer layer. The first conductive light-shielding layer is disposed between the first buffer layer and the second buffer layer, and The second conductive light-shielding layer is disposed between the substrate and the second buffer layer and is electrically connected to the second gate.

5. The display device according to claim 4, wherein, The thickness of the first buffer layer at the portion where the first conductive light-shielding layer overlaps with the first active layer is less than the sum of the thicknesses of the first buffer layer and the second buffer layer at the portion where the second conductive light-shielding layer overlaps with the second active layer.

6. The display device according to claim 4, wherein, The first buffer layer includes: A hydrogen barrier layer on the first conductive light-shielding layer; and A buffer insulating layer on the hydrogen barrier layer, The hydrogen barrier layer comprises silicon nitride.

7. The display device according to claim 1, further comprising: Interlayer insulating layer on the first gate; as well as The bridging portion on the interlayer insulation layer, The bridging section is electrically connected to the first source electrode. The bridging portion is electrically connected to the first conductive light-shielding layer through a contact hole passing through the interlayer insulating layer and the at least one buffer layer. The first active layer includes a conductor portion. Wherein, the conductor portion serves as at least a part of the first source electrode, and The bridging portion electrically connects the conductor portion of the first active layer to the first conductive light-shielding layer.

8. The display device according to claim 7, further comprising: The capacitor electrode is formed integrally with the interlayer insulating layer and the bridging portion. The display element includes a first electrode. The first electrode of the display element is electrically connected to the capacitor electrode.

9. The display device according to claim 1, wherein, The thickness of the first gate insulating layer is 1 to 3.5 times the thickness of the portion of the at least one buffer layer between the first conductive light-shielding layer and the first channel portion.

10. The display device according to claim 1, further comprising: A reference transistor, which is connected to the driving thin-film transistor and configured to be turned on or off by a sensing control signal; as well as A light-emitting control transistor is connected to the driving thin-film transistor and configured to transmit a driving voltage to the driving thin-film transistor according to a light-emitting control signal.

11. The display device according to claim 2, wherein, The first conductive light-shielding layer does not overlap with the second channel portion, and The second conductive light-shielding layer does not overlap with the first channel portion.

12. The display device according to claim 1, wherein, The first gate insulating layer includes: Gate insulating portion; and The interface layer on the gate insulating portion, Wherein, the interface layer is configured to be closer to the first channel portion than the gate insulating portion, and The interface layer contains SiO2.

13. A display device, comprising: substrate; A first conductive light-shielding layer and a second conductive light-shielding layer above the substrate. A first buffer layer on the substrate; A first thin-film transistor, the first thin-film transistor including a first active layer having a first channel portion on the first buffer layer, a first gate, a first source and a first drain on the first active layer; as well as The second thin-film transistor includes a second active layer on the first buffer layer and having a second channel portion, a second gate, a second source, and a second drain on the second active layer. Both the first active layer and the second active layer comprise oxide semiconductor materials. Wherein, the first conductive light-shielding layer overlaps with the first channel portion and is electrically connected to the first gate, and The second conductive light-shielding layer overlaps with the second channel portion and is electrically connected to the second source electrode.

14. The display device according to claim 13, wherein, The first conductive light-shielding layer and the second conductive light-shielding layer are disposed in different layers and do not overlap with each other. In the thickness direction of the substrate, the first distance between the first conductive light-shielding layer and the first channel portion is greater than the second distance between the second conductive light-shielding layer and the second channel portion.

15. The display device according to claim 14, wherein, The first thin-film transistor is a switching thin-film transistor, and the second thin-film transistor is a driving transistor. The s-factor of the second thin-film transistor is greater than that of the first thin-film transistor.

16. The display device according to claim 14, further comprising a second buffer layer between the substrate and the first buffer layer, in, The second conductive light-shielding layer is disposed between the first buffer layer and the second buffer layer, and The first conductive light-shielding layer is disposed between the substrate and the second buffer layer.

17. The display device according to claim 16, wherein, The thickness of the first buffer layer at the portion where the first conductive light-shielding layer overlaps with the first active layer is greater than the sum of the thicknesses of the first buffer layer and the second buffer layer at the portion where the second conductive light-shielding layer overlaps with the second active layer.

18. The display device of claim 17, further comprising a second gate insulating layer between the second active layer and the second gate. in, The thickness of the second gate insulating layer is 0.75 to 5 times the thickness of the portion of the first buffer layer located between the second conductive light-shielding layer and the second channel portion.

19. The display device according to claim 15, further comprising: Interlayer insulating layer on the first gate and the second gate; A bridging portion, which is on the interlayer insulating layer and electrically connected to the second source electrode; A display element, the display element including a first electrode; as well as The capacitor electrode is formed integrally with the interlayer insulating layer and the bridging portion. The bridging portion is electrically connected to the second conductive light-shielding layer through contact holes passing through the interlayer insulating layer and the first buffer layer, and The first electrode of the display element is electrically connected to the bridging portion and the capacitor electrode.

20. The display device according to claim 16, wherein, The first buffer layer includes: A hydrogen barrier layer on the second conductive light-shielding layer; and A buffer insulating layer on the hydrogen barrier layer, The hydrogen barrier layer comprises silicon nitride.

21. The display device according to claim 15, further comprising: Interlayer insulating layer on the first gate; as well as The first bridging portion on the interlayer insulation layer. Wherein, the first bridging portion is electrically connected to the first gate, and The first bridging portion is electrically connected to the first conductive light-shielding layer through a first contact hole passing through the interlayer insulation layer and the first buffer layer.

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