Array substrate, display panel and display device

Abstract

The present disclosure provides an array substrate, a display panel and a display device, and solves the problem of poor impact load resistance of the array substrate in the prior art. The array substrate provided by the present disclosure comprises a substrate, a multilayer dielectric layer and a multilayer wiring layer, at least part of the dielectric layer comprises at least one first dielectric hole; the multilayer wiring layer comprises a first wiring layer and at least one second wiring layer, the second wiring layer is located between the first wiring layer and the substrate; the first dielectric hole exposes part of the area of the first wiring layer; wherein the orthographic projection of the first dielectric hole on the substrate is a first projection, the projection of the first wiring layer on the substrate is a second projection, the orthographic projection of any one layer of the second wiring layer on the substrate is a third projection, the second projection covers the first projection, and the outer boundary contour of the third projection is located outside the first projection. Through such projection avoidance design, the area below the edge of the first dielectric hole is a continuous and pattern-free film layer, avoiding the morphology mutation caused by boundary coincidence.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to an array substrate, a display panel, and a display device. Background Technology

[0002] For OLED display panels, various reliability tests are required. One type of mechanical reliability test is the drop pen test or drop ball test. Specifically, an impact load is applied to the display panel, and the failure phenomenon of "bright spots" is observed.

[0003] Currently, display panels have poor resistance to impact loads, and their pass rate in pen drop tests or ball drop tests still needs to be improved. Summary of the Invention

[0004] In view of this, the present disclosure aims to provide an array substrate, a display panel, and a display device.

[0005] In a first aspect, this disclosure provides an array substrate, comprising: a substrate; a multilayer dielectric layer located on one side of the substrate, at least a portion of the dielectric layer including a plurality of dielectric vias penetrating at least one dielectric layer, the dielectric vias including at least one first dielectric via; a multilayer wiring layer including a first wiring layer and at least one second wiring layer, the second wiring layer being located between the first wiring layer and the substrate, and at least one dielectric layer being present between the first wiring layer and the second wiring layer; the first dielectric via exposing a portion of the first wiring layer; wherein, the orthographic projection of the first dielectric via onto the substrate is a first projection, the projection of the first wiring layer onto the substrate is a second projection, the orthographic projection of any second wiring layer onto the substrate is a third projection, the second projection covers the first projection, and the outer boundary contour of the third projection is located outside the first projection.

[0006] In one embodiment, the first projection falls within the range of at least one third projection; or, the first projection is spaced apart from at least one third projection.

[0007] In one embodiment, the first projection and all third projections are spaced apart.

[0008] In one embodiment, the second wiring layer further includes at least one polysilicon layer; the third projection corresponding to the polysilicon layer is spaced apart from the first projection.

[0009] In one embodiment, the distance between the outer boundary profile of the orthographic projection of any dielectric via on the substrate and the boundary profile of the orthographic projection of any wiring layer on the substrate is greater than 0.5 micrometers.

[0010] In one embodiment, the dielectric layer is made of an inorganic material; and / or, the first trace layer is made of molybdenum.

[0011] In a second aspect, this disclosure provides an array substrate, comprising: a substrate; a multilayer dielectric layer located on one side of the substrate, at least a portion of the dielectric layer including a dielectric via penetrating at least one dielectric layer; a multilayer wiring layer including a first wiring layer and a second wiring layer, the second wiring layer being located between the first wiring layer and the substrate, and at least one dielectric layer being present between the first wiring layer and the second wiring layer; a first dielectric via exposing a portion of the first wiring layer; wherein the orthographic projection of the first dielectric via onto the substrate is a first projection, the projection of the first wiring layer onto the substrate is a second projection, and the second projection covers the first projection; the first wiring layer has a ramp section, and the outer boundary contour of the first projection is located outside the orthographic projection of the ramp section onto the substrate.

[0012] In one embodiment, the first projection is spaced apart from the orthogonal projection of the ramp section on the substrate; or, the first projection covers the orthogonal projection of the ramp section on the substrate.

[0013] In a third aspect, this disclosure provides a display panel including the array substrate described above.

[0014] In a fourth aspect, this disclosure provides a display device including the display panel described above.

[0015] The array substrate provided in this disclosure includes a substrate, multiple dielectric layers, and multiple wiring layers. At least a portion of the dielectric layers includes multiple dielectric vias penetrating at least one dielectric layer, and each dielectric via includes at least one first dielectric via. The multiple wiring layers include a first wiring layer and at least one second wiring layer, with the second wiring layer located between the first wiring layer and the substrate. A portion of the first dielectric via exposes the first wiring layer. The orthographic projection of the first dielectric via onto the substrate is the first projection, the projection of the first wiring layer onto the substrate is the second projection, and the orthographic projection of any second wiring layer onto the substrate is the third projection. The second projection covers the first projection, and the outer boundary of the third projection is outside the first projection. This projection avoidance design ensures that the layer below the edge of the first dielectric via is a continuous film layer without patterned boundaries, preventing abrupt morphological changes caused by boundary overlap. Attached Figure Description

[0016] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to offer a further understanding of the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same parts.

[0017] Figure 1 The diagram shows a partial cross-sectional structure of an array substrate.

[0018] Figure 2The figure shown is a plan view of an array substrate provided in an embodiment of this disclosure.

[0019] Figure 3 The diagram shown is a partial cross-sectional structure of an array substrate provided in an embodiment of this disclosure.

[0020] Figure 4 The diagram shown is a partial cross-sectional structure of another array substrate provided in an embodiment of this disclosure.

[0021] Figure 5 The figure shown is a plan view of a partial structure in an array substrate according to an embodiment of the present disclosure.

[0022] Figure 6 The diagram shown is a partial cross-sectional structure schematic of another array substrate provided in an embodiment of this disclosure.

[0023] Figure 7 The diagram shown is a partial cross-sectional structure schematic of another array substrate provided in an embodiment of this disclosure.

[0024] Figure 8 The diagram shown is a partial cross-sectional structure schematic of another array substrate provided in an embodiment of this disclosure.

[0025] Figure 9 The diagram shown is a partial cross-sectional structure schematic of another array substrate provided in an embodiment of this disclosure.

[0026] Figure 10 The diagram shown is a schematic representation of a display device provided in an embodiment of this disclosure.

[0027] Explanation of reference numerals in the attached figures: AA, Display area; NA, Non-display area; 1, Substrate; 2, Dielectric layer; 20, Dielectric via; 201, First dielectric via; 31, First wiring layer; 311, Ramp section; 32, Second wiring layer; 33, Polysilicon layer; 4, Shielding layer; 5, First transistor; 51, First active layer; 52, First gate; 53, First source; 54, First drain; 6, Storage capacitor; 61, First electrode; 62, Second electrode; 7, Second transistor; 71, Second active layer; 72, Second gate; 73, Third gate; 74, Second source; 75, Second drain. Detailed Implementation

[0028] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0029] Array substrates, especially flexible array substrates used in OLED display panels, typically consist of a substrate, multiple dielectric layers, and multiple wiring layers. These dielectric and wiring layers are stacked alternately, forming the core film structure of the array substrate. Some dielectric layers contain dielectric vias, which are used to establish electrical connections between different wiring layers. In pen and ball impact tests on flexible display panels, impact failure often concentrates at the root region of the dielectric vias. Specifically, the stress caused by the impact load first concentrates around the bottom periphery of the dielectric via, then affects the brittle film layers covering the inner wall and periphery of the via, such as wiring layers made of molybdenum. Once this brittle wiring layer fractures at the root of the dielectric via, it leads to display signal interruption, resulting in localized display anomalies or bright spots.

[0030] To address the aforementioned issues, several theoretical solutions exist in the industry. The first approach is to adjust the thickness of each film layer, bringing the brittle trace layer closer to the neutral layer of the array substrate, thereby reducing the tensile strain experienced by that layer during impact bending. However, adjusting the film layer thickness is strictly limited by factors such as the overall product thickness, capacitance characteristics, and drive circuit design, resulting in a very limited adjustment range and insignificant improvement in stress. The second approach is to enhance the strength of the brittle film layer itself through process techniques, such as adjusting the film deposition stress of the molybdenum trace layer or increasing its elongation at break. However, such process optimizations must simultaneously consider multiple performance requirements, including dielectric constant, ion residue, and etching rate, leading to very limited room for improvement and making breakthrough progress difficult in the short term.

[0031] Against this backdrop, the inventors did not stop at conventional film parameter optimization, but instead conducted in-depth and systematic analysis of simulation data and failure analysis results. By comparing impact test data under a large number of different layouts, the inventors unexpectedly discovered that the stress level of the molybdenum trace layer at the root of the dielectric via exhibits a strong correlation with the relative position of the patterned trace layers within the array substrate, a correlation that had not been systematically considered in previous layout designs. Furthermore, the inventors used a micro-section scanning electron microscope to conduct precise morphological observation of the failed samples, finding that when the edge of the dielectric via coincides precisely with the pattern boundary of other trace layers (such as the gate layer and capacitor layer) below it in the vertical projection direction, a local pit or step-like morphological abrupt change forms on the film surface at that boundary. This discontinuity in micromorphology evolves into geometric stress concentration during impact bending, thereby inducing brittle fracture at the root of the dielectric via.

[0032] After repeated simulations, verifications, and experimental attributions, the inventors finally identified the key mechanism leading to stress concentration: (Refer to...) Figure 1When a dielectric via penetrates the dielectric layer and exposes a certain trace layer, if there is a boundary of another trace layer pattern directly below the edge of the dielectric via, these boundaries will cause the trace layer at the bottom of the via to lose uniform support at the edge, resulting in a sudden change in morphology, which in turn becomes the source of stress concentration.

[0033] Based on the above findings, the inventors proposed an array substrate. The core concept of this array substrate lies in fundamentally eliminating local structural discontinuities caused by pattern boundaries below the edges of the dielectric vias by establishing positional constraint rules between the projections of the dielectric vias and the projections of each wiring layer. Specifically, the orthographic projection of some dielectric vias on the substrate is completely within the orthographic projection of their exposed wiring layers, while ensuring that the outlines of all wiring layer patterns below the exposed wiring layers are outside the projection of the dielectric vias. Through this design, the area below the edges of the dielectric vias is a continuous film layer without pattern boundaries, avoiding abrupt morphological changes caused by boundary overlap. In other words, an impact-resistant pattern design scheme based on projection position avoidance is provided to solve the problem of fracture of the wiring layer at the root of the dielectric via due to stress concentration, effectively improving the impact resistance of the array substrate without significantly increasing the process difficulty and the burden of film thickness adjustment.

[0034] The array substrate provided in this disclosure will be described in detail below with reference to some specific embodiments.

[0035] This disclosure provides an array substrate, which can be a driving backplane in an organic light-emitting diode display panel, or it can be used in a liquid crystal display device, a quantum dot light-emitting display device, electronic paper, or other types of display devices.

[0036] refer to Figure 2 The display panel includes a display area AA and a non-display area NA, with at least a portion of the non-display area NA surrounding the display area AA. The shape of the display area AA can be rectangular, square, circular, elliptical, or other shapes.

[0037] Reference Figure 3 The array substrate includes a substrate 1, multiple dielectric layers 2 located on one side of the substrate 1, and multiple wiring layers. At least one dielectric layer 2 is located between adjacent wiring layers. Alternatively, the multiple dielectric layers 2 and the multiple wiring layers can be stacked alternately to form the core film structure of the array substrate. The substrate 1 serves as the supporting base of the array substrate and can be a rigid or flexible transparent substrate such as glass, quartz, or polyimide. The wiring layers are patterned conductive film layers used to form signal traces for driving circuits, capacitor electrodes or transistor gates, active layers, etc. The dielectric layers 2 are located between adjacent wiring layers or cover the topmost wiring layer, serving as isolation and insulation.

[0038] The dielectric layer 2 includes multiple dielectric vias 20. Each dielectric via 20 penetrates at least one dielectric layer 2. Among multiple wiring layers, wiring layers located at different levels can be electrically connected through the dielectric vias 20 penetrating at least one dielectric layer 2, thereby forming a multilayer interconnect structure. The dielectric via 20 is an open structure penetrating the dielectric layer 2; its interior can be filled with conductive material, or it can be filled by the material of the subsequent covering wiring layer during the deposition process to connect to the underlying wiring layer, thus realizing a vertical conductive path between upper and lower wiring layers. The array substrate typically has a display area, and at least some of the dielectric vias 20 are located within this display area AA.

[0039] In the aforementioned multilayer interconnect structure, a dielectric via 20 penetrates at least one dielectric layer 2 and exposes a portion of the surface area of ​​at least one trace layer. For ease of description, the single trace layer exposed by the dielectric via 20 is referred to as the first trace layer 31, and the dielectric via 20 exposing the first trace layer 31 is referred to as the first dielectric via 201. It should be understood that the first trace layer 31 refers to a specific trace layer exposed by a particular dielectric via 20. In the case of multiple trace layers on the substrate, at least one other trace layer may exist between the first trace layer 31 and the substrate 1. Although these trace layers located below the first trace layer 31 are not directly penetrated and exposed by the first dielectric via 201, their relative positional relationship of their orthographic projections on the substrate 1 affects the structural stress and mechanical reliability of the array substrate under external impact loads.

[0040] For ease of understanding, the other wiring layers between the first wiring layer 31 and the substrate 1 are collectively referred to as the second wiring layer 32. It should be noted that the first dielectric via 201, the first wiring layer 31, and the second wiring layer 32 do not refer to specific films in the array substrate, but rather are definitions for a particular dielectric via 20. Once the dielectric via 20 changes, both the first wiring layer 31 and the second wiring layer 32 will change. For example, for one dielectric via 20, the exposed wiring layer is the first wiring layer 31; but for another dielectric via 20, the exposed wiring layer may be the second wiring layer 32.

[0041] In other words, the multilayer wiring layer 3 includes a first wiring layer 31 and at least one second wiring layer 32. The second wiring layer 32 is located between the first wiring layer 31 and the substrate 1. At least one dielectric layer 2 is present between the first wiring layer 31 and the second wiring layer 32. A first dielectric via 201 exposes a portion of the first wiring layer 31.

[0042] refer to Figure 3Arbitrarily select a first dielectric via 201, and the orthographic projection of this first dielectric via 201 onto the substrate 1 is the first projection. The orthographic projection of the first wiring layer 31 exposed by this arbitrarily selected first dielectric via 201 onto the substrate 1 is the second projection. The orthographic projection of any second wiring layer 32 existing between the arbitrarily selected first dielectric via 201 and the substrate 1 onto the substrate 1 is the third projection. The third projection may include one or more, each corresponding to the projection of a different second wiring layer 32 located below the first wiring layer 31 onto the substrate 1. For example, if two second wiring layers 32 exist sequentially below the first wiring layer 31, then the orthographic projections of each of these two second wiring layers 32 constitute the third projection.

[0043] Regarding the first projection, second projection, and third projection, it should be noted that the first projection is the orthographic projection on the substrate 1 for a single first dielectric via 201. The second projection is the orthographic projection on the substrate 1 of the first wiring layer 31 exposed by the single first dielectric via 201. The third projection is the orthographic projection on the substrate 1 of any second wiring layer 32 between the first wiring layer 31 and the substrate 1. The first projection is different for different first dielectric vias 201, and the corresponding second and third projections may also be different. In the following descriptions of this disclosure, the first projection refers to a single first dielectric via 201, and not a collection of orthographic projections of multiple first dielectric vias 201 on the substrate 1. Furthermore, the first projection specifically refers to the orthographic projection on the substrate 1 of the bottom outline of the first dielectric via 201.

[0044] refer to Figure 3 In terms of projection relationship, the second projection covers the first projection. That is, the orthographic projection of the first dielectric via 201 on the substrate 1 is completely covered by the orthographic projection of the first wiring layer 31 exposed by the first dielectric via 201 on the substrate 1, and the edge of the orthographic projection of the first dielectric via 201 on the substrate 1 does not exceed the edge of the orthographic projection of the first wiring layer 31 on the substrate 1. This means that, from a plane view parallel to the substrate 1, the periphery of the outline of the first dielectric via 201 is completely supported by the solidity of the first wiring layer 31 exposed by the first dielectric via 201.

[0045] Meanwhile, reference Figure 3 or Figure 4 The outer boundary contour of any third projection lies outside the first projection. In other words, within the first projection area, there is no pattern boundary of the second wiring layer 32 below the first wiring layer 31. The outer boundary contour of the third projection refers to the edge of the pattern of the second wiring layer 32.

[0046] Within the first projection range, or where the pattern of the second routing layer 32 does not exist (see reference). Figure 3That is, the second wiring layer 32 is far from the first projection; or the pattern of the second wiring layer 32 is continuous within the first projection range (see reference). Figure 4 Furthermore, the outer boundary contour of the second wiring layer 32 pattern does not pass directly below the first dielectric via 201. That is, the second wiring layer 32 pattern is located below the first projection and its range is larger than the range of the first projection. Therefore, the outer boundary contour of the second wiring layer 32 pattern exceeds the outer boundary contour of the first projection. This avoids the film structure discontinuity caused by the pattern boundary of the lower second wiring layer 32 in the root region of the first dielectric via 201.

[0047] For example, refer to Figure 4 The first projection falls within the range of at least one third projection. At this time, the pattern of at least one second wiring layer 32 below the first dielectric hole 201 is continuous and the arrangement range is larger than the area where the first dielectric hole 201 is located.

[0048] For example, refer to Figure 4 The first projection and at least one third projection are spaced apart. At this time, at least one second wiring layer 32 does not have a pattern arranged below the first dielectric hole 201, that is, the pattern of at least one second wiring layer 32 avoids the area where the first dielectric hole 201 is located.

[0049] For example, refer to Figure 3 The first projection is spaced apart from all the third projections. At this time, no patterns are arranged on any of the second wiring layers 32 below the first dielectric via 201, that is, the patterns of all the second wiring layers 32 avoid the area where the first dielectric via 201 is located.

[0050] The wiring layer also includes at least one polysilicon layer 33. The polysilicon layer 33 is typically used as the channel or active layer of a thin-film transistor, and can also serve as a wiring for electrical connections. Due to manufacturing processes, the surface morphology of the polysilicon layer 33 is uneven. The dielectric layer 2 formed above the polysilicon layer 33 also inherits the morphology of the polysilicon layer 33.

[0051] In some possible examples, the wiring layer between the first wiring layer 31 exposed by the first dielectric via 201 and the substrate 1 includes at least one polysilicon layer 33, that is, the second wiring layer 32 includes at least one polysilicon layer 33. The third projection corresponding to the polysilicon layer 33 is spaced apart from the first projection. The spaced-apart means that the third projection corresponding to the polysilicon layer 33 and the first projection of the first dielectric via 201 do not overlap and maintain a certain distance from each other. At this time, the pattern boundary of the polysilicon layer 33, which is the second wiring layer 32, is completely away from the area directly below the first dielectric via 201, so as to ensure that the area of ​​the first wiring layer 31 exposed by the first dielectric via 201 does not inherit the surface unevenness of the polysilicon layer 33, thereby improving the flatness of the bottom of the first dielectric via 201 and reducing the stress of the material formed in the first dielectric via 201 at the root of the first dielectric via 201.

[0052] refer to Figures 3 to 5 To quantify the aforementioned avoidance design requirements and guide actual layout drawing, the spacing D between the outer boundary contour of the orthographic projection of any dielectric via 20 on substrate 1 and the boundary contour (including inner and outer boundary contours) of the orthographic projection of any routing layer on substrate 1 is greater than 0.5 micrometers, such as 0.52 micrometers, 0.6 micrometers, 0.68 micrometers, 0.75 micrometers, 0.82 micrometers, 0.9 micrometers, 0.98 micrometers, 1.05 micrometers, 1.13 micrometers, or 1.2 micrometers. It can be understood that the spacing D here refers to the minimum geometric distance between any point on the edge line of the projection of the dielectric via 20 and the nearest point on the edge line of the projection of any routing layer below. A lower limit of 0.5 micrometers for spacing D ensures that, after considering process variations such as photolithography and etching, there is still sufficient space between the edge of the dielectric via 20 and the boundaries of each routing layer, reliably achieving boundary separation. If the spacing is less than or equal to 0.5 micrometers, under process fluctuations, the edge of the dielectric hole 20 and the boundary of the pattern of the second trace layer 32 may get too close or even overlap. The local stiffness change and morphological change generated at the boundary will significantly increase the stress concentration at the root of the dielectric hole 20 and reduce the impact resistance reliability.

[0053] The material of the dielectric layer 2 includes inorganic materials, such as at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0054] For example, the material of the first trace layer 31 includes molybdenum. Because molybdenum-containing trace layers are highly brittle, if the stress in the dielectric via 20 corresponding to the molybdenum-containing trace layer is concentrated, damage to the dielectric via 20 can easily affect the molybdenum-containing trace layer, thus expanding the damage area. Therefore, explicitly defining the brittle molybdenum trace layer connected to the dielectric via 20 and the brittle inorganic dielectric layer 2 as the applicable objects of the aforementioned pattern avoidance rule allows the design rule to accurately focus on the most dangerous failure scenarios, thereby maximizing the stress optimization effect brought about by projection avoidance in a rigid interconnect structure employing a molybdenum-inorganic film layer.

[0055] Of course, this also applies to molybdenum-free trace layers to improve the structural stress and mechanical reliability of the array substrate when subjected to external impact loads.

[0056] For ease of understanding, this disclosure provides a specific example.

[0057] refer to Figure 6 The array substrate includes a substrate 1, a shielding layer 4, and a pixel circuit layer.

[0058] The shielding layer 4 is located between the substrate 1 and the pixel circuit layer. The shielding layer 4 has a mesh pattern to provide shielding to the pixel circuit.

[0059] The pixel circuit layer includes at least one transistor and at least one storage capacitor 6. Exemplarily, the pixel circuit layer includes at least a first transistor 5, a second transistor 7, and a storage capacitor 6.

[0060] The first transistor 5 includes a first active layer 51 and a first gate 52 sequentially disposed on a substrate 1, with the first gate 52 located on the side of the first active layer 51 facing away from the substrate 1. The first active layer 51 has a source region, a drain region, and a channel region, with the channel region located between the source region and the drain region. The orthographic projection of the first gate 52 onto the substrate 1 at least partially coincides with the orthographic projection of the first active layer 51 onto the substrate 1. When the first gate 52 is energized to apply a voltage, the first active layer 51 can form a channel within the channel region covered by the first gate 52 to conduct the source and drain regions of the first active layer 51.

[0061] A dielectric layer 2 is provided between the shielding layer 4 and the substrate 1, between the first active layer 51 and the shielding layer 4, and between the first active layer 51 and the first gate 52 for isolation.

[0062] For example, the first transistor 5 further includes a first source 53 and a first drain 54. The first source 53 is electrically connected to the source region of the first active layer 51 through a dielectric via 20 penetrating at least one dielectric layer 2, and the first drain 54 is electrically connected to the drain region of the first active layer 51 through a dielectric layer 2 penetrating at least one dielectric layer 2.

[0063] The second transistor 7 includes a second active layer 71, a second gate 72, and a third gate 73 sequentially disposed on a substrate 1. The second gate 72 is located on the side of the second active layer 71 facing away from the substrate 1, and the third gate 73 is located between the second active layer 71 and the substrate 1. The second active layer 71 has a source region, a drain region, and a channel region, with the channel region located between the source region and the drain region. The orthographic projection of the second gate 72 onto the substrate 1 at least partially coincides with the orthographic projection of the second active layer 71 onto the substrate 1. The orthographic projection of the third gate 73 onto the substrate 1 at least partially coincides with the orthographic projection of the second active layer 71 onto the substrate 1. When the second gate 72 or the third gate 73 is energized to apply a voltage, the second active layer 71 can form a channel within the channel region covered by the second gate 72 to conduct the source and drain regions of the second active layer 71.

[0064] A dielectric layer 2 is provided between the third gate 73 and the shielding layer 4, between the third gate 73 and the second active layer 71, and between the second active layer 71 and the second gate 72 for electrical isolation.

[0065] For example, the second transistor 7 further includes a second source 74 and a second drain 75. The second source 74 is electrically connected to the source region of the second active layer 71 through a dielectric via 20 penetrating at least one dielectric layer 2, and the second drain 75 is electrically connected to the drain region of the second active layer 71 through a dielectric layer 2 penetrating at least one dielectric layer 2.

[0066] The storage capacitor 6 includes a first electrode 61 and a second electrode 62. The first electrode 61 is located between the second electrode 62 and the substrate 1. A dielectric layer 2 is provided between the first electrode and the second electrode for electrical isolation.

[0067] For example, the storage capacitor 6 also includes multiple metal traces. One metal trace is electrically connected to the first electrode 61 through a dielectric via 20 penetrating at least one dielectric layer 2; another metal trace is electrically connected to the second electrode 62 through a dielectric via 20 penetrating at least one dielectric layer 2. Additionally, the metal trace electrically connected to the first electrode 61 can also pass through the second electrode 62.

[0068] It should be noted that any one of the shielding layer 4, the first active layer 51, the first gate 52, the second active layer 71, the second gate 72, the third gate 73, the first electrode 61, and the second electrode 62 is at least a partial pattern of a certain wiring layer. For example, the first electrode 61 and the first gate 52 are located in the same wiring layer. For example, the second electrode 62 and the third gate 73 are located in the same wiring layer.

[0069] For example, the wiring layer where the first active layer 51 is located is a polysilicon layer, and the wiring layer where the second active layer 71 is located is a polysilicon layer.

[0070] For example, the material of the wiring layer where the shielding layer 4 is located includes molybdenum, the material of the wiring layer where the first gate 52 is located includes molybdenum, the material of the wiring layer where the second gate 72 is located includes molybdenum, and the material of the wiring layer where the third gate 73 is located includes molybdenum.

[0071] The routing layer containing any one of the first gate 52, the second gate 72, the third gate 73, the first electrode 61, and the second electrode 62 can be the first routing layer 31 mentioned above, and the dielectric via 20 that exposes any one of the first gate 52, the second gate 72, the third gate 73, the first electrode 61, and the second electrode 62 can be the first dielectric via 201.

[0072] In some other possible embodiments, this disclosure also provides an array substrate. (See reference...) Figure 7 The array substrate includes a substrate 1, a multilayer dielectric layer 2 located on one side of the substrate 1, and a multilayer wiring layer. At least one dielectric layer 2 is present between adjacent wiring layers. Alternatively, the multilayer dielectric layer 2 and the multilayer wiring layer can be understood as being stacked alternately to form the core film structure of the array substrate.

[0073] The structure of the multilayer dielectric layer 2 and the multilayer wiring layer is the same as that of the multilayer dielectric layer 2 and the multilayer wiring layer in the array substrate of the above embodiment.

[0074] For ease of description, the layer of wiring exposed by the dielectric via 20 is referred to as the first wiring layer 31, the dielectric via 20 exposed by the first wiring layer 31 is referred to as the first dielectric via 201, and the other wiring layers between the first wiring layer 31 and the substrate 1 are collectively referred to as the second wiring layer 32. It should be noted that the first dielectric via 201, the first wiring layer 31, and the second wiring layer 32 do not refer to specific film layers in the array substrate, but are definitions specific to a particular dielectric via 20. If the dielectric via 20 changes, both the first wiring layer 31 and the second wiring layer 32 will change. For example, for one dielectric via 20, the exposed wiring layer is the first wiring layer 31; but for another dielectric via 20, the exposed wiring layer may be the second wiring layer 32.

[0075] Arbitrarily select a first dielectric via 201, and the orthographic projection of this first dielectric via 201 on the substrate 1 is the first projection. The orthographic projection of the first wiring layer 31 exposed by this arbitrarily selected first dielectric via 201 on the substrate 1 is the second projection. The second projection covers the first projection. That is, the orthographic projection of the first dielectric via 201 on the substrate 1 is completely covered by the orthographic projection of the first wiring layer 31 exposed by the first dielectric via 201 on the substrate 1, and the edge of the orthographic projection of the first dielectric via 201 on the substrate 1 does not exceed the edge of the orthographic projection of the first wiring layer 31 on the substrate 1. This means that, from a plane view parallel to the substrate 1, the periphery of the outline of the first dielectric via 201 is completely supported by the solidity of the first wiring layer 31 exposed by the first dielectric via 201.

[0076] refer to Figure 7 At least a portion of the first dielectric via 201 exposed in the first wiring layer 31 has a ramp section 311. Specifically, for a portion of the first wiring layer 31, at least a portion of the boundary contour of the orthographic projection of at least one second wiring layer 32 on the substrate 1 falls within the second projection. At this time, since at least a portion of the boundary contour of the second wiring layer 32 is within the range of the second projection, the first wiring layer 31 is lifted at the contour of the second wiring layer 32, forming the ramp section 311.

[0077] At least a portion of the outer boundary contour of the orthographic projection of the first dielectric via 201 onto the substrate 1 lies outside the orthographic projection range of the ramp section 311 onto the substrate 1. That is, the edge of the first dielectric via 201 does not fall within the ramp section 311 of the first trace layer 31. Subsequent material deposited within the first dielectric via 201 will not form a recessed notch at the root of the first dielectric via 201, thereby reducing stress at the root of the first dielectric via 201.

[0078] For example, refer to Figure 7 and Figure 8 At least a portion of the orthographic projection of the first dielectric via 201 on the substrate 1 (i.e., the first projection) is spaced apart from the orthographic projection of the ramp section 311 on the substrate 1. That is, the projection area of ​​the first dielectric via 201 is completely separated from the ramp projection area, and the bottom of the first dielectric via 201 is completely located in the flat part of the trace layer, with the smoothest morphology.

[0079] For example, refer to Figure 9 At least a portion of the orthographic projection of the first dielectric aperture 201 onto the substrate 1 (i.e., the first projection) covers at least a portion of the orthographic projection of the ramp section 311 onto the substrate 1. That is, the entire area of ​​the ramp section 311 is exposed by the first dielectric aperture 201, and the inclined morphology of the ramp section 311 is inside the dielectric aperture 201. At this time, although it will affect the morphology of the material subsequently deposited at the bottom of the first dielectric aperture 201, it will not form a concave notch at the root of the first dielectric aperture 201, and it can also reduce the stress at the root of the first dielectric aperture 201.

[0080] By controlling the inclusion or separation relationship between the orthogonal projection of the ramp section 311 on the substrate 1 and the first projection, the positions of the dielectric via 20 and the ramp section 311 can be flexibly arranged during layout design according to the actual wiring layer morphology and electrical requirements such as contact resistance, taking into account both electrical performance and impact resistance.

[0081] This disclosure also provides a display panel, including any of the array substrates described above. The display panel may be an OLED display panel. By employing the aforementioned array substrate and utilizing the projection layout rules between the internal wiring layer and the dielectric via 20, the overlap between the edge of the dielectric via 20 and the pattern boundary of the second wiring layer 32 is avoided, alleviating stress concentration at the root of the dielectric via 20 under impact loads. This results in the display panel exhibiting higher impact resistance in mechanical reliability tests such as pen drop and ball drop impacts, reducing the risk of failure phenomena such as bright spots during use.

[0082] refer to Figure 10 This disclosure also provides a display device including the aforementioned display panel. The display device can be any electronic device with display functionality, such as a mobile phone, tablet computer, laptop computer, automotive display, wearable display device, or foldable display device. By employing a display panel including the aforementioned array substrate, the overall mechanical reliability of the display device is improved, enabling it to maintain display integrity under unexpected conditions such as drops, pressure, or impacts, thereby enhancing product quality and user experience.

[0083] In the embodiments of this disclosure, unless the form of connection is explicitly defined, the connection can be a detachable connection such as a bolt and nut, screw, snap-fit, or magnetic connection. In some connections where there is no particular requirement for a non-detachable fit, a non-detachable connection can be achieved through welding, bonding, or other methods.

[0084] The terms "an embodiment" or "embodiment" used in this specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0085] It should be understood that “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something” but also “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “on top of something” but also “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0086] Furthermore, for ease of explanation, spatial relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of a component or feature relative to other components or features as shown in the figures. Spatial relative terms are intended to encompass different orientations of components in use or operation other than those shown in the figures. Devices may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0087] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0088] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications or equivalent substitutions made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An array substrate, characterized in that, include: Substrate; A multilayer dielectric layer is located on one side of the substrate, and at least a portion of the dielectric layer includes a plurality of dielectric holes that penetrate at least one layer of the dielectric layer, and the dielectric holes include at least one first dielectric hole; The multilayer wiring layer includes a first wiring layer and at least one second wiring layer, the second wiring layer being located between the first wiring layer and the substrate, and at least one dielectric layer being present between the first wiring layer and the second wiring layer; the first dielectric via exposes at least a portion of the first wiring layer. Wherein, the orthographic projection of the first dielectric via on the substrate is the first projection, the projection of the first trace layer on the substrate is the second projection, the orthographic projection of any second trace layer on the substrate is the third projection, the second projection covers the first projection, and the outer boundary contour of the third projection is located outside the first projection.

2. The array substrate according to claim 1, characterized in that, The first projection falls within the range of at least one of the third projections; or, The first projection is spaced apart from at least one of the third projections.

3. The array substrate according to claim 1, characterized in that, The first projection and all of the third projections are spaced apart.

4. The array substrate according to claim 1, characterized in that, The second wiring layer also includes at least one polysilicon layer; The third projection corresponding to the polycrystalline silicon layer is spaced apart from the first projection.

5. The array substrate according to claim 1, characterized in that, The distance between the outer boundary contour of the orthographic projection of any of the aforementioned dielectric vias on the substrate and the boundary contour of the orthographic projection of any of the aforementioned wiring layers on the substrate is greater than 0.5 micrometers. Preferably, the material of the dielectric layer includes an inorganic material; the material of the first trace layer includes molybdenum.

6. The array substrate according to claim 1, characterized in that, The first trace layer has a ramp section, and the outer boundary contour of the first projection is located outside the orthographic projection of the ramp section on the substrate. Preferably, the first projection is spaced apart from the orthographic projection of the climbing section on the substrate; or, the first projection covers the orthographic projection of the climbing section on the substrate.

7. An array substrate, characterized in that, include: Substrate; A multilayer dielectric layer is located on one side of the substrate, and at least a portion of the dielectric layer includes a dielectric via that penetrates at least one layer of the dielectric layer; The multilayer wiring layer includes a first wiring layer and a second wiring layer, the second wiring layer being located between the first wiring layer and the substrate, and at least one dielectric layer being present between the first wiring layer and the second wiring layer; the first dielectric via exposes a portion of the first wiring layer. Wherein, the orthographic projection of the first dielectric via on the substrate is the first projection, the projection of the first wiring layer on the substrate is the second projection, and the second projection covers the first projection; The first trace layer has a ramp section, and the outer boundary contour of the first projection is located outside the orthogonal projection of the ramp section on the substrate.

8. The array substrate according to claim 7, characterized in that, The first projection and the orthographic projection of the climbing section on the substrate are spaced apart; or... The first projection covers the orthographic projection of the ramp section onto the substrate.

9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 8.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

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