Array substrate, manufacturing method thereof and display panel

Abstract

The application discloses an array substrate and a manufacturing method thereof and a display panel. The array substrate comprises a first gate electrode, an active layer, a source electrode and a drain electrode. The active layer is arranged on one side of the first gate electrode. The source electrode and the drain electrode are arranged on one side of the active layer and connected with the active layer. The material of the active layer comprises a single crystal silicon material, and the surface roughness of the active layer is less than 8 nm. The single crystal silicon material is used to form the active layer, so that the mobility of the active layer can be effectively improved, and the driving current of the thin film transistor can be improved. In addition, the surface roughness of the active layer is less than 8 nm, the film layer uniformity is high, the yield of the active layer can be improved, and the reliability of the thin film transistor in the array substrate is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and its manufacturing method, and a display panel. Background Technology

[0002] Micro LED (Micro Light Emitting Diode) refers to an LED device with a pixel spacing on the order of micrometers. As a new generation of display technology, Micro LED display has the advantages of small size, wide color gamut, high brightness, and long lifespan. In addition, it has low operating voltage, high luminous efficiency, fast response speed, stable and reliable performance, and wide operating temperature range, which can well meet the needs of various scenarios and is the mainstream development direction of future micro display technology.

[0003] Currently, in Micro LED devices, IGZO (indium gallium zinc oxide) or LTPS TFT (low-temperature polycrystalline silicon thin-film transistor) are typically used as backplane driving devices to provide driving current. If a large driving current is required, the TFT size needs to be designed to be larger, which will affect the layout design and the aperture ratio of the Micro LED display. Since the mobility of the active layer made of IGZO and LTPS TFT is limited, it is difficult to further increase the driving current. Therefore, it is necessary to design new TFT devices or use active layer materials with higher mobility to further increase the driving current in order to achieve higher brightness and lower power consumption. Summary of the Invention

[0004] This application provides an array substrate and its fabrication method, as well as a display panel, which can improve the mobility of the active layer, the reliability of the thin-film transistors in the array substrate, and the driving current that can be passed through.

[0005] This application provides an array substrate, the array substrate comprising: First gate; An active layer is disposed on one side of the first gate; The source and drain are located on one side of the active layer and are connected to the active layer; The active layer is made of single-crystal silicon and has a surface roughness of less than 8 nm.

[0006] In one embodiment of this application, the surface roughness of the active layer is less than or equal to 4.5 nm.

[0007] In one embodiment of this application, hydrogen ions are distributed in the active layer, and the hydrogen ion content of the active layer on the side closer to the first gate is greater than the hydrogen ion content of the active layer on the side farther from the first gate.

[0008] In one embodiment of this application, the array substrate further includes: substrate; A first insulating layer is disposed on the substrate; The first gate is disposed on the side of the first insulating layer away from the substrate; The active layer is disposed on the side of the first gate away from the first insulating layer; The first gate is embedded in the first insulating layer.

[0009] In one embodiment of this application, Si-O-Si covalent bonds are formed between the first insulating layer and the substrate.

[0010] In one embodiment of this application, the thin-film transistor further includes a second gate disposed on the side of the active layer away from the first gate, and the second gate and the first gate are configured to be loaded with the same potential.

[0011] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a method for fabricating an array substrate, comprising: Form the first gate; An active layer is formed on one side of the first gate, the active layer being made of monocrystalline silicon and having a surface roughness of less than 8 nm. A source and a drain are formed on one side of the active layer, and the source and the drain are connected to the active layer.

[0012] In one embodiment of this application, the step of forming the first gate includes: Forming a single-crystal silicon film; A barrier layer is formed in the single-crystal silicon film; A separation layer is formed on one side of the barrier layer using a hydrogen ion implantation process, and an active material layer is formed in the single crystal silicon film on the side of the separation layer away from the barrier layer. A first gate is formed on the side of the active material layer away from the separation layer.

[0013] In one embodiment of this application, the step of forming an active layer on one side of the first gate includes: A first insulating layer is formed on the side of the first gate away from the active material layer; The first insulating layer is connected to the substrate, the bonding force between the first insulating layer and the substrate is greater than the bonding force between the active material layer and the separation layer, and the active material layer and the separation layer are separated. The active material layer is patterned to form the active layer.

[0014] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a display panel, the display panel comprising an array substrate as described above, or an array substrate manufactured by the method described above for manufacturing an array substrate.

[0015] This application provides an array substrate and its fabrication method, as well as a display panel. By using monocrystalline silicon material to form the active layer, the mobility of the active layer can be effectively improved, and the driving current that the thin-film transistors in the array substrate can pass through can be increased. In addition, the surface roughness of the active layer in this application is less than 8nm, which has high film uniformity, can improve the yield of the active layer, and thus improve the reliability of the thin-film transistors.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application; Figure 2 A flowchart illustrating a method for fabricating an array substrate provided in an embodiment of this application; Figures 3 to 6 This is a schematic diagram of the fabrication process of the array substrate provided in the embodiments of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] Please refer to Figure 1 This application provides an array substrate, which includes a first gate 11, an active layer 12, a source 13, and a drain 14.

[0022] The active layer 12 is disposed on one side of the first gate 11; the source 13 and the drain 14 are located on one side of the active layer 12 and are connected to the active layer 12.

[0023] The active layer 12 is made of single-crystal silicon and has a surface roughness of less than 8 nm.

[0024] In the implementation of the application, the array substrate provided in this application embodiment includes a thin-film transistor 10. By using single-crystal silicon material to form the active layer 12 in the thin-film transistor 10, the mobility of the active layer 12 can be effectively improved, and the driving current that the thin-film transistor 10 can pass through can be increased. In addition, the surface roughness of the active layer 12 in this application is less than 8nm, which has high film uniformity, can improve the yield of the active layer 12, and thus improve the reliability of the thin-film transistor 10.

[0025] Specifically, the array substrate 10 provided in this application embodiment includes a substrate 21 and a thin-film transistor array layer disposed on the substrate 21. The thin-film transistor array layer may include a plurality of thin-film transistors 10 arranged in an array, signal lines, and electrode components, etc.

[0026] In some embodiments, the thin-film transistor 10 may include a first gate 11, an active layer 12, a source 13, and a drain 14; wherein the first gate 11 is located on one side of the active layer 12 and is disposed corresponding to the channel of the active layer 12, while the source 13 and the drain 14 are located on the side of the active layer away from the first gate 11 or on the side of the active layer 12 close to the first gate 11, and are respectively connected to the opposite sides of the active layer 12 located in the channel.

[0027] In other embodiments of this application, the thin-film transistor may include a first gate 11, an active layer 12, a source 13, a drain 14, and a second gate 15. The first gate 11 and the second gate 15 are respectively located on opposite sides of the active layer 12 and are correspondingly disposed with respect to the channel of the active layer 12. The source 13 and the drain 14 may be located on the side of the active layer away from the first gate 11 or on the side of the active layer 12 away from the second gate 15, and are respectively connected to the opposite sides of the active layer 12 located in the channel. This allows the thin-film transistor 10 to have a top-bottom dual-gate structure.

[0028] Furthermore, the film structure of the thin-film transistor 10 will be described in detail below in conjunction with the film structure of the array substrate.

[0029] In some embodiments, the substrate 21 may be a glass substrate.

[0030] In some embodiments, the thin-film transistor array layer includes a first insulating layer 22 disposed on the substrate 21, a first gate 11 disposed on the first insulating layer 22, a first buffer layer 23 disposed on the first insulating layer 22 and covering the first gate 11, a second buffer layer 24 disposed on the first buffer layer 23, an active layer 12 disposed on the second buffer layer 24, a second insulating layer 25 disposed on the second buffer layer 24 and covering the active layer 12, a second gate 15 disposed on the second insulating layer 25, a third insulating layer 26 disposed on the second insulating layer 25 and covering the second gate 15, a capacitor plate 31 disposed on the third insulating layer 26, a fourth insulating layer 27 disposed on the third insulating layer 26 and covering the capacitor plate 31, a source 13 disposed on the fourth insulating layer 27, a drain 14, and a connection. The system comprises: a wire 32; a first planarization layer 28 disposed on the fourth insulating layer 27 and covering the source electrode 13, the drain electrode 14, and the connecting wire 32; a first dielectric layer 29 disposed on the first planarization layer 28; a first adapter wire 33 disposed on the first dielectric layer 29; a second planarization layer 210 disposed on the first dielectric layer 29 and covering the first adapter wire 33; a second dielectric layer 211 disposed on the second planarization layer 210; a second adapter wire 34 disposed on the second dielectric layer 211; a third planarization layer 212 disposed on the second dielectric layer 211 and covering the second adapter wire 34; a third dielectric layer 213 disposed on the third planarization layer 212; a first electrode 41 and a second electrode 42 disposed on the third dielectric layer 213; and a cover layer 214 disposed on the third dielectric layer 213 and covering part of the first electrode 41 and part of the second electrode 42.

[0031] In some embodiments, the active layer 12 is made of a semiconductor material, such as single-crystal silicon.

[0032] In some embodiments, the materials of the first gate 11, the second gate 15 and the capacitor plate 31 may be copper, molybdenum or molybdenum-titanium alloy, etc.

[0033] In some embodiments, the source electrode 13, the drain electrode 14, the connecting line 32, the first adapter line 33, the second adapter line 34, the first electrode 41, and the second electrode 42 may be made of copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium trilayer metal, etc.

[0034] In some embodiments, the materials of the first insulating layer 22, the first buffer layer 23, the second buffer layer 24, the second insulating layer 25, the third insulating layer 26, the fourth insulating layer 27, the first dielectric layer 29, the second dielectric layer 211, the third dielectric layer 213, and the cover layer 214 may be inorganic materials composed of silicon nitride, silicon oxide, or a combination of silicon oxynitride, or organic materials with planarity.

[0035] In some embodiments, the materials of the first planarization layer 28, the second planarization layer 210, and the third planarization layer 212 may be inorganic materials composed of silicon oxynitride or organic materials with planarity.

[0036] It should be noted that the thin-film transistor array layer has multiple conductive layers, and each conductive layer is a patterned film layer containing multiple conductive devices; the devices in the thin-film transistor 10 and each wiring electrode are all located in the multiple conductive layers; for example, the first gate 11 can be located in the first gate layer, the active layer 12 can be located in the semiconductor layer, the second gate 15 can be located in the second gate layer, the capacitor plate 31 can be located in the third gate layer, the source 13, the drain 14 and the connecting line 32 are all located in the first metal layer, the first adapter line 33 is located in the second metal layer, the second adapter line 34 is located in the third metal layer, and the first electrode 41 and the second electrode 42 are located in the fourth metal layer.

[0037] Understandable, Figure 1 Only some of the devices in the conductive layers are shown for illustrative purposes. These conductive layers also contain other devices and signal traces used to form the driving circuit. For example, the first gate layer, the second gate layer, and the third gate layer, in addition to forming the gate of the thin-film transistor 10, may also contain gate control lines connecting to the gate of the thin-film transistor 10; the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer, in addition to forming... Figure 1 In addition to the components, the device may also include data lines and other functional traces connected to the thin-film transistor 10, which are not specifically limited here.

[0038] In some embodiments, the first gate 11 is disposed on the side of the first insulating layer 22 away from the substrate 21, and the first gate 11 can be embedded in the first insulating layer 22, thereby increasing the film flatness on the side of the first insulating layer 22 away from the substrate 21, which is beneficial to improving the film yield above the first insulating layer 22.

[0039] In some embodiments, the surface of the first gate 11 on the side away from the substrate 21 is flush with the surface of the first insulating layer 22 on the side away from the substrate 21.

[0040] In some embodiments, Si-O-Si covalent bonds are formed between the first insulating layer 22 and the substrate 21; the material of the first insulating layer 22 can be silicon oxide, and the material of the substrate 21 also contains silicon oxide, thereby forming Si-O-Si covalent bonds between the first insulating layer 22 and the substrate 21, which can effectively improve the bonding strength between the first insulating layer 22 and the substrate 21 and reduce the probability of film peeling.

[0041] In some embodiments, the active layer 12 is disposed on the side of the second buffer layer 24 away from the first buffer layer 23, and the active layer 12 is located on the side of the first gate 11 away from the substrate 21; wherein, the active layer 12 may include a channel and source contact portions and drain contact portions located on opposite sides of the channel; the orthographic projection of the channel on the substrate 21 may be located within the coverage area of ​​the orthographic projection of the first gate 11 on the substrate 21; the source contact portion and the drain contact portion are semiconductor materials in the active layer 12 that have been doped, and the source contact portion is used to connect to the source 13, and the drain contact portion is used to connect to the drain 14.

[0042] In some embodiments, the second gate 15 is disposed on the second insulating layer 25 and located on the side of the active layer 12 away from the first gate 11; wherein the orthographic projection of the channel on the substrate 21 may be located within the coverage area of ​​the orthographic projection of the second gate 15 on the substrate 21.

[0043] In some embodiments, the capacitor plate 31 is disposed on the side of the third insulating layer 26 away from the second gate 15, and can be disposed opposite to the second gate 15 to form a capacitor, so as to store potential and couple voltage.

[0044] In some embodiments, the source 13, the drain 14, and the connecting line 32 are all located on the fourth insulating layer 27; wherein the source 13 and the drain 14 both pass through the fourth insulating layer 27, the third insulating layer 26, and the second insulating layer 25, and are connected to the source contact portion and the drain contact portion of the active layer 12; the connecting line 32 passes through the fourth insulating layer 27, the third insulating layer 26, the second insulating layer 25, the second buffer layer 24, and the first buffer layer 23, and is connected to the first gate 11 for applying a voltage signal to the first gate 11.

[0045] In some embodiments, the second gate 15 and the first gate 11 are configured to be loaded with the same potential; thus, the upper and lower gates work together to regulate the active layer 12, forming a dual conductive channel when turned on to increase the on-current, and depleting the channel on both sides when turned off to suppress the off-state leakage current; the dual gates can completely block light, weakening the photogenerated leakage effect of the active layer 12, while shielding the electric field coupling interference of the surrounding metal traces, reducing the device threshold drift and signal crosstalk problems; and the dual gates share a single control signal, which can simplify the backplane wiring layout and reduce the overall transistor layout area.

[0046] In this embodiment, the active layer 12 is made of monocrystalline silicon. By using monocrystalline silicon as the active layer 12 of the thin-film transistor 10, the carrier mobility of monocrystalline silicon is much higher than that of oxide and polycrystalline silicon materials, which can increase the driving current allowed by the thin-film transistor 10 and improve the charging and discharging rate of the circuit node, making it suitable for high-load driving scenarios. Furthermore, in this embodiment, the monocrystalline silicon active layer 12 can be combined with an equipotentially connected top-bottom dual-gate structure, and the upper and lower interfaces of the active layer 12 can simultaneously form dual conductive channels, further amplifying the conduction current advantage of the thin-film transistor 10.

[0047] It should be noted that, due to the limitations of existing processes, the uniformity of the monocrystalline silicon films produced by related technologies is poor, and the surface roughness is all above 8nm; the process yield is low, and incomplete peeling is prone to occur, resulting in uneven thickness of the monocrystalline silicon film.

[0048] In this embodiment, a specific process method is used to prepare the single-crystal silicon film, as detailed in subsequent embodiments. This results in better uniformity of the active layer 12, and the surface roughness of the active layer 12 is less than 8 nm. By using single-crystal silicon material to form the active layer 12, this embodiment can effectively improve the mobility of the active layer 12 and increase the driving current that the thin-film transistor 10 can pass through. Furthermore, the surface roughness of the active layer 12 in this application is less than 8 nm, which has high film uniformity, improving the yield of the active layer 12 and thus improving the reliability of the thin-film transistor 10.

[0049] In this embodiment, the active layer 12 can have a flat and uniform thin film surface, which can effectively optimize more than 10 electrical parameters of the thin film transistor and the overall device stability. Specifically, the flat interface of the active layer 12 can significantly reduce microscopic protrusions, depressions and lattice distortion defects on the film surface, making the bonding interface between the active layer 12 and adjacent film layers highly uniform, significantly reducing the interface trap state density, and effectively weakening the interface charge trapping and release effect. On the one hand, it can effectively stabilize the device threshold voltage (Vth), suppress threshold voltage drift caused by process deviations and working stress, and improve the stability of the array substrate. The device threshold voltage uniformity is improved; at the same time, the subthreshold swing (SS) can be significantly optimized, the switching steepness of the thin film transistor 10 can be improved, the off-state leakage current of the device can be reduced, the pixel charge retention capability can be improved, and it can be adapted to the display working scenarios of high resolution and low frequency constant display. On the other hand, the flat and defect-free single crystal silicon channel can greatly reduce the interface scattering and lattice scattering loss during the carrier transport process, reduce the carrier migration obstacle, effectively improve and stabilize the carrier mobility, and ensure that the thin film transistor 10 has sufficient and uniform conduction drive current to meet the driving requirements of high refresh rate backplane large RC load.

[0050] Furthermore, the low-roughness active layer 12 can significantly reduce the charge trapping hysteresis phenomenon during the positive and negative bias scanning process of the device, effectively reducing the electrical hysteresis effect of the thin-film transistor 10, improving the consistency of the hysteresis characteristics of each device in the array, and eliminating display defects such as uneven image and ghosting caused by differences in device electrical properties. At the same time, the flat active layer 12 can effectively alleviate film degradation and defect proliferation under long-term bias stress and illumination stress, greatly improving the long-term operating reliability and electrical performance stability of the thin-film transistor 10.

[0051] In some embodiments, the surface roughness of the active layer 12 can be 7.9nm, 7.5nm, 7nm, 6.5nm, 6nm, 5.5nm, 5nm, 4.5nm, 4nm, 3.5nm, 3nm, 2.5nm, 2nm, 1.5nm, 1nm, 0.5nm, or 0nm.

[0052] In some embodiments, the surface roughness of the active layer 12 is less than or equal to 4.5 nm.

[0053] In some embodiments, hydrogen ions are distributed in the active layer 12 through a specific process in this application embodiment. The hydrogen ion content of the active layer 12 on the side closer to the first gate 11 is greater than the hydrogen ion content of the active layer 12 on the side farther from the first gate 11. The higher hydrogen ion content can sufficiently passivate the interface dangling bonds between the active layer 12 and the second buffer layer 24, reduce the interface state density, improve the carrier transport efficiency, and reduce the threshold voltage drift amplitude under stress conditions, thereby improving the electrical properties of the thin film transistor 10.

[0054] It is understood that the hydrogen ion content in the active layer 12 can be molar content, mass content, or volume content; and the embodiments in this application are only used to illustrate the distribution of hydrogen ions in the active layer 12.

[0055] In some embodiments, the thickness of the active layer 12 may be greater than or equal to 400 nm and less than or equal to 500 nm; for example, the thickness of the active layer 12 may be 400 nm, 410 nm, 420 nm, 430 nm, 440 nm, 450 nm, 460 nm, 470 nm, 480 nm, 490 nm or 500 nm.

[0056] In some embodiments, the array substrate provided in this application can be used for a Micro LED display panel, and the positive and negative electrodes of the LED light-emitting element can be connected to the first electrode 41 and the second electrode 42 respectively to apply voltage to the LED light-emitting element.

[0057] In some embodiments, the array substrate provided in this application can also be used as an organic light-emitting diode display panel, in which case the first electrode 41 and the second electrode 42 can both be anodes, and the thin-film transistor 10 connected to the second electrode 42 is not shown.

[0058] In some embodiments, the array substrate provided in this application can also be used as a liquid crystal display panel, in which case the first electrode 41 and the second electrode 42 can both be pixel electrodes, and the thin film transistor 10 connected to the second electrode 42 is not shown.

[0059] Continuing from the above, this application provides a method for fabricating an array substrate, which includes a process for preparing the active layer 12 using a specific process. For details, please refer to... Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 as well as Figure 6 .

[0060] The method for manufacturing the array substrate includes the following steps: S10, Form the first gate 11.

[0061] S20. An active layer 12 is formed on one side of the first gate 11. The active layer 12 is made of single-crystal silicon and has a surface roughness of less than 8 nm.

[0062] S30. A source electrode 13 and a drain electrode 14 are formed on one side of the active layer 12, and the source electrode 13 and the drain electrode 14 are connected to the active layer 12.

[0063] In step S10, a single-crystal silicon film 121 is first formed.

[0064] A second buffer layer 24 is formed on one side of the single crystal silicon film 121, and the material of the second buffer layer 24 can be silicon oxide.

[0065] Then, a barrier layer 51 is formed in the single-crystal silicon film 121; specifically, the single-crystal silicon film 121 is subjected to B... + Ion implantation to form B + Ion blocking layer 51; due to B + The ions have a large mass, a short ion implantation projection range, and a concentrated distribution, which can then form the barrier layer 51, such as... Figure 3 As shown.

[0066] In some embodiments, the ion implanted element may also be other group III, group V or other heavy ion elements, such as P.

[0067] Next, a separation layer 52 is formed on one side of the barrier layer 51 using a hydrogen ion implantation process, and an active material layer 122 is formed in the single crystal silicon film 121 on the side of the separation layer 52 away from the barrier layer 51.

[0068] Specifically, using H + Ion implantation, H + Ions can form Si-HH-Si bonds with Si, forming a Si film separation layer. In other words, H... + It forms a bulk defect layer with Si, which can be separated by hot pressing, that is, it can be easily separated under high temperature and stress.

[0069] However, this application has found through research that, due to H + The small ion mass and long ion implantation projection range make diffusion very easy, which makes it impossible to form a uniform separation film layer. This results in extremely poor uniformity of the separated monocrystalline silicon film, or even complete separation, and extremely low yield. For example, the peeling yield of monocrystalline silicon films in related technologies is only 70-80%, and there are also instances of single-crystal silicon film peeling failure.

[0070] Therefore, the embodiments of this application utilize high concentrations of B + Injection forms the barrier layer 51, allowing H+ Ion implantation distribution is more concentrated; that is, by forming B + Ion blocking layer 51 is beneficial for blocking H + Ion implantation diffusion causes H + The ion implantation distribution is more concentrated, forming a uniform Si film separation layer 52, which makes the subsequent Si film easier to separate and the separation interface more uniform, so as to obtain a more uniform single crystal silicon film.

[0071] It should be noted that in the embodiments of this application, B + and H + The ion implantation depth can be obtained by simulation using ion stopping and range of ions in matter (SRIM).

[0072] Then, a first gate 11 is formed on the side of the active material layer 122 away from the separation layer 52.

[0073] Specifically, a SiN layer is deposited on the side of the second buffer layer 24 away from the separation layer 52 to form the first buffer layer 23.

[0074] Then, a gate metal layer is deposited on the side of the first buffer layer 23 away from the second buffer layer 24, and the gate metal layer is patterned to form the first gate 11.

[0075] Then, in step S20, the active material layer 122 and the separation layer 52 are separated to form the active layer 12.

[0076] Specifically, a first insulating layer 22 is formed on the side of the first gate 11 away from the active material layer 122; wherein, a SiO layer is deposited on the side of the first buffer layer 23 away from the second buffer layer 24, i.e., the first insulating layer 22 is formed, which can serve as a barrier layer, such as... Figure 4 As shown.

[0077] Next, the first insulating layer 22 is connected to the substrate 21. The bonding force between the first insulating layer 22 and the substrate 21 is greater than the bonding force between the active material layer 122 and the separation layer 52, and the active material layer 122 and the separation layer 52 are separated. For example, an anodic bonding process can be used to connect the first insulating layer 22 and the substrate 21.

[0078] In some embodiments, the substrate 21 is a glass substrate.

[0079] It should be noted that the embodiment of this application achieves the connection between the first insulating layer 22 and the substrate 21 through anodizing bonding process. The specific process includes: firstly, accurately aligning and bonding the component with the first insulating layer 22 to the substrate 21; applying a DC high voltage electrostatic field under high temperature environment; the electric field drives the migration of alkali metal ions inside the substrate 21; and the oxygen ions at the interface undergo a translayer chemical reaction, forming a continuous Si-O-Si covalent bond between the first insulating layer 22 and the substrate 21, realizing glue-free, hermetic, integrated bonding. The overall process has high cleanliness and strong interface bonding, avoiding defects such as gas release and device contamination caused by intermediate adhesive layers.

[0080] It should be noted that, due to the high-temperature environment and external stress during the anodic bonding process, the active material layer 122 and the separation layer 52 can separate. Figure 5 As shown; to obtain a single-crystal silicon film with better uniformity, such as Figure 6 As shown.

[0081] Then, the active material layer 122 is patterned to form the active layer 12.

[0082] It should be noted that, in this embodiment, hydrogen ions are blocked by the barrier layer 51 to prevent hydrogen ion diffusion, resulting in the hydrogen ions on the side of the active material layer 122 away from the first gate 11 being concentrated in the separation layer 52. Consequently, after the active material layer 122 separates from the separation layer 52, the hydrogen ion content of the formed active layer 12 on the side away from the first gate 11 is lower and less than the hydrogen ion content on the side of the active layer 12 close to the first gate 11. That is, the hydrogen ion content distribution in the active layer 12 in this embodiment is a specific ion distribution generated by forming a single-crystal silicon film using a specific process in this embodiment.

[0083] Next, in step S30, a second gate, a capacitor plate 31, a source 13, a drain 14, a connecting line 32, a first adapter line 33, a second adapter line 34, a first electrode 41, a second electrode 42, and a plurality of insulating layers, planarization layers, dielectric layers and capping layers are sequentially formed on the side of the active layer 12 away from the first gate 11.

[0084] It is understood that the active layer 12 with high uniformity is formed according to a specific single-crystal silicon film preparation process in this application embodiment, and other devices and film structures on the side of the active layer 12 away from the first gate 11 can be implemented with reference to conventional processes, and will not be described in detail here.

[0085] In this embodiment, the active layer 12 is formed using single-crystal silicon material, which can effectively improve the mobility of the active layer 12 and increase the driving current that the thin-film transistor 10 can pass through. In addition, the surface roughness of the active layer 12 in this application is less than 8nm, which has high film uniformity, can improve the yield of the active layer 12, and thus improve the reliability of the thin-film transistor 10.

[0086] In addition, this application provides a display panel, which includes an array substrate as described in the above embodiments, or an array substrate manufactured by the method described in the above embodiments.

[0087] In some embodiments, the display panel can be a Micro LED display panel, and the positive and negative electrodes of the LED light-emitting element can be connected to the first electrode 41 and the second electrode 42 respectively to apply voltage to the LED light-emitting element.

[0088] In some embodiments, the display panel may be an organic light-emitting diode display panel, in which case the first electrode 41 and the second electrode 42 may both be anodes, and the thin-film transistor 10 connected to the second electrode 42 is not shown.

[0089] The display panel may further include a light-emitting layer disposed on the first electrode 41, a cathode layer disposed on the light-emitting layer, and an encapsulation layer disposed on the cathode layer.

[0090] In some embodiments, the display panel may be a liquid crystal display panel, in which case the first electrode 41 and the second electrode 42 may both be pixel electrodes, and the thin-film transistor 10 connected to the second electrode 42 is not shown.

[0091] The display panel may further include a counter substrate disposed opposite to the array substrate and a liquid crystal layer located between the array substrate and the counter substrate.

[0092] Furthermore, this application also provides a display device, which includes a display panel as described in the above embodiments.

[0093] In some embodiments, the display device may include a mobile phone, computer, tablet, television, wearable device, and virtual reality display device, etc.

[0094] It is understood that since the display panel and the display device have the same array substrate as in the above embodiments, the display panel and the display device have the same beneficial effects as the array substrate in the above embodiments, and will not be repeated here.

[0095] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0096] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0097] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0098] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, characterized in that, The array substrate includes: First gate; An active layer is disposed on one side of the first gate; The source and drain are located on one side of the active layer and are connected to the active layer; The active layer is made of single-crystal silicon and has a surface roughness of less than 8 nm.

2. The array substrate according to claim 1, characterized in that, The surface roughness of the active layer is less than or equal to 4.5 nm.

3. The array substrate according to claim 1, characterized in that, Hydrogen ions are distributed in the active layer, and the hydrogen ion content of the active layer on the side closer to the first gate is greater than the hydrogen ion content of the active layer on the side farther away from the first gate.

4. The array substrate according to any one of claims 1 to 3, characterized in that, The array substrate further includes: substrate; A first insulating layer is disposed on the substrate; The first gate is disposed on the side of the first insulating layer away from the substrate; The active layer is disposed on the side of the first gate away from the first insulating layer; The first gate is embedded in the first insulating layer.

5. The array substrate according to claim 4, characterized in that, Si-O-Si covalent bonds are formed between the first insulating layer and the substrate.

6. The array substrate according to claim 1, characterized in that, The thin-film transistor further includes a second gate disposed on the side of the active layer away from the first gate, and the second gate and the first gate are configured to be loaded with the same potential.

7. A method for fabricating an array substrate, characterized in that, include: Form the first gate; An active layer is formed on one side of the first gate, the active layer being made of monocrystalline silicon and having a surface roughness of less than 8 nm. A source and a drain are formed on one side of the active layer, and the source and the drain are connected to the active layer.

8. The method for fabricating an array substrate according to claim 7, characterized in that, The step of forming the first gate includes: Forming a single-crystal silicon film; A barrier layer is formed in the single-crystal silicon film; A separation layer is formed on one side of the barrier layer using a hydrogen ion implantation process, and an active material layer is formed in the single crystal silicon film on the side of the separation layer away from the barrier layer. A first gate is formed on the side of the active material layer away from the separation layer.

9. The method for fabricating an array substrate according to claim 8, characterized in that, The step of forming an active layer on one side of the first gate includes: A first insulating layer is formed on the side of the first gate away from the active material layer; The first insulating layer is connected to the substrate, the bonding force between the first insulating layer and the substrate is greater than the bonding force between the active material layer and the separation layer, and the active material layer and the separation layer are separated. The active material layer is patterned to form the active layer.

10. A display panel, characterized in that, The display panel includes an array substrate as described in any one of claims 1 to 6, or an array substrate manufactured by a method described in any one of claims 7 to 9.

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