Array substrate and display panel

Abstract

The present disclosure provides an array substrate and a display panel, the array substrate comprising a substrate and a driving point circuit layer, the driving circuit layer being located on the substrate, the driving circuit layer comprising a plurality of pixel circuits, the plurality of pixel circuits being arranged in an array on the substrate, in a first direction, adjacent pixel circuits PX are arranged in mirror symmetry, in a second direction, adjacent pixel circuits are arranged in mirror symmetry, the first direction intersects the second direction. In the present application, by arranging adjacent pixel circuits in mirror symmetry along the first direction and the second direction, the space design can be maximized to achieve higher pixel arrangement density, while the display effect can also be guaranteed.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is to provide an array substrate and a display panel that aim to improve the performance of the array substrate.

[0005] For the purposes described above, this disclosure discloses an array substrate, which includes a substrate and a driving point circuit layer. The driving circuit layer is located on the substrate and includes a plurality of pixel circuits. The plurality of pixel circuits are arranged in an array on the substrate. In a first direction, at least one transistor in an adjacent pixel circuit is arranged in a mirror symmetrical manner. In a second direction, at least one transistor in an adjacent pixel circuit is arranged in a mirror symmetrical manner. The first direction intersects the second direction.

[0006] In one embodiment, the driving circuit layer further includes a semiconductor layer and a first conductive layer. The semiconductor layer includes active portions of each pixel circuit. The first conductive layer is located on the side of the semiconductor layer away from the substrate. The first conductive layer includes a plurality of first conductive portions. The orthographic projections of the semi-active portions and the first conductive portions on the substrate extend along a first direction and / or a second direction.

[0007] In one embodiment, the active portions of the plurality of transistors in the pixel circuit are all located in the same semiconductor layer.

[0008] In one embodiment, the plurality of first conductive portions include a plurality of light-emitting connecting portions, the light-emitting connecting portions extending along a first direction, the light-emitting connecting portions being located between active portions disposed adjacent to each other in the first direction, and the two ends of the light-emitting connecting portions in the first direction respectively at least partially overlapping the active portions disposed adjacent to each other in the first direction.

[0009] In one embodiment, the plurality of first conductive portions include a plurality of scanning connection portions. The scanning connection portions extend along a first direction and are located between adjacent active portions disposed in the first direction. The two ends of the scanning connection portions in the first direction respectively at least partially overlap with the adjacent active portions disposed in the first direction. The orthographic projection of the scanning connection portions on the substrate is located between the orthographic projections of adjacent light-emitting connection portions on the substrate in the second direction.

[0010] In one embodiment, the driving circuit layer further includes a plurality of light-emitting signal units, which are located on the side of the light-emitting connection unit away from the substrate. The orthographic projection of one light-emitting signal unit on the substrate overlaps with the orthographic projection of a plurality of light-emitting connection units arranged along a first direction on the substrate. The orthographic projection of one light-emitting signal unit on the substrate overlaps with the orthographic projection of a plurality of active units arranged along the first direction on the substrate. The light-emitting connection unit is electrically connected to the light-emitting signal unit. The plurality of light-emitting signal units are spaced apart along a second direction, and each light-emitting signal unit extends continuously along the first direction.

[0011] In one embodiment, the pixel circuit further includes a plurality of scanning signal units located on the side of the scanning connection unit away from the substrate. The orthographic projection of one scanning signal unit on the substrate overlaps with the orthographic projections of a plurality of scanning connection units arranged along a first direction on the substrate. The orthographic projection of one scanning signal unit on the substrate overlaps with the orthographic projections of a plurality of active units arranged along the first direction on the substrate. The scanning connection unit is electrically connected to the scanning signal unit. The plurality of scanning signal units are spaced apart along a second direction, and each scanning signal unit extends continuously along the first direction.

[0012] In one embodiment, the driving circuit layer further includes a plurality of reset signal lines. The reset signal lines are located on one side of the back substrate of the first conductive layer and extend along a first direction. The orthogonal projection of the reset signal lines on the substrate is located between adjacent active portions disposed in a second direction and connects to the adjacent active portions disposed in the second direction.

[0013] In one embodiment, the pixel circuit further includes a storage capacitor, which includes a first electrode and a second electrode. The first electrode is located on a first conductive layer, and the second electrode is located on the side of the first electrode away from the substrate.

[0014] In one embodiment, the pixel circuit further includes a power signal line, which includes a power connection portion and a power signal portion. The power connection portion is disposed on the same layer as the second electrode plate. The power connection portion extends along a first direction and is connected to the second electrode plate adjacent to it in the first direction. The power signal portion is located on the side of the power connection portion away from the substrate. The power connection portion extends continuously along a second direction.

[0015] In one embodiment, the pixel circuit further includes data signal lines, which are disposed on the same layer as the power signal section. The data signal lines extend continuously along a second direction, and the orthographic projection of the data signal lines on the substrate is located between the orthographic projections of adjacent power signal sections on the substrate. Adjacent data signal lines are disposed close to each other or spaced apart by at least two power signal sections.

[0016] In one embodiment, the array substrate includes a display area and a non-display area located at least partially surrounding the display area. The non-display area includes a first border area and a second border area disposed in a second direction of the display area. The driving circuit layer also includes a plurality of first capacitors located in the first border area or the second border area, and the first capacitors are electrically connected to data signal lines.

[0017] In one embodiment, the driving circuit layer further includes multiple adapters, which are disposed on the same layer as the light-emitting signal section. Some adapters are electrically connected to a partial scanning signal section and a scanning connection section, and some adapters are electrically connected to a power signal section and a power connection section.

[0018] Based on the same inventive concept, this disclosure also provides a display panel that includes the array substrate described above.

[0019] Compared with the prior art, the array substrate and display panel disclosed herein provide a design that maximizes space saving, achieves higher pixel density, and ensures display effect, in which the adjacent pixel circuits in the array substrate are mirror-symmetrically arranged along a first direction and a second direction. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the display panel structure provided in an embodiment of this application;

[0022] Figure 2 Schematic diagram of the array substrate structure provided in the embodiments of this application Figure 1 ;

[0023] Figure 3 Schematic diagram of the array substrate structure provided in the embodiments of this application Figure 2 ;

[0024] Figure 4 This is a schematic diagram of the pixel circuit in the array substrate provided in the embodiments of this application;

[0025] Figure 5 This is a partial structural diagram of the array substrate provided in an embodiment of the present invention. Figure 1 ;

[0026] Figure 6 This is a partial structural diagram of the array substrate provided in an embodiment of the present invention. Figure 2 ;

[0027] Figure 7 This is a partial structural diagram of the array substrate provided in an embodiment of the present invention. Figure 2 ;

[0028] Figure 8 This is a partial structural diagram of the array substrate provided in an embodiment of the present invention. Figure 4 ;

[0029] Figure 9 This is a partial structural diagram of the array substrate provided in an embodiment of the present invention. Figure 5 ;

[0030] Figure 10 This is a partial structural diagram of the array substrate provided in an embodiment of the present invention. Figure 6 ;

[0031] Figure 11 This is a partial structural diagram of the array substrate provided in an embodiment of the present invention. Figure 7 ;

[0032] Figure 12 This is a partial structural diagram of the array substrate provided in an embodiment of the present invention. Figure 8 ;

[0033] Figure 13 This is a partial structural diagram of the array substrate provided in an embodiment of the present invention. Figure 9 . Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0035] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] As a carrier of information and a window for human-computer interaction in the digital age, displays have become an important interface for people to receive visual information, continuously influencing people's lives and the development of the economy and society. It is worth mentioning that with technological advancements and the ever-increasing demands for information interaction, commercial displays are integrating into life at an unprecedented pace. Examples include the integration of various forms of commercial display screens with the environment and the application of augmented reality (AR), virtual reality (VR), and holographic projection functions.

[0037] Due to limitations in array and OLED segment process capabilities within the current OLED display industry, the current 7T1C circuit structure can only achieve a size of 600-800 PPI, making further exploration impossible. Therefore, there is a problem that current OLED display technology cannot be applied to the AR / VR field.

[0038] For the reasons stated above, this application provides an array substrate comprising a substrate and a driving point circuit layer. The driving circuit layer is located on the substrate and includes multiple pixel circuits PX. The multiple pixel circuits PX are arranged in an array on the substrate. Adjacent pixel circuits PX are mirror-symmetrically arranged in a first direction and in a second direction. The first and second directions intersect. By mirror-symmetrically arranging adjacent pixel circuits PX along the first direction (X direction) and the second direction (Y direction), this application maximizes space-saving design to achieve higher pixel density while ensuring display quality.

[0039] Next, combine Figures 1-13The array substrate provided in this application embodiment includes a substrate 10 and a driving circuit layer disposed on the substrate 10. The substrate 10 may be, but is not limited to, any one of a conductive silicon (Si) substrate, a silicon oxide (SiOx) substrate, an aluminum oxide (Al2O3) substrate (i.e., a sapphire substrate), a silicon carbide (SiC) substrate, or a gallium nitride (GaN) substrate. Furthermore, the substrate may also be a flexible substrate, such as a flexible substrate made of polyimide (PI).

[0040] In terms of the film structure, the driving circuit layer includes multiple conductive layers and an insulating layer disposed between adjacent conductive layers.

[0041] refer to Figure 2 In an optional embodiment, the conductive layer may include a semiconductor layer PSI, a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, a fourth conductive layer M4, and a fifth conductive layer M5 sequentially disposed along a direction away from the substrate 10. The insulating layer includes a gate insulating layer GI between the semiconductor layer PSI and the first conductive layer M1, a capacitor insulating layer CI between the first conductive layer M1 and the second conductive layer M2, a first interlayer dielectric layer ILD1 between the second conductive layer M2 and the third conductive layer M3, a second interlayer dielectric layer ILD2 between the third conductive layer M3 and the fourth conductive layer M4, and a third interlayer dielectric layer ILD3 between the fourth conductive layer M4 and the fifth conductive layer M5.

[0042] refer to Figure 3 In another optional embodiment, the conductive layer may include a semiconductor layer PSI, a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, and a fourth conductive layer M4 disposed sequentially along a direction away from the substrate 10, and the insulating layer includes a gate insulating layer GI between the semiconductor layer PSI and the first conductive layer M1, a capacitor insulating layer CI between the first conductive layer M1 and the second conductive layer M2, a first interlayer dielectric layer ILD1 between the second conductive layer M2 and the third conductive layer M3, and a second interlayer dielectric layer ILD2 between the third conductive layer M3 and the fourth conductive layer M4.

[0043] In one example, the first conductive layer M1 includes a plurality of first conductive portions 30. The plurality of first conductive portions 30 may include a plurality of spaced-apart light-emitting connection portions 31, or a plurality of spaced-apart scanning connection portions 33. At least some of the first conductive portions have their two ends in the first direction projected onto the substrate in an orthogonal projection that overlaps at least partially with the orthogonal projection of the adjacent active portions in the first direction onto the substrate, so that adjacent active portions can share light-emitting signals and scanning signals.

[0044] refer to Figures 4-13The driving circuit layer also includes multiple pixel circuits PX. The orthographic projections of the multiple pixel circuits PX on the substrate 10 are distributed in an array along a first direction (X direction) and a second direction (Y direction), and the first direction (X direction) and the second direction (Y direction) intersect, that is, the multiple pixel circuits PX are arranged in an array. In the first direction (X direction), at least one transistor in two adjacent pixel circuits PX is mirror-symmetrically arranged along the first direction (X direction), and in the second direction (Y direction), at least one transistor in two adjacent pixel circuits PX is mirror-symmetrically arranged along the second direction (Y direction). In this embodiment, by arranging adjacent pixel circuits PX mirror-symmetrically along the first direction (X direction) and the second direction (Y direction), space saving design can be maximized to achieve a higher pixel density, while also ensuring display effect.

[0045] In one embodiment, the pixel circuit PX may include multiple thin-film transistors, all of which are manufactured using PSI technology. This PSI technology is highly mature and has few defects, thereby further ensuring the display effect of high PPI products.

[0046] For example, multiple thin-film transistors are all low-temperature polycrystalline silicon (LTPS) transistors, which can be either N-type or P-type. If multiple thin-film transistors in the pixel circuit PX are all P-type transistors, costs can be reduced, the space occupied by the pixel circuit PX can be reduced, and it is easier to increase the pixel density of the display panel.

[0047] In one embodiment, the multiple thin-film transistors in the pixel circuit PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The semiconductor layer PSI includes active portions 20 of each pixel circuit PX. Adjacent active portions 20 in a first direction (X direction) are mirror-symmetrically arranged along the first direction (X direction), and adjacent active portions 20 in a second direction (Y direction) are mirror-symmetrically arranged along the second direction (Y direction). Each active portion 20 includes multiple interconnected active regions, such as active region 21 of the first transistor T1, active region 22 of the second transistor T2, active region 23 of the third transistor T3, active region 24 of the fourth transistor T4, active region 25 of the fifth transistor T5, and active region 26 of the sixth transistor T6. The active regions 24 of the fourth transistor T4 in two active portions symmetrically arranged along the second direction (Y direction) are interconnected.

[0048] For example, the active portions 20 of multiple transistors in each pixel circuit PX are disposed on the semiconductor layer PSI, the gates of each thin-film transistor are disposed on the first conductive layer M1, and the sources and drains of each thin-film transistor are disposed on the third conductive layer M3. Therefore, in this application, the active portions 20 of all pixel circuits PX are located in one layer. Compared with the double-layer TFT structure, this further improves the stability of the thin-film transistors in the pixel circuit PX and avoids the problem of poor performance of thin-film transistors due to the flatness of the film layers.

[0049] The first transistor T1 is a driving transistor. The gate of the first transistor T1 is electrically connected to the first node G, the first terminal is electrically connected to the second node S, and the second terminal is electrically connected to the third node. The first transistor T1 is configured to generate a driving current under the control of the voltage difference (Vgs) between the first node G and the second node S. This driving current is used to drive the light-emitting device 70 to emit light.

[0050] The second transistor T2 can be a data writing transistor. The gate of the second transistor T2 is electrically connected to the second scan signal line Sn2, the first terminal is electrically connected to the data signal line Date, and the second terminal is electrically connected to the second node S. In addition, the first terminal of the second transistor T2 is also used as an access point for accessing data signals.

[0051] The third transistor T3 can be a threshold compensation transistor. The gate of the third transistor T3 is electrically connected to the second scan signal line Sn2, the first terminal is electrically connected to the first node G, and the second terminal is electrically connected to the second node S. The second transistor T2 and the third transistor T3 are configured to be turned on or off under the control of the second scan signal line Sn2. When the second transistor T2 and the third transistor T3 are turned on, the second transistor T2 transmits the data signal transmitted by the data signal line Date to the first node G. After the data signal passes through the first transistor T1 and the third transistor T3 in sequence, it completes the compensation of the threshold voltage Vth of the first transistor T1 and is transmitted to the first node G, thereby improving the display uniformity of the display panel.

[0052] The fourth transistor T4 can be a first initialization transistor. The gate of the fourth transistor T4 is electrically connected to the first scan signal line Sn1, its first terminal is electrically connected to the reset signal line Vref, and its second terminal is electrically connected to the first node G. The reset signal line Vref can be used to provide a constant reference voltage; exemplarily, the reference voltage can be a negative voltage. The fourth transistor T4 is configured to be turned on or off under the control of the first scan signal line Sn1. When the fourth transistor T4 is on, it can electrically connect the reset signal line Vref to the first node G, thereby transmitting the reference voltage of the reset signal line Vref to the first node G and initializing (resetting) the potential of the first node G. In this embodiment, the fourth transistor T4 and the fourth transistor T5 can be single-gate structures.

[0053] The fifth transistor T5 can be the first light-emitting control transistor. The gate of the fifth transistor T5 is electrically connected to the light-emitting signal line EM, the first terminal is electrically connected to the first voltage signal line VDD, and the second terminal is electrically connected to the second node S.

[0054] The sixth transistor T6 can be the second light-emitting control transistor. The gate of the sixth transistor T6 is electrically connected to the light-emitting signal line EM, the first terminal is electrically connected to the third node D, and the second terminal is electrically connected to the fourth node; the fourth node is also electrically connected to the light-emitting device 70 (e.g., the anode pattern of the light-emitting device 70). The first voltage signal line VDD is configured to provide a constant positive power supply voltage. The fifth transistor T5 and the sixth transistor T6 are configured to be turned on or off under the control of the light-emitting signal line EM. When the fifth transistor T5 and the sixth transistor T6 are on, the fifth transistor T5 electrically connects the first voltage signal line VDD to the second node S. At this time, the third transistor T3 generates a drive current under the control of the voltages of the first node G and the second node S. The sixth transistor T6 transmits this drive current to the light-emitting device 70, driving the light-emitting device 70 to emit light.

[0055] The pixel circuit PX also includes a storage capacitor Cst, which comprises a first plate C1 and a second plate C2. The first plate C1 is located on the first conductive layer M1, and the second plate C2 is located on the second conductive layer M2. The orthographic projection of the first plate C1 onto the substrate 10 at least partially overlaps with the orthographic projection of the second plate C2 onto the substrate 10. The first plate C1 of the storage capacitor Cst can be electrically connected to the first node G, and the second plate C2 can be electrically connected to the power signal line VDD. The storage capacitor Cst can store and maintain the voltage of the first node G, ensuring a stable drive current generated by the first transistor T1 within one frame period.

[0056] For example, a plurality of third vias 91 and a plurality of fourth vias 92 are provided on the first interlayer dielectric layer ILD1, wherein the third vias 91 also penetrate the capacitor insulating layer, the third vias 91 expose at least a portion of the first electrode C1, the fourth vias 92 expose at least a portion of the second electrode C2, the third conductive layer M3 is connected to the first electrode C1 through the third vias 91, and the third conductive layer M3 is connected to the second electrode C2 through the fourth vias 92, wherein the third vias 91 and the fourth vias 92 are both located on the same side of the first transistor TI in the second direction (Y direction). This design can further save the arrangement space of the third conductive layer.

[0057] For example, the storage capacitor Cst includes a first plate C1 that can be reused as the gate of the first transistor T1.

[0058] The pixel circuit PX in this application has a 6T1C circuit structure, eliminating the thin-film transistor for anode reset; the anode reset is implemented by the GIP function. Of course, the pixel circuit PX in this application can also have other circuit structures, such as a 7T1C circuit structure.

[0059] In one embodiment, the pixel circuit PX may further include a light-emitting signal line EM. The light-emitting signal line EM includes a light-emitting connection portion 31 and a light-emitting signal portion 32. The light-emitting connection portion 31 is located on the side of the light-emitting signal portion 32 closer to the substrate 10. The orthographic projection of the light-emitting connection portion 31 on the substrate 10 at least partially overlaps with the orthographic projection of the light-emitting signal portion 32 on the substrate 10, and the light-emitting connection portion 31 is electrically connected to the light-emitting signal portion 32. By layering the light-emitting signal line EM, signal connectivity is ensured while maximizing the saving of wiring space (such as the first conductive layer M1) in the layer where the light-emitting connection portion 31 is located.

[0060] In one example, the light-emitting connection portion 31 is located in the first conductive layer M1. The light-emitting connection portion 31 is disposed in the same layer as the first electrode plate C1 of the storage capacitor. The light-emitting connection portion 31 extends along the first direction (X direction). The orthographic projection of the light-emitting connection portion 31 on the substrate is located between the active portions 20 disposed adjacent to each other in the first direction (X direction). The projections of the two ends of the light-emitting connection portion 31 on the substrate 10 in the first direction (X direction) at least partially overlap with the projections of the active portions 20 disposed adjacent to each other in the first direction (X direction) on the substrate 10. This design allows the two active portions 20 disposed adjacent to each other in the first direction (X direction) to share the same light-emitting signal, thereby saving the wiring space of the layer where the light-emitting connection portion 31 is located (such as the first conductive layer M1) and ensuring the capacitor area of ​​the first electrode plate C1. Specifically, the overlapping portion of the orthographic projection of the end of the light-emitting connection portion 31 in the first direction (X direction) onto the substrate 10 and the orthographic projection of the active region of the fifth transistor T5 onto the substrate 10 forms the gate of the fifth transistor T5. Since the adjacent pixel circuits PX are arranged in a mirror symmetry, some of the light-emitting connection portions 31 can be connected to the gates of two adjacent fifth transistors T5, thereby allowing the fifth transistors T5 in two adjacent pixel circuits PX to share a light-emitting signal. Similarly, the overlapping portion of the orthographic projection of the end of the light-emitting connection portion 31 in the first direction (X direction) onto the substrate 10 and the orthographic projection of the active region of the sixth transistor T6 onto the substrate 10 forms the gate of the sixth transistor T6. Since the adjacent pixel circuits PX are arranged in a mirror symmetry, some of the light-emitting connection portions 31 can be connected to the gates of two adjacent sixth transistors T6, thereby allowing the sixth transistors T6 in two adjacent pixel circuits PX to share a light-emitting signal.

[0061] In one example, the light-emitting signal section 32 is located on the side of the light-emitting connection section 31 facing away from the substrate 10. The light-emitting connection section 31 is electrically connected to the light-emitting signal section 32. Multiple light-emitting signal sections 32 are spaced apart along a second direction (Y direction), and each light-emitting signal section 32 extends continuously along a first direction (X direction). The orthographic projection of one light-emitting signal section 32 on the substrate 10 at least partially overlaps with the orthographic projections of multiple light-emitting connection sections 31 arranged along the first direction (X direction) on the substrate 10. Similarly, the orthographic projection of one light-emitting signal section 32 on the substrate 10 at least partially overlaps with the orthographic projections of multiple active sections 20 arranged along the first direction (X direction) on the substrate 10; that is, one light-emitting signal section 32 can connect to multiple light-emitting connection sections in the first direction. In this example, the light-emitting signal section 32 is located in the third conductive layer M3.

[0062] In one embodiment, the pixel circuit PX may further include a scan signal line Sn. The orthographic projection of the scan signal line Sn on the substrate 10 lies between the orthographic projections of adjacent light-emitting signal lines EM on the substrate 10. The scan signal line Sn includes multiple scan connection portions 33 and multiple scan signal portions 34. The scan connection portions 33 are disposed on the same layer as the light-emitting connection portions 31. The scan signal portions 34 are located on the side of the scan connection portions 33 facing away from the substrate 10. The orthographic projection of the scan connection portions 33 on the substrate 10 lies between the orthographic projections of adjacent light-emitting connection portions 31 on the substrate 10. The orthographic projection of the scan signal portions 34 on the substrate 10 lies between the orthographic projections of adjacent light-emitting signal portions 32 on the substrate 10. The orthographic projections of the scan connection portions 33 and the scan signal portions 34 on the substrate 10 at least partially overlap. The scan connection portions 33 and the scan signal portions 34 are electrically connected. By layering the scan signal lines Sn, signal connectivity is ensured while maximizing the saving of wiring space (such as the first conductive layer M1) in the layers containing the light-emitting connection portions 31 and the scan connection portions 33.

[0063] In one example, the scanning connection portion 33 is located in the first conductive layer M1. The scanning connection portion 33 extends along a first direction (X direction). The orthographic projection of the scanning connection portion 33 on the substrate lies between the active portions 20 adjacent to each other in the first direction (X direction). The orthographic projections of the two ends of the scanning connection portion 33 in the first direction (X direction) on the substrate at least partially overlap with the projections of the active portions 20 adjacent to each other in the first direction (X direction) on the substrate 10. The orthographic projection of the scanning connection portion 33 on the substrate 10 lies between the orthographic projections of the adjacent light-emitting connection portions 31 in the second direction (Y direction) on the substrate 10. This design allows two active portions 20 adjacent to each other in the first direction (X direction) to share the same scanning signal, thereby saving wiring space in the layer where the scanning connection portion 33 is located (such as the first conductive layer M1) and ensuring the maximum area of ​​the capacitor of the first electrode C1. Specifically, the portion of the partial scan connection 33 projected onto the substrate 10 in the first direction (X direction) overlaps with the portion of the active region of the second transistor T2 projected onto the substrate 10 to form the gate of the second transistor T2. Since the adjacent pixel circuits PX are mirror-symmetrically arranged, the partial scan connection 33 can connect the gates of two adjacent second transistors T2, thereby allowing the second transistors T2 in the two adjacent pixel circuits PX to share a scan signal. Similarly, the portion of the partial scan connection first part 33 projected onto the substrate 10 in the first direction (X direction) overlaps with the portion of the active region of the fourth transistor T4 projected onto the substrate 10 to form the gate of the fourth transistor T4. Since the adjacent pixel circuits PX are mirror-symmetrically arranged, the partial scan connection 33 can connect the gates of two adjacent fourth transistors T4, thereby allowing the fourth transistors T4 in the two adjacent pixel circuits PX to share a scan signal.

[0064] In one example, the scan signal section 34 is located on the side of the scan connection section 33 facing away from the substrate. The scan connection section 33 is electrically connected to the scan signal section 34. Multiple scan signal sections 34 are spaced apart along the second direction (Y direction), and each scan signal section 34 extends continuously along the first direction (X direction). The orthographic projection of one scan signal section 34 on the substrate 10 overlaps with the orthographic projections of multiple scan connection sections 33 arranged along the first direction (X direction) on the substrate 10. The orthographic projection of one scan signal section 34 on the substrate 10 overlaps with the orthographic projections of multiple active sections 20 arranged along the first direction (X direction) on the substrate 10. That is, one scan signal section 34 can connect to multiple scan connection sections 33 in the first direction (X direction). The scan signal line Sn includes a first scan signal line Sn1 and a second scan signal line Sn2. The scan signal section 34 corresponding to the first scan signal line Sn1 can be located in the fourth conductive layer M4, and the scan signal section 34 corresponding to the second scan signal line Sn2 can be located in the third conductive layer M3. Alternatively, the scan signal section 34 corresponding to the first scan signal line Sn1 and the scan signal section 34 corresponding to the second scan signal line Sn2 can both be located in the third conductive layer M3. This design can further save the fabrication steps of the fifth conductive layer M5 and the third interlayer dielectric layer ILD3, further simplifying the fabrication process.

[0065] In one embodiment, since the pixel circuit PX in the array substrate is mirror-symmetrically arranged along the first direction (X direction) and the second direction (Y direction), space is maximized while ensuring that the orthographic projections of the semiconductor layer PSI and the first conductive layer M1 on the substrate 10 extend along the first direction (X direction) and / or the second direction (Y direction). Specifically, at least a portion of the active portion and the first conductive portion extend along the first direction (X direction) and / or the second direction (Y direction) on the substrate. That is, the semiconductor layer PSI and the first conductive layer M1 are placed vertically on the substrate 10. This design ensures that even if there is a shift in the manufacturing process, it will not cause changes in the characteristics of the thin-film transistor, which is beneficial to improving display quality and does not challenge the limits of the manufacturing process.

[0066] In one embodiment, the pixel circuit PX may further include a reset signal line Vref. The reset signal line Vref is located on the side of the first conductive layer M1 away from the substrate 10 and on the side of the light-emitting signal section close to the substrate, i.e., the reset signal line Vref is located in the second conductive layer M2. The reset signal line Vref extends along the first direction (X direction), i.e., the reset signal line Vref is located between the light-emitting connection section 31 and the light-emitting signal section 32. The orthographic projection of the reset signal line Vref on the substrate 10 lies between the orthographic projections of the adjacent active sections 20 arranged in the second direction (Y direction) on the substrate 10, and connects the adjacent active sections 20 arranged in the second direction (Y direction). This design allows two pixel circuits PX arranged along the second direction (Y direction) to share the same reset signal, thereby further saving wiring space in the second conductive layer M2. At the same time, there are no other signal lines continuously extending along the first direction (X direction) in the second conductive layer M2, thereby avoiding space limitations of the same conductive layer and maximizing space saving. Specifically, in this embodiment, the reset signal line Vref is connected to the first terminal of the fourth transistor T4, which is disposed adjacent to it in the second direction (Y direction).

[0067] For example, the reset signal line Vref includes multiple reset signal sections, which are spaced apart, and adjacent reset signal sections are electrically connected through the first electrode (source or drain) of the fourth transistor in the third conductive layer. This design achieves the high performance and high resolution requirements of the display panel.

[0068] In one embodiment, the pixel circuit PX further includes a power signal line VDD, which includes a power connection portion 35 and a power signal portion 36. The power connection portion 35 is disposed on the same layer as the second electrode plate C2, and extends along a first direction (X direction) and connects to the adjacent second electrode plate C2 in the first direction (X direction). The power signal portion 36 is located on the side of the power connection portion 35 away from the substrate 10 and on the side of the scan signal portion 34 away from the substrate 10. The power connection portion 35 extends continuously along a second direction (Y direction). When the scan signal portion 34 of the second scan signal line Sn2 is located in the third conductive layer M3, the power signal portion 36 is located in the fourth conductive layer M4; when the scan signal portion 34 of the second scan signal line Sn2 is located in the fourth conductive layer M4, the power signal portion 36 is located in the fifth conductive layer M5. The power connection portion 35 directly connects the two switching transistors, forming a mesh connection of the VDD signal in the display area AA.

[0069] In one embodiment, the pixel circuit PX further includes a data signal line Date, which is disposed on the same layer as the power signal section 36. The data signal line Date is located on the side of the scan signal section 34 of the scan connection section 33 facing away from the substrate 10. If the scan signal section 34 of the scan connection section 33 is located in the third conductive layer M3, then the data signal line Date is located in the fourth conductive layer M4; if the scan signal section 34 of the scan connection section 33 is located in the fourth conductive layer M4, then the data signal line Date is located in the fifth conductive layer M5. The data signal line Date extends continuously along the second direction (Y direction) and is electrically connected to the first electrode of the second transistor T2. The orthographic projection of the data signal line Date on the substrate 10 lies between the orthographic projections of the adjacent power signal sections 36 on the substrate. Adjacent data signal lines are disposed close to each other or spaced apart by at least two power signal sections 36. The second conductive layer M2 also includes an extension 37 connected to the reset signal line Vref and extending along the second direction (Y direction). The extension 37 is located on opposite sides of the reset signal line Vref in the second direction (Y direction), with its projection onto the substrate 10 positioned between adjacent data signal lines Date. Since adjacent pixel circuits PX are mirror images of each other along the first direction (X direction), the distance between adjacent data signal lines Date is small, leading to signal interference when adjacent data signal lines Date are illuminated. Therefore, in this embodiment, the extension 37 forms a shielding layer at the closest position to the data signal lines Date, thereby ensuring stable transmission between adjacent data signal lines Date. Simultaneously, since the second conductive layer M2 containing the extension 37 has no other continuous signals, there is no competition with surrounding layers, maximizing space saving.

[0070] refer to Figure 1 and Figure 13 In one embodiment, the array substrate includes a display area AA and a non-display area NA located at least partially surrounding the display area AA. The non-display area NA includes a first border area N1 and a second border area N2 disposed in a second direction (Y direction) of the display area AA. The driving circuit layer also includes a plurality of first capacitors 80, which are located in the first border area N1 or the second border area N2 and are electrically connected to the data signal line Date. Due to pixel mirroring, the size of the display area AA for high PPI items is small, and the load of adjacent data signal lines Date differs. Therefore, in this embodiment, a first capacitor 80 is added to each data signal line Date to ensure the stability of the data signal line Date. The first capacitor 80 includes a third electrode plate 81 and a fourth electrode plate 82, wherein the fourth electrode plate 82 is located on one side of the third substrate, the third electrode plate 81 is located in the first conductive layer M1, and the fourth electrode plate 82 is located in the second conductive layer M2.

[0071] For example, the capacitance needs to be adjusted according to the actual resolution and the size of the display area AA. For example, the capacitance of the first capacitor 80 is about 1 picofarad (pF).

[0072] Furthermore, based on conventional LTPS technology, a high PPI array pixel scheme can be achieved with only 12 PEP, and the process flow is simple.

[0073] refer to Figures 4-12 In one embodiment, the pixel circuit PX further includes a transition section 40 located in the third conductive layer M3. The fourth conductive layer M4 is electrically connected to the first conductive layer M1 via a portion of the transition section 40, and the fifth conductive layer M5 is electrically connected to the semiconductor layer PSI via a portion of the transition section 40. Alternatively, the fifth conductive layer M5 is electrically connected to the semiconductor layer PSI via a portion of the transition section 40, and the second conductive layer is electrically connected. That is, in this embodiment, the conductive layers above the third conductive layer M3 (such as the fourth conductive layer M4 and the fifth conductive layer M5) are all directly electrically connected via the transition section 40. The transition section 40 then electrically connects to the semiconductor layer PSI, the first conductive layer M1, and the second conductive layer M2. This design simplifies the fabrication process of the array substrate, eliminates the need for deep and shallow via designs, helps ensure process uniformity, and minimizes the required design space. Specifically, the multiple adapters include a first adapter, through which a portion of the scan signal section is electrically connected to the scan connection section; the multiple adapters include a second adapter, through which the power signal section is electrically connected to the power connection section; and the multiple adapters include a third adapter, through which the data signal line is electrically connected to the active section.

[0074] When a multilayer conductive layer encapsulates five conductive layers, a plurality of first vias 51 are provided on the first interlayer dielectric layer ILD1. The first vias 51 expose at least a portion of the light-emitting connection portion 31 and at least a portion of the scanning connection portion 33. The light-emitting signal portion 32 in the third conductive layer M3 is electrically connected to the light-emitting connection portion 31 through the first vias 51. At least a portion of the scanning signal portion 34 of the scanning signal line Sn is electrically connected to the scanning connection portion 33 through the first vias 51 (e.g., the scanning signal portion 34 of the second scanning signal line Sn2 in the third conductive layer M3 is electrically connected to the scanning connection portion 33 of the second scanning signal line Sn2 through the first vias 51). The orthographic projection of the first vias 51 on the substrate 10 is located adjacent to each other in the first direction (X direction) between the active portions 20. This design can further save the wiring space of the first conductive layer M1. Multiple second vias 52 are provided on the second interlayer dielectric layer ILD2. The first via 51 exposes at least part of the scan connection portion 33 (specifically, the scan connection portion 33 of the first scan signal line Sn1). The scan signal portion 34 in the fourth conductive layer M4 is electrically connected to the scan connection portion 33 through the second vias 52.

[0075] When the multilayer conductive layer includes four conductive layers, a plurality of first vias 51 are provided on the first interlayer dielectric layer ILD1. The first vias 51 expose at least a portion of the light-emitting connection portion 31 and at least a portion of the scanning connection portion 33. The light-emitting signal portion 32 in the third conductive layer M3 is electrically connected to the light-emitting connection portion 31 through the first vias 51. The scanning signal portion 34 of the scanning signal line Sn is electrically connected to the scanning connection portion 33 through the first vias 51 (e.g., the scanning signal portion 34 of the scanning signal line Sn in the third conductive layer M3 is electrically connected to the scanning connection portion 33 through the first vias 51). The orthographic projection of the first vias 51 on the substrate 10 is located in the first direction (X direction) and is adjacent to the active portion 20. This design can further save the wiring space of the first conductive layer M1.

[0076] In one embodiment, the array substrate further includes a first electrode 71 (such as an anode) in the light-emitting device 70. The first electrode 71 is located on the side of the planarization layer opposite to the substrate. A third via is provided on the planarization layer, exposing at least a portion of the fifth conductive layer M5 or at least a portion of the fourth conductive layer M4. The first electrode 71 is electrically connected to the fifth conductive layer M5 through the third via, or the first electrode 71 is electrically connected to the fourth conductive layer M4 through the third via. Further, the array substrate also includes a pixel defining layer PDL, located on the side of the first electrode 71 opposite to the substrate. The pixel defining layer PDL also has a pixel opening exposing at least a portion of the first electrode 71.

[0077] Furthermore, in the first direction (X direction), the adjacent first electrodes 71 are mirror images of each other along the first direction (X direction); in the second direction (Y direction), the adjacent second electrodes are mirror images of each other along the second direction (Y direction).

[0078] refer to Figure 2 and Figures 4-13 In another alternative embodiment, the fabrication process of the array substrate in this application is PEP1-PEP12;

[0079] PEP1: A semiconductor layer PSI formed on substrate 10, which may include, for example, polysilicon. Here, a low-temperature polysilicon (LTPS) transistor is used as an example; it can be an N-type or P-type device. After the semiconductor layer PSI is completed, a gate insulating layer GI1 is applied without patterning.

[0080] PEP2: Forming the first conductive layer M1. The first conductive layer M1 serves as the conductive layer containing the gates of some transistors (such as the gates of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6), the first electrode C1 (lower electrode) of the storage capacitor, and some connection portions. The material of the first conductive layer M1 is, for example, Mo, Al, Cu metal, etc. After completion, a capacitor insulating layer CI is formed on the side of the first conductive layer M1 facing away from the substrate 10. The capacitor insulating layer CI is not patterned. Here, the capacitor insulating layer CI is mainly made of inorganic materials, such as SiO2, SiNx, etc.

[0081] PEP3: Forming the second conductive layer M2. The second conductive layer M2 serves as the conductive layer containing the second electrode C2 (upper electrode) of the storage capacitor and the reset signal line Vref. The material of the second conductive layer M2 is Mo, Al, Cu metal, etc.

[0082] PEP4: Form the first interlayer dielectric layer ILD1. Patterned vias are made in the first interlayer dielectric layer ILD1 for upward connection of signal lines in the second conductive layer M2 and the first conductive layer M1. Here, the first interlayer dielectric layer ILD1 is mainly composed of inorganic materials, such as SiO2, SiNx, etc.

[0083] PEP5: Form the third conductive layer M3. The third conductive layer M3 can serve as the film layer containing the scan signal section 34 of the second scan signal line Sn2 and the source / drain layer of the thin-film transistor. Here, the material of the three conductive layers can be Mo, Al, Cu metal, etc.

[0084] PEP6: Form the second interlayer dielectric layer ILD2, and create patterned openings in ILD2 for upward connection of signal lines in the third conductive layer M3. Here, the second interlayer dielectric layer ILD2 is mainly composed of inorganic materials, such as SiO2, SINx, etc.

[0085] PEP7: Form the fourth conductive layer M4. The fourth conductive layer M4 can serve as the layer containing the scan signal section 34 of the first scan signal line Sn1. The material of the fourth conductive layer M4 is a metal such as Mo, Al, or Cu.

[0086] PEP8: Form the third interlayer dielectric layer ILD3. Patterned vias are then created in the third interlayer dielectric layer ILD3 for upward connection of the third conductive layer M3 to the fifth conductive layer M5. Here, the third interlayer dielectric layer ILD3 is primarily composed of inorganic materials, such as SiO2 or SiNx.

[0087] PEP9: Form the fifth conductive layer M5. The fifth conductive layer M5 is connected to the first transistor T1 as the power signal section 36 in the power signal line VDD, and is connected to the second transistor T2 as the data signal line Date.

[0088] PEP10: Form a planarization layer PLN2, and create patterned openings in the PLN2 for subsequent upward connection of Anode nodes. Here, the planarization layer PLN2 is mainly composed of organic materials, such as polyimide.

[0089] PEP11: Forms the anode layer of the light-emitting device 70. The anode layer is commonly made of a three-layer material of ITO / Ag / ITO.

[0090] PEP12: Forms the pixel definition layer (PDL), which can be an organic material, such as polyimide.

[0091] In this embodiment, based on conventional LTPS technology, a high PPI array pixel scheme can be achieved with 12PEP. The process is simple, and the mask manufacturing cost and tape-out cost are low.

[0092] In another alternative embodiment, the fabrication process flow of the array substrate in this application is PEP1-PEP10:

[0093] PEP1: A semiconductor layer PSI formed on substrate 10, which may include, for example, polysilicon. Here, a low-temperature polysilicon (LTPS) transistor is used as an example; it can be an N-type or P-type device. After the semiconductor layer PSI is completed, a gate insulating layer GI1 is applied without patterning.

[0094] PEP2: Forming the first conductive layer M1. The first conductive layer M1 serves as the conductive layer containing the gates of some transistors (such as the gates of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6), the first electrode C1 (lower electrode) of the storage capacitor, and some connection portions. The material of the first conductive layer M1 is, for example, Mo, Al, Cu metal, etc. After completion, a capacitor insulating layer CI is formed on the side of the first conductive layer M1 facing away from the substrate 10. The capacitor insulating layer CI is not patterned. Here, the capacitor insulating layer CI is mainly made of inorganic materials, such as SiO2, SiNx, etc.

[0095] PEP3: Forming the second conductive layer M2. The second conductive layer M2 serves as the second electrode C2 (upper electrode) of the storage capacitor and the reset signal line Vref. The material of the second conductive layer M2 is Mo, Al, Cu metal, etc.

[0096] PEP4: Form the first interlayer dielectric layer ILD1. Patterned vias are made in the first interlayer dielectric layer ILD1 for upward connection of signal lines in the second conductive layer M2 and the first conductive layer M1. Here, the first interlayer dielectric layer ILD1 is mainly composed of inorganic materials, such as SiO2, SiNx, etc.

[0097] PEP5: Form the third conductive layer M3. The third conductive layer M3 can serve as the film layer containing the scan signal section 34 of the scan signal line Sn and the source / drain layer of the thin-film transistor. Here, the material of the three conductive layers can be Mo, Al, Cu metal, etc.

[0098] PEP6: Form the second interlayer dielectric layer ILD2, and create patterned openings in ILD2 for upward connection of signal lines in the third conductive layer M3. Here, the second interlayer dielectric layer ILD2 is mainly composed of inorganic materials, such as SiO2, SINx, etc.

[0099] PEP7: Form the fourth conductive layer M4. The fourth conductive layer M4 can be used as the power signal line VDD, connected to the power signal section 36 and the first transistor T1, and as the data signal line Date, connected to the second transistor T2. The material of the fourth conductive layer M4 is Mo, Al, Cu metal, etc.

[0100] PEP8: Form a planarization layer PLN2, and create patterned openings in the PLN2 for subsequent upward connection of Anode nodes. Here, the planarization layer PLN2 is mainly composed of organic materials, such as polyimide.

[0101] PEP9: Forms the anode layer of the light-emitting device 70. The commonly used material for the anode layer is a three-layer material of ITO / Ag / ITO.

[0102] PEP10: Forms a pixel definition layer (PDL). The pixel definition layer (PDL) can be an organic material, such as polyimide.

[0103] In this embodiment, based on conventional LTPS technology, a high PPI array pixel scheme can be achieved with 10PEP. The process is simple, and the mask manufacturing cost and tape-out cost are low.

[0104] Based on the same inventive concept, this disclosure also provides a display panel that includes the array substrate described in any of the above embodiments. This display panel has the beneficial effects of the array substrate provided in the embodiments of this application; for details, please refer to the specific descriptions of the array substrate in the above embodiments, which will not be repeated here. The display panel may further include a light-emitting device layer, an encapsulation layer, and a touch layer. The display panel provided in the embodiments of this application has the beneficial effects of the array substrate provided in the embodiments of this application; for details, please refer to the specific descriptions of the array substrate in the above embodiments, which will not be repeated here.

[0105] The display device has the beneficial effects of the array substrate provided in the embodiments of this application. For details, please refer to the specific descriptions of the array substrate in the above embodiments. This embodiment will not repeat them here.

[0106] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0107] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An array substrate, characterized in that, include: Substrate; A driving circuit layer is located on the substrate. The driving circuit layer includes a plurality of pixel circuits. The plurality of pixel circuits are arranged in an array on the substrate. In a first direction, at least one transistor in an adjacent pixel circuit is arranged in a mirror symmetrical manner. In a second direction, at least one transistor in an adjacent pixel circuit is arranged in a mirror symmetrical manner. The first direction and the second direction intersect.

2. The array substrate as described in claim 1, characterized in that, The driving circuit layer further includes a semiconductor layer and a first conductive layer. The semiconductor layer includes active portions of each pixel circuit. The first conductive layer is located on the side of the semiconductor layer away from the substrate. The first conductive layer includes a plurality of first conductive portions. At least a portion of the active portions and the orthographic projections of the first conductive portions on the substrate extend along the first direction and / or the second direction. The active portions of the multiple transistors in the pixel circuit are all located in the same semiconductor layer.

3. The array substrate as described in claim 2, characterized in that, The plurality of first conductive portions include a plurality of spaced-apart light-emitting connection portions, the light-emitting connection portions extending along the first direction, the orthographic projection of the light-emitting connection portions on the substrate being located between adjacent active portions arranged in the first direction, and the orthographic projections of the two ends of the light-emitting connection portions in the first direction on the substrate respectively at least partially overlap with the orthographic projections of the adjacent active portions arranged in the first direction on the substrate. The plurality of first conductive portions include a plurality of spaced-apart scanning connection portions, the scanning connection portions extending along the first direction, the orthographic projection of the scanning connection portions on the substrate being located between adjacent active portions arranged in the first direction, and the orthographic projections of the two ends of the scanning connection portions on the substrate in the first direction at least partially overlapping the orthographic projections of the adjacent active portions arranged in the first direction on the substrate, the orthographic projection of the scanning connection portions on the substrate being located between the orthographic projections of adjacent light-emitting connection portions on the substrate in the second direction.

4. The array substrate as described in claim 3, characterized in that, The driving circuit layer further includes a plurality of light-emitting signal units, which are located on the side of the light-emitting connection unit away from the substrate. The orthographic projection of one of the light-emitting signal units on the substrate overlaps with the orthographic projections of a plurality of light-emitting connection units arranged along the first direction on the substrate. The orthographic projection of one of the light-emitting signal units on the substrate overlaps with the orthographic projections of a plurality of active units arranged along the first direction on the substrate. The light-emitting connecting part is electrically connected to the light-emitting signal part, and a plurality of light-emitting signal parts are spaced apart along the second direction, and each light-emitting signal part extends continuously along the first direction; The driving circuit layer further includes a plurality of scanning signal units, the scanning signal units being located on the side of the scanning connection unit away from the substrate, the orthographic projection of one of the scanning signal units on the substrate overlapping with the orthographic projections of a plurality of the scanning connection units arranged along the first direction on the substrate, and the orthographic projection of one of the scanning signal units on the substrate overlapping with the orthographic projections of a plurality of the active units arranged along the first direction on the substrate. The scanning connection portion is electrically connected to the scanning signal portion, and a plurality of scanning signal portions are spaced apart along the second direction, and each scanning signal portion extends continuously along the first direction.

5. The array substrate as described in claim 4, characterized in that, The driving circuit layer further includes a plurality of reset signal lines, which are located on the side of the first conductive layer away from the substrate. At least a portion of the reset signal lines extend along the first direction. The orthographic projection of the reset signal lines on the substrate is located between the active portions disposed adjacent to each other in the second direction, and connects the active portions disposed adjacent to each other in the second direction.

6. The array substrate as described in claim 4, characterized in that, The pixel circuit also includes a storage capacitor, which includes a first electrode plate and a second electrode plate. The first electrode plate is located on the first conductive layer, and the second electrode plate is located on the side of the first electrode plate away from the substrate. The pixel circuit further includes a power signal line, which includes a power connection portion and a power signal portion. The power connection portion is disposed on the same layer as the second electrode plate. The power connection portion extends along the first direction and is connected to the second electrode plate adjacent to it in the first direction. The power signal portion is located on the side of the power connection portion away from the substrate. The power connection portion extends continuously along the second direction.

7. The array substrate as described in claim 6, characterized in that, The pixel circuit further includes data signal lines, which are disposed on the same layer as the power signal section. The data signal lines extend continuously along the second direction, and the orthographic projection of the data signal lines on the substrate is located between the orthographic projections of the adjacent power signal sections on the substrate. Adjacent data signal lines are disposed close to each other or spaced apart by at least two power signal sections.

8. The array substrate as claimed in claim 7, characterized in that, The array substrate includes a display area and a non-display area located at least partially surrounding the display area. The non-display area includes a first border area and a second border area disposed in a second direction of the display area. The driving circuit layer also includes a plurality of first capacitors, which are located in the first border area or the second border area and are electrically connected to the data signal line.

9. The array substrate as claimed in claim 7, characterized in that, The driving circuit layer also includes multiple adapters, which are disposed on the same layer as the light-emitting signal section. Some of the adapters are electrically connected to some of the scanning signal section and the scanning connection section, and some of the adapters are electrically connected to the power signal section and the power connection section.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

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