Bidirectional thyristor electrostatic protection device and preparation method thereof

Abstract

The application provides a bidirectional thyristor electrostatic protection device and a preparation method thereof. The bidirectional thyristor electrostatic protection device comprises a first P-type well region, an N-type well region and a second P-type well region in an epitaxial layer; a first NMOS structure comprising a first gate structure, a first P+ implantation region and a first N+ implantation region in the first P-type well region, and a second N+ implantation region across the first P-type well region and the N-type well region; and a second NMOS structure comprising a second gate structure, a third N+ implantation region across the N-type well region and the second P-type well region, a fourth N+ implantation region and a second P+ implantation region in the second P-type well region. The first NMOS structure and the second NMOS structure are interconnected by interconnecting the second N+ implantation region and the third N+ implantation region, so that the avalanche breakdown voltage and the trigger voltage of the device are reduced.

Description

Technical Field

[0001] This application relates to the field of electrostatic discharge (ESD) protection technology, specifically to a bidirectional thyristor ESD protection device and its fabrication method. Background Technology

[0002] ESD (Electro-Static Discharge) occurs throughout the entire lifecycle of chip manufacturing, packaging, testing, and system application. It can easily induce instantaneous high currents at I / O pins, causing irreversible damage such as gate oxide breakdown and metal melting. Therefore, the industry commonly integrates ESD protection devices at chip ports, among which the silicon controlled rectifier (SCR) structure is widely used due to its strong discharge capability per unit area and good flyback characteristics.

[0003] However, traditional unidirectional SCRs only provide a unidirectional electrostatic discharge path. When I / O needs to transmit symmetrical positive and negative level signals to ground, the unidirectional structure exhibits diode forward conduction in the negative voltage range, leading to a sharp increase in leakage current and significant interference with signal integrity. To balance positive and negative signal transmission, designers have introduced bidirectional SCR structures, enabling the device to have reverse voltage withstand capability of the PN junction in both positive and negative directions. However, the trigger voltage of both existing unidirectional and bidirectional SCRs is determined by the avalanche breakdown of the NW / PW junction, and the trigger voltage is generally higher than the gate oxide withstand voltage of advanced process I / O devices, posing a risk of "premature breakdown." Simultaneously, traditional lateral SCRs have short discharge paths and low sustaining voltages, making them prone to latch-up upon false triggering, with continuous high current ultimately causing chip burnout. These shortcomings limit the direct application of SCRs in low-voltage, bidirectional, and high-reliability I / O ports. Summary of the Invention

[0004] In view of the above-mentioned technical problems, the purpose of this application is to provide a bidirectional thyristor electrostatic discharge (ESD) device and its fabrication method. In this method, by introducing an interconnected NMOS structure into the device to reduce the avalanche breakdown voltage and trigger voltage of the device, and by using an N-type deep well and an N-type buried layer to isolate the first and second P-type well regions and the P-type substrate of the device and form a new longitudinal parasitic path, the on-resistance of the device is reduced and the holding voltage of the device is improved. At the same time, the device is also designed with a symmetrical structure, so that the device can have bidirectional withstand voltage and bidirectional ESD protection functions.

[0005] According to a first aspect of this application, a bidirectional thyristor electrostatic discharge (ESD) protection device is provided, comprising:

[0006] Substrate;

[0007] Epitaxial layer located on the substrate;

[0008] A first P-type well region, an N-type well region, and a second P-type well region are sequentially disposed in the epitaxial layer along the transverse direction;

[0009] The first NMOS structure includes: a first P+ injection region and a first N+ injection region disposed within the first P-type well region, a second N+ injection region spanning the first P-type well region and the N-type well region, and a first gate structure located between the first N+ injection region and the second N+ injection region.

[0010] The second NMOS structure includes: a third N+ injection region spanning the N-type well region and the second P-type well region, a fourth N+ injection region and a second P+ injection region disposed within the second P-type well region, and a second gate structure located between the third N+ injection region and the fourth N+ injection region;

[0011] The first P+ injection region, the first N+ injection region, and the first gate structure are interconnected, and the second gate structure, the fourth N+ injection region, and the second P+ injection region are interconnected.

[0012] Optionally, it also includes:

[0013] An N-type buried layer is located on the substrate and is at least partially disposed in the epitaxial layer;

[0014] An N-type deep well located above the N-type buried layer;

[0015] The N-type deep well includes a first portion, and at least a portion of the N-type well region is disposed on the first portion of the N-type deep well, including the first P-type well region, the N-type well region, and the second P-type well region.

[0016] Optionally, it also includes:

[0017] The third P+ injection region is located in the N-type well region;

[0018] The third P+ injection region is located between the second N+ injection region and the third N+ injection region.

[0019] Optionally, the first P+ injection region, the first N+ injection region, and the first gate structure are connected to one of the anode and cathode of the bidirectional thyristor electrostatic discharge device;

[0020] The second gate structure, the fourth N+ injection region, and the second P+ injection region are connected to one of the anode and cathode of the bidirectional thyristor electrostatic discharge device.

[0021] Optionally, the N-type deep well further includes: a second portion located on the side of the first P-type well region away from the N-type well region and a third portion located on the side of the second P-type well region away from the N-type well region.

[0022] Optionally, the N-type deep trap further includes a second portion;

[0023] The second part is an annular region, and the first P-type well region, the N-type well region, and the second P-type region are all located inside the annular region formed by the second part of the N-type deep well.

[0024] Optionally, it also includes:

[0025] The third P-type well region is located in the epitaxial layer on the side of the second part of the N-type deep well away from the first P-type well region;

[0026] The fourth P+ injection region is located within the third P-type well region;

[0027] The fourth P-type well region is located in the epitaxial layer on the side of the third portion of the N-type deep well away from the second P-type well region;

[0028] The fifth P+ injection region is located within the fourth P-type well region;

[0029] Both the fourth P+ injection region and the fifth P+ injection region are used to connect to the cathode of the bidirectional thyristor electrostatic discharge (ESD) device.

[0030] Optionally, it also includes:

[0031] The third P-type well region is a ring-shaped region, and the ring-shaped region formed by the third P-type well region is located in the epitaxial layer outside the ring-shaped region formed by the second part of the N-type deep well.

[0032] The fourth P+ injection region is located within the third P-type well region, and the fourth P+ injection region is used to connect to the cathode of the bidirectional thyristor electrostatic discharge device.

[0033] Optionally, the epitaxial layer is a P-type epitaxial layer.

[0034] Optionally, the first P+ injection region and the first N+ injection region, and the fourth N+ injection region and the second P+ injection region are isolated or in contact via an isolation structure.

[0035] Optionally, when there is a gap between two adjacent injection zones, an isolation structure is also provided at each gap.

[0036] Optionally, the bidirectional thyristor electrostatic discharge (ESD) device has a symmetrical structure with the center line of the N-type well region as the axis.

[0037] Optionally, the doping concentration of the N-type buried layer is greater than the doping concentration of the N-type well region.

[0038] According to a second aspect of this application, a method for fabricating a bidirectional thyristor electrostatic discharge (ESD) device is provided, comprising:

[0039] A first P-type well region, an N-type well region, and a second P-type well region are sequentially formed laterally in the epitaxial layer on the substrate.

[0040] A first P+ injection region and a first N+ injection region are respectively formed within the first P-type well region, a second N+ injection region spanning the first P-type well region and the N-type well region, a third N+ injection region spanning the N-type well region and the second P-type well region, and a fourth N+ injection region and a second P+ injection region are respectively formed within the second P-type well region.

[0041] A first gate structure is formed between the first N+ injection region and the second N+ injection region, and a second gate structure is formed between the third N+ injection region and the fourth N+ injection region;

[0042] The first P+ injection region, the first N+ injection region, and the first gate structure are interconnected; the second gate structure, the fourth N+ injection region, and the second P+ injection region are interconnected; and the second N+ injection region and the third N+ injection region are interconnected.

[0043] Optionally, before forming the first P-type well region, the N-type well region, and the second P-type well region, the following steps are also included:

[0044] An N-type buried layer, at least partially located within the epitaxial layer, is formed on the substrate;

[0045] An N-type deep well is formed above the N-type buried layer;

[0046] The N-type deep well includes a first part;

[0047] Among the first P-type well region, the N-type well region, and the second P-type well region, at least a portion of the N-type well region is disposed on the first part of the N-type deep well.

[0048] Optionally, it further includes: forming a third P+ injection region located within the N-type well region.

[0049] The beneficial effects of this application include at least the following:

[0050] The bidirectional thyristor electrostatic discharge (ESD) device and its fabrication method provided in this application have an N+ injection region spanning the P-type well region and an N-type well region, as well as a first gate structure and a second gate structure. This forms two interconnected NMOS structures in the device based on the original N+ injection region in the P-type well region. Compared with devices in the prior art that do not have NMOS structures, this application can transfer the avalanche breakdown voltage after device triggering from the reverse-biased PN junction formed by the original N-type well region and P-type well region to the reverse-biased PN junction formed by the N+ injection region and P-type well region based on the interconnected NMOS structure. Since the doping concentration of the N+ injection region is much greater than that of the N-type well region, the avalanche breakdown voltage and trigger voltage of the device can be reduced by adopting the solution of this application.

[0051] In a further preferred embodiment, a heavily doped N-type buried layer on the substrate and an N-type deep well above the buried layer are also provided in the device, thereby forming a vertical parasitic transistor structure in the device. After the device is triggered, the heavily doped N-type buried layer can attract more electrons, thereby increasing the current through the vertical parasitic transistor. A vertical SCR discharge path is formed in the device, which flows through the vertical parasitic transistor, effectively extending the discharge path of ESD current in the device, so that the device can have a higher holding voltage and a lower on-resistance.

[0052] In a further preferred embodiment, the device is configured to have a symmetrical structure with the centerline of the N-type well region as the axis, enabling the device to achieve bidirectional withstand voltage and bidirectional electrostatic protection.

[0053] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. Attached Figure Description

[0054] Figure 1 A cross-sectional view of a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device is shown.

[0055] Figure 2a Show Figure 1 A schematic diagram of the forward ESD current discharge path in the equivalent circuit diagram of a silicon controlled rectifier (SCR) electrostatic discharge protection device.

[0056] Figure 2b Show Figure 1 A schematic diagram of the reverse ESD current discharge path of a thyristor electrostatic discharge device.

[0057] Figure 3 A cross-sectional view of a bidirectional thyristor electrostatic discharge (ESD) protection device according to a first embodiment of this application is shown.

[0058] Figure 4a Show Figure 3A schematic diagram of the equivalent circuit and forward ESD current discharge path of a thyristor electrostatic discharge device.

[0059] Figure 4b Show Figure 3 A schematic diagram of the equivalent circuit and reverse ESD current discharge path of a thyristor electrostatic discharge device.

[0060] Figure 5 A flowchart illustrating the fabrication method of the bidirectional thyristor electrostatic discharge (ESD) device according to the first embodiment of this application is shown.

[0061] Figure 6a A cross-sectional view is shown of a bidirectional thyristor electrostatic discharge protection device according to a second embodiment of this application;

[0062] Figure 6b This illustration shows another cross-sectional view of the bidirectional thyristor electrostatic discharge (ESD) protection device provided according to a second embodiment of this application;

[0063] Figure 7a Show Figure 6a and Figure 6b A schematic diagram of the equivalent circuit and forward ESD current discharge path of a thyristor electrostatic discharge device.

[0064] Figure 7b Show Figure 6a and Figure 6b A schematic diagram of the equivalent circuit and reverse ESD current discharge path of a thyristor electrostatic discharge device.

[0065] Figure 8 A flowchart illustrating the fabrication method of the bidirectional thyristor electrostatic discharge (ESD) device according to the second embodiment of this application is shown. Detailed Implementation

[0066] The preferred embodiments of this disclosure are described in detail below with reference to the accompanying drawings, but this disclosure is not limited to these embodiments. This disclosure covers any alternatives, modifications, equivalent methods, and solutions made within the spirit and scope of this disclosure.

[0067] In order to provide the public with a thorough understanding of this disclosure, specific details are described in detail in the following preferred embodiments of this disclosure, but those skilled in the art can fully understand this disclosure without these details.

[0068] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0069] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0070] In the description of this application, words such as "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. The term "and / or" in this document describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0071] When describing the structure of a device in this disclosure, when referring to a layer or region as being "above" or "over" another layer or region, it may mean being directly above another layer or region, or including other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0072] It should be understood that when a component or layer is referred to as "on," "connected to," or "coupled to" other components or layers, it may be directly on, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various components, parts, areas, layers, and / or portions, these components, parts, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, area, layer, or portion from another component, part, area, layer, or portion.

[0073] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the application.

[0074] Furthermore, the same reference numerals in the figures denote the same or similar structures, thus repeated descriptions of them will be omitted. That is, the various parts in this specification are described using a combination of parallel and progressive methods, with each part focusing on its differences from the others. Similar or identical parts can be referred to interchangeably. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings in this application are for illustrating relative positional relationships only and do not represent actual scale.

[0075] Figure 1 A cross-sectional view of a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device is shown, such as... Figure 1 As shown, the thyristor electrostatic discharge (ESD) protection device 100 (hereinafter referred to as device 100) includes: a P-type substrate 110, a P-type epitaxial layer 120 on the P-type substrate 110, a P-type well region 130, an N-type well region 140, a P-type well region 150, an N-type well region 160, a P-type well region 170, a P+ injection region 131 in the P-type well region 130, an N+ injection region 141 and a P+ injection region 142 in the N-type well region 140, a P+ injection region 161 and an N+ injection region 162 in the N-type well region 160, a P+ injection region 171 in the P-type well region 170, and an isolation structure 180 located between two adjacent injection regions to isolate the injection regions. The P+ injection region 161 and the N+ injection region 162 are connected to each other to serve as the anode of device 100, and the other injection regions serve as the cathode of device 100.

[0076] Figure 1 In the SCR path of device 100, it mainly consists of a P+ implantation region, an N-type well region, a P-type well region, and an N+ implantation region. Combined with... Figure 1 and Figure 2aWhen a forward ESD pulse reaches the anode of device 100, the reverse-biased PN junction composed of N-type well region 160 and P-type well region 150 undergoes avalanche breakdown, generating a large number of charge carriers that continuously flow through the parasitic well resistance R on N-type well region 140. This increases the voltage drop Vbe between the base and emitter of the lateral parasitic NPN structure formed by N-type well region 160, P-type well region 150, and N-type well region 140 in device 100. Once Vbe exceeds 0.7V, the lateral parasitic NPN structure is triggered and operates in the amplification region, causing the parasitic PNPN structure formed by P+ injection region 161, N-type well region 160, P-type well region 150, and N-type well region 140 in device 100 to open, ultimately forming a low-resistance lateral SCR discharge path P1. The reverse operating principle of device 100 is basically similar to its forward operating principle, combined with... Figure 1 and Figure 2b When the ESD pulse reaches the cathode of device 100, the reverse-biased PN junction composed of N-type well region 140 and P-type well region 150 undergoes avalanche breakdown, generating a large number of charge carriers that continuously flow through the parasitic well resistance R on N-type well region 160. This increases the voltage drop Vbe between the base and emitter of the lateral parasitic NPN structure formed by N-type well region 140, P-type well region 150, and N-type well region 160 in device 100. Once Vbe exceeds 0.7V, the lateral parasitic NPN structure is triggered and operates in the amplification region, causing the parasitic PNPN structure formed by P+ injection region 142, N-type well region 140, P-type well region 150, and N-type well region 160 in device 100 to turn on, ultimately forming a low-resistance lateral SCR discharge path P2.

[0077] However, Figure 1 Although the SCR device 100 shown has a bidirectional SCR structure, it still has the disadvantages of high trigger voltage and low sustaining voltage.

[0078] This application is in Figure 1 Based on the existing design, a compact bidirectional low-trigger voltage bidirectional thyristor electrostatic discharge (ESD) device was designed. An interconnected NMOS structure, along with N-type deep wells and heavily doped N-type buried layers, were introduced into the device. This allows for the formation of new parasitic paths for ESD current discharge, reducing both the avalanche breakdown voltage and trigger voltage. Furthermore, the device exhibits lower on-resistance and higher holding voltage. The symmetrical device layout design enables bidirectional withstand voltage and bidirectional ESD protection, making it suitable for I / O ports capable of transmitting low-voltage positive and negative signals.

[0079] Example 1

[0080] refer to Figure 3 , Figure 4a and Figure 4b , Figure 3 A cross-sectional view of the bidirectional thyristor electrostatic discharge (ESD) protection device provided in the first embodiment of this application is shown. Figure 4a It shows Figure 3 A schematic diagram of the equivalent circuit and forward ESD current discharge path of a thyristor electrostatic discharge device. Figure 4b It shows Figure 3 A schematic diagram of the equivalent circuit and reverse ESD current discharge path of a thyristor electrostatic discharge device.

[0081] like Figure 3 , Figure 4a and Figure 4b As shown in these embodiments, the bidirectional thyristor electrostatic discharge (ESD) device 200 (hereinafter referred to as device 200) includes: a substrate 210; an epitaxial layer 230 located on the substrate 210; and P-type well regions 250, N-type well regions 260, and P-type well regions 270 sequentially disposed laterally in the epitaxial layer 230. The substrate 210 is typically P-type doped (P-SUB), while the epitaxial layer 230 can be P-type doped or N-type doped. In this embodiment, the epitaxial layer 230 is, for example, P-type doped (P-EPI). All P-type well regions are P-type doped, and all N-type well regions are N-type doped. In this embodiment, the P-type well regions 250, N-type well regions 260, and P-type well regions 270 are sequentially distributed, and the N-type well region 260 is in contact with both the P-type well regions 250 and 270, and is separated from the substrate 210 by the epitaxial layer 230. The extension depths of P-type well region 250, N-type well region 260 and P-type well region 270 can be the same or different.

[0082] Device 200 further includes: a P+ injection region 251 and an N+ injection region 252 disposed in a P-type well region 250; an N+ injection region 272 and a P+ injection region 273 disposed in a P-type well region 270; an N+ injection region 253 spanning a P-type well region 250 and an N-type well region 260; an N+ injection region 271 spanning an N-type well region 260 and a P-type well region 270; a first gate structure 254 located between the N+ injection regions 252 and 253; and a second gate structure 274 located between the N+ injection regions 271 and 272. The P+ injection region 251, the N+ injection region 252, the first gate structure 254, and the N+ injection region 253 can constitute a first NMOS structure, with the N+ injection regions 252 and 253 serving as the source and drain regions of the first NMOS structure, respectively. The N+ injection region 271, the second gate structure 274, the N+ injection region 272, and the P+ injection region 273 can constitute a second NMOS structure, with the N+ injection region 272 and N+ injection region 271 serving as the source and drain regions of the second NMOS structure, respectively. Both the first NMOS structure and the second NMOS structure can be, for example, GGNMOS structures.

[0083] Optionally, the P+ injection region 251 and the N+ injection region 252, and the N+ injection region 272 and the P+ injection region 273, are isolated by an isolation structure 290. Alternatively, the P+ injection region 251 and the N+ injection region 252, and the N+ injection region 272 and the P+ injection region 273, may be in phase contact. The isolation structure 290 may be, for example, a field oxygen isolation structure or a shallow trench isolation structure.

[0084] The P+ injection region 251, N+ injection region 252, and first gate structure 254 are interconnected via a connection structure 292 (such as a metal line or metal layer) to serve as one of the anode and cathode of device 200 (i.e., the P+ injection region 251, N+ injection region 252, and first gate structure 254 are connected to one of the anode and cathode of device 200 via the connection structure 292). The second gate structure 274, N+ injection region 272, and P+ injection region 273 are interconnected via a connection structure 293 (such as a metal line or metal layer) to serve as the other of the anode and cathode of device 200 (i.e., the second gate structure 274, N+ injection region 272, and P+ injection region 273 are connected to the other of the anode and cathode of device 200 via the connection structure 293). The N+ injection region 253 and N+ injection region 271 are also interconnected via the connection structure 291 (such as a metal line or metal layer), thereby realizing the series connection of the first NMOS structure and the second NMOS structure. This embodiment sets up a first NMOS structure and a second NMOS structure that span two P-type well regions (250 and 270) and an N-type well region respectively and are short-circuited to each other. This allows a bidirectional current discharge path to be formed through the symmetrically arranged first NMOS structure and second NMOS structure during the initial triggering of the device 200. Furthermore, the reverse bias PN junctions in the high-doped N+ injection region and the P-type well region of the NMOS structure can reduce the avalanche breakdown voltage and trigger voltage of the device.

[0085] The first gate structure 254 and the second gate structure 274 are, for example, multi-layer stacked structures, such as both including a gate oxide layer and a polysilicon gate (not shown). The first gate structure 254 and the second gate structure 274 are connected to the corresponding implantation regions through the polysilicon gate therein.

[0086] In a further embodiment, device 200 further includes: a P-type well region 281 and a P-type well region 282 located in the P-type epitaxial layer 230, and a P+ implantation region 283 located in the P-type well region 281 and a P+ implantation region 284 located in the P-type well region 282. The P-type well region 281 is spaced apart from the P-type well region 250, and the P-type well region 281 is located in the epitaxial layer 230 on the side of the P-type well region 250 away from the N-type well region 260. The P-type well region 282 is spaced apart from the P-type well region 270, and the P-type well region 282 is located in the epitaxial layer 230 on the side of the P-type well region 270 away from the N-type well region 260. Both the P+ implantation regions 283 and 284 are used to connect to the cathode of device 200. The extension depths of the P-type well regions 281, 282, 250, and 270 can be the same or different.

[0087] Of course, in other embodiments, the P-type well region 281, P-type well region 282, P+ injection region 283 and P+ injection region 284 can also be omitted or replaced with other settings, and the discharge path to be formed in this embodiment can still be formed in the device 200 after omission or replacement.

[0088] Optionally, in some embodiments, P-type well region 281 and P-type well region 282 are independent well region structures, that is, from the top view of device 200, P-type well region 281 and P-type well region 282 are located on opposite sides of device 200 and are not connected. In these embodiments, P+ injection region 283 and P+ injection region 284 are also two independent injection regions. In other embodiments, P-type well region 281 and P-type well region 282 are manifestations of a ring-shaped P-type well region at different positions on the same cross-section. That is, from the top view of device 200, P-type well region 281 and P-type well region 282 are connected to each other to form a whole ring-shaped region. P-type well region 250, N-type well region 260 and P-type well region 270 are all located inside the ring-shaped region formed by P-type well region 281 and P-type well region 282. In these embodiments, P+ injection region 283 and P+ injection region 284 are also connected to each other to form a whole ring-shaped injection region.

[0089] In this embodiment, among all regions with P-type doping (including well regions, implantation regions, epitaxial layers, and substrates, etc.) within device 200, the doping concentration of the P+ implantation region is the highest. Similarly, among all regions with N-type doping (including well regions, implantation regions, etc.), the doping concentration of the N+ implantation region is the highest. The doping concentrations of the P+ and N+ implantation regions can also be the same or different.

[0090] In addition, when there is a gap between two adjacent injection zones (such as between P+ injection zone 283 and P+ injection zone 251, between N+ injection zone 253 and P+ injection zone 261, between P+ injection zone 261 and N+ injection zone 271, between P+ injection zone 273 and P+ injection zone 284, etc.), an isolation structure 290 is provided at each gap to achieve isolation between the corresponding two injection zones. The isolation structure 290 can be a field oxygen isolation structure or a shallow trench isolation structure.

[0091] Figure 3 In the device 200, the P-type well region 250, the N-type well region 260, and the P-type well region 270 constitute the parasitic transistor PNP1; the N-type well region 260, the P-type well region 250, and the N+ injection region 252 constitute the lateral parasitic transistor NPN1 in the device 200; and the N-type well region 260, the P-type well region 270, and the N+ injection region 272 constitute the lateral parasitic transistor NPN2 in the device 100.

[0092] In this embodiment, the device 200 has a symmetrical structure with the center line of the N-type well region 260 as the axis, that is, the device 200 has symmetrical electrical characteristics and can achieve the effects of bidirectional withstand voltage and bidirectional electrostatic protection.

[0093] Taking the example of P+ injection region 251, N+ injection region 252, and first gate structure 254 connected to the anode of device 200 via connection structure 292, and second gate structure 274, N+ injection region 272, and P+ injection region 273 connected to the cathode of device 200 via connection structure 293, combined with... Figure 3 and Figure 4aBy introducing an NMOS structure (including a first NMOS structure and a second NMOS structure interconnected) into device 200, when device 200 is forward-triggered, for example when an ESD pulse reaches the anode of device 200, the introduced first NMOS structure can shift the location of avalanche breakdown of device 200 from the reverse-biased PN junction formed by the N-type well region and the P-type well region (when no NMOS structure is introduced) to the reverse-biased PN junction formed by the N+ injection region 271 and the P-type well region 270. Since the doping concentration of the N+ injection region 271 is much greater than that of the N-type well region, the avalanche breakdown voltage and trigger voltage of device 200 are reduced. At this time, the avalanche breakdown voltage of device 200 is basically consistent with the drain-source breakdown voltage of the NMOS structure. After avalanche breakdown occurs in device 200, a large number of charge carriers are generated and continuously flow through the parasitic trap resistor Rp2 on the P-type trap region 270. This increases the voltage drop Vbe between the base and emitter of the lateral parasitic transistor NPN2. When this voltage drop Vbe increases to a value greater than a predetermined value (e.g., 0.7V), the lateral parasitic transistor NPN2 is triggered and operates in the amplification region. The amplified collector current flows into the base of the parasitic transistor PNP1, eventually turning on PNP1. At this time, the parasitic transistors NPN2 and PNP1 form an effective positive feedback loop, ultimately forming a low-resistance lateral SCR discharge path P1 in device 200 (e.g., ...). Figure 4a The red solid arrow in the image shows the forward current discharge path.

[0094] Figure 3 In this device 200, the structure is symmetrical with the center line of the N-type well region as the axis, so that when the ESD pulse flows into the device 200 from either the anode or the cathode, there is a reverse-biased PN junction inside the device 200 to withstand the voltage. At the same time, positive and negative symmetrical avalanche breakdown voltage, trigger voltage and sustaining voltage can also be formed inside the device 200.

[0095] The reverse working principle of device 200 is basically similar to its forward working principle, combined with Figure 3 and Figure 4bWhen device 200 is reverse-triggered, for example when an ESD pulse reaches the cathode of device 200, the introduced second NMOS structure can shift the location of avalanche breakdown of device 200 from the reverse-biased PN junction formed by the N-type well region and P-type well region (when the NMOS structure is not introduced) to the reverse-biased PN junction formed by the N+ injection region 253 and P-type well region 250. Since the doping concentration of N+ injection region 253 is much greater than that of N-type well region, the avalanche breakdown voltage and trigger voltage of device 200 are reduced. At this time, the avalanche breakdown voltage of device 200 is basically the same as the drain-source breakdown voltage of NMOS structure. After avalanche breakdown occurs in device 200, a large number of charge carriers are generated and continuously flow through the parasitic well resistor Rp1 on the P-type well region 250. This increases the voltage drop Vbe between the base and emitter of the lateral parasitic transistor NPN1. When this voltage drop Vbe increases to a value greater than a predetermined value (e.g., 0.7V), the lateral parasitic transistor NPN1 is triggered and operates in the amplification region. The amplified collector current flows into the base of the parasitic transistor PNP1, eventually turning on PNP1. At this time, the parasitic transistors NPN1 and PNP1 form an effective positive feedback loop, ultimately forming a low-resistance lateral SCR discharge path P3 in device 200 (e.g., ...). Figure 4b The blue solid arrow in the image shows the reverse circuit discharge path.

[0096] It is understood that the bidirectional thyristor electrostatic discharge (ESD) device 200 disclosed in this embodiment not only has bidirectional withstand voltage and bidirectional ESD protection functions, but also has low avalanche breakdown voltage and trigger voltage. Meanwhile, the high doping concentration in the N+ implantation region also enables the device 200 to have low on-resistance.

[0097] Example 2

[0098] refer to Figure 6a , Figure 6b , Figure 7a and Figure 7b , Figure 6a and Figure 6b Cross-sectional views of the bidirectional thyristor electrostatic discharge (ESD) device provided in the second embodiment of this application are shown in different implementations. Figure 7a It shows Figure 6a and Figure 6b A schematic diagram of the equivalent circuit and forward ESD current discharge path of a thyristor electrostatic discharge device. Figure 7b It shows Figure 6a and Figure 6b A schematic diagram of the equivalent circuit and reverse ESD current discharge path of a thyristor electrostatic discharge device.

[0099] In this embodiment, the bidirectional thyristor electrostatic discharge (ESD) protection device 200 has a structure that is basically the same as that of the bidirectional thyristor ESD protection device 200 in the first embodiment described above, and the similarities will not be repeated here.

[0100] The difference lies in: in this embodiment, such as Figure 6a , Figure 6b , Figure 7a and Figure 7b As shown, the device 200 further includes: an N-type buried layer 220 located on the substrate 210 and at least partially disposed in the epitaxial layer 230; and an N-type deep well 240 located above the N-type buried layer 220 and in contact with the upper surface of the N-type buried layer 220.

[0101] In this embodiment, the doping concentration of the N-type buried layer 220 is greater than the doping concentration of the N-type well region, and the doping concentration of the N-type buried layer 220 is less than the doping concentration of the N+ implanted region. The doping concentration of the N-type well region is greater than the doping concentration of the N-type deep well 240.

[0102] By setting the N-type buried layer 220, on the one hand, a vertical parasitic transistor structure can be formed in the device 200 based on the heavily doped N-type buried layer 220; on the other hand, the N-type buried layer 220 can form a reverse-biased PN junction with the P-type substrate 210 and the P-type epitaxial layer 230, which can prevent leakage current.

[0103] It should be noted that, Figure 6a and Figure 6b The illustration shows an example where a portion of the N-type buried layer 220 is located within the P-type substrate 210 and another portion is located within the P-type epitaxial layer 230. However, other implementations are also possible. For example, the N-type buried layer 220 may be entirely located within the P-type substrate 210, with only its upper surface in contact with the P-type epitaxial layer 230. Alternatively, the N-type buried layer 220 may also be entirely located within the P-type epitaxial layer 230, with only its lower surface in contact with the P-type substrate 210.

[0104] The N-type deep well 240 includes a first portion, and at least a portion of the P-type well region 250, N-type well region 260, and P-type well region 270 are disposed on the first portion of the N-type deep well 240. For example, Figure 6a The illustration shows an embodiment where the first part of the N-type deep well 240 is located only between the N-type well region 260 and the N-type buried layer 220 (i.e., the upper surface of the first part of the N-type deep well 240 is in contact with the N-type well region 260 and the lower surface is in contact with the N-type buried layer 220). Figure 6aThe illustration shows an embodiment where the first portion of the N-type deep well 240 is located below the P-type well regions 250, 260, and 270, between the N-type buried layer 220. In this embodiment, since the doping concentration of the N-type deep well 240 is greater than the doping concentration of the epitaxial layer 230, the parasitic resistance in these regions can be further reduced. Of course, in other embodiments, the first portion of the N-type deep well 240 may also be disposed in all or part of the region between the P-type well regions 250, 260, and 270, between the N-type buried layer 220, and / or may be disposed in all or part of the region of the epitaxial layer 230 surrounding the P-type well regions 250 and 270.

[0105] The N-type deep well 240 further includes: a second portion located between the P-type well region 281 and the P-type well region 250 (the upper surface of the second portion contacts the corresponding isolation structure 290, and the lower surface contacts the N-type buried layer 220), and a third portion located between the P-type well region 270 and the P-type well region 282 (the upper surface of the third portion contacts the corresponding isolation structure 290, and the lower surface contacts the N-type buried layer 220). In some other embodiments, the second and third portions of the N-type deep well 240 may be replaced with other isolation structures depending on the actual situation.

[0106] Optionally, in some embodiments, the second and third portions of the N-type deep well 240 are independent well region structures, that is, from the top view of the device 200, the second and third portions of the N-type deep well 240 are not connected. At the same time, in these embodiments, the P-type well region 281 and the P-type well region 282 are also independent well region structures. In other embodiments, the second and third portions of the N-type deep well 240 are manifestations of an annular well region at different positions on the same cross-section. That is, from the top view of the device 200, the second and third portions of the N-type deep well 240 are connected to each other to form a whole annular region, and the P-type well region 250, N-type well region 260 and P-type well region 270 are all located inside the annular region formed by the second and third portions of the N-type deep well 240. At the same time, in these embodiments, the P-type well region 281 and P-type well region 282 also form an annular region, and the P-type well region 281 and P-type well region 282 also form an annular region located outside the annular region formed by the second and third portions of the N-type deep well 240.

[0107] In addition, when the first part of the N-type deep well 240 is not arranged to surround the P-type well region 250 and the P-type well region 270, there is a certain gap between the second and third parts of the N-type deep well 240 and the adjacent P-type well region.

[0108] It is understandable that the second and third parts of the N-type deep well 240 can also form a reverse-biased PN junction with the outermost P-type epitaxial layer 230, which can further improve the leakage protection effect.

[0109] In a further preferred embodiment, device 200 further includes a P+ injection region 261 located in the N-type well region 260 and between the N+ injection regions 253 and 271. This P+ injection region 261 is a floating injection region, which increases the doping concentration in the local area below it, thereby suppressing current from passing through the device surface, i.e., suppressing the discharge current from passing through the lateral SCR current discharge path. This further promotes the activation of the vertical SCR current discharge path in device 200, making it the dominant current discharge path. While maintaining low avalanche breakdown voltage and trigger voltage, this further reduces the on-resistance and clamping voltage of the device, effectively avoiding the risk of premature breakdown of internal circuitry due to excessive clamping voltage.

[0110] Furthermore, the N+ injection region 253 and the P+ injection region 261, as well as the P+ injection region 261 and the N+ injection region 271, are isolated via the isolation structure 290.

[0111] Figure 6a and Figure 6b If the N-type well region 260, the N-type deep well 240 and the N-type buried layer 220 are considered as an integral structure (as denoted as N1), then N1, together with the P-type well region 250 and the N+ injection region 252, also constitutes the longitudinal parasitic transistor NPN3 in the device 200, and N1, together with the P-type well region 270 and the N+ injection region 272, also constitutes the longitudinal parasitic transistor NPN4 in the device 200.

[0112] It should be noted that, in this embodiment, in addition to forming structures such as P-type well region 281, P-type well region 282, P+ injection region 283 and P+ injection region 284, other regions outside the second and third parts of the N-type deep well 240 can also be configured in other ways, as long as it does not affect the formation of current discharge based on the longitudinal parasitic transistors NPN3 and NPN4 and the parasitic transistor PNP1 in the device.

[0113] Similarly, taking the example of P+ injection region 251, N+ injection region 252, and first gate structure 254 connected to the anode of device 200 via connection structure 292, and second gate structure 274, N+ injection region 272, and P+ injection region 273 connected to the cathode of device 200 via connection structure 293, combined with... Figure 6a , Figure 6b and Figure 7aBy introducing an NMOS structure (including an interconnected first NMOS structure and a second NMOS structure) into device 200, and simultaneously introducing a heavily doped N-type buried layer 220, when device 200 is forward-triggered, for example, when an ESD pulse reaches the anode of device 200, a low-resistance lateral SCR discharge path P1 can be formed in device 200. Then, the heavily doped N-type buried layer 220 can attract more electrons from the N-type well region 260, reducing the current through the lateral parasitic transistor NPN2 and increasing the current through the vertical parasitic transistor NPN4. Finally, the vertical SCR discharge path P2 formed by the parasitic transistors PNP1 and NPN4 serves as the main ESD current discharge path of device 200 (e.g., ...). Figure 7a The red solid arrow P2 in the diagram shows the forward circuit discharge path. Compared to the current flowing to the device cathode through the lateral parasitic transistor NPN2, the current path when flowing to the device cathode through the vertical parasitic transistor NPN4 is longer. This is equivalent to extending the ESD current discharge path in device 200, enabling device 200 to have a higher sustaining voltage. At the same time, the N-type buried layer 220 with a higher doping concentration also enables device 200 to have a lower on-resistance.

[0114] Figure 6a and Figure 6b In the device 200, the structure is also symmetrical with the center line of the N-type well region as the axis, so that when the ESD pulse flows into the device 200 from the anode or the cathode, there is a reverse biased PN junction inside the device 200 to withstand the voltage. At the same time, positive and negative symmetrical avalanche breakdown voltage, trigger voltage and sustaining voltage can also be formed inside the device 200.

[0115] The reverse operating principle of device 200 is basically similar to its forward operating principle. When device 200 is reverse-triggered, for example, when an ESD pulse reaches the cathode of device 200, a low-resistance lateral SCR discharge path P3 can be formed in device 200 first. Then, the heavily doped N-type buried layer 220 can attract more electrons from the N-type well region 260, thereby reducing the current through the lateral parasitic transistor NPN1 and increasing the current through the vertical parasitic transistor NPN3. Finally, the vertical SCR discharge path P4 formed by the parasitic transistors PNP1 and NPN3 is used as the main ESD current discharge path of device 200 (e.g., Figure 7bThe blue solid arrow P4 in the diagram shows the forward circuit discharge path. Compared to the current flowing to the device anode through the lateral parasitic transistor NPN1, the current path when flowing to the device anode through the vertical parasitic transistor NPN3 is longer. This is equivalent to extending the ESD current discharge path in device 200, enabling device 200 to have a higher sustaining voltage. At the same time, the N-type buried layer 220 with a higher doping concentration also enables device 200 to have a lower on-resistance.

[0116] It is understood that the bidirectional thyristor electrostatic discharge (ESD) protection device 200 disclosed in this embodiment not only has bidirectional withstand voltage and bidirectional ESD protection functions, but also has lower avalanche breakdown voltage, lower trigger voltage, higher sustaining voltage and smaller on-resistance, and its ESD protection capability is superior.

[0117] Furthermore, this application also discloses an embodiment of a method for fabricating a bidirectional thyristor electrostatic discharge (ESD) device, which can be used to manufacture the bidirectional thyristor ESD device 200 disclosed in the first embodiment above. In specific implementation, as follows... Figure 5 As shown, the preparation method includes performing the following steps:

[0118] Step 510: A first P-type well region, an N-type well region, and a second P-type well region are sequentially formed in the epitaxial layer on the substrate along the lateral direction.

[0119] Step 520: A first P+ injection region and a first N+ injection region are formed within the first P-type well region; a second N+ injection region spanning the first P-type well region and the N-type well region; a third N+ injection region spanning the N-type well region and the second P-type well region; and a fourth N+ injection region and a second P+ injection region are formed within the second P-type well region.

[0120] Step 530: A first gate structure is formed between the first N+ injection region and the second N+ injection region, and a second gate structure is formed between the third N+ injection region and the fourth N+ injection region.

[0121] Step 540: Interconnect the first P+ implantation region, the first N+ implantation region, and the first gate structure; interconnect the second gate structure, the fourth N+ implantation region, and the second P+ implantation region; interconnect the second N+ implantation region and the third N+ implantation region; interconnect the first N+ implantation region and the first gate structure; and interconnect the second gate structure and the fourth N+ implantation region.

[0122] It should be noted that the specific implementation of each step in the fabrication method of the bidirectional thyristor electrostatic discharge (ESD) device described above, and the effects to be obtained during implementation, can be referred to the aforementioned [section / section / etc.]. Figure 3 and Figure 4a , 4b The embodiments of bidirectional thyristor electrostatic discharge (ESD) devices are described in detail here.

[0123] Furthermore, this application also discloses an embodiment of another method for fabricating a bidirectional thyristor electrostatic discharge (ESD) device, which can be used to manufacture the bidirectional thyristor ESD device 200 disclosed in the second embodiment above. In specific implementation, as follows... Figure 8 As shown, this preparation method is similar to the aforementioned Figure 5 The preparation methods disclosed in the literature are basically the same, and their similarities will not be repeated here.

[0124] The difference lies in that the preparation method in this embodiment further includes performing the following steps before performing step 510 above:

[0125] Step 810: Form an N-type buried layer on the substrate, at least partially located in the epitaxial layer.

[0126] Step 820: Form an N-type deep well located above the N-type buried layer. The N-type deep well includes a first part, and at least a portion of the N-type well region is disposed on the first part of the N-type deep well, including the first P-type well region, the N-type well region, and the second P-type well region.

[0127] In some embodiments, the N-type deep well further includes: a second portion located on the side of the first P-type well region away from the N-type well region and a third portion located on the side of the second P-type well region away from the N-type well region.

[0128] In other embodiments, the N-type deep well further includes a second portion; the second portion is an annular region, and the first P-type well region, the N-type well region, and the second P-type region are all located inside the annular region formed by the second portion of the N-type deep well.

[0129] In a further preferred embodiment, step 530 further includes forming a third P+ injection region located in the N-type well region. This third P+ injection region is located between the second N+ injection region 253 and the third N+ injection region 271.

[0130] It should be noted that the specific implementation of each step in the fabrication method of the bidirectional thyristor electrostatic discharge (ESD) device described above, and the effects to be obtained during implementation, can be referred to the aforementioned [section / section / etc.]. Figure 6a , Figure 6b and Figure 7a , 7b The embodiments of bidirectional thyristor electrostatic discharge (ESD) devices are described in detail here.

[0131] In summary, the bidirectional thyristor electrostatic discharge (ESD) device and its fabrication method provided in this application have an N+ injection region spanning the P-type well region and an N-type well region, as well as a first gate structure and a second gate structure. This forms two interconnected NMOS structures in the device based on the original N+ injection region in the P-type well region. Compared with devices in the prior art that do not have NMOS structures, this application can transfer the avalanche breakdown voltage after device triggering from the reverse-biased PN junction formed by the original N-type well region and P-type well region to the reverse-biased PN junction formed by the N+ injection region and P-type well region based on the interconnected NMOS structure. Since the doping concentration of the N+ injection region is much greater than that of the N-type well region, the avalanche breakdown voltage and trigger voltage of the device can be reduced by adopting the solution of this application.

[0132] In a further preferred embodiment, a heavily doped N-type buried layer on the substrate and an N-type deep well above the buried layer are also provided in the device, thereby forming a vertical parasitic transistor structure in the device. After the device is triggered, the heavily doped N-type buried layer can attract more electrons, thereby increasing the current through the vertical parasitic transistor. A vertical SCR discharge path is formed in the device, which flows through the vertical parasitic transistor, effectively extending the discharge path of ESD current in the device, so that the device can have a higher holding voltage and a lower on-resistance.

[0133] In a further preferred embodiment, the device is configured to have a symmetrical structure with the centerline of the N-type well region as the axis, enabling the device to achieve bidirectional withstand voltage and bidirectional electrostatic protection.

[0134] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A bidirectional silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection device, comprising: Substrate; Epitaxial layer located on the substrate; A first P-type well region, an N-type well region, and a second P-type well region are sequentially disposed in the epitaxial layer along the transverse direction; The first NMOS structure includes: a first P+ injection region and a first N+ injection region disposed within the first P-type well region, a second N+ injection region spanning the first P-type well region and the N-type well region, and a first gate structure located between the first N+ injection region and the second N+ injection region. The second NMOS structure includes: a third N+ injection region spanning the N-type well region and the second P-type well region, a fourth N+ injection region and a second P+ injection region disposed within the second P-type well region, and a second gate structure located between the third N+ injection region and the fourth N+ injection region; The first P+ injection region, the first N+ injection region, and the first gate structure are interconnected, and the second gate structure, the fourth N+ injection region, and the second P+ injection region are interconnected.

2. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 1, wherein, The first P+ injection region, the first N+ injection region, and the first gate structure are connected to one of the anode and cathode of the bidirectional thyristor electrostatic discharge device; The second gate structure, the fourth N+ injection region, and the second P+ injection region are connected to one of the anode and cathode of the bidirectional thyristor electrostatic discharge device.

3. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 1, wherein, Also includes: An N-type buried layer is located on the substrate and is at least partially disposed in the epitaxial layer; An N-type deep well located above the N-type buried layer; The N-type deep well includes a first portion, and at least a portion of the N-type well region is disposed on the first portion of the N-type deep well, including the first P-type well region, the N-type well region, and the second P-type well region.

4. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 1, wherein, Also includes: The third P+ injection region is located in the N-type well region; The third P+ injection region is located between the second N+ injection region and the third N+ injection region.

5. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 3, wherein, The N-type deep well further includes: a second portion located on the side of the first P-type well region away from the N-type well region, and a third portion located on the side of the second P-type well region away from the N-type well region.

6. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 3, wherein, The N-type deep well also includes a second part; The second part is an annular region, and the first P-type well region, the N-type well region, and the second P-type region are all located inside the annular region formed by the second part of the N-type deep well.

7. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 5, wherein, Also includes: The third P-type well region is located in the epitaxial layer on the side of the second part of the N-type deep well away from the first P-type well region; The fourth P+ injection region is located within the third P-type well region; The fourth P-type well region is located in the epitaxial layer on the side of the third portion of the N-type deep well away from the second P-type well region; The fifth P+ injection region is located within the fourth P-type well region; Both the fourth P+ injection region and the fifth P+ injection region are used to connect to the cathode of the bidirectional thyristor electrostatic discharge (ESD) device.

8. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 6, wherein, Also includes: The third P-type well region is a ring-shaped region, and the ring-shaped region formed by the third P-type well region is located in the epitaxial layer outside the ring-shaped region formed by the second part of the N-type deep well. The fourth P+ injection region is located within the third P-type well region, and the fourth P+ injection region is used to connect to the cathode of the bidirectional thyristor electrostatic discharge device.

9. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 1, wherein, The epitaxial layer is a P-type epitaxial layer.

10. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 1, wherein, The first P+ injection region and the first N+ injection region, and the fourth N+ injection region and the second P+ injection region are isolated or in contact via an isolation structure.

11. The bidirectional thyristor electrostatic discharge (ESD) protection device according to any one of claims 1-8, wherein, When there is a gap between two adjacent injection zones, an isolation structure is also provided at each gap.

12. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 1, wherein, The bidirectional thyristor electrostatic discharge (ESD) device has a symmetrical structure with the center line of the N-type well region as the axis.

13. The bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 3, wherein, The doping concentration of the N-type buried layer is greater than the doping concentration of the N-type well region.

14. A method for fabricating a bidirectional thyristor electrostatic discharge (ESD) device, comprising: A first P-type well region, an N-type well region, and a second P-type well region are sequentially formed laterally in the epitaxial layer on the substrate. A first P+ injection region and a first N+ injection region are respectively formed within the first P-type well region, a second N+ injection region spanning the first P-type well region and the N-type well region, a third N+ injection region spanning the N-type well region and the second P-type well region, and a fourth N+ injection region and a second P+ injection region are respectively formed within the second P-type well region. A first gate structure is formed between the first N+ injection region and the second N+ injection region, and a second gate structure is formed between the third N+ injection region and the fourth N+ injection region; The first P+ injection region, the first N+ injection region, and the first gate structure are interconnected; the second gate structure, the fourth N+ injection region, and the second P+ injection region are interconnected; and the second N+ injection region and the third N+ injection region are interconnected.

15. The preparation method according to claim 14, wherein, Before the formation of the first P-type well region, the N-type well region, and the second P-type well region, the following steps are also included: An N-type buried layer, at least partially located within the epitaxial layer, is formed on the substrate; An N-type deep well is formed above the N-type buried layer; The N-type deep well includes a first part; Among the first P-type well region, the N-type well region, and the second P-type well region, at least a portion of the N-type well region is disposed on the first part of the N-type deep well.

16. The preparation method according to claim 14 or 15, wherein, Also includes: A third P+ injection region is formed within the N-type well region.

Images