An anti-radiation double-junction three-terminal silicon-based passivated contact structure solar cell and a preparation method thereof
Patent Information
- Application Number
- CN202611092380.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-22
- Publication Date
- 2026-10-13
Smart Images
Figure CN122909902A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the technical field of the solar photovoltaic industry, specifically relating to a radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell and its preparation method. Background Technology
[0002] Currently, the green energy system represented by photovoltaic power generation is being built at an accelerated pace. Its large-scale application has placed higher demands on crystalline silicon solar cells, especially in terms of continuously improving photoelectric conversion efficiency and significantly reducing the cost per kilowatt-hour.
[0003] Passivated back contact (BC) crystalline silicon solar cell technology has approached the theoretical efficiency limit (~29%) of single-junction silicon solar cells, with mass production efficiency exceeding 26%, demonstrating the highest level currently achieved by the crystalline silicon route. To further overcome the efficiency bottleneck, perovskite / crystalline silicon tandem solar cells have become a research hotspot, with theoretical efficiencies reaching over 40%. However, they face challenges such as complex fabrication processes, poor process compatibility, and high mass production costs, making it difficult to meet the stringent reliability requirements for terrestrial and space applications in the short term.
[0004] Existing passivated back contact structures (such as traditional SiO2 tunneling layers and amorphous silicon layers) face the following technical bottlenecks when applied to terrestrial and space environments: First, under high-temperature processes, tunneling layers are prone to pinhole defects, leading to direct contact between the doped layer and the silicon substrate, resulting in high recombination currents and severely degrading passivation performance. Second, in space environments, the synergistic effect of chemical passivation and field-effect passivation degrades due to the increased irradiation-induced interface state density, resulting in a decrease in carrier selective transport capability. Third, traditional passivated back contact structures struggle to further break through the theoretical efficiency limit of crystalline silicon and cannot meet the requirements for efficient carrier collection in space environments, thus restricting their long-term service stability in both terrestrial and space environments.
[0005] Therefore, it is urgent to explore battery technology pathways that combine high efficiency potential, simple process, and adaptability to both terrestrial and space environments, based on existing crystalline silicon technology, in order to achieve a synergistic breakthrough in photoelectric conversion performance and environmental tolerance. Summary of the Invention
[0006] The purpose of this section is to outline some aspects of the embodiments of the present invention and to briefly describe some preferred embodiments.
[0007] In view of the problems existing in the above and / or prior art, the present invention is proposed.
[0008] Therefore, the purpose of this invention is to overcome the shortcomings of the prior art and provide a radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell.
[0009] To solve the above technical problems, the present invention provides the following technical solution: a radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell, characterized in that: the structure of the cell is arranged from top to bottom as follows: electrode one (1), passivation antireflection layer / conductive layer one (2), high-k stack one (3), front surface pn junction layer (4), heterojunction high-k double barrier layer one (5), silicon substrate (6), heterojunction high-k double barrier layer two (7), electron transport layer (8), hole transport layer (9), high-k stack two (10), passivation antireflection layer / conductive layer two (11) and electrode two (12).
[0010] As a preferred embodiment of the radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell of the present invention, wherein: the electrode one (1) includes n + Electrode, the second electrode (12) includes p + Electrode.
[0011] As a preferred embodiment of the radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell of the present invention, wherein: the silicon substrate (6) includes a p-type Ga-doped silicon wafer with a resistivity of 3-10 Ω·cm and a minority carrier lifetime of >1.5 ms.
[0012] As a preferred embodiment of the radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell of the present invention, wherein: the passivation antireflection layer comprises a double-sided composite layer of aluminum oxide and silicon nitride, wherein the thickness ratio of aluminum oxide to silicon nitride is 6 nm:80 nm.
[0013] As a preferred embodiment of the radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell of the present invention, wherein: the high-k stack comprises,
[0014] A heterojunction double-barrier layer synthesized from a tunneling layer and a lanthanide-doped high-k dielectric layer; wherein...
[0015] The tunneling layer includes SiO x SiO x N y ia-Si:H, lanthanide-doped high-k dielectric layers include HfO2 and TiO2;
[0016] As a preferred embodiment of the radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell of the present invention, wherein: the thickness of the tunneling layer is 1-3 nm, and the thickness of the lanthanide-doped high-k dielectric layer is 3-20 nm.
[0017] The heterojunction high-k double barrier layer includes,
[0018] A heterojunction double-barrier layer synthesized from a tunneling layer and a lanthanide-doped high-k dielectric layer; wherein...
[0019] The tunneling layers include SiOx, SiOxNy, and ia-Si:H; the lanthanide-doped high-k dielectric layers include HfO2 and TiO2.
[0020] The tunneling layer is 1 nm thick, the lanthanide-doped high-k dielectric layer is 1-2.5 nm thick, and the total thickness is approximately 1-2.5 nm.
[0021] As a preferred embodiment of the radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell of the present invention, wherein: the front surface pn junction layer is a phosphorus-doped polycrystalline silicon layer with a thickness of 115 nm and a phosphorus doping concentration of 7.5 × 10⁻⁶. 20 atoms / cm 3 The sheet resistance is 125 Ω / sq.
[0022] As a preferred embodiment of the radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell of the present invention, wherein: the raw material of the electron transport layer is MoO3, V2O5, WO3, NiOx, Cu2O, PDOT:PSS, CuI, microcrystalline silicon, polycrystalline silicon, polycrystalline silicon oxide, or polycrystalline silicon carbon oxide, and the thickness of the electron transport layer is 20-260 nm.
[0023] The hole transport layer is made of TiO2 and ZnO. x , SnO2, Ta2O5, Nb2O5, TiN, TiO x N y TaN x Microcrystalline silicon, polycrystalline silicon, polycrystalline silicon oxide, and polycrystalline silicon carbon oxide are all examples of materials that require doping with group III elements when the hole transport layer is a silicon-based material.
[0024] Another objective of this invention is to overcome the shortcomings of the prior art and provide a method for fabricating a double-junction three-terminal silicon-based passivated contact battery structure, comprising,
[0025] Double-sided polishing: Using an n / p type monocrystalline silicon wafer as a silicon substrate, the wafer is first pre-cleaned with alkali / hydrogen peroxide, and then polished to form a flat surface structure.
[0026] Depositing a high-k double-barrier tunneling layer and hole transport layer in a heterostructure: The tunneling layer, hole transport layer and mask layer are sequentially constructed using chemical vapor deposition, atomic layer deposition or physical vapor deposition, and marked as the back side. The thickness of the tunneling layer is 1-2.5 nm, the thickness of the hole transport layer is 20-400 nm, and the thickness of the mask layer is 20-100 nm.
[0027] Backside grooving to form n-region: The n-region is created using ultraviolet picosecond / ultraviolet femtosecond / green picosecond lasers, and the backside mask layer, the tunneling layer / hole transport layer of the laser area and the frontside coating layer are removed by wet or dry etching.
[0028] Depositing a high-k double-barrier tunneling layer and an electron transport layer in a heterostructure: The tunneling layer and the electron transport layer are prepared sequentially by chemical vapor deposition, atomic layer deposition or physical vapor deposition. The thickness of the tunneling layer is 1-2 nm, the thickness of the electron transport layer is 20-260 nm, and the thickness of the mask layer is 30-100 nm.
[0029] Backside grooving to form p-region and np-region isolation bands: A mask layer is deposited on the backside, and the n-region above the p-region and the np-region isolation band are opened using ultraviolet picosecond / ultraviolet femtosecond / green picosecond lasers. The electron transport layer, tunneling passivation layer and front-side coating layer of the backside laser area are removed by wet or dry etching. The laser area width is 500-900 μm.
[0030] Front surface pn junction region: A good textured structure is formed on the front side by alkaline texturing. Then, a tunneling layer and a transport layer are formed sequentially by chemical vapor deposition, atomic layer deposition, or physical vapor deposition to form the front surface pn junction region. The thickness of the tunneling layer is 1-2 nm, the thickness of the transport layer is 20-300 nm, and the thickness of the mask layer is 40-100 nm.
[0031] Front surface finger structure: A mask layer is deposited on the front side, and the reserved non-finger area is patterned using ultraviolet picosecond / ultraviolet femtosecond / green picosecond lasers. The transmission layer and tunneling passivation layer of the laser area on the back side are removed by wet or dry etching. The width of the laser area is 800-1500 μm.
[0032] Deposition of high-k stack: A layer of SiO is sequentially deposited on both sides of the cell. x The oxide layer thickness is 1-3 nm; then a high-k material is deposited and lanthanide doping is performed, with the high-k material thickness being 3-20 nm.
[0033] Antireflective layer / transparent conductive layer: deposited double-sided passivated aluminum oxide with a thickness controlled at 3-20 nm, silicon nitride with a thickness controlled at 65-90 nm, and a refractive index of 1.7-2.3;
[0034] Alternatively, a transparent conductive oxide layer, with a thickness controlled at 65-100nm and a sheet resistance of 20-50 ohm / sqr;
[0035] Backside Gap Area Isolation and Insulation: The Gap area is patterned using ultraviolet picosecond / ultraviolet femtosecond / green picosecond lasers, and the conductive layer of the Gap area is removed by wet or dry etching.
[0036] Screen printing: Non-burn-through conductive paste is used to screen print the n / p area on the back of the battery and the pn area on the front to form electrodes. The finished product is then manufactured through a sintering process.
[0037] Beneficial effects of this invention:
[0038] This invention provides a dual-junction three-terminal passivated contact crystalline silicon solar cell that combines excellent efficiency and high reliability, meeting the urgent needs of ground and space applications for high conversion efficiency and long lifespan photovoltaic power sources.
[0039] (1) The present invention uses SiO2 as an ingredient. x SiO x N y Together with lanthanide-doped high-k dielectric layers (such as HfO2, TiO2, etc.), they form a heterojunction high-k double barrier structure. Compared with traditional SiO2 or amorphous silicon passivation layers, it can suppress pinhole defects under high temperature and long-term service, reduce interfacial carrier recombination, and simultaneously improve passivation effect and device reliability.
[0040] (2) Simultaneously construct a dual-junction three-terminal battery structure with front surface pn junction and back passivation contact to optimize carrier transport path, break through the carrier collection bottleneck of traditional single-junction battery, reduce carrier recombination loss and improve photoelectric conversion efficiency.
[0041] (3) By stabilizing the interfacial chemical bonds through lanthanide doping high-k interfacial layers, the passivation stability and carrier selective transport capability under space irradiation environment are significantly enhanced, solving the degradation problem of traditional passivation structures and meeting the long life requirements of aerospace photovoltaics; Attached Figure Description
[0042] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0043] Figure 1 This is a structural diagram of a double-junction three-terminal silicon-based passivated contact solar cell in Embodiment 1 of the present invention.
[0044] Figure 2 This is a partial flowchart of the method for fabricating a double-junction three-terminal silicon-based passivated contact structure solar cell in Embodiment 1 of the present invention.
[0045] Figure 3 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0046] Figure 4 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0047] Figure 5 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0048] Figure 6 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0049] Figure 7 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0050] Figure 8 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0051] Figure 9 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0052] Figure 10 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0053] Figure 11 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0054] Figure 12 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0055] Figure 13 This is a flowchart illustrating the fabrication method of a double-junction, three-terminal silicon-based passivated contact solar cell in an embodiment of the present invention.
[0056] Figure 14 This is a structural diagram of the solar cell in Comparative Example 1 of the present invention.
[0057] Figure 15 This is a structural diagram of the solar cell in Comparative Example 2 of the present invention.
[0058] Figure 16 The figure shows the external quantum efficiency test results of the crystalline silicon solar cells prepared in Example 1 and Comparative Example 1 according to the present invention. Detailed Implementation
[0059] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the examples in the specification. The raw materials used in the present invention are all commercially available products.
[0060] Example 1
[0061] This embodiment provides a radiation-resistant dual-junction three-terminal silicon-based passivated contact structure solar cell, such as... Figure 1 As shown, the battery structure is arranged with n units from top to bottom. +Electrode (1), passivation layer (2), high-k stack (3), front surface pn junction (4), heterojunction double barrier layer (5), silicon substrate (6), heterojunction double barrier tunneling layer (7), electron transport layer (8), hole transport layer (9), high-k stack (10), passivation layer (11) and p + Electrode (12);
[0062] The battery structure fabrication method in this embodiment uses a p-type Ga-doped silicon wafer with high minority carrier lifetime as the substrate, which has a resistivity of 3-10 Ω·cm and a minority carrier lifetime of >1.5 ms.
[0063] (1) Double-sided polishing: Using p-type single crystal silicon wafers as silicon substrates, the wafers are first pre-cleaned with alkali / hydrogen peroxide in a tank-type machine, and then polished to form a flat surface structure, resulting in a silicon substrate with a grain size of 12.5 µm and a reflectivity of 38%.
[0064] See Figure 2 The structure includes a silicon substrate (1).
[0065] (2) Deposition of heterojunction double-barrier tunneling layer, boron-doped polycrystalline silicon layer, borosilicate glass layer and front-side coating, see [reference] Figure 3 The structure includes a silicon substrate (1), a heterojunction double barrier tunneling layer (2), a boron-doped polycrystalline silicon layer (3), a borosilicate glass layer (4), and a front-side wrapping layer (5).
[0066] The specific method is as follows:
[0067] A high-k double-barrier tunneling layer for heterostructures was deposited using atomic layer deposition (ALD): SiO₂ x / Synthesis of a heterojunction double-barrier tunneling layer using lanthanide-doped high-k dielectric layer (HfO2) (2), wherein 1nm SiO x / 1 nm lanthanide-doped high-k dielectric layer (HfO2), with a lanthanide doping concentration of 2%;
[0068] Specifically, the silicon substrate from step (1) is placed in the ALD reaction chamber, and a 1 nm thick SiO2 layer is deposited alternately using diethylaminosilane as the silicon precursor and O3 as the oxygen source. x Tunneling layer;
[0069] Then in the SiO x On the surface of the tunneling layer, a 1 nm thick lanthanide-doped HfO2 high-k dielectric layer was deposited using tetradimethylaminohafnium as a hafnium precursor, triisopropylcyclopentadienyllanthanum as a lanthanum doping source, and H2O as an oxygen source. The lanthanide doping concentration was 2%.
[0070] After deposition, the material was annealed at 400 °C in a nitrogen-hydrogen mixed atmosphere to obtain a heterojunction double barrier tunneling layer (2).
[0071] An amorphous silicon layer was deposited on the surface of a heterojunction double-barrier tunneling layer (2) using silane as the silicon source via LPCVD. Then, boron doping was performed in a high-temperature tube furnace using BCl3 as the boron source at 300 mBar and 900 °C, with BCl3 at 50 sccm, N2 at 2000 sccm, and O2 at 450 sccm, forming boron-doped amorphous silicon. This was followed by annealing at 900 °C to crystallize the silicon and activate the boron doping atoms, resulting in a thickness of 300 nm and a doping concentration of 6.5 × 10⁻⁶. 19 atoms / cm 3 A boron-doped polycrystalline silicon layer with a sheet resistance of 130 Ω / sq (3);
[0072] During this process, a borosilicate glass layer (4) with a thickness of 35 nm is simultaneously formed covering the surface of the boron-doped polycrystalline silicon layer (3);
[0073] Meanwhile, as the gaseous reactants flow around the edge of the silicon wafer and are deposited or reacted on the non-target surface, a front-side coating (5) is formed with a thickness of 30-40 nm.
[0074] (3) Backside slot n area:
[0075] The borosilicate glass layer was patterned using an ultraviolet picosecond laser, and the back mask layer (BSG layer), the polysilicon layer in the laser area, and the front coating layer were removed by wet etching.
[0076] See Figure 4 It includes a silicon substrate (1), a heterojunction double-barrier tunneling layer (2), and a hole transport layer (3).
[0077] The laser region has a width of 550 μm and a laser power of 55 W.
[0078] (4) Deposition of a heterostructure with a high-k double-barrier tunneling layer and an electron transport layer:
[0079] The tunneling layer was deposited using atomic layer deposition (ALD), and the phosphorus-doped polycrystalline silicon layer was deposited using LPCVD. (See [link to relevant documentation]). Figure 5 It includes a silicon substrate (1), a heterojunction double barrier layer (2), a hole transport layer (3), a heterojunction double barrier layer (4), a doped polycrystalline silicon layer (5), a phosphosilicate glass layer (6), and a front-side coating layer (7).
[0080] Specifically, the silicon wafer obtained in step (3) is placed in the ALD reaction chamber, and a SiO2 layer with a thickness of 1 nm is deposited alternately using diethylaminosilane as the silicon precursor and O3 as the oxygen source. x Tunneling layer; then in the SiO xOn the surface of the tunneling layer, a 1 nm thick lanthanide-doped HfO2 high-k dielectric layer was deposited using tetradimethylaminohafnium as the hafnium precursor, triisopropylcyclopentadienyllanthanum as the lanthanum dopant source, and H2O as the oxygen source, via cyclic atomic layer deposition. The lanthanide doping concentration was 2%. After deposition, the layer was annealed at 400 °C in a nitrogen-hydrogen mixed atmosphere to obtain SiO2. x / Lanthanide-doped HfO2 heterojunction double barrier layer (4);
[0081] An amorphous silicon layer was deposited on the surface of a heterojunction double barrier layer (4) using LPCVD with silane as the silicon source. Then, phosphorus doping was performed in a high-temperature tube furnace using POCl3 as the phosphorus source at 300 mBar and 800 °C, with N2 flow rate of 2000 sccm, O2 flow rate of 250 sccm, and POCl3 flow rate of 50 sccm. This resulted in a phosphorus-doped amorphous silicon layer, which was then annealed at 850 °C to crystallize and activate the phosphorus-doped atoms, yielding a thickness of 200 nm and a doping concentration of 4.5 × 10²⁰ atoms / cm². 3 A phosphorus-doped polycrystalline silicon layer with a sheet resistance of 115 Ω / sq (5);
[0082] During this process, a 50 nm thick phosphorus-silicon glass layer (6) is formed covering the surface of the phosphorus-doped polycrystalline silicon layer (5); at the same time, due to the gaseous reactants flowing around the edge of the silicon wafer and being deposited or reacted on the non-target surface, a coating layer (7) with a thickness of 30-50 nm is formed.
[0083] (5) Backside slotting to form p-region and np-region isolation band: Ultraviolet picosecond laser is used to pattern the electron transport layer above the gap to be reserved and the hole transport layer area. Wet etching is used to remove the electron transport layer, tunneling passivation layer and front-side coating layer in the backside laser area to form a front-side textured structure. The laser area width is 450 μm, the laser power is 53 W, and the front-side textured reflectivity is 9%.
[0084] See structure Figure 6 It includes a textured surface structure (1), a silicon substrate (2), a heterojunction double barrier layer (3), a hole transport layer (4), and an electron transport layer (5).
[0085] (6) Construct the front surface pn junction region:
[0086] Atomic layer deposition (ALD) was used to deposit the tunneling layer (SiO2). x A lanthanide-doped high-k dielectric layer (HfO2) was deposited, followed by LPCVD deposition of a phosphorus-doped polycrystalline silicon layer and annealing to form a front-surface pn junction region. (See...) Figure 7It includes a front surface pn junction region (1), a heterojunction double barrier tunneling layer (2), a silicon substrate (3), a heterojunction double barrier tunneling layer (4), a hole transport layer (5), an electron transport layer (6), and a phosphosilicate glass layer (7).
[0087] The specific preparation process is as follows:
[0088] In process (5), the silicon wafer is placed in the ALD reaction chamber, and a SiO2 layer with a thickness of 1 nm is deposited alternately using diethylaminosilane as the silicon precursor and O3 as the oxygen source. x Tunneling layer; then in the SiO x On the surface of the tunneling layer, a 1 nm thick lanthanide-doped HfO2 high-k dielectric layer was deposited using tetradimethylaminohafnium as the hafnium precursor, triisopropylcyclopentadienyllanthanum as the lanthanum dopant source, and H2O as the oxygen source, via cyclic atomic layer deposition. The lanthanide doping concentration was 2%. After deposition, the layer was annealed at 400 °C in a nitrogen-hydrogen mixed atmosphere to obtain SiO2. x / Lanthanide-doped HfO2 heterojunction double barrier layer (2).
[0089] An amorphous silicon layer was deposited on the surface of the heterojunction double barrier layer (2) using LPCVD with silane as the silicon source. Then, phosphorus doping was performed in a high-temperature tube furnace using POCl3 as the phosphorus source at 300 mBar and 800 °C, with an N2 flow rate of 2000 sccm, an O2 flow rate of 250 sccm, and a POCl3 flow rate of 50 sccm. This resulted in a phosphorus-doped amorphous silicon layer, which was then annealed at 850 °C to crystallize and activate the phosphorus doping atoms, yielding a layer with a thickness of 115 nm and a doping concentration of 7.5 × 10⁻⁶. 20 atoms / cm 3 A phosphorus-doped polycrystalline silicon layer with a sheet resistance of 125 Ω / sq, i.e., the front surface pn junction region (1);
[0090] During this process, a 50 nm thick phosphorosilicate glass layer (7) is simultaneously formed covering the surface of the front surface pn junction region (1).
[0091] (7) Construct the front surface finger structure:
[0092] In process (6), the non-finger area of the front side of the silicon wafer is patterned using an ultraviolet femtosecond laser, and the polysilicon layer of the front laser area is removed by wet etching.
[0093] The laser region width is 550 μm, and the laser power is 50 W.
[0094] See structure Figure 8It includes a front surface pn junction region (1), a heterojunction double barrier tunneling layer (2), a silicon substrate (3), a heterojunction double barrier tunneling layer (4), a hole transport layer (5), and an electron transport layer (6).
[0095] (8) Deposition of high-k strata:
[0096] A SiO layer was deposited sequentially on the front and back sides of the battery using atomic layer deposition (ALD). x , with lanthanide-doped high-k material (HfO2); oxide layer thickness 2 nm, lanthanide-doped high-k material 12 nm;
[0097] See Figure 9 It includes a high-k stack (1), a front surface pn junction region (2), a heterojunction double barrier tunneling layer (3), a silicon substrate (4), a heterojunction double barrier tunneling layer (5), a hole transport layer (6), an electron transport layer (7), and a high-k stack (8).
[0098] The specific method is as follows:
[0099] In step (7), the silicon wafer is placed in the ALD reaction chamber, and a 2 nm thick SiO2 layer is deposited alternately using diethylaminosilane as the silicon precursor and O3 as the oxygen source. x Tunneling layer; then in the SiO x On the surface of the tunneling layer, a 12 nm thick lanthanide-doped HfO2 high-k dielectric layer is deposited by cyclic atomic layer deposition, using tetradimethylaminohafnium as a hafnium precursor, triisopropylcyclopentadienyl lanthanum as a lanthanum doping source and H2O as an oxygen source.
[0100] After deposition, annealing was performed at 400 °C in a nitrogen-hydrogen mixed atmosphere to obtain SiO2. x / Lanthide element-doped HfO2 high-k stack (1);
[0101] The depositional mode of the high-k stack (8) is consistent with that of the high-k stack (1).
[0102] (9) Anti-reflection layer: Deposit double-sided alumina (AlO2) x Thickness controlled at 6 nm) / Silicon nitride (SiN) x Thickness controlled at 80nm, refractive index 2.1), see Figure 10 It includes a passivation layer (1), a high-k stack (2), a front surface pn junction region (3), a heterojunction double barrier tunneling layer (4), a silicon substrate (5), a heterojunction double barrier tunneling layer (6), a hole transport layer (7), an electron transport layer (8), a high-k stack (9), and a passivation layer (10).
[0103] (10) Screen printing: Non-burn-through conductive paste is used to screen print the n / p area on the back of the battery and the pn area on the front, forming n+ p + and n + The electrodes are then sintered to complete the finished product.
[0104] Example 2
[0105] This embodiment provides a radiation-resistant dual-junction three-terminal silicon-based passivated contact structure solar cell, such as... Figure 11 As shown, the battery structure is arranged with p from top to bottom. + Electrode (1), passivation layer (2), high-k stack (3), front surface pn junction region (4), heterojunction double barrier layer (5), silicon substrate (6), heterojunction double barrier layer (7), hole transport layer (8), electron transport layer (9), high-k stack (10), conductive layer (11), and n + Electrode (12).
[0106] The specific preparation method in this embodiment is as follows:
[0107] An n-type silicon wafer with high minority carrier lifetime is used as the substrate, with a resistivity of 3-10 Ω·cm and a minority carrier lifetime of >1.5 ms.
[0108] (1) Double-sided polishing: Using an n-type single crystal silicon wafer as a silicon substrate, the wafer is first pre-cleaned with alkali / hydrogen peroxide in a tank machine, and then polished to form a flat surface structure (1); the grain size is 17.5 µm and the reflectivity is above 40%, and the structure is the same as step (1) in Example 1.
[0109] (2) Deposition of high-k double-barrier tunneling layer and electron transport layer in heterostructure: The tunneling layer (2) (SiO) was deposited by atomic layer deposition (ALD). x / Lanthanide-doped high-k dielectric layer (HfO2) ), phosphorus-doped polycrystalline silicon layer deposited by LPCVD (3), and annealed: tunneling layer thickness 2 nm, polycrystalline silicon layer thickness 150 nm, doping concentration 2×10 20 atoms / cm 3 The sheet resistance is 60 ohms / sqr, and the phosphorus silicate glass (PSG) thickness is 50 nm. The specific method and structure are the same as step (2) in Example 1.
[0110] (3) Backside grooved p-region: The phosphorosilicate glass is patterned using an ultraviolet femtosecond laser, and the backside mask layer, the polysilicon layer in the laser area, and the frontside coating layer are removed by wet etching. The laser area width is 650 μm, and the laser power is 55W. The specific method and structure are the same as step (3) in Example 1.
[0111] (4) Depositional heterostructure high-k double-barrier tunneling layer and hole transport layer:
[0112] The tunneling layer (4) (a-Si:H and lanthanide-doped high-k dielectric layer (HfO2)) was first deposited by PECVD, followed by the deposition of boron-doped nc-SiO2. x :H(5), finally grow SiN x As a mask layer (6).
[0113] Tunneling layer thickness 2 nm, nc-SiO x :H thickness 30 nm, SiN x Thickness 60 nm. See Figure 12 The structure includes a front-side coating (1), a silicon substrate layer (2), a heterojunction double barrier layer (3), a heterojunction double barrier layer (4), a boron-doped polycrystalline silicon layer (5), a mask layer (6), and an electron transport layer (7). a-Si:H and lanthanide-doped high-k dielectric layer (HfO2): 1 nm thick nc-SiO2 was deposited on the silicon substrate surface using PECVD. x H layer. A hydrogenated amorphous silicon layer was deposited under plasma irradiation using SiH4 as the silicon source and H2 as the dilution gas. Subsequently, a 1 nm lanthanide-doped HfO2 high-k dielectric layer was deposited under plasma-assisted conditions using tetradimethylaminohafnium as the hafnium source, triisopropylcyclopentadienyllanthanum as the lanthanum doping source, and a mixture of O2 and N2O as the oxygen source, forming a composite tunneling layer composed of a-Si:H / lanthanide-doped HfO2 with a total thickness of 2 nm.
[0114] nc-SiO x H: On the surface of the tunneling layer, a 30nm boron-doped nanocrystalline silicon-oxygen layer is formed by reaction deposition under the action of radio frequency plasma using the PECVD method with SiH4 as silicon source, CO2 as oxygen source, B2H6 as boron doping source and H2 as dilution gas.
[0115] SiN x In the boron-doped nc-SiO x On the surface of the H layer, a 60 nm silicon nitride layer is formed by reaction deposition under plasma action using the PECVD method with SiH4 as the silicon source, NH3 as the nitrogen source, and H2, N2 or Ar as the dilution gas.
[0116] (5) Forming isolation bands for n-region and np-region by back-side slotting: The hole transport layer above the gap and n-region to be reserved is patterned using an ultraviolet femtosecond laser. The hole transport layer, tunneling passivation layer and front-side coating layer in the back-side laser area are removed by wet etching. The laser area width is 800 μm and the laser power is 55 W. The specific method and structure are the same as step (5) in Example 1.
[0117] (6) Front surface pn junction region: A good textured surface structure is formed on the front side using alkaline texturing. Then, a tunneling layer (3) (SiO2) is deposited using atomic layer deposition (ALD). x A lanthanide-doped high-k dielectric layer (HfO2) was deposited, and a boron-doped polycrystalline silicon layer was deposited by LPCVD and annealed to form a front surface pn junction region (2). The tunneling layer thickness was 2 nm, the polycrystalline silicon layer thickness was 175 nm, and the doping concentration was 7 × 10⁻⁶. 19 atoms / cm 3 The sheet resistance is 230 ohm / sqr, and the borosilicate glass (BSG) thickness is 30 nm. The specific method and structure are the same as step (6) in Example 1.
[0118] (7) Front surface finger structure: The non-finger area on the front surface is patterned using ultraviolet femtosecond laser, and the polysilicon layer in the front laser area is removed by wet etching. The laser area width is 900 μm, and the laser power is 40 W. The specific method and structure are the same as step (7) in Example 1.
[0119] (8) Deposition of high-k stack: A layer of SiO is deposited sequentially on the front and back sides of the battery using atomic layer deposition (ALD). x The oxide layer was 2 nm thick, and the lanthanide-doped high-k material (1, 8) (HfO2) was 12 nm thick. The specific method and structure were the same as step (8) in Example 1.
[0120] (9) Anti-reflection layer: Alumina (AlO2) is deposited on the front side. x Thickness controlled at 6 nm) / Silicon nitride (SiN) x The thickness is controlled at 80 nm, and the refractive index is 2.1 (1). A transparent conductive oxide layer (ITO thickness 70 nm) is deposited on the back side (10). The specific method and structure are the same as the steps (9) in Example 1.
[0121] (10) Backside Gap Area Insulation: Etching material was screen-printed onto the reserved gap, followed by wet etching to remove the ITO layer in the gap area. The etching mask width was 100 μm. See [link to documentation]. Figure 13 (The n / p region junction shown in the figure only needs to be opened with ITO, and there is no need to leave the inside of the figure blank.) It includes a passivation layer (1), a high-k stack (2), a front surface pn junction region (3), a heterojunction double barrier layer (4), a silicon substrate (5), a heterojunction double barrier layer (6), a hole transport layer (7), an electron transport layer (8), a high-k stack (9), and a conductive layer (10).
[0122] (11) Screen printing: Non-burn-through conductive paste is used to screen print the n / p area on the back of the battery and the pn area on the front, forming n + p + and n + The electrodes are then sintered to complete the finished product.
[0123] Comparative Example 1
[0124] The same p-type Ga-doped silicon wafer as in Example 1 was used as the substrate, with a resistivity of 3-10 Ω·cm and a minority carrier lifetime of >1.5 ms.
[0125] The core steps of this patent—front surface pn junction fabrication, front surface finger patterning, and double-sided high-k stacked passivation—are omitted. Only the back tunneling / transport layer deposition, back n / p region trenching, conventional passivation anti-reflection layer deposition, and back electrode printing are completed. The final result is a conventional back electrode tunneling passivation contact cell without a front surface junction, without high-k stacked passivation, without double-sided carrier selective transport, and without a complete three-terminal structure. See [link to patent details]. Figure 14 The battery structure includes a silicon substrate (1), a heterojunction double barrier layer (2), an electron transport layer (3), a hole transport layer (4), a passivation layer (5), and an electrode (6).
[0126] (1) Double-sided polishing: Using a p-type single crystal silicon wafer as the silicon substrate, the wafer is first pre-cleaned with alkali / hydrogen peroxide in a tank-type machine, and then polished to form a flat surface structure; the grain size is 12.5 µm and the reflectivity is 38%;
[0127] (2) Deposition of high-k double-barrier tunneling layer and hole transport layer in heterostructure: The tunneling layer (SiO2) is deposited by atomic layer deposition (ALD). x A heterojunction double barrier layer was synthesized from a lanthanide-doped high-k dielectric layer (HfO2). A boron-doped polycrystalline silicon layer was deposited using LPCVD and then annealed. The tunneling layer thickness was 2 nm, the polycrystalline silicon layer thickness was 300 nm, and the doping concentration was 6.5 × 10⁻⁶. 19 atoms / cm 3 Sheet resistance 130 ohm / sqr, borosilicate glass (BSG) thickness 35 nm.
[0128] (3) Backside groove n-region: The borosilicate glass is patterned using an ultraviolet picosecond laser, and the backside mask layer, the polysilicon layer in the laser area, and the frontside coating layer are removed by wet etching. The laser area width is 550 μm and the laser power is 55W.
[0129] (4) Deposition of high-k double-barrier tunneling layer and electron transport layer in heterostructure: The tunneling layer (SiO2) is deposited by atomic layer deposition (ALD). xA lanthanide-doped high-k dielectric layer (HfO2) was deposited, followed by phosphorus-doped polycrystalline silicon deposition using LPCVD and annealing. The tunneling layer thickness was 2 nm, the electron transport layer thickness was 200 nm, and the doping concentration was 4.5 × 10⁻⁶. 20 atoms / cm 3 Sheet resistance 115 ohm / sqr, phosphorus silicate (PSG) glass thickness 50 nm.
[0130] (5) Backside grooving to form p-region and np-region isolation bands: A picosecond ultraviolet laser is used to pattern the electron transport layer above the gap and hole transport layer areas to be reserved. Wet etching is then used to remove the electron transport layer, tunneling passivation layer, and front-side coating in the backside laser area, forming a textured surface structure on the front side. The laser area width is 450 μm, and the laser power is 53 W. The reflectivity of the textured surface on the front side is 9%.
[0131] (6) Anti-reflection and passivation layer: Deposition of double-sided alumina (AlO2) x Thickness controlled at 6 nm) / Silicon nitride (SiN) x The thickness is controlled at 80 nm, and the refractive index is 2.1.
[0132] (7) Screen printing: Non-burn-through conductive paste is used to screen print the n / p areas on the back of the battery to form n + p + Finally, the finished product is manufactured through a sintering process.
[0133] Comparative Example 2
[0134] The same n-type silicon wafer as in Example 2 was used as the substrate. The n-type silicon wafer with high minority carrier lifetime was used as the substrate, with a resistivity of 3-10 Ω·cm and a minority carrier lifetime of >1.5 ms.
[0135] The core steps of this patent—front surface pn junction fabrication, front surface finger patterning, and double-sided high-k stacked passivation—are omitted. Only the back tunneling / transport layer deposition, back n / p region isolation from the gap, conventional passivation anti-reflection / transparent conductive layer deposition, and back electrode printing are completed. This results in a conventional back electrode hybrid passivated contact cell without a front surface junction, without high-k stacked passivation, without double-sided carrier selective transport, and without a complete three-terminal structure. See [link to patent details]. Figure 15 The battery structure includes a silicon substrate (1), a heterojunction double barrier layer (2), a hole transport layer (3), an electron transport layer (4), a conductive layer (5), a purification layer (6), and an electrode (7).
[0136] (1) Double-sided polishing: Using an n-type single crystal silicon wafer as a silicon substrate, the wafer is first pre-cleaned with alkali / hydrogen peroxide in a tank-type machine, and then polished to form a flat surface structure; the grain size is 17.5 µm and the reflectivity is over 40%.
[0137] (2) Deposition of high-k double-barrier tunneling layer and electron transport layer in heterostructure: The tunneling layer (SiO2) is deposited by atomic layer deposition (ALD). x A lanthanide-doped high-k dielectric layer (HfO2) was deposited, followed by phosphorus-doped polycrystalline silicon deposition using LPCVD and annealing. The tunneling layer was 2 nm thick, the polycrystalline silicon layer was 150 nm thick, and the doping concentration was 2 × 10⁻⁶. 20 atoms / cm 3 Sheet resistance 60 ohm / sqr, phosphorus silicate glass (PSG) thickness 50nm.
[0138] (3) Backside slotted p-region: The phosphorosilicate glass was patterned using an ultraviolet femtosecond laser, and the backside mask layer, the polysilicon layer in the laser area, and the frontside coating were removed by wet etching. The laser area width was 600 μm and the laser power was 55W.
[0139] (4) Deposition of high-k double-barrier tunneling layer and hole transport layer in heterostructure: The tunneling layer (a-Si:H) and lanthanide-doped high-k dielectric layer (HfO2) are deposited first by PECVD, followed by deposition of boron-doped nc-SiO x Finally, SiNx is grown as a mask layer. The tunneling layer is 2 nm thick and consists of nc-SiO2. x :H thickness 30 nm, SiN x Thickness 60 nm.
[0140] (5) Backside slotting to form n-region and np-region isolation bands: The hole transport layer above the gap and n-region to be reserved is patterned using ultraviolet femtosecond laser. The hole transport layer, tunneling passivation layer and front-side coating layer in the backside laser area are removed by wet etching. The laser area width is 800 μm and the laser power is 55 W.
[0141] (6) Anti-reflection layer and conductive layer: Alumina (AlO2) is deposited on the front side. x Thickness controlled at 6 nm) / Silicon nitride (SiN) x The thickness is controlled at 80 nm, and the refractive index is 2.1. A transparent conductive oxide layer (ITO thickness 70 nm) is deposited on the back side.
[0142] (7) Backside Gap Area Insulation: The etchant is printed onto the gap area using screen printing and then etched. The etchant is then removed by wet cleaning. The etchant mask width is 70-120 μm.
[0143] (8) Screen printing: Using a non-burn-through conductive paste, n / p areas on the back of the battery are formed respectively. + p + The electrodes are then sintered to complete the finished product.
[0144] Test Example 1
[0145] Electrical performance testing:
[0146] The crystalline silicon solar cells prepared in Examples 1-2 and Comparative Examples 1-2 were subjected to terminal output performance testing using a solar cell testing system (WAVELABS, Germany). The results are shown in Table 1.
[0147] Test conditions: IV measurements were performed at 25.0 ± 0.5 ℃. Irradiance calibration was 1000 ± 5 %W·m. -2 (AM1.5G equivalent). Four-terminal measurement, forward / reverse scan (20 mV·ms) -1 The critical operating point dwell time is 200 ms; each piece is repeated 3 times and the average value is taken; the area is 182×182 mm. 2 calculate.
[0148] Table 1. Test data on the terminal output performance of crystalline silicon solar cells
[0149]
[0150] Test Example 2
[0151] External quantum efficiency test:
[0152] The external quantum efficiency of the crystalline silicon solar cells prepared in Example 1 and Comparative Example 1 was tested, and the results are as follows: Figure 16 As shown in Table 2, the output performance test data of the bottom and top batteries of the 3T battery are as follows: the current density of the bottom battery is 19.25 mA / cm², the current density of the top battery is 20.61 mA / cm², the calculated current density of the battery in Example 1 is 39.82 mA / cm², and the current density of the battery in Comparative Example 1 is 38.32 mA / cm².
[0153] The calculation process is as follows: Total short-circuit current density J of the parallel system sc,total = J sc,Bottom + J sc,Top = 19.21 + 20.61 = 39.82 mA / cm 2 The open-circuit voltage is limited by the low-voltage sub-cell. oc,total =0.659 V; Equivalent series resistance R= R s,eq ≈1.41 Ω,Rsh,eq≈112.92 Ω,V m ≈ 0.5293 V, I m ≈ 0.033171 A; FF = = 67.22%, E ff = = =
[0154] Table 2. Test data on the output performance of the bottom and top cells of crystalline silicon solar cells.
[0155]
[0156] This invention proposes a structural design suitable for crystalline silicon back-contact solar cells. Based on the BC cell architecture, a double pn junction structure and a high-k stack are introduced to realize a three-terminal cell with radiation resistance, high carrier transport, and low parasitic absorption, thereby improving photoelectric conversion efficiency.
[0157] This invention designs the battery tunneling layer as a heterojunction high-k double-barrier structure, which, compared to traditional SiO2 or amorphous silicon passivation layers, can suppress pinhole defects under high temperatures and long-term service, and reduce interfacial carrier recombination. By stabilizing interfacial chemical bonds through a lanthanide-doped high-k interfacial layer, it significantly enhances passivation stability and carrier selective transport capability under space irradiation, solves the attenuation problem of traditional passivation structures, and improves passivation effect and device reliability. At the same time, it constructs a double-junction three-terminal battery structure with a front surface pn junction and a back passivation contact working together, optimizes the carrier transport path, breaks through the carrier collection bottleneck of traditional single-junction batteries, reduces carrier recombination loss, and improves photoelectric conversion efficiency.
[0158] In summary, this patent effectively improves the selective transport and collection efficiency of charge carriers in crystalline silicon solar cells through innovative structural design and interface passivation process, breaking through the performance bottleneck of traditional crystalline silicon solar cells and demonstrating significant technical advantages and application potential.
[0159] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the present invention.
Claims
1. A radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell, characterized in that: The battery structure consists of, from top to bottom, an electrode (1), a passivation antireflection layer / conductive layer (2), a high-k stack (3), a front surface pn junction layer (4), a heterojunction high-k double barrier layer (5), a silicon substrate (6), a heterojunction high-k double barrier layer (7), an electron transport layer (8), a hole transport layer (9), a high-k stack (10), a passivation antireflection layer / conductive layer (11), and an electrode (12).
2. The radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell as described in claim 1, characterized in that: The electrode one (1) includes n + Electrode, the second electrode (12) includes p + Electrode.
3. The radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell as described in claim 1 or 2, characterized in that: The silicon substrate (6) includes a p-type Ga-doped silicon wafer with a resistivity of 3-10 Ω·cm and a minority carrier lifetime of >1.5 ms.
4. The radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell as described in claim 1, characterized in that: The passivation antireflection layer comprises a double-sided composite layer of aluminum oxide and silicon nitride, wherein the thickness ratio of aluminum oxide to silicon nitride is 6 nm:80 nm.
5. The radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell as described in claim 1, characterized in that: The high-k stack includes, A heterojunction double-barrier layer synthesized from a tunneling layer and a lanthanide-doped high-k dielectric layer; wherein... The tunneling layers include SiOx, SiOxNy, and ia-Si:H; the lanthanide-doped high-k dielectric layers include HfO2 and TiO2. The tunneling layer has a thickness of 1-3 nm, and the lanthanide-doped high-k dielectric layer has a thickness of 3-20 nm.
6. The radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell as described in claim 1, characterized in that: The heterojunction high-k double barrier layer includes, A heterojunction double-barrier layer synthesized from a tunneling layer and a lanthanide-doped high-k dielectric layer; wherein... The tunneling layers include SiOx, SiOxNy, and ia-Si:H; the lanthanide-doped high-k dielectric layers include HfO2 and TiO2. The tunneling layer is 1 nm thick, the lanthanide-doped high-k dielectric layer is 1-2.5 nm thick, and the total thickness is approximately 1-2.5 nm.
7. The radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell as described in claim 1, characterized in that: The front surface pn junction layer is a phosphorus-doped polycrystalline silicon layer with a thickness of 115 nm and a phosphorus doping concentration of 7.5 × 10⁻⁶. 20 atoms / cm 3 The sheet resistance is 125 Ω / sq.
8. The radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell as described in claim 1, characterized in that: The raw materials for the electron transport layer are MoO3, V2O5, WO3, NiOx, Cu2O, PDOT:PSS, CuI, microcrystalline silicon, polycrystalline silicon, polycrystalline silicon oxide, and polycrystalline silicon carbide, and the thickness of the electron transport layer is 20-260 nm. The hole transport layer is made of TiO2, ZnOx, SnO2, Ta2O5, Nb2O5, TiN, or TiO2. x N y TaN x Microcrystalline silicon, polycrystalline silicon, polycrystalline silicon oxide, and polycrystalline silicon carbon oxide are all examples of materials that require doping with group III elements when the hole transport layer is a silicon-based material.
9. The radiation-resistant double-junction three-terminal silicon-based passivated contact structure solar cell and its preparation method according to any one of claims 1 to 8, characterized in that: include, Double-sided polishing: Using an n / p type monocrystalline silicon wafer as a silicon substrate, the wafer is first pre-cleaned with alkali / hydrogen peroxide, and then polished to form a flat surface structure. Depositing a high-k double-barrier tunneling layer and hole transport layer in a heterostructure: The tunneling layer, hole transport layer and mask layer are sequentially constructed using chemical vapor deposition, atomic layer deposition or physical vapor deposition, and marked as the back side. The thickness of the tunneling layer is 1-2.5 nm, the thickness of the hole transport layer is 20-400 nm, and the thickness of the mask layer is 20-100 nm. Backside grooving to form n-region: The n-region is created using ultraviolet picosecond / ultraviolet femtosecond / green picosecond lasers, and the backside mask layer, the tunneling layer / hole transport layer of the laser area and the frontside coating layer are removed by wet or dry etching. Depositing a high-k double-barrier tunneling layer and an electron transport layer in a heterostructure: The tunneling layer and the electron transport layer are prepared sequentially by chemical vapor deposition, atomic layer deposition or physical vapor deposition. The thickness of the tunneling layer is 1-2 nm, the thickness of the electron transport layer is 20-260 nm, and the thickness of the mask layer is 30-100 nm. Backside grooving to form p-region and np-region isolation bands: A mask layer is deposited on the backside, and the n-region above the p-region and the np-region isolation band are opened using ultraviolet picosecond / ultraviolet femtosecond / green picosecond lasers. The electron transport layer, tunneling passivation layer and front-side coating layer of the backside laser area are removed by wet or dry etching. The laser area width is 500-900μm. Front surface pn junction region: A good textured structure is formed on the front side by alkaline texturing. Then, a tunneling layer and a transport layer are formed sequentially by chemical vapor deposition, atomic layer deposition, or physical vapor deposition to form the front surface pn junction region. The thickness of the tunneling layer is 1-2 nm, the thickness of the transport layer is 20-300 nm, and the thickness of the mask layer is 40-100 nm. Front surface finger structure: A mask layer is deposited on the front side, and the reserved non-finger area is patterned using ultraviolet picosecond / ultraviolet femtosecond / green picosecond lasers. The transmission layer and tunneling passivation layer of the laser area on the back side are removed by wet or dry etching. The width of the laser area is 800-1500μm. Deposition of high-k stack: SiOx layer is deposited sequentially on both sides of the battery, with an oxide layer thickness of 1-3 nm; then high-k material is deposited and lanthanide doped, with a high-k material thickness of 3-20 nm. Antireflective layer / transparent conductive layer: deposited double-sided passivated aluminum oxide with a thickness controlled at 3-20 nm, silicon nitride with a thickness controlled at 65-90 nm, and a refractive index of 1.7-2.3; Alternatively, a transparent conductive oxide layer, with a thickness controlled at 65-100nm and a sheet resistance of 20-50 ohm / sqr; Backside Gap Area Isolation and Insulation: The Gap area is patterned using ultraviolet picosecond / ultraviolet femtosecond / green picosecond lasers, and the conductive layer of the Gap area is removed by wet or dry etching. Screen printing: Non-burn-through conductive paste is used to screen print the n / p area on the back of the battery and the pn area on the front to form electrodes. The finished product is then manufactured through a sintering process.