A solar cell preparation method, a solar cell and a photovoltaic module

Abstract

The application relates to the technical field of solar cells, in particular to a solar cell preparation method, a solar cell and a photovoltaic module. The preparation method comprises the following steps: providing a substrate, forming a doped layer and a first passivation layer on a first surface of the substrate, removing part of the first passivation layer to form a window, forming a seed layer in the window, forming a cutting groove on the first surface, electroplating a first plating layer on a side of the seed layer away from the substrate, and cutting the substrate along the cutting groove to form a plurality of cell fragments. The seed layer is formed first, then the cutting groove is formed by pre-cutting, and then the first electrode is formed by electroplating. The cutting groove can pre-cut the substrate into a plurality of independent regions to block the conductive path of each region in the electroplating process, thereby realizing the isolation of the metal plating layer of each region. In the subsequent process of cutting the substrate, the risk of first electrode fracture and local resistance increase caused by cutting damage to the metal plating layer formed by electroplating can be reduced.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a method for preparing a solar cell, a solar cell, and a photovoltaic module. Background Technology

[0002] Tunnel oxide passivated contact (TOPCon) cells have become the mainstream technology in the current photovoltaic market due to their excellent passivation effect and high conversion efficiency. Traditional TOPCon cells are processed using a single large silicon wafer (such as M10, 182mm). The large size of the silicon wafer results in high heat loss of the module. Electrodes can be fabricated on the whole silicon wafer first, and then the whole silicon wafer can be cut into multiple smaller pieces to form multiple smaller solar cells. This can reduce the single string current and reduce the risk of heat loss and microcracks. However, the risk of electrode breakage is relatively high during the cutting and slicing process. Summary of the Invention

[0003] This application provides a method for preparing a solar cell, a solar cell, and a photovoltaic module that can reduce the risk of electrode breakage.

[0004] The first aspect of this application provides a method for fabricating a solar cell, the method comprising: providing a substrate; forming a doped layer on a first surface of the substrate; forming a first passivation layer on the doped layer; removing a portion of the first passivation layer to form a window, the doped layer being exposed at the window; forming a seed layer inside the window, the seed layer at least partially covering the doped layer; forming a dicing groove on the first surface, the dicing groove and the window being distributed perpendicular to the thickness direction of the substrate; electroplating a first plating layer on the side of the seed layer away from the substrate; and cutting the substrate along the dicing groove to form multiple cell wafers.

[0005] In some possible designs, the thickness of the substrate is H1, and the depth of the cutting groove in the thickness direction of the substrate is H2, where 1 / 2 ≤ H2 / H1 ≤ 2 / 3.

[0006] In some possible designs, before electroplating to form the first coating on the side of the seed layer away from the substrate, the preparation method includes: electroplating to form a barrier layer on the seed layer. Electroplating to form the first coating on the side of the seed layer away from the substrate includes: electroplating to form the first coating on the barrier layer.

[0007] In some possible designs, the preparation method also includes forming a protective layer on the first coating.

[0008] In some possible designs, after the substrate is cut along the cutting groove, the preparation method further includes: printing and curing an isolation material on the edge of the cutting groove to form an isolation layer, wherein the isolation layer blocks at least a portion of the first coating in the thickness direction of the substrate.

[0009] In some possible designs, the distance between the windows on both sides of the cutting groove in the width direction of the cutting groove is L, where L≥0.5mm.

[0010] In some possible designs, forming a seed layer within a window includes: providing silver-coated copper paste, printing the silver-coated copper paste within the window, and forming a seed layer.

[0011] In some possible designs, the silver-coated copper paste also includes diffusion inhibitors, which account for 0.5% to 1% of the total mass of the silver-coated copper paste.

[0012] In some possible designs, the fabrication method further includes: forming an emitter on a second surface of a substrate, forming a second passivation layer on the emitter, printing electrode paste on the second passivation layer and sintering it to form a second electrode, and connecting the second electrode to the emitter.

[0013] A second aspect of this application provides a solar cell fabricated by any of the methods described above. The solar cell includes a substrate having a first surface and a second surface along its thickness direction. The first surface has a doped layer, a first passivation layer, and a first electrode. The first passivation layer is located on the side of the doped layer facing away from the substrate and has a window. At least a portion of the first electrode is located within the window and connected to the doped layer. The first electrode includes at least a seed layer and a first plating layer, with the seed layer located between the first plating layer and the doped layer. The second surface has an emitter, a second passivation layer, and a second electrode. The second passivation layer is located on the side of the emitter facing away from the substrate, and the second electrode is connected to the emitter.

[0014] In some possible designs, the first electrode also includes a barrier layer located between the seed layer and the first plating layer. In the thickness direction of the substrate, the thickness of the first plating layer is h1, the thickness of the barrier layer is h2, and the width of the first plating layer is W1, where (h1+h2) / W1≥0.8.

[0015] In some possible designs, 8μm≤h1≤12μm, 0.5μm≤h2≤1μm, and 8μm≤W1≤12μm.

[0016] In some possible designs, the first electrode also includes a protective layer located on the side of the first plating layer away from the seed layer, with a thickness of h3 in the thickness direction of the substrate, where 0.5 μm ≤ h3 ≤ 1 μm.

[0017] In some possible designs, an isolation layer is provided on the surface of the first passivation layer. In the length direction of the first electrode, a portion of the isolation layer is located between the first electrode and the edge of the solar cell, and in the thickness direction of the substrate, a portion of the isolation layer is located on the side of the first electrode away from the substrate. In the length direction of the first electrode, the width of the isolation layer is W2, 1mm≤W2≤2mm.

[0018] A third aspect of this application provides a photovoltaic module, the photovoltaic module including a cover plate, an encapsulation layer and a battery string, the battery string including a plurality of electrically connected solar cells, the solar cells being configured as the solar cells described in any of the above claims.

[0019] In this application, a seed layer is first formed, then a cutting groove is pre-cut to form a cutting groove, and then the first electrode is formed by electroplating. The cutting groove can pre-cut the substrate into at least two independent regions. During the electroplating of the first electrode, the cutting groove can block the conductive path of each region, allowing each region to grow a metal coating independently. This reduces the risk of local current accumulation caused by mutual interference of current paths in each region, thereby improving the uniformity of current distribution in each battery cell, reducing power dispersion, and improving the uniformity and controllability of the thickness and coverage of the metal coating in each battery cell. In addition, by separating the seed layer of each region by the cutting groove, the metal coating in each region can be isolated. During the subsequent substrate cutting process, the risk of the first electrode breaking and local resistance increasing due to cutting and damaging the electroplated metal coating can be reduced.

[0020] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0021] Figure 1 Partial structural cross-sectional views of the solar cell provided in this application in some embodiments; Figure 2 for Figure 1 Enlarged view of part A in some embodiments; Figure 3 for Figure 1 Enlarged view of part A in some other embodiments; Figure 4 for Figure 1 Enlarged view of part A in some other embodiments; Figure 5 for Figure 1 A schematic diagram of the back surface of a solar cell in some embodiments; Figure 6 for Figure 5 A partial structural cross-sectional view along the BB direction in some embodiments; Figure 7 for Figure 1 A schematic diagram of the backlight surface of the solar cell in some other embodiments; Figure 8 for Figure 1 A schematic diagram of the backlight surface of a solar cell in some embodiments; Figure 9 for Figure 5 Partial structural cross-sectional view along the BB direction in some other embodiments; Figure 10 A schematic diagram of part of the fabrication process of the back surface of the solar cell provided in this application in some embodiments; Figure 11 A schematic diagram of the preparation process of the first electrode in some embodiments of the preparation method provided in this application; Figure 12 A schematic diagram of the cutting groove formed in the preparation method provided in this application in some embodiments; Figure 13 For along Figure 12 A schematic diagram of the process of cutting the substrate using the cutting groove; Figure 14 A schematic diagram of the cutting groove formed in the preparation method provided in this application in some other embodiments; Figure 15 For along Figure 14 A schematic diagram of the process of cutting the substrate using the cutting groove; Figure 16 for Figure 12 A partial structural cross-sectional view along the CC direction; Figure 17 for Figure 5 Partial structural cross-sectional view along the BB direction in some other embodiments; Figure 18 A schematic diagram of the fabrication process of the solar cell's light-facing surface provided in this application in some embodiments; Figure 19 The photovoltaic module provided in this application is shown in some embodiments as a structural cross-sectional view.

[0022] Figure label: 100 - Cover plate; 200 - Encapsulation layer; 300 - Battery string; 10 - Battery segmentation; 101 - Edge trimming; 1-Base; 11-First face; 111-Cutting groove; 12-Second face; 121-Pyramid structure; 2-Doped layer; 21-Tunneling layer; 22-N-type polysilicon layer; 3-First passivation layer; 31-Window; 4-First electrode; 41-Seed layer; 42-First plating layer; 43-Barrier layer; 44-Protective layer; 5-Emitter; 6-Second passivation layer; 7-Second electrode; 8-Isolation layer; 81-First isolation section; 82-Second isolation section; X - First direction; Y - Second direction; Z - Thickness direction.

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Detailed Implementation

[0024] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0025] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0026] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0027] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0028] In the accompanying drawings corresponding to the embodiments of this application, for clarity, the proportions of structures such as layers, films, and regions may not be proportions of actual structures. It should be understood that when it is mentioned that feature a (e.g., a layer, film, or region) is "located" "on" feature b, feature a may be directly located on feature b, or there may be other features c between feature a and feature b. Conversely, when it is mentioned that feature a is "directly located" "on" feature b, it means that there are no other features between feature a and feature b.

[0029] In the description of the embodiments of this application, the meaning of "electrical connection" may include: after two structures with conductive properties are physically connected, under the action of an electric field, one of the two physically connected structures with conductive properties can conduct electricity to the other. The physical connection for conducting electricity can be a direct connection or an indirect connection through other conductive media.

[0030] In the description of the embodiments of this application, the use of terms such as "same," "equal," or "consistent" regarding dimensions does not require absolute mathematical or geometric precision. Given the actual manufacturing, measurement, and material factors, those skilled in the art should understand that the aforementioned dimensional terms include deviations within permissible limits or unavoidable deviations. As long as such deviations do not affect the functionality and technical effects of the corresponding dimensions in this application, they should be considered to fall within the meaning of "same dimensions" as described in the embodiments of this application.

[0031] The first aspect of this application provides a solar cell, such as... Figure 1 As shown, the solar cell includes a substrate 1. The substrate 1 has a first surface 11 and a second surface 12 along its thickness direction Z. One of the first surface 11 and the second surface 12 is a light-facing surface, and the other is a back-lighting surface. The light-facing surface is the side of the substrate 1 that faces the sun during the use of the solar cell, and the back-lighting surface is the side of the substrate 1 that faces away from the sun during the use of the solar cell. The following examples will use the first surface 11 as the back-lighting surface and the second surface 12 as the light-facing surface.

[0032] The first surface 11 is provided with a doped layer 2, a first passivation layer 3 and a first electrode 4. The first passivation layer 3 is located on the side of the doped layer 2 away from the substrate 1. The first passivation layer 3 has a window 31. At least a portion of the first electrode 4 is located in the window 31 and is connected to the doped layer 2. Specifically, at least a portion of the first electrode 4 is located in the window 31 and is in contact with the doped layer 2, so that the first electrode 4 is electrically connected to the doped layer 2.

[0033] The doped layer 2 includes a tunneling layer 21 and an N-type polysilicon layer 22. The N-type polysilicon layer 22 is located on the side of the tunneling layer 21 away from the substrate 1, and the first electrode 4 is connected to the N-type polysilicon layer 22.

[0034] The tunneling layer 21 can be a dielectric layer such as silicon oxide or silicon oxynitride, and the N-type polycrystalline silicon layer 22 is doped with N-type elements such as phosphorus, arsenic, antimony, and bismuth.

[0035] The second surface 12 is provided with an emitter 5, a second passivation layer 6, and a second electrode 7. The second passivation layer 6 is located on the side of the emitter 5 away from the substrate 1, and the second electrode 7 is connected to the emitter 5. The emitter 5 is doped with P-type elements such as boron, gallium, and indium.

[0036] The second surface 12 has multiple pyramid structures 121, and the emitter 5 is formed at the pyramid structure 121, so that the light-facing surface of the solar cell is velvety, which can reduce the reflection of light on the light-facing surface, thereby improving the light trapping effect of the light-facing surface, so as to improve the light utilization rate and output power of the solar cell.

[0037] In this embodiment, the solar cell is a tunnel-oxide-passivated contact (TOPCon) cell, and the first electrode 4 and the second electrode 7 with opposite polarities are located on both sides of the substrate 1 in the thickness direction Z.

[0038] In the thickness direction Z of the substrate 1, the thickness of the tunneling layer 21 is 1.2 nm to 1.5 nm, for example, the thickness of the tunneling layer 21 is 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, etc.

[0039] For example, the thickness of the tunneling layer 21 is 1.2 nm to 1.3 nm, such as 1.2 nm, 1.22 nm, 1.24 nm, 1.26 nm, 1.28 nm, 1.3 nm, etc.

[0040] For example, the thickness of the tunneling layer 21 is 1.3nm to 1.5nm, such as 1.3nm, 1.32nm, 1.34nm, 1.36nm, 1.38nm, 1.4nm, 1.42nm, 1.44nm, 1.46nm, 1.48nm, 1.5nm, etc.

[0041] In the thickness direction Z of the substrate 1, the thickness of the N-type polysilicon layer 22 is 80nm to 100nm, for example, the thickness of the N-type polysilicon layer 22 is 80nm, 85nm, 90nm, 95nm, 100nm, etc.

[0042] For example, the thickness of the N-type polysilicon layer 22 is 80nm to 90nm, such as 80nm, 80.5nm, 81nm, 81.5nm, 82nm, 82.5nm, 83nm, 83.5nm, 84nm, 84.5nm, 85nm, 85.5nm, 86nm, 86.5nm, 87nm, 87.5nm, 88nm, 88.5nm, 89nm, 89.5nm, 90nm, etc.

[0043] For example, the thickness of the N-type polysilicon layer 22 is 90nm to 100nm, such as 90nm, 90.5nm, 91nm, 91.5nm, 92nm, 92.5nm, 93nm, 93.5nm, 94nm, 94.5nm, 95nm, 95.5nm, 96nm, 96.5nm, 97nm, 97.5nm, 98nm, 98.5nm, 99nm, 99.5nm, 100nm, etc.

[0044] like Figure 2As shown, the first electrode 4 includes at least a seed layer 41 and a first plating layer 42. The seed layer 41 is located between the first plating layer 42 and the doped layer 2. Specifically, the seed layer 41 is located between the first plating layer 42 and the N-type polysilicon layer 22.

[0045] In this embodiment, the first electrode 4 is composed of a seed layer 41 and a plating layer formed on the seed layer 41, so that the first electrode 4 is formed by electroplating. Compared with the screen printing method in related technologies, the electroplating process can reduce the width of the first electrode 4 and improve the dimensional accuracy of the first electrode 4. It is beneficial to reduce the amount of metal paste used in the preparation process of the first electrode 4, thereby reducing the material cost of the first electrode 4.

[0046] The seed layer 41 can be made of copper, silver, silver-clad copper, copper alloy, etc. In this embodiment, the seed layer 41 is a silver-clad copper layer, and the slurry for preparing the seed layer 41 includes at least a carrier, copper particles mixed in the carrier, and a silver layer coated on the surface of the copper particles. By using a silver-clad copper layer for the seed layer 41, the amount of metallic silver used in the seed layer 41 can be reduced while still meeting the resistivity and conductivity requirements, thereby lowering the material cost of the seed layer 41.

[0047] Seed layer 41 may also include diffusion inhibitors, which may be bismuth oxide, titanium chloride, etc. For example, if the diffusion inhibitor is bismuth oxide, in the slurry of seed layer 41, the mass of copper is not less than 80% of the total mass of the slurry, the mass of silver is 10% to 15% of the total mass of the slurry, and the mass of the diffusion inhibitor is 0.5% to 1% of the total mass of the slurry.

[0048] In this embodiment, during the high-temperature sintering process, the diffusion inhibitor can effectively reduce the diffusion of metal atoms from the first coating layer 42 to the doped layer 2 and the substrate 1, thereby reducing the contact resistance between the first electrode 4 and the doped layer 2, and also reducing the risk of leakage current caused by high-temperature metal diffusion and reducing open-circuit voltage, so as to improve the output power and performance stability of the solar cell.

[0049] The width of the seed layer 41 in the first direction X is 10μm to 15μm, for example, the width of the seed layer 41 is 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, etc.

[0050] If the width of the seed layer 41 is large, the width of the first electrode 4 will be large and the material cost will be high.

[0051] If the width of the seed layer 41 is small, the printing difficulty of the seed layer 41 and the electroplating difficulty of the first plating layer 42 will be high.

[0052] In this embodiment, the width of the seed layer 41 is 10μm-15μm, which can reduce the processing difficulty, material cost and processing cost of the seed layer 41 and the first electrode 4.

[0053] For example, the width of the seed layer 41 is 10μm-13μm, such as 10μm, 10.2μm, 10.4μm, 10.6μm, 10.8μm, 11μm, 11.2μm, 11.4μm, 11.6μm, 11.8μm, 12μm, 12.2μm, 12.4μm, 12.6μm, 12.8μm, 13μm, etc.

[0054] For example, the width of the seed layer 41 is 13μm-15μm, such as 13μm, 13.2μm, 13.4μm, 13.6μm, 13.8μm, 14μm, 14.2μm, 14.4μm, 14.6μm, 14.8μm, 15μm, etc.

[0055] The thickness of the seed layer 41 in the thickness direction Z of the substrate 1 is 2μm-3μm, for example, the thickness of the seed layer 41 is 2μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, 3μm, etc.

[0056] If the seed layer 41 is thick, the first electrode 4 will be thicker and the material cost will be higher.

[0057] If the thickness of the seed layer 41 is small, it will be more difficult to print the seed layer 41.

[0058] In this embodiment, the thickness of the seed layer 41 is 2μm-3μm, which can reduce the processing difficulty, material cost and processing cost of the seed layer 41 and the first electrode 4.

[0059] The sheet resistance of the seed layer 41 is no higher than 50 milliohms per square meter, which can reduce the contact resistance between the first electrode 4 and the doped layer 2.

[0060] The seed layer 41 can be formed in the window 31 by screen printing or sputtering. In this embodiment, the seed layer 41 is formed by screen printing. The seed layer 41 can be formed by using a printing screen for forming electrodes in related technologies, so that the seed layer 41 is compatible with the screen printing production line of the electrodes, thereby reducing the equipment cost of processing the seed layer 41.

[0061] The first plating layer 42 can be a metal such as silver or copper. In this embodiment, the first plating layer 42 is a copper layer. While satisfying the resistivity and conductivity of the seed layer 41, the amount of silver used in the first electrode 4 can be further reduced, thereby further reducing the material cost of the first electrode 4.

[0062] like Figure 3 As shown, the first electrode 4 also includes a barrier layer 43, which is located between the seed layer 41 and the first plating layer 42. During the preparation of the first electrode 4, the seed layer 41 is first formed at the window 31, and then a second plating layer is formed on the seed layer 41 by electroplating. The second plating layer is the aforementioned barrier layer 43. Then, the first plating layer 42 is formed on the second plating layer by electroplating.

[0063] In this embodiment, the second coating layer used as the barrier layer 43 can reduce the risk of metal atoms from the first coating layer 42 diffusing into the doped layer 2 and the substrate 1 at high temperatures, thereby reducing the risk of leakage current caused by high-temperature metal diffusion and reducing the open-circuit voltage, so as to improve the output power and performance stability of the solar cell.

[0064] The barrier layer 43 can be made of nickel, cobalt, tungsten, molybdenum, nickel alloy, etc. In this embodiment, the barrier layer 43 is a nickel layer. Compared with other materials, the electroplating process of nickel is more mature, which can reduce the processing difficulty and cost of the barrier layer 43. At the same time, nickel has high stability in low temperature environment, and the contact resistance between nickel and silver and copper is small, which can reduce the contact resistance between the barrier layer 43 and the seed layer 41 and the first plating layer 42. The barrier layer 43 being a nickel layer can improve the output power and performance stability of the solar cell.

[0065] like Figure 3 As shown, in the thickness direction Z of the substrate 1, the thickness of the first plating layer 42 is h1, the thickness of the barrier layer 43 is h2, and the width of the first plating layer 42 is W1, (h1+h2) / W1≥0.8. For example, the ratio of the total thickness of the first plating layer 42 and the barrier layer 43 to the width of the first plating layer 42 is 0.8, 0.9, 1, 1.1, 1.2, 1.3, etc.

[0066] In this embodiment, the ratio of the total thickness of the first coating layer 42 and the barrier layer 43 to the width of the first coating layer 42 is not less than 0.8, which can increase the series resistance of the first electrode 4, thereby increasing the output power of the solar cell.

[0067] The thickness h1 of the first coating layer 42 satisfies: 8μm≤h1≤12μm. For example, the thickness of the first coating layer 42 is 8μm, 9μm, 10μm, 11μm, 12μm, etc.

[0068] If the thickness of the first plating layer 42 is small, the electroplating of the first plating layer 42 will be more difficult. If the thickness of the first plating layer 42 is large, the material cost of the first plating layer 42 will be higher. In this embodiment, the thickness of the first plating layer 42 is 8μm to 12μm, which can balance the electroplating difficulty and material cost.

[0069] For example, 8μm≤h1≤10μm, such as the thickness of the first coating 42 being 8μm, 8.2μm, 8.4μm, 8.6μm, 8.8μm, 9μm, 9.2μm, 9.4μm, 9.6μm, 9.8μm, 10μm, etc.

[0070] For example, 10μm≤h1≤12μm, such as the thickness of the first coating 42 being 10μm, 10.2μm, 10.4μm, 10.6μm, 10.8μm, 11μm, 11.2μm, 11.4μm, 11.6μm, 11.8μm, 12μm, etc.

[0071] The thickness h2 of the barrier layer 43 satisfies: 0.5μm≤h2≤1μm. For example, the thickness of the barrier layer 43 is 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, etc.

[0072] If the thickness of the barrier layer 43 is small, the electroplating of the barrier layer 43 will be more difficult. If the thickness of the barrier layer 43 is large, the material cost of the barrier layer 43 will be higher. In this embodiment, the thickness of the barrier layer 43 is 0.5μm to 1μm, which can balance the electroplating difficulty and material cost.

[0073] For example, 0.5μm≤h2≤0.7μm, such as the thickness of the barrier layer 43 being 0.5μm, 0.52μm, 0.54μm, 0.56μm, 0.58μm, 0.6μm, 0.62μm, 0.64μm, 0.66μm, 0.68μm, 0.7μm, etc.

[0074] For example, 0.7μm≤h2≤1μm, such as the thickness of the barrier layer 43 being 0.7μm, 0.72μm, 0.74μm, 0.76μm, 0.78μm, 0.8μm, 0.82μm, 0.84μm, 0.86μm, 0.88μm, 0.9μm, 0.92μm, 0.94μm, 0.96μm, 0.98μm, 1μm, etc.

[0075] The width W1 of the first coating layer 42 satisfies: 8μm≤W1≤12μm. For example, the width of the first coating layer 42 is 8μm, 9μm, 10μm, 11μm, 12μm, etc.

[0076] The first plating layer 42 and the barrier layer 43 have the same width. If the width of the first plating layer 42 is too small, the width of the first electrode 4 will be small, resulting in a higher resistivity of the first electrode 4, which affects the output power of the solar cell. If the width of the first plating layer 42 is too large, the width of the first electrode 4 will be large, leading to higher material cost of the first electrode 4. In this embodiment, the width of the first plating layer 42 is 8 μm to 12 μm, which can balance the resistivity and material cost of the first electrode 4, and is beneficial to improving the output power of the solar cell.

[0077] As Figure 4 shown, the first electrode 4 further includes a protective layer 44. The protective layer 44 is located on the side of the first plating layer 42 facing away from the seed layer 41, and the protective layer 44 can reduce the risk of oxidation of the first plating layer 42.

[0078] The material of the protective layer 44 may be silver, tin, gold, nickel, etc. In this embodiment, the material of the protective layer 44 is silver. Using a silver layer as the protective layer 44 on the first plating layer 42 can reduce the material cost of the protective layer 44 while lowering the oxidation risk of the first plating layer 42, and can also improve the welding reliability between the first electrode 4 and the solder ribbon, which is conducive to enhancing the output power of the solar cell.

[0079] As Figure 4 shown, the protective layer 44 is U-shaped or in a shape of the Chinese character "几", so that a part of the protective layer 44 covers the surface of the first plating layer 42 exposed outside the first passivation layer 3, and the other part of the protective layer 44 extends along the first direction X and covers the first passivation layer 3, which can improve the integrity of the coverage and protection of the first plating layer 44 by the protective layer 44, reduce the risks of oxidation, short circuit, aging, etc. caused by partial exposure of the first plating layer 42. Moreover, the protective layer 44 is in contact with both the first plating layer 42 and the first passivation layer 3 at the same time, which can increase the bonding stability of the protective layer 44.

[0080] In the thickness direction Z of the substrate 1, the thickness of the protective layer 44 is h3, and 0.5μm≤h3≤1μm. For example, the thickness of the protective layer 44 is 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, etc.

[0081] If the thickness of the protective layer 44 is too small, the manufacturing difficulty of the protective layer 44 will be high, and the risk of damage to the protective layer 44 during the printing process and subsequent processes such as welding and lamination will be high, resulting in higher risks of oxidation, short circuit, aging, etc. caused by the exposure of the first plating layer 42.

[0082] If the protective layer 44 is thick, the material cost of the protective layer 44 will be high, and the overall thickness of the first electrode 4 will be large, resulting in a large height difference between the first electrode 4 and the first passivation layer 3. In subsequent welding, lamination and other processes, the risk of microcracks in the solar cell is high due to stress concentration at the junction of the first electrode 4 and the first passivation layer 3.

[0083] In this embodiment, the thickness of the protective layer 44 is 0.5μm to 1μm, which can balance the difficulty of its preparation and the material cost, and can also reduce the risk of damage and microcracks to the protective layer 44 and the solar cell in various processes, thereby improving the yield of the solar cell.

[0084] For example, 0.5μm≤h3≤0.7μm, such as the thickness of the protective layer 44 being 0.5μm, 0.52μm, 0.54μm, 0.56μm, 0.58μm, 0.6μm, 0.62μm, 0.64μm, 0.66μm, 0.68μm, 0.7μm, etc.

[0085] For example, 0.7μm≤h3≤1μm, such as the thickness of the protective layer 44 being 0.7μm, 0.72μm, 0.74μm, 0.76μm, 0.78μm, 0.8μm, 0.82μm, 0.84μm, 0.86μm, 0.88μm, 0.9μm, 0.92μm, 0.94μm, 0.96μm, 0.98μm, 1μm, etc.

[0086] like Figure 5 and Figure 6 As shown, an isolation layer 8 is provided on the surface of the first passivation layer 3. In the first direction X and / or in the second direction Y, a portion of the isolation layer 8 is located between the first electrode 4 and the edge of the solar cell. The second direction Y is parallel to the length direction of the first electrode 4 and in the thickness direction Z of the substrate 1. A portion of the isolation layer 8 is located on the side of the first electrode 4 away from the substrate 1.

[0087] Figure 5 The example shows that the length direction of the insulating layer 8 is parallel to or approximately parallel to the first direction X, and in the second direction Y, a portion of the insulating layer 8 is located between the first electrode 4 and the edge of the solar cell, and the insulating layer 8 covers the end of the first electrode 4 in the length direction.

[0088] Figure 7 The example shows that the length direction of the insulating layer 8 is parallel to the second direction Y, and in the first direction X, a portion of the insulating layer 8 is located between the first electrode 4 and the edge of the solar cell, and the insulating layer 8 covers the end of the first electrode 4 in the width direction.

[0089] Figure 8The example shows that the insulating layer 8 includes a first insulating portion 81 and a second insulating portion 82. The length direction of the first insulating portion 81 is parallel to the first direction X. In the second direction Y, a portion of the first insulating portion 81 is located between the first electrode 4 and the edge of the solar cell, and the insulating layer 8 covers the end of the first electrode 4 in the length direction. Meanwhile, the length direction of the second insulating portion 82 is parallel to the second direction Y. In the first direction X, a portion of the second insulating portion 82 is located between the first electrode 4 and the edge of the solar cell, and the second insulating portion 82 covers the end of the first electrode 4 in the width direction.

[0090] In this embodiment, an insulating isolation layer 8 is covered at the edge of the solar cell, and the isolation layer covers the end of the first electrode 4 near the edge. The isolation layer 8 can improve the isolation between the first electrode 4 and external moisture, thereby reducing the risk of edge leakage and electrochemical corrosion of the first electrode 4 caused by external moisture seeping in through the edge. It can also reduce the risk of metal atoms in the first electrode 4 diffusing to the edge and substrate 1 through moisture, thereby improving the resistance of the first electrode 4 and the solar cell to damp heat aging, and reducing the risk of corrosion and detachment of the first electrode 4 and increased resistance.

[0091] by Figure 5 Taking the isolation layer 8 shown as an example, in the second direction Y, the width of the isolation layer 8 is W2, 1mm≤W2≤2mm. For example, the width of the isolation layer 8 is 1mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm, 1.9mm, 2mm, etc.

[0092] If the width of the insulating layer 8 is small, the coverage area of ​​the insulating layer 8 over the edges and the first electrode 4 will be small, resulting in poor isolation between the insulating layer 8 and external moisture, and there is even a risk of the end of the first electrode 4 being exposed. If the width of the insulating layer 8 is large, the material cost of the insulating layer 8 will be high. In this embodiment, the width of the insulating layer 8 is 1mm to 2mm, which can balance the material cost and the moisture isolation effect of the insulating layer 8.

[0093] For example, 1mm≤W2≤1.5mm, such as the width of the isolation layer 8 being 1mm, 1.02mm, 1.04mm, 1.06mm, 1.08mm, 1.1mm, 1.12mm, 1.14mm, 1.16mm, 1.18mm, 1.2mm, 1.22mm, 1.24mm, 1.26mm, 1.28mm, 1.3mm, 1.32mm, 1.34mm, 1.36mm, 1.38mm, 1.4mm, 1.42mm, 1.44mm, 1.46mm, 1.48mm, 1.5mm, etc.

[0094] For example, 1.5mm≤W2≤2mm, such as the width of the isolation layer 8 being 1.5mm, 1.52mm, 1.54mm, 1.56mm, 1.58mm, 1.6mm, 1.62mm, 1.64mm, 1.66mm, 1.68mm, 1.7mm, 1.72mm, 1.74mm, 1.76mm, 1.78mm, 1.8mm, 1.82mm, 1.84mm, 1.86mm, 1.88mm, 1.9mm, 1.92mm, 1.94mm, 1.96mm, 1.98mm, 2mm, etc.

[0095] Figures 5 to 8 An example is shown where the insulating layer 8 covers the back surface of the solar cell. In addition, such as... Figure 9 As shown, a portion of the insulating layer 8 can extend along the thickness direction Z of the substrate 1 and cover the side of the solar cell, so that the insulating layer 8 can wrap the edge of the solar cell, which can further reduce the risk of edge leakage, metal atom migration of the first electrode 4 and water vapor erosion, thereby improving the long-term reliability of the solar cell.

[0096] The solar cell based on any of the above embodiments can be a whole cell, or it can be divided into half, one-third, or one-quarter cells.

[0097] A whole solar cell refers to a large whole silicon wafer that is directly used as a substrate 1 after the silicon rod is cut into silicon wafers. The whole silicon wafer has a doped layer 2, a first passivation layer 3, a first electrode 4, an emitter 5, a second passivation layer 6 and a second electrode 7 as described in the above embodiments.

[0098] Taking a quarter-wafer as an example, battery slicing refers to cutting a silicon rod into silicon wafers, and then dividing the larger whole silicon wafer into four smaller silicon wafers. Each smaller silicon wafer has the doped layer 2, the first passivation layer 3, the first electrode 4, the emitter 5, the second passivation layer 6, and the second electrode 7 as described in the above embodiment.

[0099] Smaller battery cells can reduce single-string current and decrease the risk of heat loss and microcracks.

[0100] A second aspect of this application provides a method for fabricating a solar cell, which is used to fabricate the solar cell in any of the above embodiments. The fabrication method includes: like Figure 10 As shown, a substrate 1 is provided, and the thickness of the substrate 1 is H1; A doped layer 2 is formed on the first surface 11 of the substrate 1. Specifically, a tunneling layer 21 and an N-type polysilicon layer 22 as described in the above embodiment are formed on the first surface 11. A first passivation layer 3 is formed on the doped layer 2, specifically, the first passivation layer 3 is formed on the N-type polysilicon layer 22; Part of the first passivation layer 3 is removed to form a window 31, and the doped layer 2 is exposed at the window 31. Specifically, the N-type polysilicon layer 22 is exposed at the window 31. like Figure 11 As shown, a seed layer 41 is formed within window 31, and at least a portion of the seed layer 41 covers the doped layer 2. Specifically, at least a portion of the seed layer 41 covers the surface of the N-type polysilicon layer 22. A first plating layer 42 is formed by electroplating on the side of the seed layer 41 away from the substrate 1.

[0101] The window 31 can be formed by etching, laser grooving, etc. In this embodiment, the window 31 is formed on the first passivation layer 3 by laser grooving, which can improve the dimensional accuracy of the window 31, and thus improve the dimensional accuracy of the first electrode 4 formed at the window 31.

[0102] During the process of laser grooving to form window 31, at least one of the following conditions must be met: a 355nm ultraviolet laser is used, with a power of 5 to 8 watts and a frequency of 100kHz.

[0103] In addition, the width of window 31 is 8μm to 12μm, for example, the width of window 31 is 8μm, 9μm, 10μm, 11μm, 12μm, etc.

[0104] For example, the width of window 31 is 8μm to 10μm, such as 8μm, 8.2μm, 8.4μm, 8.6μm, 8.8μm, 9μm, 9.2μm, 9.4μm, 9.6μm, 9.8μm, 10μm, etc.

[0105] For example, the width of window 31 is 10μm to 12μm, such as 10μm, 10.2μm, 10.4μm, 10.6μm, 10.8μm, 11μm, 11.2μm, 11.4μm, 11.6μm, 11.8μm, 12μm, etc.

[0106] In the width direction of window 31, the spacing between adjacent windows 31 matches the gap of the first electrode 4. For example, the spacing between adjacent windows 31 is 500μm to 800μm, and the spacing between adjacent windows 31 can be 500μm, 600μm, 700μm, 800μm, etc.

[0107] If the spacing of the windows 31 is small, the number of first electrodes 4 formed by electroplating is large, resulting in a higher material cost for the first electrodes 4. If the spacing of the windows 31 is large, the number of first electrodes 4 is small, resulting in lower current collection efficiency and higher losses for the first electrodes 4.

[0108] In this embodiment, the spacing between adjacent windows 31 is 500μm to 800μm, which can balance the material cost, current collection efficiency and heat loss of the first electrode 4.

[0109] For example, the spacing between adjacent windows 31 is 500μm to 650μm. For instance, the spacing between adjacent windows 31 can be 500μm, 510μm, 520μm, 530μm, 540μm, 550μm, 560μm, 570μm, 580μm, 590μm, 600μm, 610μm, 620μm, 630μm, 640μm, 650μm, etc.

[0110] For example, the spacing between adjacent windows 31 is 650μm to 800μm. For instance, the spacing between adjacent windows 31 can be 650μm, 660μm, 670μm, 680μm, 690μm, 700μm, 710μm, 720μm, 730μm, 740μm, 750μm, 760μm, 770μm, 780μm, 790μm, 800μm, etc.

[0111] The seed layer 41 can be formed by methods such as screen printing, sputtering, or spraying. In this embodiment, forming the seed layer 41 within the window 31 includes: The silver-plated copper paste is provided. The specific material of the silver-plated copper paste can be referred to the relevant content in the above embodiments, and will not be repeated here. Silver-coated copper paste is printed inside window 31 to form seed layer 41.

[0112] In some embodiments, the first electrode 4 includes only a seed layer 41 and a first plating layer 42, which can be determined by the structure and fabrication process of the first electrode 4.

[0113] In other embodiments, such as Figure 11 As shown, the preparation method includes the following steps after the seed layer 41 is formed and before the first coating layer 42 is formed: A barrier layer 43 is formed by electroplating on the seed layer 41; At this time, electroplating to form a first plating layer 42 on the side of the seed layer 41 opposite to the substrate 1 includes: A first plating layer 42 is formed by electroplating on the barrier layer 43.

[0114] When the first electrode 4 also includes a protective layer 44, such as Figure 11 As shown, after forming the first coating 42, the preparation method further includes: A protective layer 44 is formed on the first plating layer 42, and a portion of the protective layer 44 covers the first passivation layer 3.

[0115] The protective layer 44 can be formed by screen printing, electroplating, spraying, etc. For example, forming the protective layer 44 on the first plating layer 42 includes: A protective layer 44 is printed on the first coating layer 42.

[0116] In this embodiment, the protective layer 44 is formed by screen printing, which simplifies the preparation process of the protective layer 44 and reduces the preparation cost.

[0117] Based on the preparation method in any of the above embodiments, when the solar cell is divided into half, one-third, or one-quarter cells, it is necessary to divide the large whole silicon wafer into at least two smaller silicon wafers. However, the risk of the first electrode 4 breaking is relatively high during the silicon wafer cutting process.

[0118] Therefore, in the preparation method provided in this application embodiment, after forming the seed layer 41 and before forming the first coating layer 42, the preparation method further includes: like Figure 12 As shown, a cutting groove 111 is formed on the first surface 11, and the distribution direction of the cutting groove 111 and the window 31 is perpendicular to or approximately perpendicular to the thickness direction Z of the substrate 1. After the first coating 42 is formed, when a protective layer 44 covers the first coating 42, the preparation method further includes the following steps after the formation of the protective layer 44: like Figure 13 As shown, the substrate 1 is cut along the cutting groove 111 to form multiple battery segments 10. The substrate 1 can be cut by wire cutting or laser cutting.

[0119] In this embodiment, a seed layer 41 is first formed, then a cutting groove 111 is pre-cut, and then the first electrode 4 is formed by electroplating. The cutting groove 111 can pre-cut the substrate 1 into at least two independent regions. During the electroplating of the first electrode 4, the cutting groove 111 can block the conductive path of each region, allowing each region to grow a metal coating independently. This reduces the risk of local current accumulation and high heat loss caused by mutual interference of current paths in each region. This can improve the uniformity of current distribution in each battery segment 10, reduce power dispersion, and improve the uniformity and controllability of the thickness and coverage of the metal coating in each battery segment 10. In addition, by separating the seed layer 41 of each region by the cutting groove 111, the metal coating of each region can be isolated. During the subsequent cutting of the substrate 1, the risk of the first electrode 4 breaking and local resistance increasing due to cutting and damaging the electroplated metal coating can be reduced.

[0120] like Figure 12As shown, in the width direction of the cutting groove 111, the distance between the windows 31 on both sides of the cutting groove 111 is L, where L ≥ 0.5 mm. For example, the distance between the windows 31 on both sides of the cutting groove 111 in the width direction is 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, etc.

[0121] In this embodiment, the spacing between the windows 31 on both sides of the width direction of the cutting groove 111 is not less than 0.5mm, which can further reduce the risk of mutual interference of current paths in each region.

[0122] The cutting groove 111 can extend along the first direction X and / or the second direction Y.

[0123] Figure 12 and Figure 13 An example is given where a cutting groove 111 extends along a first direction X and another cutting groove 111 extends along a second direction Y, forming a cross shape to divide the substrate 1 into four battery segments 10.

[0124] Figure 14 and Figure 15 An example is provided showing multiple cutting grooves 111 extending along the second direction Y, which divide the substrate 1 into four battery segments arranged along the first direction X.

[0125] like Figure 16 As shown, in the thickness direction Z of the substrate 1, the depth of the cutting groove 111 is H2, 1 / 2≤H2 / H1≤2 / 3. For example, the depth of the cutting groove 111 is 18 / 36, 19 / 36, 20 / 36, 21 / 36, 22 / 36, 23 / 36, 24 / 36, etc. of the depth of the substrate 1.

[0126] If the cutting groove 111 is deep, the remaining thickness of the substrate 1 at the cutting groove 111 will be small, and the risk of substrate 1 breaking during subsequent processing will be high. If the cutting groove 111 is shallow, there is a risk that conductive metal plating layers will form in different areas during the electroplating process, affecting the uniformity of current distribution.

[0127] In this embodiment, the depth of the cutting groove 111 is 1 / 2 to 2 / 3 of the thickness of the substrate 1, which can preserve the connection of the substrate 1 in each region, reduce the risk of cracking in subsequent processes, thereby improving the yield of solar cells, and reducing the risk of forming conductive metal coatings in each region during the plating process. This facilitates the improvement of current distribution uniformity, the reduction of power dispersion, and the uniformity and controllability of the thickness and coverage of the metal coating.

[0128] For example, 1 / 2 ≤ H2 / H1 ≤ 7 / 12, such as the depth of the cutting groove 111 being 36 / 72, 37 / 72, 38 / 72, 39 / 72, 40 / 72, 41 / 72, 42 / 72, etc., of the depth of the base 1.

[0129] For example, 7 / 12≤H2 / H1≤2 / 3, for instance, the depth of the cutting groove 111 is 42 / 72, 43 / 72, 44 / 72, 45 / 72, 46 / 72, 47 / 72, 48 / 72, etc., of the depth of the base 1.

[0130] In some embodiments, after the substrate 1 is cut along the cutting groove 111 to form the battery segment 10, as follows: Figure 6 and Figure 9 As shown, the cutting edge is aligned with the edge of the cutting groove 111, so that the side of the battery slice 10 in the second direction Y has a high flatness.

[0131] In other embodiments, after the substrate 1 is diced along the cutting groove 111 to form the battery segments 10, as... Figure 17 As shown, the cutting edge 101 is misaligned with the edge of the cutting groove 111. In this embodiment, as long as the cutting position is within the cutting groove 111, the cutting difficulty and accuracy can be reduced.

[0132] After the battery segments 10 are formed on the slitting substrate 1, as follows Figure 13 , Figure 15 and Figure 17 As shown, the preparation method also includes: An insulating material is printed and cured at the edge of the cutting groove 111 to form an insulating layer 8. In the thickness direction Z of the substrate 1, the insulating layer 8 blocks at least a portion of the first electrode 4. Specifically, the insulating layer 8 blocks at least a portion of the first plating layer 42. The specific structure of the insulating layer 8 and the positional relationship between the insulating layer 8 and the first electrode 4 can be referred to the relevant content in the above embodiments, and will not be repeated here.

[0133] Based on the solar cell fabrication method in any of the above embodiments, such as Figure 18 As shown, the preparation method also includes: An emitter 5 is formed on the second surface 12 of the substrate 1; A second passivation layer 6 is formed on the emitter 5; Electrode paste is printed on the second passivation layer 6 and sintered to form the second electrode 7, which is connected to the emitter 5.

[0134] The formation of the second passivation layer 6 and the formation of the first passivation layer 3 can be performed simultaneously or separately.

[0135] In summary, the exemplary method for fabricating a solar cell provided in this application is as follows: First, a substrate 1 is provided. The second surface 12 of the substrate 1 is texturized and cleaned to form multiple pyramid structures 121. Low-pressure chemical vapor deposition (LPCVD) is used to deposit 1.2 nm to 1.5 nm silicon oxide on the first surface 11 of the substrate 1 to form a tunneling layer 21. An intrinsic polycrystalline silicon layer is deposited on the tunneling layer 21 using LPCVD and phosphorus is doped to form an 80 nm to 100 nm N-type polycrystalline silicon layer 22, finally obtaining the doped layer 2. Then, plasma-enhanced chemical vapor deposition (PECVD) is used to deposit silicon nitride on the N-type polycrystalline silicon layer 22 and the second surface 12 to form a first passivation layer 3 and a second passivation layer 6 to reduce the surface recombination rate of the solar cell.

[0136] Then, laser grooving is performed on the first passivation layer 3 to form a window 31 with a width of 8μm to 12μm, using a 355nm ultraviolet laser with a power of 5W to 8W and a frequency of 100kHz. Next, silver-coated copper paste is used, and a seed layer 41 is printed within the window 31 by screen printing, followed by drying and sintering. The screen printing linewidth is 12μm, the squeegee pressure is 40N / cm² to 50N / cm², the printing speed is 600mm / s, and after printing, the material is dried at 150℃ to 180℃ for 10 minutes, followed by sintering at 530℃ to 535℃ for 30 minutes.

[0137] Next, the substrate 1 is cut in half along the preset centerline to form a cutting groove 111 with a depth of 1 / 2 to 2 / 3 of the thickness of the substrate 1.

[0138] Subsequently, an alkaline electroplating solution with a copper atom concentration of 50 g / L to 60 g / L and a pH value of 8.5 to 9.5 is used. Nickel is plated at the cutting groove 111 to form a barrier layer 43, followed by copper plating to form the first plating layer 42. During the nickel plating process, the current density is 4 ASD to 6 ASD and the time is 5 min. During the copper plating process, the current density is 8 ASD to 10 ASD and the time is 15 min to 20 min. A pulsed current with a duty cycle of 50% is used to reduce pinholes and burrs, ensuring that the density of the first plating layer 42 is not less than 98% and the surface flatness does not exceed 0.8 μm. A protective layer 44 with a thickness of 0.5 μm to 1 μm is then formed on the first plating layer 42 by screen printing and dried at 200°C for 10 min.

[0139] After that, the substrate 1 is completely divided into four battery segments 10 along the cutting groove 111, and then insulating resin is printed at the edge of the cutting groove 111 on the battery segment 10 and cured at 120°C for 20 minutes to form the isolation layer 8.

[0140] Finally, electrode paste is printed and sintered on the second passivation layer 6 of the second surface 12 to form the second electrode 7 connected to the emitter 5. Then, the electrical performance, such as open-circuit voltage, short-circuit current, conversion efficiency, series resistance, and appearance of each battery segment 10 are tested.

[0141] A third aspect of this application also provides a photovoltaic module, such as... Figure 19 As shown, the photovoltaic module includes a cover plate 100, an encapsulation layer 200, and a cell string 300. The cell string 300 includes a plurality of electrically connected solar cells, which are configured as solar cells in any of the above embodiments.

[0142] The cover plate 100 can be made of one of the following rigid materials: tempered glass, polyethylene terephthalate (PET), polycarbonate (PC), etc., or one of the following flexible materials: polyvinyl fluoride (PVF), ethylene-tetrafluoroethylene copolymer (Ethylene-Tetra-Fluoro-EthyleneETFE), polyvinylidene fluoride (PVDF).

[0143] The encapsulation layer 200 is an adhesive film. The material of the adhesive film can be one of the following: EVA (Ethylene-Vinyl Acetate Copolymer), POE (Polyolefin Elastomer), PVB (Polyvinyl Butyral). The encapsulation layer 200 can also be an EPE adhesive film (EVA-POE-EVA co-extrusion structure) or an EP adhesive film (EVA-EP co-extrusion structure).

[0144] The above description is merely a preferred embodiment of this application and is not intended to limit the application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. Alternatively, the scope of this application is defined by the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that, The preparation method includes: Provide a base; A doped layer is formed on the first surface of the substrate; A first passivation layer is formed on the doped layer; A portion of the first passivation layer is removed to form a window, where the doped layer is exposed at the window. A seed layer is formed within the window, and at least a portion of the seed layer covers the doped layer; A cutting groove is formed on the first surface, and the distribution direction of the cutting groove and the window is perpendicular to the thickness direction of the substrate; A first plating layer is formed by electroplating on the side of the seed layer opposite to the substrate; The substrate is cut along the cutting groove to form multiple battery segments.

2. The method for preparing a solar cell according to claim 1, characterized in that, The thickness of the substrate is H1, and the depth of the cutting groove in the thickness direction of the substrate is H2, where 1 / 2 ≤ H2 / H1 ≤ 2 / 3.

3. The method for preparing a solar cell according to claim 1, characterized in that, Before electroplating the seed layer on the side opposite to the substrate to form the first coating, the preparation method includes: A barrier layer is formed by electroplating on the seed layer; Electroplating the first coating layer on the side of the seed layer opposite to the substrate includes: The first coating is formed by electroplating on the barrier layer.

4. The method for preparing a solar cell according to claim 1, characterized in that, The preparation method further includes: A protective layer is formed on the first coating.

5. The method for preparing a solar cell according to any one of claims 1 to 4, characterized in that, After the substrate is cut along the cutting groove, the preparation method further includes: An isolation material is printed and cured at the edge of the cut groove to form an isolation layer that, in the thickness direction of the substrate, blocks at least a portion of the first coating.

6. The method for preparing a solar cell according to any one of claims 1 to 4, characterized in that, In the width direction of the cutting groove, the distance between the windows located on both sides of the cutting groove is L, where L≥0.5mm.

7. The method for preparing a solar cell according to any one of claims 1 to 4, characterized in that, Forming a seed layer within the window includes: Provide silver-plated copper paste; The silver-coated copper paste is printed within the window to form the seed layer.

8. The method for preparing a solar cell according to claim 7, characterized in that, The silver-coated copper paste also includes a diffusion inhibitor, the mass of which accounts for 0.5% to 1% of the total mass of the silver-coated copper paste.

9. The method for preparing a solar cell according to any one of claims 1 to 4, characterized in that, The preparation method further includes: An emitter is formed on the second surface of the substrate; A second passivation layer is formed on the emitter; Electrode paste is printed on the second passivation layer and sintered to form a second electrode, which is connected to the emitter.

10. A solar cell, characterized in that, The solar cell is prepared by the preparation method according to any one of claims 1 to 9, and the solar cell includes a substrate having a first surface and a second surface in its own thickness direction; The first surface is provided with a doped layer, a first passivation layer and a first electrode. The first passivation layer is located on the side of the doped layer opposite to the substrate. The first passivation layer has a window, and at least a portion of the first electrode is located within the window and connected to the doped layer. The first electrode includes at least a seed layer and a first plating layer, wherein the seed layer is located between the first plating layer and the doped layer; The second surface is provided with an emitter, a second passivation layer and a second electrode. The second passivation layer is located on the side of the emitter away from the substrate, and the second electrode is connected to the emitter.

11. The solar cell according to claim 10, characterized in that, The first electrode further includes a barrier layer, which is located between the seed layer and the first plating layer; In the thickness direction of the substrate, the thickness of the first coating is h1, the thickness of the barrier layer is h2, the width of the first coating is W1, and (h1+h2) / W1≥0.

8.

12. The solar cell according to claim 11, characterized in that, 8μm≤h1≤12μm, 0.5μm≤h2≤1μm, 8μm≤W1≤12μm.

13. The solar cell according to claim 10, characterized in that, The first electrode further includes a protective layer located on the side of the first plating layer opposite to the seed layer; In the thickness direction of the substrate, the thickness of the protective layer is h3, where 0.5μm≤h3≤1μm.

14. The solar cell according to any one of claims 10 to 13, characterized in that, An isolation layer is provided on the surface of the first passivation layer. In the length direction of the first electrode, a portion of the isolation layer is located between the first electrode and the edge of the solar cell, and in the thickness direction of the substrate, a portion of the isolation layer is located on the side of the first electrode away from the substrate. Along the length of the first electrode, the width of the insulating layer is W2, where 1mm ≤ W2 ≤ 2mm.

15. A photovoltaic module, characterized in that, The photovoltaic module includes a cover plate, an encapsulation layer, and a battery string, the battery string including a plurality of electrically connected solar cells, the solar cells being configured as the solar cells of any one of claims 10 to 14.

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