A back contact solar cell and a method of manufacturing

Abstract

The application relates to the technical field of solar cells, and particularly discloses a back contact solar cell and a preparation method, wherein the back contact solar cell comprises an N-type silicon wafer, a 1nm-5nm thick tunneling oxide layer is grown on the back surface of the N-type silicon wafer, a 100-350nm thick intrinsic polycrystalline silicon film layer is deposited on the side, away from the back surface of the N-type silicon wafer, of the tunneling oxide layer, a 60-90nm thick mask is deposited on the side, away from the back surface of the N-type silicon wafer, of the intrinsic polycrystalline silicon film layer, a plurality of windows are arranged at intervals on the side, away from the back surface of the N-type silicon wafer, of the mask, the windows extend into the intrinsic polycrystalline silicon film layer, P-doped regions or N-doped regions are doped in the plurality of windows, and the P-doped regions and the N-doped regions are alternately arranged on the side, away from the tunneling oxide layer, of the intrinsic polycrystalline silicon film layer. The application can simplify the manufacturing process of the TBC cell, significantly reduce the production cost, and improve the product yield and reliability.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically to a back-contact solar cell and its fabrication method. Background Technology

[0002] TBC (Tunneling oxide passivated back contact) cells, as a next-generation high-efficiency photovoltaic technology combining the advantages of back contact (BC) structure and tunneling oxide passivated contact (TOPCon) technology, have long been constrained by bottlenecks such as complex manufacturing processes, high costs, and difficulties in yield control. Traditional processes typically involve multiple steps of polycrystalline silicon thin film deposition, masking, etching, and doping, resulting in lengthy processes and significant problems of thermal stress accumulation. Summary of the Invention

[0003] The purpose of this invention is to provide a back contact solar cell and its preparation method, which can simplify the TBC cell manufacturing process, significantly reduce production costs, and improve product yield and reliability.

[0004] The objective of this invention can be achieved through the following technical solutions: This invention provides a back-contact solar cell, comprising an N-type silicon wafer, a tunneling oxide layer with a thickness of 1nm-5nm grown on the back side of the N-type silicon wafer, an intrinsic polycrystalline silicon thin film layer with a thickness of 100-350nm deposited on the side of the tunneling oxide layer away from the back side of the N-type silicon wafer, and a mask layer with a thickness of 60-90nm deposited on the side of the intrinsic polycrystalline silicon thin film layer away from the back side of the N-type silicon wafer. The mask layer has multiple spaced windows on the side away from the back side of the N-type silicon wafer, the windows extending into the intrinsic polycrystalline silicon thin film. Within the film layer, multiple windows are doped to form P-doped or N-doped regions, and the P-doped and N-doped regions are alternately arranged on the side of the intrinsic polycrystalline silicon thin film layer away from the tunneling oxide layer. On the side of the mask away from the back of the N-type silicon wafer, a passivation layer and an anti-reflection film are deposited sequentially. On the side of the P-doped and N-doped regions away from the back of the N-type silicon wafer, metal electrodes are connected to pass through the passivation layer and the anti-reflection film in sequence. On the front side of the N-type silicon wafer, there is a texturing structure to reduce reflectivity, and a passivation layer and an anti-reflection film are deposited sequentially on the texturing structure.

[0005] Furthermore, the flocking structure is pyramidal in shape and has a thickness of 1-4 μm.

[0006] Furthermore, the surface roughness Ra of the N-type silicon wafer is ≤0.2nm; the scratch depth is ≤5nm; there are no corrosion pits or pits after etching; the number of particles larger than or equal to 0.1μm on the surface is ≤10 per wafer; the ultrapure water contact angle is ≤10°; and the single metal element content is ≤1×10¹. 0 atoms / cm².

[0007] Furthermore, the window width is 200-500 micrometers.

[0008] Furthermore, the passivation layer on the front and back sides of the N-type silicon wafer is made of aluminum oxide with a thickness of 3-8 nm; the antireflection coating is made of one or more of SiO2, SiNx and SiONx, with the antireflection coating on the front side of the N-type silicon wafer having a thickness of 70-120 nm and the antireflection coating on the back side of the N-type silicon wafer having a thickness of 80-100 nm.

[0009] Furthermore, the mask is any one, two, or three of silicon oxide, silicon nitride, and silicon oxynitride stacked together.

[0010] Another aspect of the present invention provides a method for preparing a back-contact solar cell, used to prepare any of the back-contact solar cells described above, comprising the following steps: S1. Pre-clean and polish the cut N-type silicon wafers; S2. A tunneling oxide layer with a thickness of 1nm-5nm is generated on the back side of the processed silicon wafer by thermal oxidation or chemical oxidation, and an intrinsic polycrystalline silicon thin film layer with a thickness of 100-350nm is deposited on the tunneling oxide layer. S3. A 60-90 nm thick mask is deposited on the intrinsic polycrystalline silicon thin film layer using plasma-enhanced chemical vapor deposition. S4. The preset electrode area is patterned by laser windowing using a preset laser to remove the mask and form a window. Doping is then performed in the window using ion implantation or diffusion equipment until P-doped regions as emitters and N-doped regions as back field are alternately formed on the intrinsic polycrystalline silicon thin film layer. S5. The doped silicon wafer is cleaned and texturized, and then annealed to obtain a fully crystallized silicon wafer. S6. After the passivation layer and anti-reflection film are deposited sequentially on both the front and back sides of the crystallized silicon wafer, metal electrodes are led out at preset positions in the P-doped and N-doped regions using screen printing or copper plating processes to form a back contact solar cell.

[0011] Furthermore, step S1 includes: The cut N-type silicon wafers are polished with an alkaline solution. After polishing, the size of the base on one side is 2-20 micrometers, and the reflectivity is 30-50%.

[0012] Furthermore, the steps in S4 include: P-region and N-region are preset on the mask, and doping sources corresponding to the preset P-region and N-region are obtained respectively. One region is selected for the first laser windowing, and the corresponding doping source is selected to perform the first doping on the intrinsic polycrystalline silicon thin film layer within the window. Select another region pattern for a second laser windowing, with the two windowing positions spaced 20-100 μm apart. Select the corresponding doping source to perform a second doping on the intrinsic polycrystalline silicon thin film layer within the other window, until P-doped regions serving as emitters and N-doped regions serving as back field are alternately formed on the intrinsic polycrystalline silicon thin film layer.

[0013] Furthermore, the doping source corresponding to the preset P region is a boron source. The preset P region is doped by depositing the boron source within the window of the first window opening, controlling the deposition temperature at 700℃-1000℃, and controlling the doping source flow rate and deposition time until the surface boron concentration of the doped region is 5×10⁻⁶. 19 -8×10 20 cm -3 BSG thickness 40-80nm; The N-region was pre-selected as a phosphorus source for doping. The N-region was doped by depositing the phosphorus source within a second window, at a deposition temperature of 700℃-900℃. The doping source flow rate and deposition time were controlled until the phosphorus concentration on the surface of the doped region reached 3×10⁻⁶. 19 -5×10 20 cm -3 PSG thickness 5-30nm; The laser used is a green or ultraviolet picosecond laser with an output power of 30-60W and a frequency of 100-500kHz.

[0014] Furthermore, the steps in S5 include: Use HF with a concentration of 3%-20% and a temperature of 25±5℃ to remove the oxide layer in the doped region and to coat BSG and PSG around it. After texturing, control the peak annealing temperature to 850℃ - 1000℃ and maintain the peak annealing temperature for 20-45 minutes.

[0015] The beneficial effects of this invention are: This invention designs an integrated composite structure consisting of a back-side tunneling oxide layer, an intrinsic polycrystalline silicon layer, alternating P / N doped regions, and a multilayer passivation antireflection film. Combined with a front-side pyramidal high-efficiency antireflection texturing structure, it simplifies the redundant processes of traditional multi-round deposition and etching, significantly reduces the number of high-temperature thermal processes, and fundamentally avoids problems such as thermal stress accumulation, warpage, and lattice damage in silicon wafers. At the same time, relying on the ultra-thin tunneling passivation and partitioned alternating doping structure, it effectively reduces carrier interface recombination and bulk recombination losses during the photoelectric conversion process of the battery, significantly improving the photoelectric conversion efficiency of the battery. This enables the battery to have extremely low recombination rate, excellent surface passivation performance, and long-term working stability, making it suitable for large-scale mass production. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a partial schematic diagram of a back-contact solar cell in an embodiment of the present invention; Figure 2 This is a key step in the preparation method of a back-contact solar cell in an embodiment of the present invention; In the figure: 1. N-type silicon wafer; 2. Tunneling oxide layer; 3. Intrinsic polycrystalline silicon thin film layer; 4. P-doped region; 5. N-doped region; 6. Passivation layer; 7. Anti-reflection coating layer; 8. Texturing structure; 9. Metal electrode. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] like Figure 2 As shown, a back-contact solar cell includes an N-type silicon wafer. A tunneling oxide layer with a thickness of 1 nm-5 nm is grown on the back side of the N-type silicon wafer. An intrinsic polycrystalline silicon thin film layer with a thickness of 100-350 nm is deposited on the side of the tunneling oxide layer away from the back side of the N-type silicon wafer. A mask with a thickness of 60-90 nm is deposited on the side of the intrinsic polycrystalline silicon thin film layer away from the back side of the N-type silicon wafer. The mask has multiple spaced windows on the side away from the back side of the N-type silicon wafer, and the windows extend into the intrinsic polycrystalline silicon thin film layer. Each of the multiple windows is doped to form either P-doped or N-doped regions, with the P-doped and N-doped regions alternately arranged on the side of the intrinsic polycrystalline silicon thin film away from the tunneling oxide layer. A passivation layer and an antireflection film are sequentially deposited on the side of the mask away from the back of the N-type silicon wafer. Metal electrodes, sequentially passing through the passivation layer and antireflection film, are connected to the P-doped and N-doped regions on the side away from the back of the N-type silicon wafer. A texturing structure to reduce reflectivity is present on the front side of the N-type silicon wafer, on which a passivation layer and an antireflection film are sequentially deposited. The positions of the P-doped or N-doped regions in the figure can be interchanged.

[0020] The tunneling oxide layer enables efficient carrier tunneling transport while blocking silicon wafer surface defects and reducing interfacial recombination rates. The intrinsic polycrystalline silicon thin film provides a stable substrate for subsequent ion doping and electrode contact. Utilizing the insulating and shielding properties of the mask, it provides precise constraints for subsequent zoned laser windowing and selective doping. The mask layer can precisely control the range of subsequent doping regions. The two types of doped regions are arranged alternately without cross-interference, realizing the zoned conductivity function of the battery's back electrode. The passivation layer and antireflection film layer achieve full-surface passivation and optical antireflection on the back side. The metal electrode forms an ohmic contact with the internal doped region, enabling current conduction. In some embodiments, the texturing structure is pyramidal in shape and has a thickness of 1-4 μm. This is used to significantly reduce the surface reflectivity of the silicon wafer and improve light absorption utilization. After texturing, the reflectivity of the front surface is stably controlled at 9%-13%, balancing excellent anti-reflection effects with silicon wafer structural stability.

[0021] In some embodiments, the surface roughness Ra of the N-type silicon wafer is ≤0.2nm; the scratch depth is ≤5nm; there are no corrosion pits or pinholes after etching; the number of particles larger than or equal to 0.1μm on the surface is ≤10 per wafer; the ultrapure water contact angle is ≤10°; and the single metal element content is ≤1×10¹. 0 atoms / cm². Strict requirements are placed on the original surface quality of the silicon wafer to avoid carrier recombination problems caused by impurities, ensuring battery performance and yield from the source.

[0022] In some embodiments, the window width is 200-500 micrometers. This facilitates doping, and the spacing between adjacent window opening positions is controlled at 20-100 μm, ensuring the accuracy of the partitioned structure.

[0023] In some embodiments, the product passivation layer on the front and back sides of the N-type silicon wafer is made of aluminum oxide with a thickness of 3-8 nm, which has excellent surface defect passivation capability and can effectively suppress carrier recombination on the silicon wafer surface; the antireflection film is made of one or more of SiO2, SiNx and SiONx, with the antireflection film on the front side of the N-type silicon wafer having a thickness of 70-120 nm to match the optical characteristics of front-side texturing and maximize the absorption of sunlight, and the antireflection film on the back side of the N-type silicon wafer having a thickness of 80-100 nm to balance back-side passivation protection and optical reflection optimization.

[0024] In some embodiments, the mask is any one or a combination of two or three of silicon oxide, silicon nitride, and silicon oxynitride.

[0025] like Figure 1 As shown, this embodiment of the invention also proposes a method for preparing a back-contact solar cell, used to prepare any of the back-contact solar cells described in the above embodiments, comprising the following steps: S1. Pre-clean and polish the cut N-type silicon wafers to provide a high-quality substrate for subsequent film deposition and doping processes.

[0026] S2. A tunneling oxide layer with a thickness of 1nm-5nm is generated on the back side of the processed silicon wafer by thermal oxidation or chemical oxidation. An intrinsic polycrystalline silicon thin film layer with a thickness of 100-350nm is deposited on the tunneling oxide layer. The film layer is undoped and has a uniform thickness to ensure the consistency of subsequent doping processes.

[0027] S3. A 60-90 nm thick mask is deposited on the intrinsic polycrystalline silicon thin film layer using plasma-enhanced chemical vapor deposition. S4. A patterned laser windowing process is performed on a preset electrode area using a preset laser to remove the mask and form a window. Doping is then performed in the window using ion implantation or diffusion equipment until P-doped regions as emitters and N-doped regions as back field are alternately formed on the intrinsic polycrystalline silicon thin film layer. S5. The doped silicon wafer is cleaned and texturized, and then annealed to obtain a fully crystallized silicon wafer. S6. After depositing passivation layers and antireflection films on both the front and back sides of the crystallized silicon wafer, metal electrodes are led out at preset positions in the P-doped and N-doped regions using screen printing or copper plating processes to form the back contact solar cell.

[0028] In some embodiments, step S1 includes: The cut N-type silicon wafers are polished with an alkaline solution. After polishing, the size of the substrate on one side is 2-20 micrometers, and the reflectivity is 30-50%. Double-sided polishing with an alkaline solution thoroughly removes surface damage layers, oil, particulate impurities, and the native oxide layer generated during the wafer cutting process, optimizing the surface flatness and cleanliness of the silicon wafer. This ensures that the surface requirements of the N-type silicon wafer before depositing the tunneling oxide layer in the above embodiments are met. Generally, the substrate size on one side of the polished silicon wafer can be controlled to 2-20 micrometers, and the surface reflectivity is maintained at 30-50%.

[0029] In some embodiments, step S4 includes: S41. Pre-set P-region and N-region on the mask, obtain doping sources corresponding to the pre-set P-region and N-region respectively, select one of the regions to perform the first laser windowing, and select the corresponding doping source to perform the first doping on the intrinsic polycrystalline silicon thin film layer in the window. S42. Select another region pattern for a second laser windowing, with the two windowing positions spaced 20-100μm apart. Select the corresponding doping source to perform a second doping on the intrinsic polycrystalline silicon thin film layer in the other window, until P-doped regions as emitters and N-doped regions as back field are alternately formed on the intrinsic polycrystalline silicon thin film layer.

[0030] In some embodiments, the laser is a green light or an ultraviolet picosecond laser with an output power of 30-60W and a frequency of 100-500kHz.

[0031] In some embodiments, the doping source corresponding to the preset P region is a boron source. The preset P region is doped by depositing the boron source within the window of the first window opening, controlling the deposition temperature at 700℃-1000℃, and controlling the doping source flow rate and deposition time until the surface boron concentration of the doped region is 5×10⁻⁶. 19 -8×10 20 cm 3. BSG thickness 40-80nm; The preset N-region is doped with a phosphorus source. The preset N-region is doped by depositing the phosphorus source within the second window opening. The deposition temperature is 700℃-900℃, and the doping source flow rate and deposition time are controlled until the phosphorus concentration on the surface of the doped region reaches 3×10⁻⁶. 19 -5×10 20 cm -3 PSG thickness is 5-30nm.

[0032] In some embodiments, step S5 includes: S51. Use HF with a concentration of 3%-20% and a temperature of 25±5℃ to remove the oxide layer in the doped region and the BSG and PSG winding plating. S52. After texturing, control the peak annealing temperature to 850℃ - 1000℃ and maintain the peak annealing temperature for 20-45 minutes. This allows for post-processing of the doped silicon wafer, removing process residues, optimizing the texturing structure, solidifying the doping concentration, and improving carrier mobility.

[0033] This invention's back-contact solar cell employs an ultra-thin tunneling oxide layer and an intrinsic polycrystalline silicon composite passivation structure, combined with a double-sided Al2O3 passivation layer, to achieve all-around passivation of the silicon wafer surface, significantly reducing carrier recombination losses and improving the cell's open-circuit voltage. It utilizes a back-side partitioned alternating doping and back-contact electrode design to avoid light-shielding losses at the front electrode, maximizing the utilization of solar radiation energy. Through precise laser windowing, partitioned doping, and high-temperature annealing processes, the doping concentration and regional precision can be accurately controlled, resulting in high cell performance consistency. This invention's back-contact solar cell is compatible with various mass production processes such as screen printing and copper electroplating, offering controllable processes, moderate costs, and promising prospects for large-scale mass production and market application.

[0034] Example 1: The substrate is a standard N-type silicon wafer with a surface roughness Ra=0.15nm, no obvious scratches or surface defects, and the metal impurity content meets the standards; the back tunneling oxide layer thickness is 2nm, and the intrinsic polycrystalline silicon layer thickness is 220nm; the mask layer material is silicon nitride with a thickness of 75nm; the laser window width is 350μm, and the window spacing between the P and N regions is 60μm; laser parameters: power 45W, frequency 300kHz; boron doping concentration in the P region is 2×10⁻⁶. 20 cm - ³, BSG thickness 60 nm, doping temperature 850 °C; N-region phosphorus doping concentration 1 × 10⁻⁶ 20 cm - ³, PSG thickness 18nm, doping temperature 800℃; HF cleaning concentration 10%, temperature 25℃; annealing peak temperature 920℃, holding time 30min; front pyramid texturing thickness 2.5μm, texturing surface reflectivity 11%; front and back Al2O3 passivation layer thickness 5nm, front antireflection film thickness 95nm, back antireflection film thickness 90nm; metal electrodes are fabricated using screen printing process.

[0035] Finished battery performance: Open circuit voltage Voc=728mV, short circuit current Jsc=42.6mA / cm², fill factor FF=83.2%, photoelectric conversion efficiency EFF=25.85%.

[0036] Example 2: The substrate parameters are the same as in Example 1; the thickness of the back tunneling oxide layer is 1 nm, and the thickness of the intrinsic polycrystalline silicon layer is 100 nm; the mask layer is a composite superposition layer of silicon oxide and silicon nitride with a thickness of 60 nm; the laser window width is 200 μm, and the window spacing is 20 μm; the laser power is 30 W, and the frequency is 100 kHz; the boron doping concentration in the P-region is 5 × 10⁻⁶. 19 cm - ³, BSG thickness 40 nm, doping temperature 700℃; N-region phosphorus doping concentration 3 × 10⁻⁶ 19 cm - ³, PSG thickness 5nm, doping temperature 700℃; HF cleaning concentration 3%, temperature 20℃; annealing peak temperature 850℃, holding time 20min; front pyramid texturing thickness 1μm, texturing surface reflectivity 13%; passivation layer thickness 3nm, front antireflective film thickness 70nm, back antireflective film thickness 80nm; electrodes are prepared using copper electroplating process.

[0037] Finished battery performance: Open circuit voltage Voc=722mV, short circuit current Jsc=41.8mA / cm², fill factor FF=82.5%, photoelectric conversion efficiency EFF=24.82%.

[0038] Example 3: Substrate parameters are the same as in Example 1; back-side tunneling oxide layer thickness is 5 nm, intrinsic polycrystalline silicon layer thickness is 350 nm; mask layer is a single layer of silicon oxynitride with a thickness of 90 nm; laser window width is 500 μm, window spacing is 100 μm; laser power is 60 W, frequency is 500 kHz; boron doping concentration in the P-region is 8 × 10⁻⁶. 20 cm - ³, BSG thickness 80 nm, doping temperature 1000℃; N-region phosphorus doping concentration 5 × 10⁻⁶ 20 cm - ³, PSG thickness 30nm, doping temperature 900℃; HF cleaning concentration 20%, temperature 30℃; annealing peak temperature 1000℃, holding for 45min; front pyramid texturing thickness 4μm, texturing surface reflectivity 9%; passivation layer thickness 8nm, front antireflective film thickness 120nm, back antireflective film thickness 100nm; electrode fabricated using PVD process.

[0039] Finished battery performance: Open circuit voltage Voc=731mV, short circuit current Jsc=43.1mA / cm², fill factor FF=83.5%, photoelectric conversion efficiency EFF=26.32%.

[0040] To highlight the innovativeness and performance advantages of the structure and process of this invention, two sets of comparative examples were set up, corresponding to the traditional PERT cell structure and the back contact cell structure without partitioned alternating doping, respectively. All comparative examples used the same N-type silicon wafers, the same testing standards and testing environment. The specific parameters and performance differences are as follows: Comparative Example 1: A conventional N-type PERT cell structure with a front electrode is adopted, without a back tunneling oxide layer and intrinsic polycrystalline silicon passivation structure. The back side uses conventional aluminum back field passivation, and the front side has grid electrodes, which cause light-shielding losses. There is no laser partitioning windowing and alternating doping process. The whole process adopts a single ion diffusion back field process. Only a single layer of SiNx antireflection film is deposited on the front and back sides, without an Al2O3 fine passivation layer. The remaining substrate cleaning, texturing, and annealing processes are consistent with those of Example 1 of this invention.

[0041] Finished battery performance: Open circuit voltage Voc=705mV, short circuit current Jsc=40.2mA / cm², fill factor FF=80.1%, photoelectric conversion efficiency EFF=22.68%.

[0042] Comparative Example 2 The back-contact battery structure is adopted, retaining the tunneling oxide layer, intrinsic polycrystalline silicon layer and double-sided passivation anti-reflection structure. The core secondary laser windowing and alternating P / N doping process of this invention are eliminated. A uniform doping process is adopted for the whole wafer, with no partitioned P and N alternating arrangement structure. The remaining film parameters and process parameters are completely consistent with those of Example 1.

[0043] Finished battery performance: Open circuit voltage Voc=716mV, short circuit current Jsc=41.5mA / cm², fill factor FF=81.3%, photoelectric conversion efficiency EFF=24.15%.

[0044] Analysis of Results from Examples and Comparative Examples: 1. Compared with traditional PERT cells (Comparative Example 1), the cells in each embodiment of the present invention have no front-side light-blocking loss. With the combination of tunneling oxide layer + polycrystalline silicon composite passivation and double-sided fine passivation structure, carrier recombination is greatly reduced, and open-circuit voltage, short-circuit current and fill factor are significantly improved. The overall conversion efficiency is improved by 2.14%-3.64%, showing significant performance advantages.

[0045] 2. Compared with the back contact battery without partitioned alternating doping (Comparative Example 2), the partitioned alternating P / N doping structure of the present invention can effectively avoid carrier crosstalk and local recombination problems, with lower electrode contact impedance, higher current extraction efficiency, and improved battery conversion efficiency by 0.67%-2.17%, which verifies the necessity and advancement of the core partitioned doping process of the present invention.

[0046] 3. Within the parameter range of this invention, the film thickness, laser parameters, doping concentration and annealing temperature can be adapted to different process scenarios. Example 3, with thick film and high-temperature precision annealing, can achieve the optimal conversion efficiency. Example 1 with conventional parameters balances performance and mass production cost, and can be adapted to the needs of large-scale mass production. It has wide process adaptability and strong performance stability.

[0047] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein.

[0048] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0049] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A back-contact solar cell, characterized in that, The device includes an N-type silicon wafer. A tunneling oxide layer with a thickness of 1 nm to 5 nm is grown on the back side of the N-type silicon wafer. An intrinsic polycrystalline silicon thin film layer with a thickness of 100 to 350 nm is deposited on the side of the tunneling oxide layer away from the back side of the N-type silicon wafer. A mask with a thickness of 60 to 90 nm is deposited on the side of the intrinsic polycrystalline silicon thin film away from the back side of the N-type silicon wafer. The mask has multiple spaced windows on the side away from the back side of the N-type silicon wafer. The windows extend into the intrinsic polycrystalline silicon thin film layer. Each of the multiple windows is doped to form a P-doped region or an N-doped region. The P-doped regions and N-doped regions are alternately arranged on the side of the intrinsic polycrystalline silicon thin film layer away from the tunneling oxide layer. A passivation layer and an antireflection film layer are sequentially deposited on the side of the mask away from the back side of the N-type silicon wafer. Metal electrodes that pass through the passivation layer and the antireflection film layer are connected to the P-doped regions and the N-doped regions on the side away from the back side of the N-type silicon wafer. The front side of the N-type silicon wafer has a texturing structure to reduce reflectivity. A passivation layer and an antireflection film layer are sequentially deposited on the texturing structure.

2. A back-contact solar cell according to claim 1, characterized in that, The flocking structure is pyramid-shaped and has a thickness of 1-4 μm.

3. A back-contact solar cell according to claim 1, characterized in that, The surface roughness Ra of the N-type silicon wafer is ≤0.2nm; the scratch depth is ≤5nm; there are no corrosion pits or pinholes after etching; the number of particles larger than or equal to 0.1μm on the surface is ≤10 per wafer; the ultrapure water contact angle is ≤10°; and the single metal element content is ≤1×10¹. 0 atoms / cm².

4. A back-contact solar cell according to claim 1, characterized in that, The window width is 200-500 micrometers.

5. A back-contact solar cell according to claim 1, characterized in that, The passivation layer on the front and back sides of the N-type silicon wafer is made of aluminum oxide with a thickness of 3-8 nm; the antireflection coating is made of one or more of SiO2, SiNx and SiONx, with the antireflection coating on the front side of the N-type silicon wafer having a thickness of 70-120 nm and the antireflection coating on the back side of the N-type silicon wafer having a thickness of 80-100 nm.

6. A back-contact solar cell according to claim 1, characterized in that, The mask is any one, two, or three of silicon oxide, silicon nitride, and silicon oxynitride stacked together.

7. A method for fabricating a back-contact solar cell, characterized in that, The preparation of the back-contact solar cell according to any one of claims 1-6 includes the following steps: S1. Pre-clean and polish the cut N-type silicon wafers; S2. A tunneling oxide layer with a thickness of 1nm-5nm is generated on the back side of the processed silicon wafer by thermal oxidation or chemical oxidation, and an intrinsic polycrystalline silicon thin film layer with a thickness of 100-350nm is deposited on the tunneling oxide layer. S3. A 60-90 nm thick mask is deposited on the intrinsic polycrystalline silicon thin film layer using plasma-enhanced chemical vapor deposition. S4. A patterned laser windowing process is performed on a preset electrode area using a preset laser to remove the mask and form a window. Doping is then performed in the window using ion implantation or diffusion equipment until P-doped regions as emitters and N-doped regions as back field are alternately formed on the intrinsic polycrystalline silicon thin film layer. S5. The doped silicon wafer is cleaned and texturized, and then annealed to obtain a fully crystallized silicon wafer. S6. After depositing passivation layers and antireflection films on both the front and back sides of the crystallized silicon wafer, metal electrodes are led out at preset positions in the P-doped and N-doped regions using screen printing or copper plating processes to form the back contact solar cell.

8. The method for fabricating a back-contact solar cell according to claim 7, characterized in that, The steps in S4 include: P-region and N-region are preset on the mask. Doping sources corresponding to the preset P-region and N-region are obtained respectively. One of the regions is selected for the first laser windowing. The corresponding doping source is selected to perform the first doping on the intrinsic polycrystalline silicon thin film layer in the window. Select another region pattern for a second laser windowing, with the two windowing positions spaced 20-100 μm apart. Select the corresponding doping source to perform a second doping on the intrinsic polycrystalline silicon thin film layer within the other window, until P-doped regions serving as emitters and N-doped regions serving as back field are alternately formed on the intrinsic polycrystalline silicon thin film layer.

9. A method for fabricating a back-contact solar cell according to claim 8, characterized in that, The doping source corresponding to the preset P region is a boron source. The preset P region is doped by depositing the boron source within the first window opening, controlling the deposition temperature at 700℃-1000℃, and controlling the doping source flow rate and deposition time until the surface boron concentration of the doped region reaches 5×10⁻⁶. 19 -8×10 20 cm -3 BSG thickness 40-80nm; The preset N-region is doped with a phosphorus source. The preset N-region is doped by depositing the phosphorus source within the second window opening. The deposition temperature is 700℃-900℃, and the doping source flow rate and deposition time are controlled until the phosphorus concentration on the surface of the doped region reaches 3×10⁻⁶. 19 -5×10 20 cm -3 PSG thickness 5-30nm; The laser used is a green or ultraviolet picosecond laser with an output power of 30-60W and a frequency of 100-500kHz.

10. A method for fabricating a back-contact solar cell according to claim 8, characterized in that, The steps in S5 include: Use HF with a concentration of 3%-20% and a temperature of 25±5℃ to remove the oxide layer in the doped region and to coat BSG and PSG around it. After texturing, control the peak annealing temperature to 850℃ - 1000℃ and maintain the peak annealing temperature for 20-45 minutes.

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