Solar cell, method of manufacturing the same, and photovoltaic module

Abstract

The present disclosure provides a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises: a semiconductor substrate, the semiconductor substrate comprising a first textured structure on at least part of a surface of the semiconductor substrate; a first doped semiconductor layer on a side of the semiconductor substrate having the first textured structure; and an anti-reflection layer on a side of the first doped semiconductor layer away from the semiconductor substrate, the anti-reflection layer comprising a second textured structure on a surface of the anti-reflection layer away from the semiconductor substrate, the second textured structure being arranged correspondingly to the first textured structure, and the second textured structure comprising a plurality of first protrusions, each of the first protrusions comprising a first apex, and a shape of a cross section of one of the first protrusions in a plane perpendicular to the semiconductor substrate and passing through the first apex comprising a first edge and a second edge intersecting at the first apex, and an included angle between the first edge and the second edge being greater than or equal to 83°. The solar cell has low reflectivity and high performance.

Description

Technical Field

[0001] This disclosure relates to the field of battery technology, specifically to solar cells, their preparation methods, and photovoltaic modules. Background Technology

[0002] In the field of crystalline silicon solar cell manufacturing, especially for high-efficiency cell structures such as tunnel oxide-passivated contacts (TOPCon), surface texturing is a key process for reducing light reflection loss and improving short-circuit current and photoelectric conversion efficiency. Surface texturing creates rough microstructures on the solar cell surface, converting specular reflection into multiple diffuse reflections, significantly reducing surface light reflection loss, lengthening the light propagation path within the cell, and improving photon absorption efficiency. However, due to limitations in related technologies, the performance of current solar cells still needs further improvement. Summary of the Invention

[0003] In view of this, the present disclosure provides a solar cell, a method for its fabrication, and a photovoltaic module.

[0004] This disclosure provides a solar cell comprising: a semiconductor substrate including a first textured structure located on at least a portion of the surface of the semiconductor substrate; a first doped semiconductor layer located on the side of the semiconductor substrate having the first textured structure; an antireflection layer located on the side of the first doped semiconductor layer facing away from the semiconductor substrate, the antireflection layer including a second textured structure located on the surface of the antireflection layer facing away from the semiconductor substrate; the second textured structure being disposed corresponding to the first textured structure; the second textured structure including a plurality of first protrusions, each first protrusion including a first vertex, and the shape of a cross-section of a first protrusion in a plane perpendicular to the semiconductor substrate and passing through the first vertex including a first side and a second side intersecting at the first vertex, the included angle between the first side and the second side being greater than or equal to 83°.

[0005] A second aspect of this disclosure provides a method for fabricating a solar cell, comprising: texturing at least a portion of the surface of a semiconductor substrate to obtain a semiconductor substrate including a fifth textured surface structure; forming a first doped semiconductor layer on the surface of the fifth textured surface structure by doping, thereby obtaining a first textured surface structure and a fourth textured surface structure; fabricating an antireflection layer including a second textured surface structure on the side of the first doped semiconductor layer facing away from the semiconductor substrate, the second textured surface structure being located on the surface of the antireflection layer facing away from the semiconductor substrate; the second textured surface structure being disposed correspondingly to the first textured surface structure; the second textured surface structure including a plurality of first protrusions, each first protrusion including a first vertex, and the shape of a cross-section of a first protrusion in a plane perpendicular to the semiconductor substrate and passing through the first vertex including a first side and a second side intersecting at the first vertex, the included angle between the first side and the second side being greater than or equal to 83°.

[0006] The third aspect of this disclosure provides a photovoltaic module, including the solar cell provided in the first aspect, or including a solar cell prepared by the preparation method provided in the second aspect.

[0007] According to the solar cell provided in this embodiment, the antireflection layer includes a second textured structure. The angle between the first side and the second side corresponding to the first vertex of the first protrusion in the second textured structure is appropriate. When light shines on the surface of the antireflection layer away from the semiconductor substrate, the light tends to undergo multiple reflections between adjacent sides of the first protrusion with a suitable tilt angle, forming a light-trapping effect. This significantly increases the optical path length of light propagating inside the cell, thereby increasing the probability of light absorption and consequently greatly reducing the reflectivity. The surface of the antireflection layer away from the semiconductor substrate is relatively stable and regular, providing sufficient and stable contact area for the subsequent fabrication of the first electrode, effectively reducing contact resistance, and ensuring good ohmic contact between the first electrode and the antireflection layer. This results in a higher open-circuit voltage and fill factor for the solar cell, and a higher electro-conversion efficiency. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the cross-sectional structure of a solar cell in one embodiment of the present disclosure.

[0009] Figure 2 In one embodiment of this disclosure, the solar cell is Figure 1 A magnified schematic diagram of the structure at point A in the middle.

[0010] Figure 3 This is a schematic diagram of the cross-sectional structure of a solar cell in another embodiment of this disclosure.

[0011] Figure 4 In one embodiment of this disclosure, the antireflection layer is in Figure 1 A magnified schematic diagram of the structure at point A in the middle.

[0012] Figure 5 This is a schematic diagram of the cross-sectional structure of a solar cell in another embodiment of this disclosure.

[0013] Figure 6 In one embodiment of this disclosure, the solar cell is Figure 5 A magnified schematic diagram of the structure at point B in the middle.

[0014] Figure 7 This is a schematic diagram of the cross-sectional structure of a solar cell in another embodiment of this disclosure.

[0015] Figure 8 This is a schematic diagram of a method for fabricating a solar cell in one embodiment of the present disclosure.

[0016] Figure 9This is a scanning electron microscope image of the fifth textured surface structure obtained after the second texturing process in Example 1.

[0017] Figure 10 This is a scanning electron microscope image of the antireflection layer away from the surface of the semiconductor substrate in Example 1.

[0018] Figure 11 This is a scanning electron microscope image of the antireflection layer in Comparative Example 1 facing away from the surface of the semiconductor substrate. Detailed Implementation

[0019] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0020] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods and means well-known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0023] In the fabrication of crystalline silicon solar cells, especially TOPCon cells, reducing the reflection loss of incident light on the cell surface is a key approach to improving photoelectric conversion efficiency. To achieve this, the commonly used technique is wet chemical texturing of the silicon wafer surface to form a pyramid-shaped textured structure. However, the inventors of this disclosure have discovered that the current pyramid structure has a relatively sharp apex angle, resulting in high light reflectivity of the solar cell. Furthermore, the contact area between the first electrode and the antireflection layer in the solar cell is small, leading to high contact resistance and consequently, lower solar cell performance.

[0024] In view of this, the first aspect of this disclosure provides a solar cell, with reference to... Figure 1 The schematic diagram of the cross-sectional structure of the solar cell shown, and Figure 2 The partial magnified structural diagram of the antireflection layer shown includes: a semiconductor substrate 100, a first doped semiconductor layer 200, and an antireflection layer 300.

[0025] Exemplarily, the semiconductor substrate 100 includes a first textured structure 110 located on at least a portion of the surface of the semiconductor substrate 100; a first doped semiconductor layer 200 is located on the side of the semiconductor substrate 100 having the first textured structure 110; an antireflective layer 300 is located on the side of the first doped semiconductor layer 200 facing away from the semiconductor substrate 100, and the antireflective layer 300 includes a second textured structure 310 located on the surface of the antireflective layer 300 facing away from the semiconductor substrate 100; the second textured structure 310 and the first textured structure 110 are paired. The second textured structure 310 should include a plurality of first protrusions 310a, each first protrusion 310a including a first vertex Q1. The shape of the cross-section of a first protrusion 310a in a plane perpendicular to the semiconductor substrate 100 and passing through the first vertex Q1 includes a first side L1 and a second side L2 intersecting at the first vertex Q1. The included angle between the first side L1 and the second side L2 is greater than or equal to 83°, for example, it can be 83°, 84°, 85°, 88°, 90°, 92°, 95°, 100°, 105°, 110°, 115° or 120°, etc.

[0026] It is understood that there can be multiple planes perpendicular to the semiconductor substrate 100 and passing through the first vertex Q1. Correspondingly, a first protrusion 310a can have multiple cross sections in the plane perpendicular to the semiconductor substrate 100 and passing through the first vertex Q1. Each cross section corresponds to an angle value between a first side L1 and a second side L2. An angle between the first side L1 and the second side L2 greater than or equal to 83° means that the angle between the first side L1 and the second side L2 in any cross section is greater than or equal to 83°.

[0027] According to the solar cell provided in this embodiment, the antireflection layer 300 includes a second textured structure 310. The angle between the first side L1 and the second side L2 corresponding to the first vertex Q1 of the first protrusion 310a in the second textured structure 310 is appropriate. When light shines on the surface of the antireflection layer 300 away from the semiconductor substrate 100, the light tends to undergo multiple reflections between adjacent sides of the first protrusion 310a with relatively appropriate tilt angles, forming a light-trapping effect. This significantly increases the optical path length of light propagating inside the cell, thereby increasing the probability of light absorption and significantly reducing the reflectivity. The surface of the antireflection layer 300 away from the semiconductor substrate 100 is relatively stable and regular, providing sufficient and stable contact area for the subsequent fabrication of the first electrode, effectively reducing contact resistance, and ensuring good ohmic contact between the first electrode and the antireflection layer 300. This results in a higher open-circuit voltage and fill factor for the solar cell, and a higher electrical conversion efficiency.

[0028] It should be noted that velvety texture refers to a surface with regular or irregular three-dimensional texture designed and manufactured to reduce optical reflection.

[0029] For example, the first velvet structure 110 includes a plurality of first pyramid structures, and the second velvet structure 310 includes a plurality of second pyramid structures (i.e., first protrusions). The correspondence between the second velvet structure 310 and the first velvet structure 110 means that a second pyramid structure is disposed on top of a first pyramid structure, and the surface of the second pyramid structure near the first pyramid structure is almost completely fitted with the first pyramid structure.

[0030] For example, refer to Figure 3 The solar cell also includes a first electrode 500, partially located on the side of the antireflective layer 300 facing away from the semiconductor substrate 100. The first electrode 500 penetrates the antireflective layer 300 and directly contacts the first doped semiconductor layer 200. A larger contact area between the first electrode 500 and the first doped semiconductor layer 200 results in lower contact resistance and higher open-circuit voltage and fill factor for the solar cell. The first electrode 500 includes main grid lines and sub-grid lines. When the solar cell includes a first passivation layer 400, refer to... Figure 5 Part of the first electrode 500 is located on the side of the antireflection layer 300 away from the semiconductor substrate 100, and the first electrode 500 penetrates the first passivation layer 400 and the antireflection layer 300 and then directly contacts the first doped semiconductor layer 200.

[0031] For example, the semiconductor substrate 100 includes a first textured structure 110 formed on its light-receiving surface. The first textured structure 110 includes a micron-scale pyramid array, the core function of which is to reduce reflection of ambient light, increase light absorption, and improve light utilization. At the same time, the first textured structure 110 has a large surface area, which is beneficial for the deposition of the antireflection layer 300 and the first passivation layer 400, thereby improving the passivation effect and the carrier collection effect.

[0032] It is understandable that the first doped semiconductor layer 200 can be a P-type doped layer (or P-type doped layer). + An emitter is formed by infiltrating boron atoms into a semiconductor substrate through ion implantation or high-temperature diffusion.

[0033] In one embodiment, refer to Figure 2The first doped semiconductor layer 200 includes a fourth textured structure 210, which is located on the surface of the first doped semiconductor layer 200 away from the semiconductor substrate 100. The fourth textured structure 210 includes a plurality of third protrusions 210a, each of which includes a third vertex Q3. The shape of the cross section of a third protrusion 210a in a plane perpendicular to the semiconductor substrate 100 and passing through the third vertex Q3 includes a fifth side L5 and a sixth side L6 intersecting at the third vertex Q3. The included angle between the fifth side L5 and the sixth side L6 is less than or equal to the included angle between the first side L1 and the second side L2. Optionally, the included angle between the fifth side L5 and the sixth side L6 is greater than or equal to 58° and less than or equal to 114°, for example, it can be 58°, 60°, 65°, 70°, 75°, 80°, 83°, 84°, 85°, 88°, 90°, 92°, 95°, 100°, 105°, 110°, 114°, etc. Thus, at the apex of the third protrusion 210a in the fourth textured structure 210, the included angle between the fifth side L5 and the sixth side L6 is suitable, which is beneficial for the subsequent fabrication of the antireflection layer 300. This also makes the included angle between the first side L1 and the second side L2 at the apex of the first protrusion 310a in the antireflection layer 300 suitable, which is beneficial for improving the light trapping effect, fill factor, and open-circuit voltage of the solar cell.

[0034] It should be noted that in the fourth velvet structure 210, the included angles of the fifth side L5 and the sixth side L6 corresponding to the plurality of third protrusions 210a may be equal or unequal, and the included angles of the fifth side L5 and the sixth side L6 corresponding to the plurality of third protrusions 210a are between 58° and 114°.

[0035] It can be understood that there can be multiple planes perpendicular to the semiconductor substrate 100 and passing through the third vertex Q3. Correspondingly, a third protrusion 210a can have multiple cross-sections within the planes perpendicular to the semiconductor substrate 100 and passing through the third vertex Q3. Each cross-section corresponds to an angle value between the fifth side L5 and the sixth side L6. An angle between the fifth side L5 and the sixth side L6 greater than or equal to 58° means that the angle between the fifth side L5 and the sixth side L6 in any cross-section is greater than or equal to 58°. An angle between the fifth side L5 and the sixth side L6 less than or equal to 114° means that the angle between the fifth side L5 and the sixth side L6 in any cross-section is less than or equal to 114°.

[0036] It is understandable that in the region near the third vertex Q3, the third protrusion 210a has no concave structure, and the contact area between the first electrode 500 and the first doped semiconductor layer 200 is large, which is beneficial to improving the light trapping effect, fill factor and open circuit voltage of the solar cell.

[0037] It is understood that the first doped semiconductor layer 200 has a uniform thickness. After the first doped semiconductor layer 200 is doped into the semiconductor substrate, the resulting fourth textured structure 210 is exactly the same as the first textured structure 110.

[0038] In one embodiment, the third protrusion 210a includes a second pyramid structure body 201 and at least one second protrusion unit 202, the at least one second protrusion unit 202 being located on the sidewall of the second pyramid structure body 201. It is understood that after the antireflection layer 300 is formed on the surface of the first doped semiconductor layer 200, a corresponding protrusion structure will also be present in the antireflection layer 300. Therefore, the provision of the third protrusion 210a is beneficial for further enhancing the light-trapping effect of the solar cell.

[0039] For example, the height of the second protrusion unit 202 protruding from the sidewall of the second pyramid structure body 201 is greater than or equal to 13 nm and less than or equal to 68 nm. For example, it can be 13 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, or 68 nm. With a suitable protrusion height of the second protrusion unit 202, when the subsequently formed antireflection layer 300 is uniformly formed on the surface of the second protrusion unit 202, a first protrusion unit with a suitable protrusion height can be formed on the surface of the second protrusion unit 202 on the side opposite to the first doped semiconductor layer 200, resulting in excellent light trapping effect of the solar cell.

[0040] Exemplarily, the second protruding units 202 surround the second pyramid structure body 201. Exemplarily, multiple second protruding units 202 are arranged at intervals along the extension direction of the sidewall of the second pyramid structure body 201. This forms a multi-level micro-nano composite light-trapping structure. After incident light is reflected by the sidewall of the second protruding units 202, it is further scattered and refracted by the second protruding units 202, extending the optical path of the light on the surface of the semiconductor substrate 100 and reducing specular reflection loss. Simultaneously, the spaced-apart second protruding units 202 can disrupt regular reflection paths, allowing light to couple into the semiconductor substrate 100 at multiple angles, improving the absorption of short-wavelength light, and enhancing the overall light-trapping and anti-reflection effects, thereby improving the light utilization rate of the solar cell.

[0041] In one embodiment, refer to Figure 2The first protrusion 310a includes a first pyramid structure body 301 and at least one first protrusion unit 302, with the at least one first protrusion unit 302 located on the sidewall of the first pyramid structure body 301. This allows for the formation of a multi-level composite microstructure. When incident light hits the inclined surface, it is not only reflected by the first pyramid structure body 301 but also further scattered and refracted by the first protrusion unit 302, significantly extending the optical path on the surface, reducing specular reflection loss, effectively widening the reflection angle of the incident light, allowing more light to couple into the first semiconductor substrate 100, improving the absorption of incident light at different angles, enhancing the overall light trapping and anti-reflection effect, and improving photoelectric conversion efficiency.

[0042] For example, the height of the first protruding unit 302 protruding from the sidewall of the first pyramid structure body 301 is greater than or equal to 19 nm and less than or equal to 121 nm. For example, it can be 19 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 68 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 121 nm, etc. Thus, the first protruding unit 302 can effectively generate strong Mie scattering and interference effects on short-wavelength light, destroying specular reflection, while avoiding shadow loss and increased carrier recombination caused by excessive size. The protrusion height of the first protruding unit 302 can extend the optical path, widen the incident angle range, and improve short-wavelength absorption, ensuring excellent anti-reflection and light trapping effects without significantly deteriorating surface passivation, balancing optical gain and electrical performance, and improving overall photoelectric conversion efficiency.

[0043] For example, the first protruding unit 302 surrounds the first pyramid structure body 301. For example, a plurality of first protruding units 302 are arranged at intervals along the extension direction of the sidewall of the first pyramid structure body 301.

[0044] In one embodiment, along the extension direction of the sidewall of the first pyramid structure 301, the ratio of the length of the sidewall between the two farthest first protruding units 302 to the total length of the sidewall of the first pyramid structure 301 is greater than or equal to 70%, for example, it can be 70%, 75%, 80%, 85%, 90%, 95%, 100%, etc. Therefore, the first protruding units 302 are widely distributed on the sidewall of the first pyramid structure 301, covering a large effective area, and can form a continuous and uniform micro-nano scattering structure on most of the sidewall surface. When incident light is reflected by the sidewall of the first pyramid structure 301, it can be fully scattered and refracted, reducing regular specular reflection, effectively extending the optical path and improving optical coupling efficiency. The widely distributed first protruding units 302 can achieve good control over incident light at different angles, improving the overall light trapping and anti-reflection performance, avoiding excessively high local reflection due to sparse protrusion distribution, and ensuring uniform and stable light trapping effect.

[0045] For example, a first protrusion unit 302 and a second protrusion unit 202 are correspondingly arranged. The positions of the first protrusion unit 302 and the second protrusion unit 202 are matched and arranged in a corresponding relationship, which can make the upper and lower structures form a symmetrical and regular composite micro-morphology, which is conducive to uniformly controlling light reflection and scattering, ensuring the consistency of light trapping and passivation effects, and improving the overall performance stability of the solar cell.

[0046] For example, the correspondence between a first protrusion unit 302 and a second protrusion unit 202 means that the surface of the first protrusion unit 302 near the second protrusion unit 202 is almost completely fitted with the second protrusion unit 202.

[0047] In one embodiment, the included angle between the first side L1 and the second side L2 is less than or equal to 116°. The included angle between the first side L1 and the second side L2 is between 83° and 116°, so that the first protrusion 310a is not too flat, thereby ensuring that the first protrusion 310a has a strong macroscopic light-trapping ability, which is conducive to achieving a good combination of a gentle apex that is beneficial to electrical contact and an inclined side that is effective for optical capture.

[0048] It is understood that there can be multiple planes perpendicular to the semiconductor substrate 100 and passing through the first vertex Q1. Correspondingly, a first protrusion 310a can have multiple cross sections in the plane perpendicular to the semiconductor substrate 100 and passing through the first vertex Q1. Each cross section corresponds to an angle value between a first side L1 and a second side L2. An angle between the first side L1 and the second side L2 that is less than or equal to 116° means that the angle between the first side L1 and the second side L2 in any cross section is less than or equal to 116°.

[0049] It is understandable that the angle between the first side L1 and the second side L2 can be called the apex angle of the first velvet structure 110. The definition of the apex angle in the other velvet structures can refer to the apex angle of the first velvet structure 110, and will not be elaborated further here.

[0050] It is understood that in the same solar cell, the second textured structure 310 includes multiple first protrusions 310a. The included angles of the first side L1 and the second side L2 corresponding to the multiple first protrusions 310a may be the same or different. When the included angles of the first side L1 and the second side L2 corresponding to the multiple first protrusions 310a are different, the included angles of the first side L1 and the second side L2 corresponding to the multiple first protrusions 310a are between 83° and 116°. It is understood that when the included angle of the first side L1 and the second side L2 is less than 83° (e.g., 55°, 60°, 65°, 70°, etc.), it indicates that the side of the first protrusion 310a is too steep and the tip is too sharp. This will reduce the effective contact area between the subsequent screen-printed metal electrode paste and the pyramid side, and may lead to poor local contact due to the small radius of curvature of the tip, thereby increasing the contact resistance (Rs) and directly damaging the fill factor (FF). Furthermore, an overly sharp or steep shape of the first protrusion 310a can easily create coverage defects or stress concentration points at the tip, leading to increased surface recombination and consequently reducing the open-circuit voltage (Uoc). When the angle between the first side L1 and the second side L2 is greater than 116°, although it may be beneficial for electrode contact and film coverage, it will severely weaken the core light-trapping function of the pyramid textured surface. In addition, an overly gentle side angle of the first protrusion 310a will significantly reduce the opportunity for light to undergo multiple reflections between adjacent pyramid sides, causing more incident light to be reflected away upon first contact with the surface, resulting in increased surface reflectivity (especially short-wavelength reflectivity), thereby reducing the battery's short-circuit current (Isc).

[0051] In one embodiment, refer to Figure 2 The first side L1 includes a first straight line portion L11, and the second side L2 includes a second straight line portion L21. The first straight line portion L11 and the second straight line portion L21 intersect at the first vertex Q1. The included angle between the first straight line portion L11 and the second straight line portion L21 is greater than or equal to 83°.

[0052] For example, the first side L1 includes a first end 311a, which is positioned opposite to the first vertex Q1. The ratio of the length of the first straight section L11 to the length of the line connecting the first end 311a and the first vertex Q1 is greater than or equal to 0 and less than or equal to 5%, for example, it can be 0, 1%, 2%, 3%, 3.5%, 4%, 4.5%, or 5%. For example, it can be 0, 1%, 2%, 3%, 3.5%, 4%, 4.5%, or 5%. For example, the second side L2 includes a second end 312a, which is positioned opposite to the first vertex Q1. The ratio of the length of the second straight section L21 to the length of the line connecting the second end 312a and the first vertex Q1 is greater than or equal to 0 and less than or equal to 5%, for example, it can be 0, 1%, 2%, 3%, 3.5%, 4%, 4.5%, or 5%. Therefore, the ratio of the straight segments of the first side L1 and the second side L2 is relatively small, resulting in less light reflection and thus reducing reflectivity.

[0053] In one embodiment, refer to Figure 4 The first side L1 includes a first straight section L11 and a first arc section H1. The first straight section L11 is connected to the second side L2 through the first arc section H1. The first arc section H1 protrudes in a direction away from the second side L2. The second side L2 includes a second straight section L21 and a second arc section H2. The second straight section L21 is connected to the first side L1 through the second arc section H2. The second arc section H2 protrudes in a direction away from the first side L1. The angle between the extension of the first straight section L11 and the extension of the second straight section L21 is greater than or equal to 83°. It can be understood that there is no depression near the first vertex Q1, and the position near the first vertex Q1 is a convex arc shape. The arc transition eliminates sharp corners, reduces specular reflection and stray scattering of light at the corners, improves light capture capability, and reduces surface reflectivity. It can avoid electric field concentration, reduce dangling bonds and interface defects on the surface of the semiconductor substrate 100, reduce recombination loss, and improve open-circuit voltage. It can also alleviate stress concentration in the antireflection layer 300, prevent film cracking, and ensure passivation uniformity; it can also improve the spreading and sintering penetration uniformity of the first electrode 500 (e.g., the material of the first electrode 500 is silver paste), reduce contact resistance, increase fill factor and short-circuit current, and ultimately improve battery conversion efficiency and reliability.

[0054] In one embodiment, along the direction away from the first vertex Q1, the distance from the first arc portion H1 to the semiconductor substrate 100 gradually decreases and the magnitude of the decrease gradually increases; and / or, the distance from the second arc portion H2 to the semiconductor substrate 100 gradually decreases and the magnitude of the decrease gradually increases.

[0055] In one embodiment, the first side L1 includes a first end 311a, which is disposed opposite to the first vertex Q1. The ratio of the length of the first straight section L11 to the length of the line connecting the first end 311a and the first vertex Q1 is greater than or equal to 0 and less than or equal to 4%, for example, it can be 0, 1%, 2%, 2.5%, 3%, 3.5%, or 4%, etc. The ratio of the length of the first arc section H1 to the length of the line connecting the first end 311a and the first vertex Q1 is greater than or equal to 0 and less than or equal to 2%, for example, it can be 0, 0.5%, 1%, 1.2%, 1.4%, 1.8%, or 2%, etc. The second side L2 includes a second end 312a, which is positioned opposite to the first vertex Q1. The ratio of the length of the second straight portion L21 to the length of the line connecting the second end 312a and the first vertex Q1 is greater than or equal to 0 and less than or equal to 4%, for example, it can be 0, 1%, 2%, 2.5%, 3%, 3.5%, or 4%, etc. The ratio of the length of the second arc portion H2 to the length of the line connecting the second end 312a and the first vertex Q1 is greater than or equal to 0 and less than or equal to 2%, for example, it can be 0, 0.5%, 1%, 1.2%, 1.4%, 1.8%, or 2%, etc. This allows for a precise balance between optical and electrical performance, ensuring sufficient arc transition, reducing specular reflection and stray light caused by sharp corners, lowering surface reflectivity, and improving light absorption; while also avoiding excessive arc leading to electric field concentration and increased interface defects, effectively reducing recombination loss and improving passivation effect. Simultaneously, it optimizes the spreading and sintering uniformity of the first electrode 500, reducing contact resistance and series loss, and improving fill factor and short-circuit current. The appropriate size ratio balances stress dispersion and structural stability of the film layer, reduces the risk of cracking of the anti-reflection layer 300, and ultimately improves the conversion efficiency and yield of solar cells.

[0056] For example, the first protruding unit 302 is located on the side of the first straight portion L11 near the bottom wall of the first pyramid structure body 301.

[0057] In one embodiment, the reflectivity of light after being irradiated onto the antireflection layer 300 on the side of the antireflection layer 300 away from the semiconductor substrate 100 is less than or equal to 7.5%, for example, it can be 7.5%, 7%, 6.5%, 6%, 5.5%, 5%, 4.5%, 4%, 3.5%, 3%, 2.5%, 2%, 1.5%, 1%, 0.5%, or 0.

[0058] For example, refer to Figure 5 The solar cell also includes: a first passivation layer 400 located on the side of the antireflection layer 300 away from the semiconductor substrate 100. A first electrode 500 is located on the side of the first passivation layer 400 away from the semiconductor substrate 100, and the first electrode 500 penetrates the first passivation layer 400 and the antireflection layer 300 and then directly contacts the first doped semiconductor layer 200.

[0059] For example, refer to Figure 5 The first passivation layer 400 includes a third textured structure 410, which is located on the surface of the first passivation layer 400 away from the semiconductor substrate 100; the third textured structure 410 is correspondingly disposed with the second textured structure 310.

[0060] In one embodiment, refer to Figure 6 The third textured structure 410 includes a plurality of second protrusions 410a, each second protrusion 410a including a second vertex Q2. The shape of the cross-section of a second protrusion 410a in a plane perpendicular to the semiconductor substrate 100 and passing through the second vertex Q2 includes a third side L3 and a fourth side L4 intersecting at the second vertex Q2. The included angle between the third side L3 and the fourth side L4 is less than or equal to the included angle between the first side L1 and the second side L2. This helps to reduce light reflection, improve light utilization, and enhance the performance of the solar cell.

[0061] It is understandable that the angle between the third side L3 and the fourth side L4 of the second protrusion 410a is greater than or equal to the angle between the fifth side L5 and the sixth side L6 of the corresponding third protrusion 210a.

[0062] It is understandable that the angle between the third side L3 and the fourth side L4 can be called the apex angle of the third velvet structure 410.

[0063] For example, the correspondence between the third textured structure 410 and the second textured structure 310 means that a second protrusion 410a is correspondingly provided with a first protrusion 310a. Specifically, a second protrusion 410a is located on the side of a first protrusion 310a that is away from the semiconductor substrate 100, and the trend of the second protrusion 410a matches the trend of the first protrusion 310a.

[0064] For example, the third velvet structure 410 includes a plurality of third pyramid structures. The correspondence between the third velvet structure 410 and the second velvet structure 310 means that a third pyramid structure is disposed on top of a second pyramid structure, and the surface of the third pyramid structure close to the second pyramid structure is almost completely fitted with the second pyramid structure.

[0065] For example, the material of the first passivation layer 400 includes aluminum oxide, silicon oxide, etc. The preparation method of the first passivation layer 400 includes atomic layer deposition (ALD), plasma-enhanced ALD, etc. The function of the first passivation layer 400 is to passivate the surface states of the semiconductor substrate 100 and suppress carrier recombination. The correspondence between the third textured structure 410 and the first textured structure 110 means that the third textured structure 410 includes a micron-scale pyramid array, and the first passivation layer 400 is a film layer of uniform thickness with strong conformability. It can completely preserve the original pyramid structure in the first textured structure 110 without destroying the microstructure of the first textured structure 110, thereby maintaining the good anti-reflection and light absorption characteristics of the semiconductor substrate 100 surface, while achieving efficient passivation of the semiconductor substrate 100 surface and improving the photoelectric conversion performance of the solar cell. It can be understood that the pyramid structure on the surface of the semiconductor substrate 100 includes multiple pyramids, with one pyramid corresponding to one first protrusion 310a.

[0066] For example, the thickness of the first passivation layer 400 is greater than or equal to 12 nm and less than or equal to 14 nm, such as 12 nm, 12.5 nm, 13 nm, 13.5 nm, or 14 nm. It can be understood that the increased spatial volume of the fourth textured structure 210 on the surface of the first doped semiconductor layer 200 and the deeper surface trenches, within the aforementioned range, allows the first passivation layer 400 to fully fill the depressions, forming a complete and dense film layer. This enhances the chemical and field-effect passivation effect, reduces interface defects and surface recombination, and increases the open-circuit voltage. Simultaneously, it optimizes anti-reflection performance, reduces reflection, enhances light absorption, and increases short-circuit current. The first passivation layer 400 with the aforementioned thickness can also alleviate stress at the textured tips, prevent film cracking, buffer electrode sintering impact, prevent excessive ablation damage to the first doped semiconductor layer 200, improve contact uniformity, reduce contact resistance, and increase the fill factor and solar cell conversion efficiency.

[0067] For example, the fourth textured structure 210 on the surface of the first doped semiconductor layer 200 is relatively regular, which is beneficial to the fabrication of the first passivation layer 400.

[0068] For example, refer to Figure 7 The solar cell also includes a stacked tunneling oxide layer 600, a second doped semiconductor layer 700, a second passivation layer 800, and a second electrode 900. The second doped semiconductor layer 700 is located on the side of the tunneling oxide layer 600 facing away from the semiconductor substrate 100. For example, the tunneling oxide layer 600 may be made of silicon oxide. For example, the second doped semiconductor layer 700 may be a phosphorus-doped semiconductor layer, deposited on the side of the tunneling oxide layer 600 facing away from the semiconductor substrate 100, and is n +A polycrystalline silicon layer. For example, the second passivation layer 800 may be made of silicon nitride. For example, the second electrode 900 penetrates the second passivation layer 800 and comes into direct contact with the second doped semiconductor layer 700. For example, the solar cell in this embodiment is a TOPCon cell.

[0069] The second aspect of this disclosure provides a method for fabricating a solar cell, referring to... Figure 8 The diagram shows a process flow chart for fabricating a solar cell, which includes the following steps.

[0070] S100: At least a portion of the surface of a semiconductor substrate is texturized to obtain a semiconductor substrate including a fifth texturized structure.

[0071] It should be noted that the semiconductor substrate is the same as described above, and will not be repeated here.

[0072] In one embodiment, prior to texturing at least a portion of the surface of the semiconductor substrate, the method further includes: performing a first cleaning treatment on the semiconductor substrate using a cleaning solution; the cleaning solution includes an aqueous hydrogen peroxide solution and a first additive.

[0073] For example, the concentration of the hydrogen peroxide solution is greater than or equal to 0.5 wt% and less than or equal to 0.6 wt%, such as 0.50 wt%, 0.52 wt%, 0.54 wt%, 0.56 wt%, 0.58 wt%, 0.60 wt%, etc.

[0074] For example, the first additive comprises components having the following mass percentages: sodium carbonate 3.0% to 4.0% (e.g., 3.0%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, 4.0%, etc.), sodium sulfate 2.0% to 3.0% (e.g., 2.0%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3.0%, etc.), wetting agent 1.0% to 1.5% (e.g., 1.0%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, etc.), stabilizer 1.0% to 2.0% (e.g., 1.0%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2.0%, etc.), and dispersant 1.0%. % to 1.5% (e.g., 1.0%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, etc.), plus the remainder water.

[0075] It is understood that the wetting agent, stabilizer, and dispersant can be conventional materials. For example, the wetting agent can include, but is not limited to, at least one of sodium dodecylbenzenesulfonate and sodium dodecyl sulfate; the stabilizer can include, but is not limited to, at least one of sodium gluconate and sodium citrate; and the dispersant can include, but is not limited to, at least one of sodium polyacrylate and ammonium polyacrylate.

[0076] For example, the mass ratio of the first additive to the hydrogen peroxide solution is (0.5 to 1.5):100, such as (0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, etc.):100. This allows the first additive to fully synergize with hydrogen peroxide to effectively remove organic matter, metal ions, and particulate impurities from the semiconductor substrate surface, avoiding residual contamination that could affect texturing uniformity. The appropriate additive ratio of the first additive to the hydrogen peroxide solution stabilizes the hydrogen peroxide and slows its decomposition without causing excessive residue and secondary contamination, providing a clean and uniform surface for subsequent texturing and improving texturing effect and device yield.

[0077] For example, the cleaning process meets at least one of the following conditions: the time is greater than or equal to 240 s and less than or equal to 280 s, such as 240 s, 250 s, 260 s, 270 s, 280 s, etc.; the temperature is greater than or equal to 60°C and less than or equal to 70°C, such as 60°C, 62°C, 64°C, 66°C, 68°C, 70°C, etc. This fully activates the reactivity of the cleaning solution, effectively removing impurities and organic matter from the surface of the semiconductor substrate, ensuring thorough cleaning. A suitable temperature avoids both insufficient cleaning due to excessively low temperatures and damage to the semiconductor substrate due to excessively high temperatures; a reasonable time ensures uniform cleaning without dead corners, providing a clean surface for subsequent texturing, improving texturing quality and solar cell yield.

[0078] In one embodiment, texturing at least a portion of the surface of a semiconductor substrate includes performing a first texturing process and a second texturing process on the semiconductor substrate sequentially.

[0079] For example, a first solution is used to perform a texturing process on a semiconductor substrate, the first solution comprising a first alkaline solution and a second additive.

[0080] For example, the first alkaline solution includes at least one of sodium hydroxide and potassium hydroxide. For example, the concentration of the first alkaline solution is greater than or equal to 0.4 wt% and less than or equal to 0.5 wt% (e.g., it can be 0.40 wt%, 0.42 wt%, 0.44 wt%, 0.46 wt%, 0.48 wt%, 0.50 wt%, etc.). For example, the second additive comprises components having the following mass percentages: potassium sorbate 1.0% to 2.0% (e.g., 1.0%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2.0%, etc.), sodium acetate 2.0% to 4.0% (e.g., 2.0%, 2.2%, 2.4%, 2.6%, 2.8%, 3.0%, 3.2%, 3.4%, 3.6%, 3.8%, 4.0%, etc.), defoamer 5.0% to 7.0% (e.g., 5.0%, 5.2%, 5.4%, 5.6%, 5.8%, 6.0%, 6.2%, 6.4%, 6.6%, 6.8%, 7.0%, etc.), and surfactant 5.0% to 10.0%. The percentage (e.g., 5.0%, 5.5%, 6.0%, 6.5%, 7.0%, 7.5%, 8.0%, 8.5%, 9.0%, 9.5%, 10.0%, etc.) and the balance being water. Thus, the first alkaline solution and the second additive formulation can gently etch the semiconductor substrate to form a uniform textured surface. Potassium sorbate and sodium acetate stabilize the system, while defoamers and surfactants reduce defects, ensuring a uniform textured surface morphology and improving light absorption and solar cell performance.

[0081] It is understood that defoamers and surfactants can be conventional materials. For example, defoamers can include, but are not limited to, at least one of polyether defoamers, silicone defoamers, and polyether-modified silicone defoamers; surfactants can include, but are not limited to, at least one of fatty alcohol polyoxyethylene ethers, isomeric alcohol polyoxyethylene ethers, and acetylenic diol surfactants.

[0082] For example, the mass ratio of the second additive to the first alkaline solution is (0.15 to 0.2):100, such as 0.15:100, 0.16:100, 0.17:100, 0.18:100, 0.19:100, 0.20:100, etc. Thus, the second additive and the first alkaline solution synergistically etch, with a moderate dosage and no residue. This allows for the control of the etching rate, avoidance of over-etching, and no impact on the alkaline solution concentration, ensuring consistent texturing and surface cleanliness.

[0083] For example, a single texturing process satisfies at least one of the following conditions: the time is greater than or equal to 260 s and less than or equal to 300 s (e.g., 260 s, 270 s, 280 s, 290 s, 300 s, etc.); the temperature is greater than or equal to 80°C and less than or equal to 90°C (e.g., 80°C, 82°C, 84°C, 86°C, 88°C, 90°C, etc.). This ensures sufficient and uniform texturing, forming a suitable light-trapping structure; the temperature is moderate to avoid damaging the substrate; and the time is sufficient to avoid insufficient etching, thereby improving the texture quality and the photoelectric conversion efficiency of the solar cell.

[0084] In one embodiment, a second solution is used to perform a second texturing process on the semiconductor substrate after the first texturing process. The second solution includes a second alkaline solution and a third additive.

[0085] For example, the second alkaline solution includes at least one of sodium hydroxide and potassium hydroxide.

[0086] For example, the concentration of the second alkaline solution is less than the concentration of the first alkaline solution. For instance, the concentration of the second alkaline solution is greater than or equal to 0.1 wt% and less than or equal to 0.2 wt% (e.g., it can be 0.10 wt%, 0.12 wt%, 0.14 wt%, 0.16 wt%, 0.18 wt%, 0.20 wt%, etc.). For example, the third additive includes components having the following mass percentages: sodium benzoate 1.0% to 3.0% (e.g., 1.0%, 1.2%, 1.4%, 1.6%, 1.8%, 2.0%, 2.2%, 2.4%, 2.6%, 2.8%, 3.0%, etc.), sodium acetate 2.0% to 4.0% (e.g., 2.0%, 2.2%, 2.4%, 2.6%, 2.8%, 3.0%, 3.2%, 3.4%, 3.6%, 3.8%, 4.0%, etc.), defoamer 1.0% to 3.0% (e.g., 1.0%, 1.2%, 1.4%, 1.6%, 1.8%, 2.0%, 2.2%, 2.4%, 2.6%, 2.8%, 3.0%, etc.), surfactant 2.0% to 5.0% (e.g., 2.0%, 2.5%, 3.0%, 3.5%, 4.0%, 4.5%, 5.0%, etc.), and the balance being water. Therefore, by using a relatively low concentration of second alkaline solution combined with a third additive containing sodium benzoate, sodium acetate, defoamer, and surfactant, the textured surface can be finely finished in a single etching process, removing sharp peaks and valleys and defects, resulting in a more uniform and dense texture. The additive stabilizes the etching system, improves wettability, suppresses bubbles, prevents over-etching, optimizes light-trapping structures, and enhances the surface quality and photoelectric properties of the semiconductor substrate; ensuring that the included angle between the first side and the second side corresponding to the first vertex of the first protrusion is greater than or equal to 83°.

[0087] For example, the mass ratio of the third additive to the second alkaline solution is (0.2 to 0.3):100 (e.g., 0.20:100, 0.21:100, 0.22:100, 0.23:100, 0.24:100, 0.25:100, 0.26:100, 0.27:100, 0.28:100, 0.29:100, 0.30:100, etc.). Therefore, the appropriate amounts of the third additive and the second alkaline solution can effectively synergize with the low-concentration second alkaline solution to achieve gentle etching. This effectively controls the etching rate, ensures the uniformity of the secondary texturing, and prevents surface residue or impurities from being introduced due to excessive third additive. Simultaneously, it stabilizes the bath environment, reduces batch-to-batch fluctuations, and provides a consistent substrate for subsequent processes.

[0088] For example, the temperature of the secondary texturing process is lower than that of the primary texturing process, and / or the time of the secondary texturing process is shorter than that of the primary texturing process. Therefore, the secondary texturing process, using lower temperatures and shorter times, enables gentler and more precise etching, avoiding excessive damage to the light-trapping structure formed in the primary texturing process, effectively refining the textured surface morphology, and reducing surface reflectivity. Simultaneously, it reduces semiconductor substrate loss, controls the degree of reaction, and improves the uniformity of the textured surface and the photoelectric conversion efficiency of the solar cell.

[0089] For example, the secondary texturing process meets at least one of the following conditions: the time is greater than or equal to 90 s and less than or equal to 110 s (e.g., 90 s, 95 s, 100 s, 105 s, 110 s, etc.); the temperature is greater than or equal to 55℃ and less than or equal to 65℃ (e.g., 55℃, 57℃, 59℃, 61℃, 63℃, 65℃, etc.). This allows for precise surface finishing after the primary texturing, optimizing the textured surface morphology, without excessive etching that damages the structure. The moderate temperature avoids thermal damage, and the reasonable time ensures uniform finishing, effectively improving surface smoothness and light trapping effect, thereby increasing the yield and performance of solar cells.

[0090] In one embodiment, after texturing at least a portion of the surface of the semiconductor substrate to obtain a semiconductor substrate including a fifth textured structure, and before forming a first doped semiconductor layer on the surface of the fifth textured structure through doping, the process further includes: performing a second cleaning treatment on the semiconductor substrate. This effectively removes residual impurities, metal ions, and reaction byproducts from the surface of the fifth textured structure, preventing impurities from affecting doping uniformity. Simultaneously, it repairs minor surface damage caused by texturing, ensuring a clean and smooth semiconductor substrate surface, laying the foundation for the subsequent formation of a uniform and dense first doped semiconductor layer, and improving solar cell performance and yield.

[0091] For example, the second cleaning process includes a single alkaline wash and an acid wash on the semiconductor substrate.

[0092] For example, a third solution is used to perform alkaline cleaning on the semiconductor substrate; the third solution includes a third alkaline solution, a hydrogen peroxide solution, and a first additive. For example, the third alkaline solution includes at least one of sodium hydroxide and potassium hydroxide. For example, the mass ratio of the first additive to the third alkaline solution is (1.5 to 2):100 (e.g., 1.50:100, 1.55:100, 1.60:100, 1.65:100, 1.70:100, 1.75:100, 1.80:100, 1.85:100, 1.90:100, 1.95:100, 2.00:100, etc.). This allows the first additive to fully synergize with the third alkaline solution and hydrogen peroxide to exert a cleaning effect, enhancing the solution's wetting and chelating capabilities, and efficiently removing organic and metallic contaminants. A suitable proportion of the first additive stabilizes the cleaning system, slows down hydrogen peroxide decomposition, and avoids excessive residue, preventing the introduction of new impurities and ensuring the effectiveness of the alkaline cleaning and surface cleanliness.

[0093] For example, the concentration of the third alkaline solution is greater than or equal to 0.03 wt% and less than or equal to 0.04 wt% (e.g., 0.03 wt%, 0.032 wt%, 0.034 wt%, 0.036 wt%, 0.038 wt%, 0.04 wt%, etc.), and the concentration of the hydrogen peroxide solution is greater than or equal to 1.2 wt% and less than or equal to 1.3 wt% (e.g., 1.20 wt%, 1.22 wt%, 1.24 wt%, 1.26 wt%, 1.28 wt%, 1.30 wt%, etc.). Thus, the low-concentration alkaline solution combined with an appropriate amount of hydrogen peroxide can gently oxidize and decompose surface impurities without excessively etching and damaging the formed fifth textured surface structure. Hydrogen peroxide provides oxidative cleaning capabilities, while the third alkaline solution assists in removing particles and organic matter. The matching concentrations of the two ensure thorough cleaning while protecting the morphology of the fifth textured surface structure, thus improving the quality of subsequent doping.

[0094] For example, the alkaline washing satisfies at least one of the following conditions: the time is greater than or equal to 100 s and less than or equal to 120 s (e.g., it can be 100 s, 105 s, 110 s, 115 s, 120 s, etc.); the temperature is greater than or equal to 60°C and less than or equal to 70°C (e.g., it can be 60°C, 62°C, 64°C, 66°C, 68°C, 70°C, etc.).

[0095] For example, a fourth solution is used to acid-wash the alkaline-washed semiconductor substrate; the fourth solution includes an acid solution. For example, the acid solution includes hydrofluoric acid; the concentration of the acid solution is greater than or equal to 1.56 wt% and less than or equal to 1.61 wt% (e.g., it can be 1.56 wt%, 1.57 wt%, 1.58 wt%, 1.59 wt%, 1.60 wt%, 1.61 wt%, etc.). For example, the acid washing satisfies at least one of the following conditions: the time is greater than or equal to 100 s and less than or equal to 120 s (e.g., it can be 100 s, 105 s, 110 s, 115 s, 120 s, etc.); the temperature is greater than or equal to 25°C and less than or equal to 35°C (e.g., it can be 25°C, 27°C, 29°C, 31°C, 33°C, 35°C, etc.).

[0096] S200: A first doped semiconductor layer is formed on the surface of the fifth textured structure by doping, and the first textured structure and the fourth textured structure are obtained.

[0097] It should be noted that the first doped semiconductor layer is consistent with the previous description, and will not be elaborated on further here.

[0098] It can be understood that the first doped semiconductor layer formed on the surface of the fifth textured structure by doping is not a new film layer formed on top of the fifth textured structure, but a film layer formed by doping and penetrating into the semiconductor substrate.

[0099] For example, the first textured structure is located below the first doped semiconductor layer, and the fourth textured structure is located on the surface of the first doped semiconductor layer facing away from the semiconductor substrate. The first textured structure and the fourth textured structure are provided correspondingly.

[0100] It is understandable that the fifth velvet structure follows the same trend as the fourth velvet structure. The apex angle of the fifth velvet structure is equal to the angle between the fifth and sixth sides of the fourth velvet structure.

[0101] It is understandable that increasing the surface area of ​​the fifth textured structure will result in a lower surface concentration of the boron source per unit volume. Therefore, it is necessary to increase the ratio of the boron source gas flow rate to the total introduced gas flow rate. In one embodiment, when a first doped semiconductor layer is formed on the surface of the fifth textured structure by doping, the ratio of the boron source gas flow rate to the total introduced gas flow rate is greater than or equal to 2 × 10⁻⁶. 18 Atoms per cubic centimeter, and less than or equal to 2.7 × 10⁻⁶. 18 atoms per cubic centimeter, for example, could be 2 × 10⁻⁶. 18 Atoms per cubic centimeter, 2.1 × 10⁻⁶ 18 Atoms per cubic centimeter, 2.2 × 10⁻⁶ 18 Atoms per cubic centimeter, 2.3 × 10⁻⁶ 18Atoms per cubic centimeter, 2.4 × 10⁻⁶ 18 Atoms per cubic centimeter, 2.5 × 10⁻⁶ 18 Atoms per cubic centimeter, 2.6 × 10⁻⁶ 18 Atoms per cubic centimeter, 2.7 × 10⁻⁶ 18 Atoms per cubic centimeter, etc. Therefore, this doping concentration range can create a suitable doping gradient and carrier concentration within the semiconductor substrate, ensuring that the first doped semiconductor layer possesses good conductivity and field effects. Furthermore, the raised units in the fifth textured structure increase the surface area of ​​the fifth textured structure, and the ratio of boron source gas flow rate to total introduced gas flow rate within the aforementioned range can effectively complete the fabrication of the first doped semiconductor layer.

[0102] S300: An antireflection layer including a second textured structure is prepared on the side of the first doped semiconductor layer away from the semiconductor substrate. The second textured structure is located on the surface of the antireflection layer away from the semiconductor substrate.

[0103] It should be noted that the anti-reflective layer is consistent with the previous description, and will not be elaborated further here.

[0104] For example, the second textured structure is provided corresponding to the first textured structure; the second textured structure includes a plurality of first protrusions, each first protrusion including a first vertex, and the shape of the cross section of a first protrusion in a plane perpendicular to the semiconductor substrate and passing through the first vertex includes a first side and a second side intersecting at the first vertex, the included angle between the first side and the second side being greater than or equal to 83°.

[0105] Optionally, after forming a first doped semiconductor layer on the surface of the fifth textured structure by doping, and before preparing an antireflection layer including a second textured structure on the side of the first doped semiconductor layer away from the semiconductor substrate, the method further includes: preparing a first passivation layer on the side of the first doped semiconductor layer away from the semiconductor substrate.

[0106] For example, an atomic layer deposition (ALD) method is used to prepare a first passivation layer on the side of the first doped semiconductor layer facing away from the semiconductor substrate. For instance, the number of ALD cycles is greater than or equal to 38 and less than or equal to 42, such as 38, 39, 40, 41, or 42 cycles. This forms a first passivation layer with uniform thickness and high density, simultaneously constructing a regular second textured structure. A moderate number of ALD cycles achieves good surface passivation, reduces interface defect density and recombination rate, without affecting light transmission and contact performance due to excessive film thickness, thus improving the open-circuit voltage and fill factor of the solar cell and ensuring its performance and reliability. Furthermore, the raised units in the second textured structure increase its surface area. Within the aforementioned range, a uniform first passivation layer can be formed, almost completely covering the first doped semiconductor layer.

[0107] The third aspect of this disclosure provides a photovoltaic module, including the solar cell provided in the first aspect, or including a solar cell prepared by the preparation method provided in the second aspect.

[0108] It should be noted that, in addition to the aforementioned solar cells, photovoltaic modules may also include the structures that conventional photovoltaic cells should have, such as the casing and encapsulation structure, which will not be elaborated on further here.

[0109] The following embodiments and comparative examples further illustrate the present disclosure. It should be noted that the following embodiments and comparative examples are only used to explain the present disclosure and should not be construed as limiting the present disclosure.

[0110] Example 1 The method for manufacturing solar cells includes the following steps: 1. Chemically etch the silicon wafer to remove the damaged layer on the surface of the silicon.

[0111] The first additive and hydrogen peroxide solution were mixed at a mass ratio of 0.9:100. The silicon wafer was placed in the mixture and cleaned at 65°C for 260 seconds.

[0112] 2. The silicon wafers obtained in step 1 are subjected to a first alkaline wet texturing process and a second alkaline wet texturing process.

[0113] The second additive is mixed with NaOH solution (concentration of 0.42 wt%) at a mass ratio of 0.18:100. The silicon wafer obtained in step 1 is placed in the above mixture and reacted at 82°C for 280 seconds to complete one texturing process.

[0114] The third additive was mixed with NaOH solution (concentration of 0.15 wt%) at a mass ratio of 0.23:100. The product obtained from the first texturing process was placed in the above mixture and reacted at 60°C for 100 seconds to complete the second texturing process.

[0115] The first additive consists of: sodium carbonate 4.0%, sodium sulfate 3.0%, wetting agent 1.5%, stabilizer 2.0%, dispersant 1.5%, and the balance being water; the second additive consists of: potassium sorbate 2.0%, sodium acetate 4.0%, defoamer 7.0%, surfactant (hydroxypropyl methylcellulose) 10.0%, and the balance being water; the third additive consists of: sodium benzoate 3.0%, sodium acetate 4.0%, defoamer 3.0%, surfactant (fluorocarbon surfactant) 5.0%, and the balance being water.

[0116] 3. The first additive and an alkaline solution (containing 0.037 wt% NaOH and 1.278 wt% H2O2) are mixed at a mass ratio of 1.8:100. The silicon wafer after secondary texturing is placed in the above mixture and alkaline washed at 65°C for 110s. Then the silicon wafer is placed in an aqueous solution of 1.60 wt% HF and acid washed at 30°C for 110s to obtain a semiconductor substrate.

[0117] 4. Boron doping is performed on the side of the semiconductor substrate with the textured surface to form the first doped semiconductor layer.

[0118] 5. Perform alkaline polishing on the product from step 4 to remove the borosilicate glass layer and surface impurities generated during the boron diffusion process. At the same time, refine the second textured surface structure of the first doped semiconductor layer to optimize the surface morphology.

[0119] 6. Prepare a tunneling layer and a polycrystalline silicon layer on the surface of the semiconductor substrate away from the first doped semiconductor layer.

[0120] 7. An atomic layer deposition process is used to prepare a first passivation layer on the surface of the first doped semiconductor layer. The deposition precursor is an aluminum-containing or silicon-containing precursor. The deposition temperature is 250℃ and the number of cycles is 42. The first passivation layer has a second textured structure.

[0121] 8. Deposit a silicon nitride antireflection layer on the surface of the first passivation layer.

[0122] 9. Prepare a first metal electrode paste on the surface of the antireflection layer, and print a second metal electrode paste on the surface of the second passivation layer to obtain the first electrode and the second electrode.

[0123] In this embodiment, the scanning electron microscope image of the fifth textured surface structure obtained after the second texturing process is as follows: Figure 9 As shown, the scanning electron microscope image of the antireflection layer facing away from the semiconductor substrate surface is as follows. Figure 10 As shown.

[0124] Example 2 The preparation method of the solar cell is basically the same as in Example 1, except that the alkaline solution for the secondary wet texturing is a 0.11 wt% NaOH aqueous solution, and the mass ratio of the third additive to the NaOH aqueous solution is 0.16:100.

[0125] Example 3 The preparation method of the solar cell is basically the same as in Example 1, except that the temperature of the secondary wet texturing is 57°C, the alkaline solution is a 0.11wt% NaOH aqueous solution, and the mass ratio of the third additive to the NaOH aqueous solution is 0.19:100.

[0126] Example 4 The method for preparing solar cells is basically the same as in Example 1, except that the number of cycles in step 8 is 30.

[0127] Example 5 The method for preparing solar cells is basically the same as in Example 1, except that the number of cycles in step 8 is 50.

[0128] Comparative Example 1 The preparation method of the solar cell is basically the same as in Example 1, except that the third additive is replaced with 0.6 wt% of 2-phenylimidazoline, 0.6 wt% of 2-methyl-3-butyn-2-ol, 1.1 wt% of tannic acid and the balance water, and the mass ratio of the third additive to NaOH solution is 0.12:100, and the concentration of NaOH solution is 0.21 wt%.

[0129] In this comparative example solar cell, the scanning electron microscope image of the antireflection layer facing away from the semiconductor substrate is shown below. Figure 11 As shown.

[0130] Comparative Example 2 The preparation method of the solar cell is basically the same as in Example 1, except that a secondary wet texturing process is not performed.

[0131] Comparative Example 3 The preparation method of the solar cell is basically the same as in Example 1, except that the third additive is replaced with 0.6 wt% of 2-phenylimidazoline, 0.6 wt% of 2-methyl-3-butyn-2-ol, 1.1 wt% of tannic acid and the balance water, and the mass ratio of the third additive to NaOH solution is 0.1:100, and the concentration of NaOH solution is 0.38 wt%.

[0132] In the solar cells of Examples 1 to 5 and Comparative Examples 1 to 3, the apex angle of the fifth textured surface structure obtained by secondary texturing, the apex angle of the second textured surface structure in the antireflection layer, the reflectivity, short-circuit current, fill factor (FF), open-circuit voltage (Uoc), and photoelectric conversion efficiency of the solar cells are shown in Table 1 below: Table 1 It should be noted that the pyramid apex angles in Table 1 are range values. Taking the pyramid apex angle of the second velvet structure in Example 1, which is 83°-116°, as an example, the pyramid apex angles differ due to the non-uniform size of the pyramids in the second velvet structure. Therefore, the minimum pyramid apex angle of the second velvet structure is 83°, and the maximum is 116°. The pyramid apex angles of multiple pyramids fall between 83° and 116°. The pyramid apex angles of other embodiments and comparative examples are explained above and will not be elaborated further here.

[0133] As can be seen from the data of Examples 1 to 5, the apex angle of the second velvet structure is in the range of 83°-116°, and the apex angle of the fifth velvet structure (which is the same as the fourth velvet structure) is in the range of 59°-114°, which is more effective.

[0134] Data from Examples 1 to 5 and Comparative Examples 1 to 3 show that when the apex angle of the second textured structure is greater than 83°, the photoelectric conversion efficiency of the solar cell is relatively high.

[0135] As can be seen from the data of Example 1, Comparative Example 1, and Comparative Example 3, the mass ratio of the additives in the secondary texturing process, the third additive, and the NaOH solution, as well as the concentration of the NaOH solution, will affect the apex angle of the fifth texturing structure, which in turn will affect the apex angle of the second texturing structure, thereby affecting the short-circuit current, fill factor, open-circuit voltage, and photoelectric conversion efficiency of the solar cell.

[0136] As can be seen from the data of Example 1 and Comparative Example 2, not performing secondary texturing results in a smaller apex angle of the second texturing structure, which in turn leads to a higher reflectivity of the solar cell and lower short-circuit current, fill factor, open-circuit voltage, and photoelectric conversion efficiency.

[0137] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0138] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A solar cell, characterized in that, include: A semiconductor substrate, the semiconductor substrate including a first textured structure, the first textured structure being located on at least a portion of the surface of the semiconductor substrate; A first doped semiconductor layer is located on the side of the semiconductor substrate having the first textured surface structure; An antireflection layer is located on the side of the first doped semiconductor layer away from the semiconductor substrate. The antireflection layer includes a second textured structure located on the surface of the antireflection layer away from the semiconductor substrate. The second velvet structure is provided in correspondence with the first velvet structure; The second textured structure includes a plurality of first protrusions, each first protrusion including a first vertex. The shape of a cross section of a first protrusion in a plane perpendicular to the semiconductor substrate and passing through the first vertex includes a first side and a second side intersecting at the first vertex, the included angle between the first side and the second side being greater than or equal to 83°.

2. The solar cell according to claim 1, characterized in that, The angle between the first side and the second side is less than or equal to 116°.

3. The solar cell according to claim 1, characterized in that, The first side includes a first straight line portion, and the second side includes a second straight line portion, wherein the first straight line portion and the second straight line portion intersect at the first vertex; The angle between the first straight section and the second straight section is greater than or equal to 83°.

4. The solar cell according to claim 1, characterized in that, The first side includes a first straight section and a first curved section, the first straight section being connected to the second side through the first curved section; the first curved section protrudes in a direction away from the second side; The second side includes a second straight section and a second arc section, the second straight section being connected to the first side through the second arc section; the second arc section protrudes in a direction away from the first side; The angle between the extension of the first straight section and the extension of the second straight section is greater than or equal to 83°; Preferably, along the direction away from the first vertex, the distance from the first arc portion to the semiconductor substrate gradually decreases and the magnitude of the decrease gradually increases; and / or, the distance from the second arc portion to the semiconductor substrate gradually decreases and the magnitude of the decrease gradually increases.

5. The solar cell according to claim 3 or 4, characterized in that, The first protrusion includes a first pyramid structure body and at least one first protrusion unit, wherein the at least one first protrusion unit is located on the side wall of the first pyramid structure body; Preferably, the height of the first protruding unit protruding from the side wall of the first pyramid structure body is greater than or equal to 19 nm and less than or equal to 121 nm. Preferably, the first protruding unit surrounds the first pyramid structure body; Preferably, a plurality of the first protruding units are arranged at intervals along the extension direction of the sidewall of the first pyramid structure body; Preferably, the first protruding unit is located on the side of the first straight section near the bottom wall of the first pyramid structure body.

6. The solar cell according to claim 5, characterized in that, Along the extension direction of the sidewall of the first pyramid structure, the ratio of the length of the sidewall of the first pyramid structure between the two farthest first protruding units to the total length of the sidewall of the first pyramid structure is greater than or equal to 70%.

7. The solar cell according to claim 1, characterized in that, Also includes: A first passivation layer is located between the antireflection layer and the first doped semiconductor layer. The first passivation layer includes a third textured structure, which is located on the surface of the first passivation layer facing away from the semiconductor substrate. The third velvet structure is provided in correspondence with the second velvet structure; Preferably, the third textured structure includes a plurality of second protrusions, each second protrusion including a second vertex, and the shape of a cross section of one of the second protrusions in a plane perpendicular to the semiconductor substrate and passing through the second vertex includes a third side and a fourth side intersecting at the second vertex, wherein the included angle between the third side and the fourth side is less than or equal to the included angle between the first side and the second side. Preferably, the thickness of the first passivation layer is greater than or equal to 12 nm and less than or equal to 14 nm.

8. The solar cell according to claim 1, characterized in that, The first doped semiconductor layer includes a fourth textured structure, which is located on the surface of the first doped semiconductor layer opposite to the semiconductor substrate. The fourth textured structure includes a plurality of third protrusions, each third protrusion including a third vertex. The shape of a cross section of one of the third protrusions in a plane perpendicular to the semiconductor substrate and passing through the third vertex includes a fifth side and a sixth side intersecting at the third vertex. The angle between the fifth side and the sixth side is less than or equal to the angle between the first side and the second side. Preferably, the included angle between the fifth side and the sixth side is greater than or equal to 58° and less than or equal to 114°.

9. The solar cell according to claim 8, characterized in that, The third protrusion includes a second pyramid structure body and at least one second protrusion unit, wherein the at least one second protrusion unit is located on the side wall of the second pyramid structure body; Preferably, the height of the second protruding unit protruding from the side wall of the second pyramid structure body is greater than or equal to 13 nm and less than or equal to 68 nm. Preferably, the second protruding unit surrounds the main body of the second pyramid structure; Preferably, a plurality of the second protruding units are arranged at intervals along the extension direction of the sidewall of the second pyramid structure body; Preferably, the first protrusion includes a first pyramid structure body and at least one first protrusion unit, wherein the at least one first protrusion unit is located on the side wall of the first pyramid structure body, and one first protrusion unit is correspondingly arranged with one second protrusion unit.

10. The solar cell according to claim 1, characterized in that, The reflectivity of the antireflection layer after light shines on the side of the antireflection layer away from the semiconductor substrate is less than or equal to 7.5%.

11. A method for preparing a solar cell, characterized in that, include: At least a portion of the surface of a semiconductor substrate is texturized to obtain a semiconductor substrate including a fifth texturized structure; A first doped semiconductor layer is formed on the surface of the fifth textured structure by doping, thus obtaining the first textured structure and the fourth textured structure; An antireflection layer including a second textured structure is prepared on the side of the first doped semiconductor layer away from the semiconductor substrate, the second textured structure being located on the surface of the antireflection layer away from the semiconductor substrate; The second velvet structure is provided in correspondence with the first velvet structure; The second textured structure includes a plurality of first protrusions, each first protrusion including a first vertex. The shape of a cross section of a first protrusion in a plane perpendicular to the semiconductor substrate and passing through the first vertex includes a first side and a second side intersecting at the first vertex, the included angle between the first side and the second side being greater than or equal to 83°.

12. The preparation method according to claim 11, characterized in that, Before texturing at least a portion of the surface of the semiconductor substrate, the method further includes: The semiconductor substrate is subjected to a first cleaning treatment using a cleaning solution; the cleaning solution includes a hydrogen peroxide solution and a first additive. Preferably, the concentration of the hydrogen peroxide aqueous solution is greater than or equal to 0.5 wt% and less than or equal to 0.6 wt%. Preferably, the first additive comprises components having the following mass percentages: 3.0% to 4.0% sodium carbonate, 2.0% to 3.0% sodium sulfate, 1.0% to 1.5% wetting agent, 1.0% to 2.0% stabilizer, 1.0% to 1.5% dispersant, and the balance being water; Preferably, the mass ratio of the first additive to the hydrogen peroxide solution is (0.5 to 1.5): 100; Preferably, the cleaning process satisfies at least one of the following conditions: The time is greater than or equal to 240 s and less than or equal to 280 s; The temperature is greater than or equal to 60℃ and less than or equal to 70℃.

13. The preparation method according to claim 11 or 12, characterized in that, The texturing process on at least a portion of the surface of the semiconductor substrate includes: The semiconductor substrate is subjected to a first texturing process and a second texturing process in sequence; Preferably, the semiconductor substrate is subjected to the first texturing process using a first solution, wherein the first solution comprises a first alkaline solution and a second additive; Preferably, the first alkaline solution includes at least one of sodium hydroxide and potassium hydroxide; Preferably, the concentration of the first alkaline solution is greater than or equal to 0.4 wt% and less than or equal to 0.5 wt%. Preferably, the second additive comprises the following components in the indicated weight percentages: potassium sorbate 1.0% to 2.0%, sodium acetate 2.0% to 4.0%, defoamer 5.0% to 7.0%, surfactant 5.0% to 10.0%, and the balance being water; Preferably, the mass ratio of the second additive to the first alkaline solution is (0.15 to 0.2):100; Preferably, the primary flocking process satisfies at least one of the following conditions: The time is greater than or equal to 260 s and less than or equal to 300 s; The temperature is greater than or equal to 80℃ and less than or equal to 90℃.

14. The preparation method according to claim 13, characterized in that, The semiconductor substrate after the first texturing process is subjected to the second texturing process using a second solution, wherein the second solution comprises a second alkaline solution and a third additive. Preferably, the second alkaline solution comprises at least one of sodium hydroxide and potassium hydroxide; Preferably, the concentration of the second alkaline solution is less than the concentration of the first alkaline solution; Preferably, the concentration of the second alkaline solution is greater than or equal to 0.1 wt% and less than or equal to 0.2 wt%. Preferably, the third additive comprises components having the following mass percentages: sodium benzoate 1.0% to 3.0%, sodium acetate 2.0% to 4.0%, defoamer 1.0% to 3.0%, surfactant 2.0% to 5.0%, and the balance being water; Preferably, the mass ratio of the third additive to the second alkaline solution is (0.2 to 0.3):100; Preferably, the temperature of the secondary texturing process is lower than the temperature of the primary texturing process, and / or the time of the secondary texturing process is shorter than the time of the primary texturing process; Preferably, the secondary flocking process satisfies at least one of the following conditions: The time is greater than or equal to 90 seconds and less than or equal to 110 seconds; The temperature is greater than or equal to 55℃ and less than or equal to 65℃.

15. The preparation method according to claim 11, characterized in that, After texturing at least a portion of the surface of the semiconductor substrate to obtain a semiconductor substrate including a fifth textured structure, before forming a first doped semiconductor layer on the surface of the fifth textured structure by doping, the method further includes: The semiconductor substrate is subjected to a second cleaning process; Preferably, the second cleaning process includes performing an alkaline wash and an acid wash on the semiconductor substrate in one step; Preferably, the semiconductor substrate is subjected to alkaline washing using a third solution; the third solution comprises a third alkaline solution, a hydrogen peroxide solution, and a first additive. Preferably, the third alkaline solution comprises at least one of sodium hydroxide and potassium hydroxide; Preferably, the mass ratio of the first additive to the third alkaline solution is (1.5 to 2):100; Preferably, the concentration of the third alkaline solution is greater than or equal to 0.03 wt% and less than or equal to 0.04 wt%, and the concentration of the hydrogen peroxide solution is greater than or equal to 1.2 wt% and less than or equal to 1.3 wt%. Preferably, the alkaline washing satisfies at least one of the following conditions: The time is greater than or equal to 100 seconds and less than or equal to 120 seconds; The temperature is greater than or equal to 60℃ and less than or equal to 70℃; Preferably, the acid washing of the alkaline-washed semiconductor substrate is performed using a fourth solution; the fourth solution includes an acid solution. Preferably, the acid solution comprises hydrofluoric acid; Preferably, the concentration of the acid solution is greater than or equal to 1.56 wt% and less than or equal to 1.61 wt%. Preferably, the pickling satisfies at least one of the following conditions: The time is greater than or equal to 100 seconds and less than or equal to 120 seconds; The temperature is greater than or equal to 25℃ and less than or equal to 35℃.

16. The preparation method according to claim 11, characterized in that, When the first doped semiconductor layer is formed on the surface of the fifth textured structure by doping, the ratio of the boron source gas flow rate to the total introduced gas flow rate is greater than or equal to 2 × 10⁻⁶. 18 Atoms per cubic centimeter, and less than or equal to 2.7 × 10⁻⁶. 18 atoms per cubic centimeter; Preferably, after forming a first doped semiconductor layer on the surface of the fifth textured structure by doping, and before fabricating an antireflection layer including a second textured structure on the side of the first doped semiconductor layer facing away from the semiconductor substrate, the method further includes: A first passivation layer is prepared on the side of the first doped semiconductor layer that is away from the semiconductor substrate; Preferably, the first passivation layer is prepared on the side of the first doped semiconductor layer away from the semiconductor substrate using atomic layer deposition. Preferably, the number of atomic layer deposition cycles is greater than or equal to 38 and less than or equal to 42.

17. A photovoltaic module, characterized in that, It includes the solar cell according to any one of claims 1 to 10, or the solar cell prepared by the preparation method according to any one of claims 11 to 16.

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