Solar cell and composite passivation contact structure thereof

Abstract

The present application relates to the technical field of solar cells, and discloses a solar cell and a composite passivation contact structure thereof. The composite passivation contact structure comprises a contact region suitable for arranging an electrode structure and a non-contact region, the contact region comprises a plurality of groups of passivation contact units arranged in layers, and the passivation contact units comprise a passivation layer and a doped semiconductor layer. The number of passivation contact units in the contact region is greater than that in the non-contact region. The composite passivation contact structure disclosed in the present application is designed in a differentiated manner in terms of the number of films in the contact region and the non-contact region, so that the contact region has a greater number of passivation layers than the non-contact region. The multilayer passivation layer can effectively block the penetration of metal paste, and the synergistic effect of low parasitic absorption and high carrier transport efficiency is achieved.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically to a solar cell and its composite passivated contact structure. Background Technology

[0002] With the continuous development of photovoltaic technology, solar cells with tunneling passivation structures, such as TOPCon cells and TBC cells, have become one of the mainstream technologies for improving cell conversion efficiency due to their excellent passivation performance. However, in practical applications, these cells are always affected by the parasitic absorption effect of the polycrystalline silicon layer, which significantly reduces the short-circuit current of the cell, becoming a key bottleneck restricting further improvement in cell performance.

[0003] To address the problem of parasitic photoabsorption, related technologies commonly employ thinning of the polycrystalline silicon layer to reduce photoabsorption loss caused by parasitic absorption. However, this approach introduces new technical challenges. An excessively thin polycrystalline silicon layer is difficult to form an effective buffer barrier, and during subsequent fabrication, the metal paste can easily penetrate the tunneling passivation structure and directly contact the silicon substrate, thereby triggering severe carrier recombination and significantly degrading the passivation effect and electrical performance of the battery. Summary of the Invention

[0004] This invention provides a solar cell and its composite passivated contact structure to solve the problem that existing solar cells cannot simultaneously achieve low parasitic absorption and high carrier transport efficiency, and the photoelectric conversion efficiency is difficult to further improve.

[0005] In a first aspect, the present invention provides a composite passivation contact structure suitable for forming on a substrate layer of a solar cell, including a contact region and a non-contact region, wherein an electrode structure is suitable for being disposed on the contact region; the contact region includes multiple sets of passivation contact units stacked together, each passivation contact unit including a passivation layer and a doped semiconductor layer stacked together, wherein the passivation layer is disposed relatively close to the substrate layer; the number of passivation contact units in the contact region is greater than the number of passivation contact units in the non-contact region.

[0006] Beneficial effects: The composite passivated contact structure disclosed herein differentiates the number of film layers in the contact area and the non-contact area, resulting in a greater number of passivation layers in the contact area compared to the non-contact area. When metal paste is applied to the contact area to form an electrode structure, the multiple passivation layers can effectively block the penetration of the metal paste, thereby reducing carrier recombination and parasitic absorption. On the other hand, the non-contact area retains relatively few passivation layers, which has a smaller impact on the lateral transport of carriers, helping to ensure the carrier transport efficiency of the composite passivated contact structure and achieving a synergistic effect of low parasitic absorption and high carrier transport efficiency.

[0007] In one alternative embodiment, the passivation contact unit includes a tunneling layer and a doped polysilicon layer stacked together.

[0008] In one alternative embodiment, the material of the tunneling layer includes one or more of the following: silicon oxide layer, hydrogenated silicon oxide layer, silicon nitride layer, hydrogenated silicon nitride layer, aluminum oxide layer, silicon oxynitride layer, hydrogenated silicon oxynitride layer, silicon carbide layer, molybdenum oxide layer, chromium oxide layer, and thallium oxide layer.

[0009] Beneficial effects: Whether in the contact area or the non-contact area, the tunneling layer can be a single-layer film or a corresponding number of stacked films made of the above-mentioned different materials, which improves the structural diversity and adaptability. As long as it can block the metal paste and reduce carrier recombination, it is acceptable.

[0010] In one alternative embodiment, the stacked passivated contact units include at least an outermost doped semiconductor layer relatively far from the substrate layer and the remaining inner doped semiconductor layers, wherein the thickness of the outermost doped semiconductor layer is greater than the thickness of the inner doped semiconductor layers.

[0011] Beneficial effects: When the contact area or non-contact area has multiple doped semiconductor layers, the multiple doped semiconductor layers are divided into an outermost doped semiconductor layer and other inner doped semiconductor layers. The thickness of the outermost doped semiconductor layer is set to be greater than the thickness of any inner doped semiconductor layer. The outermost doped semiconductor layer has a larger thickness, which reduces the expansion of external doped atoms and metal atoms at the contact interface and effectively reduces carrier recombination.

[0012] In one alternative embodiment, the plurality of inner doped semiconductor layers include an innermost doped semiconductor layer disposed immediately adjacent to the substrate layer, or include an innermost doped semiconductor layer disposed immediately adjacent to the substrate layer and an intermediate doped semiconductor layer located between the innermost and outermost doped semiconductor layers. The thickness of the multiple inner doped semiconductor layers is equal; or, the thickness of the intermediate doped layers is equal and less than the thickness of the innermost doped semiconductor layer; or, in the direction from the surface of the substrate layer away from the substrate layer, the thickness of the multiple inner doped semiconductor layers increases or decreases sequentially.

[0013] Beneficial effects: When multiple inner doped semiconductor layers are present in the contact or non-contact regions, these layers can be differentiated and designed with varying thicknesses. Equal thickness of multiple inner doped semiconductor layers simplifies the fabrication process and improves film consistency. The thickness of the intermediate doped layers is equal and less than that of the innermost doped semiconductor layer. This ensures that both the outermost layer directly contacting the dopant source and the innermost layer closest to the substrate have greater thicknesses than the intermediate doped semiconductor layers, further optimizing the inward diffusion of doped elements. Furthermore, the thickness of the multiple inner doped semiconductor layers increases sequentially from the substrate surface outwards, allowing for uniform diffusion of doped elements across all layers, optimizing the doping concentration in each layer, and precisely controlling the diffusion effect.

[0014] In one alternative implementation, the thicknesses of the multiple passivation layers may be equal or unequal.

[0015] Beneficial effects: Regardless of whether it is the contact area or the non-contact area, the thickness of all passivation layers can be set to be equal, which helps to reduce the impact on the lateral transport of charge carriers and improve the uniformity of passivation layers in different areas of the battery; or they can be set to be unequal, so as to flexibly adjust the doping effect of each doped semiconductor layer to achieve better passivation performance.

[0016] In one alternative implementation, the width of the contact area is less than or equal to 2 / 3 of the total width of the contact area and the non-contact area, or the width of the contact area is greater than or equal to 1 / 10 of the total width of the contact area and the non-contact area; or the width of the contact area is 3 to 15 times the width of the electrode structure.

[0017] Beneficial effects: On the one hand, the proportion of the contact area in the overall width of the composite passivation contact structure is limited to less than or equal to 2 / 3 to avoid the influence of excessive width on the lateral transport of charge carriers. On the other hand, its width is limited to be greater than or equal to 1 / 10 of the total width of the contact area and the non-contact area, or between 3 and 15 times the width of the electrode structure to avoid the influence of excessive width on the printing of metal paste in the preparation of the electrode structure.

[0018] In one alternative implementation, the thickness of the contact area is greater than or equal to the thickness of the non-contact area; or, the thickness of the non-contact area is greater than or equal to 0 nm.

[0019] Beneficial effects: This not only helps to ensure good contact performance between the contact area and the metal electrode structure, but also ensures lateral carrier transport between the contact area and the non-contact area.

[0020] In one optional embodiment, the contact area includes a first passivation contact unit to an Nth passivation contact unit stacked together, and the non-contact area includes an Mth passivation contact unit, where N is a positive integer greater than or equal to 2, and M equals N+1; the first passivation contact unit includes a first passivation layer and a first doped semiconductor layer, the Nth passivation contact unit includes an Nth passivation layer and an Nth doped semiconductor layer, and the Mth passivation contact unit includes an Mth passivation layer and an Mth doped semiconductor layer; The Mth passivation layer has the same thickness as the first passivation layer and is integrally connected. The thickness of the Mth doped semiconductor layer is less than or equal to the total thickness of the first doped semiconductor layer to the Nth doped semiconductor layer.

[0021] Beneficial effects: The more passivation layers there are in the contact area, the stronger the ability to block the puncture of metal paste, and the more it helps to reduce the overall thickness of the doped semiconductor layer in the composite passivation contact structure, thereby reducing parasitic absorption. Therefore, the passivation contact units stacked in the contact area, or the passivation layers stacked in multiple layers, can effectively balance electrical and optical performance and improve the photoelectric conversion efficiency of the battery.

[0022] In one optional embodiment, the contact area includes stacked first passivation contact units to Nth passivation contact units, and the non-contact area includes Mth passivation contact units to Kth passivation contact units, where N is a positive integer greater than or equal to 2, M = N + 1, and K is a positive integer greater than M; the first passivation contact unit includes a first passivation layer and a first doped semiconductor layer, the Nth passivation contact unit includes an Nth passivation layer and an Nth doped semiconductor layer, the Mth passivation contact unit includes an Mth passivation layer and an Mth doped semiconductor layer, and the Kth passivation contact unit includes a Kth passivation layer and a Kth doped semiconductor layer; Passivation layers M to K are all integrally formed with the first to J passivation layers in their respective horizontally adjacent contact areas, where J = (KM) + 1; the thickness of the K-th doped semiconductor layer is less than or equal to the total thickness of the J-th to N-th doped semiconductor layers.

[0023] Beneficial effects: Stacked passivation contact units are set in both the contact and non-contact regions, which makes the doping concentration of the surface doped semiconductor layer much higher than that of the inner doped semiconductor layer. The higher doping concentration helps to increase the potential field strength, thereby improving the passivation effect. Moreover, the stacked structure can further control the further inward expansion of doped atoms into the substrate layer, thereby reducing carrier recombination and improving passivation performance, creating further room for improving power generation efficiency.

[0024] Secondly, this disclosure also provides a solar cell, comprising: a substrate layer, the substrate layer including a light-receiving surface and a back-lighting surface opposite to each other; a first passivation contact structure and a second passivation contact structure respectively disposed on the light-receiving surface and the back-lighting surface or alternately disposed on the back-lighting surface; at least one of the first passivation contact structure and the second passivation contact structure adopts the above-mentioned composite passivation contact structure; a first electrode and a second electrode are respectively connected to the first passivation contact structure and the second passivation contact structure. Attached Figure Description

[0025] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of a composite passivation contact structure according to an embodiment of the present invention; Figure 2 This is a schematic diagram of another composite passivation contact structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of another composite passivation contact structure according to an embodiment of the present invention; Figure 4 This is a schematic diagram of another composite passivation contact structure according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention; Figure 6 This is a schematic diagram of another solar cell structure according to an embodiment of the present invention; Figure 7 This is a schematic diagram of another type of solar cell according to an embodiment of the present invention.

[0027] Explanation of reference numerals in the attached figures: 10. Substrate layer; 101. Light-receiving surface; 102. Backlight-receiving surface; 20. Composite passivation contact structure; 201. First passivation contact structure; 202. Second passivation contact structure; 30. Electrode structure; 301. First electrode; 302. Second electrode; A. Contact area; B. Non-contact area; 1. First passivated contact unit; 11. First passivation layer; 12. First doped semiconductor layer; 2. Second passivated contact unit; 21. Second passivation layer; 22. Second doped semiconductor layer; 3. Third passivated contact unit; 31. Third passivation layer; 32. Third doped semiconductor layer; 4. Fourth passivated contact unit; 41. Fourth passivation layer; 42. Fourth doped semiconductor layer; 5. Fifth passivated contact unit; 51. Fifth passivation layer; 52. Fifth doped semiconductor layer; 6. Sixth passivated contact unit; 61. Sixth passivation layer; 62. Sixth doped semiconductor layer; 7. Passivation and antireflection layer; 71. Alumina layer; 72. Silicon nitride layer. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] To balance the excessively thin or thick polycrystalline silicon layers, a stacked tunneling passivation structure has been proposed in related technologies. By adding an additional tunneling layer to the tunneling passivation structure, further corrosion of the metal paste is blocked, allowing tunneling passivation solar cells to be adapted to thinner polycrystalline silicon layers. This reduces parasitic absorption while maintaining a high passivation effect. However, the tunneling layer is usually made of insulating or high-resistivity material, which significantly reduces the lateral transport capability of charge carriers and affects the fill factor of the cell, making it impossible to simultaneously meet the dual requirements of low parasitic absorption and high charge carrier transport efficiency.

[0030] Based on this, such as Figures 1 to 4 As shown, this disclosure provides a composite passivated contact structure 20, suitable for forming on the substrate layer 10 of a solar cell, including a contact region A and a non-contact region B. An electrode structure 30 is suitable for being disposed on the contact region A. The contact region A includes multiple sets of passivated contact units stacked together. Each passivated contact unit includes a passivation layer and a doped semiconductor layer stacked together, wherein the passivation layer is disposed relatively close to the substrate layer 10. The number of passivated contact units in the contact region A is greater than the number of passivated contact units in the non-contact region B.

[0031] Specifically, this disclosure divides the entire composite passivation contact structure 20 on a horizontal plane into a contact area A that is in direct contact with the electrode structure 30 and a non-contact area B that is not in direct contact with the electrode structure 30. The number of passivation contact units in the contact area A is greater than the number of passivation contact units in the non-contact area B. The number of passivation contact units in the non-contact area B is at least one, although it is possible that it is zero. Each passivation contact unit includes a passivation layer and a doped semiconductor layer stacked together. It is known that the passivation layer has the function of blocking metal elements from passing through and carrier recombination, but its thickness is negligible compared to the doped semiconductor layer and the overall passivation contact unit.

[0032] Therefore, the composite passivated contact structure 20 of this disclosure differentiates the number of film layers in the contact region A and the non-contact region B, resulting in a larger number of passivation layers in the contact region A compared to the non-contact region B. When the electrode structure 30 is disposed on the contact region A, the multiple passivation layers can effectively block the penetration of the metal paste, thereby reducing carrier recombination and parasitic absorption. On the other hand, the non-contact region B retains relatively few passivation layers, which has a smaller impact on the lateral transport of carriers, helping to ensure the carrier transport efficiency of the composite passivated contact structure 20. In other words, this disclosure achieves a synergistic effect of low parasitic absorption and high carrier transport efficiency by dividing the composite passivated contact structure 20 into regions and designing different numbers of passivation contact units in different regions, thereby achieving the high-efficiency passivation performance of the composite passivated contact unit. In this way, compared with conventional solutions that use a thicker doped semiconductor layer to reduce the risk of the metal paste of the electrode structure 30 penetrating the contact substrate 10 of the passivation contact structure, this disclosure has multiple passivation layers in the contact area A. Therefore, even if the thickness of the contact area A is relatively thin, the paste of the electrode structure 30 can be prevented from penetrating, thereby ensuring the passivation effect and contact performance of the composite passivation contact structure 20. In addition, a thinner contact area A means a thinner doped semiconductor layer thickness, which helps to reduce parasitic absorption and ensure optical performance.

[0033] In some embodiments, the thickness of the non-contact region B is greater than or equal to 0 nm and less than or equal to the thickness of the contact region A. For example, the thickness of the non-contact region B is 0.1 times, 0.3 times, 0.5 times, 0.7 times, or 0.9 times the thickness of the contact region A. This helps to ensure good contact performance between the contact region A and the metal electrode structure 30, and also ensures lateral carrier transport between the contact region A and the non-contact region B. Alternatively, the thickness of the non-contact region B is 0 nm, that is, in the surface of the substrate layer 10 used to set the composite passivated contact structure 20, a portion of the surface is provided with multiple stacked passivated contact units, while other areas can have relatively few passivated contact units, or no passivated contact units at all. This results in lower parasitic absorption on the battery surface and improves battery current gain. This scheme of not setting passivated contact units in the non-contact region B can be used for back contact batteries, such as... Figure 7 As shown.

[0034] In other embodiments, such as Figures 1 to 3 As shown, the thickness of the contact area A and the non-contact area B are equal, which helps to ensure the overall consistency of the structure and simplifies the manufacturing process.

[0035] In some alternative embodiments, such as Figure 1 and Figure 2 As shown, taking the contact area A and the non-contact area B as having approximately equal thicknesses, and the non-contact area B having one passivation contact unit, while the contact area A has two or more passivation contact units as an example. The contact area A includes stacked first passivation contact units 1 to Nth passivation contact units, and the non-contact area B includes the Mth passivation contact unit, where N is a positive integer greater than or equal to 2, and M equals N+1; the first passivation contact unit 1 includes a first passivation layer 11 and a first doped semiconductor layer 12, the Nth passivation contact unit includes an Nth passivation layer and an Nth doped semiconductor layer, and the Mth passivation contact unit includes an Mth passivation layer and an Mth doped semiconductor layer.

[0036] In some embodiments, the Mth passivation layer and the first passivation layer 11 have the same thickness and are integrally connected, and the thickness of the Mth doped semiconductor layer is less than or equal to the total thickness of the first doped semiconductor layer 12 to the Nth doped semiconductor layer.

[0037] Exemplarily, in some alternative implementations, such as Figure 1 As shown, contact area A includes a first passivation contact unit 1 and a second passivation contact unit 2 stacked together, and non-contact area B includes a third passivation contact unit 3, that is, N is 2 and M is 3. The first passivation contact unit 1 includes a first passivation layer 11 and a first doped semiconductor layer 12 stacked together, the second passivation contact unit 2 includes a second passivation layer 21 and a second doped semiconductor layer 22 stacked together, and the third passivation contact unit 3 includes a third passivation layer 31 and a third doped semiconductor layer 32 stacked together; at this time, the thickness of the third passivation contact unit 3 is less than or equal to the total thickness of the first passivation contact unit 1 and the second passivation contact unit 2. Based on this, in order to simplify the preparation steps and enhance the overall consistency of the composite passivation contact structure 20, the first passivation layer 11 of the first passivation contact unit 1 and the third passivation layer 31 of the third passivation contact unit 3 are integrally formed. The two are formed simultaneously in the same step and have the same material composition, thickness and other parameters, only located in different regions. At this time, the total thickness of the first doped semiconductor layer 12, the second passivation layer 21 and the second doped semiconductor layer 22 is greater than or equal to the thickness of the third doped semiconductor layer 32. In other words, since the thickness of the passivation layer is extremely small and can be ignored in the thickness of the overall structure, it can also be understood that the total thickness of the first doped semiconductor layer 12 and the second doped semiconductor layer 22 is greater than or equal to the thickness of the third doped semiconductor layer 32.

[0038] In other alternative implementations, such as Figure 2 As shown, the passivation contact unit in contact area A can be further configured as two or more, such as including a first passivation contact unit 1, a second passivation contact unit 2, and a third passivation contact unit 3 stacked together, while the non-contact area B includes a fourth passivation contact unit 4. In this case, N is 3 and M is 4. The first passivation contact unit 1 includes a first passivation layer 11 and a first doped semiconductor layer 12 stacked together; the second passivation contact unit 2 includes a second passivation layer 21 and a second doped semiconductor layer 22 stacked together; the third passivation contact unit 3 includes a third passivation layer 31 and a third doped semiconductor layer 32 stacked together; and the fourth passivation contact unit 4 includes a fourth passivation layer 41 and a fourth doped semiconductor layer 42 stacked together. In this case, the thickness of the fourth passivation contact unit 4 is less than or equal to the total thickness of the first passivation contact unit 1, the second passivation contact unit 2, and the third passivation contact unit 3. Similarly, based on this, in order to simplify the preparation steps and enhance the overall consistency of the composite passivation contact structure 20, the first passivation layer 11 of the first passivation contact unit 1 and the fourth passivation layer 41 of the fourth passivation contact unit 4 are integrally formed. The two are formed simultaneously in the same step and have the same material composition, thickness and other parameters, only located in different regions. At this time, the total thickness of the first doped semiconductor layer 12, the second passivation layer 21, the second doped semiconductor layer 22, the third passivation layer 31 and the third doped semiconductor layer 32 is greater than or equal to the thickness of the fourth doped semiconductor layer 42. In other words, since the thickness of the passivation layer is extremely small and can be ignored in the thickness of the overall structure, it can also be understood that the total thickness of the first doped semiconductor layer 12, the second doped semiconductor layer 22 and the third doped semiconductor layer 32 is greater than or equal to the thickness of the fourth doped semiconductor layer 42.

[0039] As shown above, the more passivation layers there are in contact region A, the stronger the ability to block the puncture of metal paste, and the more it helps to reduce the overall thickness of the doped semiconductor layer in the composite passivation contact structure 20, thereby reducing parasitic absorption. Therefore, the passivation contact units stacked in contact region A, or the multi-layered passivation layers, can effectively balance electrical and optical performance and improve the photoelectric conversion efficiency of the battery.

[0040] In some other alternative embodiments, such as Figure 3As shown, when the contact area A has two or more passivated contact units, the non-contact area B can also have two or more passivated contact units. Specifically, the contact area A includes stacked first passivated contact units 1 to Nth passivated contact units, and the non-contact area B includes Mth passivated contact units to Kth passivated contact units, where N is a positive integer greater than or equal to 2, M = N + 1, and K is a positive integer greater than M; the first passivated contact unit 1 includes a first passivation layer 11 and a first doped semiconductor layer 12, the Nth passivated contact unit includes an Nth passivation layer and an Nth doped semiconductor layer, the Mth passivated contact unit includes an Mth passivation layer and an Mth doped semiconductor layer, and the Kth passivated contact unit includes a Kth passivation layer and a Kth doped semiconductor layer.

[0041] Among them, the Mth passivation layer to the Kth passivation layer are all integrally formed with the first passivation layer 11 to the Jth passivation layer of their respective horizontally adjacent contact areas A, and J = (KM) + 1; the thickness of the Kth doped semiconductor layer is less than or equal to the total thickness of the Jth doped semiconductor layer to the Nth doped semiconductor layer.

[0042] For example, such as Figure 3 As shown, the passivation contact unit in the contact area A is set to 4, namely the first passivation contact unit 1, the second passivation contact unit 2, the third passivation contact unit 3 and the fourth passivation contact unit 4 stacked together. The non-contact area B includes two passivation contact units, namely the fifth passivation contact unit 5 and the sixth passivation contact unit 6 stacked together. At this time, N is 4, M is 5, K is 6 and J is 2. The first passivation contact unit 1 includes a first passivation layer 11 and a first doped semiconductor layer 12 stacked together; the second passivation contact unit 2 includes a second passivation layer 21 and a second doped semiconductor layer 22 stacked together; the third passivation contact unit 3 includes a third passivation layer 31 and a third doped semiconductor layer 32 stacked together; the fourth passivation contact unit 4 includes a fourth passivation layer 41 and a fourth doped semiconductor layer 42 stacked together; the fifth passivation contact unit 5 includes a fifth passivation layer 51 and a fifth doped semiconductor layer 52 stacked together; and the sixth passivation contact unit 6 includes a sixth passivation layer 61 and a sixth doped semiconductor layer 62 stacked together. At this time, the sum of the thicknesses of the fifth passivation contact unit 5 and the sixth passivation contact unit 6 is equal to the sum of the thicknesses of the first passivation contact unit 1, the second passivation contact unit 2, the third passivation contact unit 3, and the fourth passivation contact unit 4.

[0043] Based on this, to further simplify the preparation steps and enhance the overall consistency of the composite passivated contact structure 20, taking the film layer of the non-contact region B as a reference, all other film layers except the outermost doped semiconductor layer are uniformly laid out, partly forming the film layer composition of the non-contact region B and partly forming the film layer composition of the contact region A, for example, using... Figure 3For example, the fifth passivation layer 51, the fifth passivation layer 52, and the sixth passivation layer 61 (excluding the sixth doped semiconductor layer 62) are all laid out on the entire surface and integrally connected with the corresponding film layers of the contact area A on the horizontal plane. That is, the fifth passivation layer 51 of the fifth passivation contact unit 5 is integrally formed with the first passivation layer 11 of the first passivation contact unit 1, the fifth doped semiconductor layer 52 of the fifth passivation contact unit 5 is integrally formed with the first doped semiconductor layer 12 of the first passivation contact unit 1, and the sixth passivation layer 61 of the sixth passivation contact unit 6 is integrally formed with the second passivation layer 21 of the second passivation contact unit 2. In the molding process, the integrally molded film layers are formed simultaneously in the same step, having the same material composition, thickness and other parameters. At this time, the total thickness of the second doped semiconductor layer 22, the third passivation layer 31, the third doped semiconductor layer 32, the fourth passivation layer 41 and the fourth doped semiconductor layer 42 is greater than or equal to the thickness of the sixth doped semiconductor layer 62. In other words, since the thickness of the passivation layer is extremely small and can be ignored in the overall structure thickness, it can also be understood that the total thickness of the second doped semiconductor layer 22, the third doped semiconductor layer 32 and the fourth doped semiconductor layer 42 is greater than or equal to the thickness of the sixth doped semiconductor layer 62.

[0044] Both the contact region A and the non-contact region B are provided with a stacked structure, so that the doping concentration of the surface doped semiconductor layer is much higher than that of the inner doped semiconductor layer. The higher doping concentration helps to increase the potential field strength, thereby improving the passivation effect. Moreover, the stacked structure can also further control the further inward expansion of doped atoms into the substrate layer 10, thereby reducing carrier recombination and improving passivation performance, creating further room for improving power generation efficiency.

[0045] Of course, in some embodiments, the integrally formed structural layers described above can also be fabricated separately, and the structural parameters of the structural layers can be flexibly adjusted, such as... Figure 4 As shown. For example, in some embodiments, the Mth passivation layer and the first passivation layer 11 are not integrally formed, and the thicknesses of the Mth passivation layer and the first passivation layer 11 are different. In other embodiments, the Mth passivation layer and the first passivation layer 11 are not integrally formed, and the total thickness of the Mth doped semiconductor layer to the Kth doped semiconductor layer is less than or equal to the total thickness of the first doped semiconductor layer 12 to the Nth doped semiconductor layer.

[0046] In some embodiments, the passivation contact unit includes a tunneling layer and a doped polycrystalline silicon layer stacked together. That is, the passivation contact unit is a TOPCon type passivation contact film layer, wherein the passivation layer is a tunneling layer and the doped semiconductor layer is a doped polycrystalline silicon layer. Of course, in other embodiments, the passivation contact unit can also be selected from passivation contact film layers of other battery types, such as the intrinsic amorphous silicon layer and doped amorphous silicon layer of a HIT battery.

[0047] Furthermore, in some embodiments, the material of the tunneling layer includes one or more of the following: silicon oxide layer, hydrogenated silicon oxide layer, silicon nitride layer 72, hydrogenated silicon nitride layer 72, aluminum oxide layer 71, silicon oxynitride layer, hydrogenated silicon oxynitride layer, silicon carbide layer, molybdenum oxide layer, chromium oxide layer, and thallium oxide layer.

[0048] In other words, whether in the contact area A or the non-contact area B, the tunneling layer can be a single-layer film or a corresponding number of stacked films made of different materials, which improves the structural diversity and adaptability. As long as it can block the metal paste and reduce carrier recombination, it is acceptable.

[0049] In some embodiments, when the contact area A or the non-contact area B includes a plurality of passivated contact units stacked together, that is, a plurality of doped semiconductor layers, the plurality of doped semiconductor layers include at least the outermost doped semiconductor layer that is relatively far from the substrate layer 10 and the remaining inner doped semiconductor layers, and the thickness of the outermost doped semiconductor layer is greater than the thickness of the inner doped semiconductor layers.

[0050] That is, when the contact area A or the non-contact area B has multiple doped semiconductor layers, the multiple doped semiconductor layers are divided into an outermost doped semiconductor layer and other inner doped semiconductor layers. The thickness of the outermost doped semiconductor layer is set to be greater than the thickness of any inner doped semiconductor layer. The outermost doped semiconductor layer has a larger thickness, which reduces the expansion of external doped atoms and metal atoms at the contact interface and effectively reduces carrier recombination.

[0051] For example, in Figure 1 When the contact area A shown includes a first doped semiconductor layer 12 and a second doped semiconductor layer 22, the second doped semiconductor layer 22 is the outermost doped semiconductor layer, and the first doped semiconductor layer 12 is the innermost doped semiconductor layer. In this case, the thickness of the second doped semiconductor layer 22 is greater than the thickness of the first doped semiconductor layer 12, wherein the thickness of the first doped semiconductor layer 12 ranges from 20 to 50 nm, and the thickness of the second doped semiconductor layer 22 ranges from 40 to 120 nm. Figure 2 When the contact area A shown includes a first doped semiconductor layer 12, a second doped semiconductor layer 22, and a third doped semiconductor layer 32, the third doped semiconductor layer 32 is the outermost doped semiconductor layer, and the second doped semiconductor layer 22 and the first doped semiconductor layer 12 are the inner doped semiconductor layers. In this case, the thickness of the third doped semiconductor layer 32 is greater than the thickness of the first doped semiconductor layer 12 and the second doped semiconductor layer 22. The relative thickness of the first doped semiconductor layer 12 and the second doped semiconductor layer 22 is not limited; for example, the thickness of the first doped semiconductor layer 12 can range from 20 to 50 nm, the thickness of the second doped semiconductor layer 22 from 20 to 40 nm, and the thickness of the third doped semiconductor layer 32 from 40 to 120 nm. Figure 3When the contact area A shown includes a first doped semiconductor layer 12, a second doped semiconductor layer 22, a third doped semiconductor layer 32, and a fourth doped semiconductor layer 42, the fourth doped semiconductor layer 42 is the outermost doped semiconductor layer, and the third doped semiconductor layer 32, the second doped semiconductor layer 22, and the first doped semiconductor layer 12 are inner doped semiconductor layers. In this case, the thickness of the fourth doped semiconductor layer 42 is greater than the thickness of the first doped semiconductor layer 12, the second doped semiconductor layer 22, and the third doped semiconductor layer 32. The relative thickness of the first doped semiconductor layer 12, the second doped semiconductor layer 22, and the third doped semiconductor layer 32 is not limited. For example, the thickness range of the first doped semiconductor layer 12 is 20~50nm, the thickness range of the second doped semiconductor layer 22 and the third doped semiconductor layer 32 is 20~40nm, and the thickness range of the fourth doped semiconductor layer 42 is 40~120nm. Similarly, in the fifth doped semiconductor layer 52 and the sixth doped semiconductor layer 62 of the non-contact area B, the thickness of the sixth doped semiconductor layer 62 is greater than the thickness of the fifth doped semiconductor layer 52.

[0052] In some embodiments, the plurality of inner doped semiconductor layers may include the innermost doped semiconductor layer disposed immediately adjacent to the substrate layer 10, or may include the innermost doped semiconductor layer disposed immediately adjacent to the substrate layer 10 and an intermediate doped semiconductor layer located between the innermost and outermost doped semiconductor layers.

[0053] That is, when there are multiple inner doped semiconductor layers in the contact area A or the non-contact area B, the inner doped semiconductor layers can be distinguished and different thicknesses can be designed accordingly.

[0054] In some alternative embodiments, the thickness of the plurality of inner doped semiconductor layers is equal, simplifying the fabrication process and resulting in better passivation consistency among the layers. For example... Figure 2 The first doped semiconductor layer 12 and the second doped semiconductor layer 22 shown in the diagram have equal thicknesses; for example... Figure 3 The first doped semiconductor layer 12, the second doped semiconductor layer 22, and the third doped semiconductor layer 32 in the contact area A shown have the same thickness.

[0055] In some alternative implementations, the thickness of the intermediate doped layers is equal to and less than the thickness of the innermost doped semiconductor layer. This ensures that both the outermost layer directly contacting the dopant source and the innermost layer closest to the substrate 10 have a greater thickness than the intermediate doped semiconductor layer, further optimizing the inward expansion of the doped elements. For example... Figure 2 The thickness of the second doped semiconductor layer 22 is less than the thickness of the first doped semiconductor layer 12; or... Figure 3 The thicknesses of the second doped semiconductor layer 22 and the third doped semiconductor layer are equal and less than the thickness of the first doped semiconductor layer 12.

[0056] In some alternative embodiments, the thickness of the multiple inner doped semiconductor layers increases or decreases sequentially in the direction away from the surface of the substrate 10. This gradient thickness of the multiple inner doped layers allows the dopant element to propagate uniformly in each doped semiconductor layer, optimizes the doping concentration of each layer, and precisely controls the diffusion effect. When the thickness of the multiple inner doped semiconductor layers increases from the inside out, the passivation contact unit has better passivation and contact performance; when the thickness of the multiple inner doped semiconductor layers decreases from the inside out, it helps to improve the lateral transport performance of charge carriers after tunneling into the doped semiconductor layer.

[0057] for example Figure 2 The thickness of the second doped semiconductor layer 22 is greater than the thickness of the first doped semiconductor layer 12. In this case, the thicknesses of the first doped semiconductor layer 12, the second doped semiconductor layer 22, and the third doped semiconductor layer 32 form a gradually increasing gradient; or... Figure 3 In the first doped semiconductor layer 12, the second doped semiconductor layer 22, and the third doped semiconductor layer, the thickness increases sequentially. At this point, the thicknesses of the first doped semiconductor layer 12, the second doped semiconductor layer 22, the third doped semiconductor layer 32, and the fourth doped semiconductor layer 42 form a gradually increasing gradient. For example... Figure 2 The thickness of the second doped semiconductor layer 22 can also be less than the thickness of the first doped semiconductor layer 12; or... Figure 3 The thicknesses of the first doped semiconductor layer 12, the second doped semiconductor layer 22, and the third doped semiconductor layer decrease sequentially.

[0058] In some embodiments, the thickness of the plurality of passivation layers is equal, ranging from 1 to 3 nm. That is, regardless of whether it is contact region A or non-contact region B, all passivation layers are set to the same thickness, which helps to reduce the impact on lateral carrier transport and improve the uniformity of passivation layers in different regions of the battery. In other embodiments, the different passivation layers can have different thicknesses, thereby flexibly adjusting the doping effect of each doped semiconductor layer to achieve better passivation performance. In other embodiments, the thickness of the innermost passivation layer in contact region A and / or non-contact region B is greater than the thickness of the other passivation layers.

[0059] In some embodiments, the width of the contact area A is less than or equal to 2 / 3 of the total width of the contact area A and the non-contact area B, and the width of the contact area A is less than or equal to 1 / 10 of the total width of the contact area A and the non-contact area B. For example, the width of the contact area A is 0.2 times, 0.3 times, 0.4 times, 0.5 times, or 0.6 times the total width of the contact area A and the non-contact area B. In some embodiments, the width of the contact area A is 3 to 15 times the width of the electrode structure 30, for example, 5 times, 7 times, 9 times, 11 times, or 13 times.

[0060] In some embodiments, such as Figures 1 to 3 As shown, a passivation antireflection layer 7 is also provided on the outer surface of the multiple passivation contact units that is relatively far away from the substrate layer 10. The passivation antireflection layer 7 can be an aluminum oxide layer 71, a silicon nitride layer 72, or a stacked structure of an aluminum oxide layer 71 and a silicon nitride layer 72.

[0061] That is, on the one hand, the proportion of the contact area A in the overall width of the composite passivation contact structure 20 is limited to less than or equal to 2 / 3 to avoid the influence of excessive width on the lateral transport of charge carriers. On the other hand, its width is limited to between 3 and 15 times the width of the electrode structure 30 to avoid the printing of metal paste in the preparation of the electrode structure 30 being too small.

[0062] Based on the above, the composite passivated contact structure 20, which forms a localized design with differentiated contact area A and non-contact area B, can be formed by laser patterning local oxidation, photolithography patterning and local thermal oxidation, or ink patterning and local thermal oxidation.

[0063] Taking an example where the thickness of contact region A and non-contact region B are approximately equal, and contact region A includes two passivation contact units while non-contact region B includes one passivation contact unit, the passivation layer is a tunneling layer, and the doped semiconductor layer is a doped polysilicon layer: In an alternative embodiment, the process of forming the composite passivated contact structure 20 by laser patterned local oxidation is more stable, and specifically includes the following steps: S1, on the polished silicon wafer (i.e., the substrate layer 10) with a 5-35 μm tower base structure formed by wet polishing, firstly, an initial passivation layer is prepared on the entire surface by low-pressure chemical vapor deposition (LPCVD). The specific process conditions are: oxygen flow rate 30000 sccm, process temperature 600℃, process time 1900s, and the thickness of the initial passivation layer is 1.5 nm. Then, after the furnace tube is evacuated, polycrystalline silicon is deposited on the entire surface to prepare the first initial semiconductor layer. The specific process conditions are: silane flow rate 1200 sccm, process temperature 610℃, process time 800s, and the thickness of the first initial semiconductor layer is 40 nm. The portion of the initial passivation layer and the first initial semiconductor layer located in the contact area A forms the first passivation layer 11 and the first intrinsic semiconductor layer, and the remaining portion located in the non-contact area B is used to form the third passivation layer 31 and a third intrinsic semiconductor layer of a certain thickness. S2, a second passivation layer 21 is prepared on the first intrinsic semiconductor layer in a local area, i.e., contact area A, using laser oxidation. The specific process conditions are: laser wavelength 355 nm, pulse width 30 ns, laser power 3W, pulse frequency 100kHz, spot size 10μm, and inter-row overlap 10%, forming a second passivation layer 21 with a thickness of 1.5nm located only in contact area A. S3, the second initial semiconductor layer is prepared by LPCVD process. The specific process conditions are: silane flow rate 1200 sccm, process temperature 610℃, process time 1200s, and the thickness of the second initial semiconductor layer is 60nm. The part of the second initial semiconductor layer located in the contact region A forms the second intrinsic semiconductor layer, and the remaining part located in the non-contact region B is used to form a third intrinsic semiconductor layer of another thickness. S4. Using a tube diffusion furnace, the crystallization and diffusion processes of the first intrinsic semiconductor layer, the second intrinsic semiconductor layer, and the third intrinsic semiconductor layer are completed to obtain the first doped semiconductor layer 12, the second doped semiconductor layer 22, and the third doped semiconductor layer 32, thereby preparing a locally stacked composite passivated contact structure 20. The specific process conditions are: the diffusion temperature is controlled at 935℃, the diffusion time is 600s, the boron source gas flow rate is 160sccm, and the O2 flow rate is 600sccm.

[0064] In another alternative embodiment, the passivation layer in the composite passivation contact structure 20 formed by ink patterning and localized thermal oxidation exhibits superior performance, specifically including the following steps: S1, on the polished silicon wafer (base layer 10) with a 15-25 μm tower base structure formed by wet polishing, an initial passivation layer is first prepared by plasma-enhanced chemical vapor deposition (PECVD). Specific process conditions are: nitrous oxide (N2O) flow rate of 12000 sccm, gas pressure of 1800 mtorr, process temperature of 450℃, deposition power of 10000 W, RF on / off ratio of 2 ms:180 ms, deposition time of 105 s, and initial passivation layer thickness of 1.5 nm. Then, the first initial doped semiconductor layer is prepared by PECVD. Specific process conditions are as follows... The components are as follows: the reaction gases are SiH4, H2, PH3 and CH4, the flow rate ratio is 4800sccm:10000sccm:350sccm:350sccm, the gas pressure is 3600mtorr, the process temperature is 450℃, the deposition power is 5000W, the RF on / off ratio is 3ms:50ms, the deposition time is 210s, the thickness of the first initial doped semiconductor layer is 30nm, the portion of the first initial doped semiconductor layer located in the contact region A forms the first doped semiconductor layer 12, and the remaining portion located in the non-contact region B is used to form a third doped semiconductor layer 32 of a certain thickness; S2, the non-contact area B is physically isolated using an ink coating process. The specific process conditions are as follows: first, ink is printed on the non-contact area B and cured at 300℃ for 15 seconds under a nitrogen inert atmosphere; then, a second passivation layer 21 is prepared in the contact area A using chain oxidation. The specific process is as follows: conveyor belt speed 3m / min, oxidation temperature 600℃, oxygen flow rate 30L / min, oxidation time 100s, and the thickness of the second passivation layer 21 is 1.5nm; the ink is removed by chain cleaning. The specific process is as follows: roller drive speed 6m / s, spray solution is a mixed solution of H2O2 and NaOH, both with a concentration of 2%. S3, a second initial doped semiconductor layer is prepared by PECVD process. The specific process conditions are as follows: the reaction gases are SiH4, H2, PH3 and CH4, the flow rate ratio is 4800 sccm:10000 sccm:350 sccm:350 sccm, the gas pressure is 3600 mtorr, the process temperature is 450℃, the deposition power is 5000 W, the RF on / off ratio is 3 ms:50 ms, the deposition time is 210 s, and the thickness of the second initial doped semiconductor layer is 30 nm. The portion of the second initial doped semiconductor layer located in the contact region A forms the second doped semiconductor layer 22, and the remaining portion located in the non-contact region B is used to form a third doped semiconductor layer 32 of another thickness. S4. Polycrystalline silicon is crystallized through chain annealing to obtain a first doped semiconductor layer 12, a second doped semiconductor layer 22 and a third doped semiconductor layer 32, thereby preparing a locally stacked composite passivated contact structure 20. The specific process conditions are: conveyor belt speed 3m / min, annealing atmosphere: pure N2 (99.999%), flow rate 30 L / min, annealing temperature 910℃, and annealing time 120s.

[0065] It is known that steps S2 and S3 above can be repeated to prepare more sets of passivated contact units in contact region A.

[0066] In some embodiments, taking the thickness of contact region A as greater than the thickness of non-contact region B, and contact region A including two passivation contact units, non-contact region B including one passivation contact unit, passivation layer as a tunneling layer, and doped semiconductor layer as a doped polysilicon layer as an example, the preparation method for forming the above-mentioned composite passivation contact structure 20 specifically includes the following steps: S1, on the polished silicon wafer (base layer 10) with a 5-35 μm tower base structure formed by wet polishing, firstly, a first initial passivation layer is prepared across the entire surface using low-pressure chemical vapor deposition (LPCVD). The specific process conditions are: oxygen flow rate 30000 sccm, process temperature 600℃, process time 1900 s, and the thickness of the first initial passivation layer is 1.5 nm. Then, after vacuuming the furnace tube, a first initial semiconductor layer is prepared by polycrystalline silicon deposition across the entire surface. The specific process conditions are: silane flow rate 1200 sccm, process temperature 610℃, and process time 800 s. The initial semiconductor layer has a thickness of 40 nm. Then, after evacuating the furnace tube, a second initial passivation layer is prepared on the entire surface using low-pressure chemical vapor deposition (LPCVD). The specific process conditions are: oxygen flow rate 30000 sccm, process temperature 600℃, and process time 1200 s. The thickness of the second initial passivation layer is 1.2 nm. Then, after evacuating the furnace tube, a second initial semiconductor layer is prepared by polycrystalline silicon deposition on the entire surface. The specific process conditions are: silane flow rate 1200 sccm, process temperature 610℃, and process time 1600 s. The thickness of the second initial semiconductor layer is 80 nm. S2, using a tube diffusion furnace, the crystallization and diffusion processes of the first and second initial semiconductor layers are completed to obtain the first and second initial doped semiconductor layers. The specific process conditions are: the diffusion temperature is controlled at 935℃, the diffusion time is 600s, the boron source gas flow rate is 160sccm, and the O2 flow rate is 600sccm. The diffusion process forms a doped oxide layer on the shallow surface of the second initial doped semiconductor layer. S3 uses an ultraviolet picosecond laser to pattern the surface of the silicon wafer. The processing area is the non-contact region B, in order to remove the doped oxide layer on the shallow surface of the non-contact region B. The specific process is as follows: laser power 54%, spot size 50×50um, and spot overlap rate 50%. S4. Use a tank-type alkaline polishing cleaning method to chemically polish the non-contact area B until the base layer is cleaned, that is, remove the part of each passivation contact unit in the non-contact area B, thereby forming the first passivation contact unit 1 and the second passivation contact unit 2 located in the contact area A. The specific process is as follows: in a 500L alkaline polishing tank, the alkaline concentration is 2.5%, the alkaline polishing additive is 3L, and the cleaning time is 120s. S5. The third initial passivation layer is prepared on the entire surface using low-pressure chemical vapor deposition (LPCVD). The specific process conditions are: oxygen flow rate 30000 sccm, process temperature 600℃, process time 1900s, and the thickness of the third initial passivation layer is 1.5nm. Then, after vacuuming the furnace tube, polycrystalline silicon is deposited on the entire surface to prepare the third initial semiconductor layer. The specific process conditions are: silane flow rate 1200 sccm, process temperature 610℃, process time 2000s, and the thickness of the third initial semiconductor layer is 100nm. S6. Using a tube diffusion furnace, the crystallization and diffusion processes of the third initial semiconductor layer are completed to obtain the third initial doped semiconductor layer. The specific process conditions are: the diffusion temperature is controlled at 935℃, the diffusion time is 600s, the boron source gas flow rate is 160sccm, and the O2 flow rate is 600sccm. Similarly, a doped oxide layer is formed on the shallow surface of the third initial doped semiconductor layer. S7 uses an ultraviolet picosecond laser to pattern the surface of a silicon wafer, with the treatment area being contact region A, removing the doped oxide layer on the surface of contact region A; the specific process is as follows: laser power 54%, spot size 50×50um, and spot overlap rate 50%; S8, using a tank-type alkaline cleaning method, chemical cleaning is performed on contact area A until the doped oxide layer on the surface of the second doped semiconductor layer is removed. Specifically, the process involves using a 500L alkaline polishing tank with an alkaline concentration of 2.5% for 50 seconds. Finally, a tank-type acid cleaning method is used to remove the doped oxide layer on the surfaces of contact area A and non-contact area B, resulting in contact area A with a first passivated contact unit 1 and a second passivated contact unit 2, and non-contact area B with a third passivated contact unit 3. In this embodiment, the outermost doped semiconductor layer of non-contact area B can be flexibly processed to achieve different height settings for contact area A and non-contact area B.

[0067] like Figure 5 and Figure 6 As shown, this disclosure also provides a solar cell, including: a substrate layer 10, a first passivation contact structure 201 and a second passivation contact structure 202, and a first electrode 301 and a second electrode 302. The substrate layer 10 includes a light-receiving surface 101 and a backlighting surface 102 facing each other. The first passivation contact structure 201 and the second passivation contact structure 202 are respectively disposed on the light-receiving surface 101 and the backlighting surface 102 or alternately disposed on the backlighting surface 102. At least one of the first passivation contact structure 201 and the second passivation contact structure 202 adopts the above-mentioned composite passivation contact structure 20. The first electrode 301 and the second electrode 302 are respectively connected to the first passivation contact structure 201 and the second passivation contact structure 202.

[0068] like Figure 5As shown, in one embodiment, the solar cell is a TOPCon cell. The first passivation contact structure 201 and the second passivation contact structure 202 are respectively disposed on the light-receiving surface 101 and the backlight surface 102. The first passivation contact structure 201 disposed on the light-receiving surface 101 is an emitter layer. The second passivation contact structure 202 disposed on the backlight surface 102 adopts the above-mentioned composite passivation contact structure 20. The composite passivation contact structure 20 on the backlight surface 102 can be configured as multiple spaced apart from each other. The first electrode 301 is disposed on the first passivation contact structure 201 on one side of the light-receiving surface 101, and the second electrode 302 is disposed on the second passivation contact structure 202 on the backlight surface 102. The first electrode 301 and the second electrode 302 are adapted to pass through the passivation antireflection layer 7 and be electrically connected to the passivation contact structure.

[0069] like Figure 6 As shown, in one embodiment, the solar cell is a back contact cell. The first passivation contact structure 201 and the second passivation contact structure 202 are alternately arranged on the backlight surface 102. Both the first passivation contact structure 201 and the second passivation contact structure 202 can adopt the above-mentioned composite passivation contact structure 20. The first electrode 301 is disposed on the first passivation contact structure 201, and the second electrode 302 is disposed on the second passivation contact structure 202. The first electrode 301 and the second electrode 302 are adapted to pass through the passivation antireflection layer 7 and be electrically connected to the passivation contact structure.

[0070] Further functional descriptions of the above structures are the same as those of the corresponding embodiments described above, and will not be repeated here.

[0071] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A composite passivated contact structure suitable for formation on the substrate layer of a solar cell, characterized in that, include: The system includes a contact area and a non-contact area, wherein the contact area is adapted to have an electrode structure disposed thereon; the contact area includes multiple sets of passivation contact units stacked together, each of the passivation contact units including a passivation layer and a doped semiconductor layer stacked together, wherein the passivation layer is disposed relatively close to the substrate layer; the number of passivation contact units in the contact area is greater than the number of passivation contact units in the non-contact area.

2. The composite passivated contact structure according to claim 1, characterized in that, The passivated contact unit includes a tunneling layer and a doped polysilicon layer stacked together.

3. The composite passivated contact structure according to claim 2, characterized in that, The material of the tunneling layer includes one or more of the following: silicon oxide layer, hydrogenated silicon oxide layer, silicon nitride layer, hydrogenated silicon nitride layer, aluminum oxide layer, silicon oxynitride layer, hydrogenated silicon oxynitride layer, silicon carbide layer, molybdenum oxide layer, chromium oxide layer, and thallium oxide layer.

4. The composite passivated contact structure according to claim 1, characterized in that, The stacked passivated contact units include at least an outermost doped semiconductor layer that is relatively far from the substrate layer and the remaining inner doped semiconductor layers, wherein the thickness of the outermost doped semiconductor layer is greater than the thickness of the inner doped semiconductor layers.

5. The composite passivated contact structure according to claim 4, characterized in that, The plurality of inner doped semiconductor layers include an innermost doped semiconductor layer disposed immediately adjacent to the substrate layer, or include an innermost doped semiconductor layer disposed immediately adjacent to the substrate layer and an intermediate doped semiconductor layer located between the innermost doped semiconductor layer and the outermost doped semiconductor layer; The thickness of the plurality of inner doped semiconductor layers is equal; or, the thickness of the intermediate doped layers is equal and less than the thickness of the innermost doped semiconductor layer; or, in a direction from the surface of the substrate layer away from the substrate layer, the thickness of the plurality of inner doped semiconductor layers increases or decreases sequentially.

6. The composite passivated contact structure according to claim 1, characterized in that, The thicknesses of the multiple passivation layers may be equal or unequal.

7. The composite passivated contact structure according to claim 1, characterized in that, The width of the contact area is less than or equal to 2 / 3 of the total width of the contact area and the non-contact area; Alternatively, the width of the contact area is greater than or equal to 1 / 10 of the total width of the contact area and the non-contact area; Alternatively, the width of the contact area is 3 to 15 times the width of the electrode structure.

8. The composite passivated contact structure according to claim 1, characterized in that, The thickness of the contact area is greater than or equal to the thickness of the non-contact area; Alternatively, the thickness of the non-contact area is greater than or equal to 0 nm.

9. The composite passivated contact structure according to any one of claims 1-8, characterized in that, The contact area includes a first passivated contact unit to the Nth passivated contact unit stacked together, and the non-contact area includes the Mth passivated contact unit, where N is a positive integer greater than or equal to 2, and M equals N+1; The first passivation contact unit includes a first passivation layer and a first doped semiconductor layer, the Nth passivation contact unit includes an Nth passivation layer and an Nth doped semiconductor layer, and the Mth passivation contact unit includes an Mth passivation layer and an Mth doped semiconductor layer; The Mth passivation layer has the same thickness as the first passivation layer and is integrally formed. The thickness of the Mth doped semiconductor layer is less than or equal to the total thickness from the first doped semiconductor layer to the Nth doped semiconductor layer.

10. The composite passivated contact structure according to any one of claims 1-8, characterized in that, The contact area includes stacked first passivation contact units to Nth passivation contact units, and the non-contact area includes Mth passivation contact units to Kth passivation contact units, where N is a positive integer greater than or equal to 2, M = N + 1, and K is a positive integer greater than M; the first passivation contact unit includes a first passivation layer and a first doped semiconductor layer, the Nth passivation contact unit includes an Nth passivation layer and an Nth doped semiconductor layer, the Mth passivation contact unit includes an Mth passivation layer and an Mth doped semiconductor layer, and the Kth passivation contact unit includes a Kth passivation layer and a Kth doped semiconductor layer; The Mth passivation layer to the Kth passivation layer are all integrally formed with the first passivation layer to the Jth passivation layer of their respective horizontally adjacent contact areas, where J = (KM) + 1; the thickness of the Kth doped semiconductor layer is less than or equal to the total thickness of the Jth doped semiconductor layer to the Nth doped semiconductor layer.

11. A solar cell, characterized in that, include: A substrate layer, the substrate layer comprising an opposing light-receiving surface and a backlighting surface; The first passivation contact structure and the second passivation contact structure are respectively disposed on the light-receiving surface and the backlight surface, or are alternately disposed on the backlight surface; at least one of the first passivation contact structure and the second passivation contact structure adopts the composite passivation contact structure according to any one of claims 1-10. The first electrode and the second electrode are respectively connected to the first passivation contact structure and the second passivation contact structure.

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