Pixel unit of back emission micro LED and preparation method

Abstract

The present application belongs to the technical field of semiconductor light emitting devices, and discloses a pixel unit of back emission Micro LED and a preparation method thereof, so as to solve the problems of low light extraction efficiency and serious light crosstalk between pixels in the prior art. The pixel unit is provided with a spacer layer isolated by a side wall, and the outer surface thereof is in an arc-shaped structure. The metal reflection layer comprises a planar reflection layer and a side reflection layer, the side reflection layer conformally covers the arc-shaped outer surface of the spacer layer, and is connected with the planar reflection layer to form a three-dimensional surrounding reflection structure. Through the synergistic effect of the three-dimensional surrounding reflection structure and the arc-shaped spacer layer, omnidirectional reflection of the leaked photons is realized, the light extraction efficiency is greatly improved, and the light crosstalk between adjacent pixels is effectively suppressed. The present application is mainly used for high-resolution Micro LED display devices.

Description

Technical Field

[0001] This invention belongs to the technical field of semiconductor light-emitting devices, and in particular to a pixel unit of a back-emitting Micro LED and its fabrication method. Background Technology

[0002] Micro LEDs, as a next-generation display technology, have shown broad application prospects in micro-displays, automotive displays, and high-end displays due to their outstanding advantages such as ultra-high brightness, ultra-high contrast, long lifespan, low power consumption, and fast response. Among them, rear-emitting Micro LEDs have become one of the core structural choices for high-end Micro LED display devices because their light emission direction and electrode layout do not interfere with each other, effectively avoiding light loss caused by electrode shading in front-emitting structures.

[0003] In back-emitting Micro LEDs, the reflector is a crucial component determining the Light Extraction Efficiency (LEE). Its core function is to efficiently reflect photons leaking from the multi-quantum-well (MQW) active layer into the chip (non-emitting side) and to the back-emitting surface, reducing photon absorption losses within the chip and suppressing crosstalk between adjacent pixels, thus improving display contrast. LEE directly determines the brightness, power consumption, and display effect of the back-emitting Micro LED. Research shows that the effective reflective area of ​​the reflector is one of the core factors affecting LEE; a larger reflective area results in stronger capture and reflection of leaked photons, higher LEE, and superior luminous performance of the device.

[0004] Therefore, for the commercialization of Micro LED ultra-high-definition displays, it is crucial to develop a reflective mirror structure with a larger effective reflective area to ensure that Micro LEDs have higher light extraction efficiency.

[0005] In existing back-emitting Micro LED technology, the core area of ​​the reflector structure is usually limited to the region corresponding to the MQW (Multi-Level Wave) light-emitting layer of a single pixel unit, forming a planar metal reflector by depositing a single layer of metal material. To recover photons leaking into the corners of the pixel gaps, existing technologies often fill the trenches between adjacent pixel units with AuSn bump metal as a supplementary reflective structure.

[0006] Since the reflectivity of the p-electrode directly affects the light extraction efficiency, the industry generally uses silver (Ag) as the core material for both the mirror and the p-electrode to achieve high-power, high-efficiency LED performance, leveraging its high reflectivity in the visible light band to improve photon extraction efficiency. However, the existing mirror structure using a planar silver mirror supplemented with an Au-based bump has significant shortcomings: on the one hand, Au material has very low reflectivity in the blue light band (e.g., ...). Figure 2 As shown in the diagram, the leakage photons in the gap region cannot be efficiently recovered; on the other hand, the sharp corner structure of the trench corners easily causes photon scattering and absorption, further aggravating light loss. This results in a large number of photons being dissipated in the trench, which not only fails to effectively improve the overall light extraction efficiency, but also reduces the display contrast between adjacent pixels due to crosstalk photons in the gap region, severely restricting the brightness and image quality performance of the device. Summary of the Invention

[0007] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0008] To address this, the present invention proposes a pixel unit and fabrication method for a back-emitting Micro LED. A three-dimensional surround reflective structure is formed by connecting a planar reflective layer and a side reflective layer. The side reflective layer conformally covers the surface of the arc-shaped Spacer layer on the sidewall of the pixel to effectively increase the reflective area, improve the light extraction efficiency, and suppress light crosstalk between adjacent pixels.

[0009] A pixel unit for a back-emitting Micro LED according to an embodiment of the present invention includes a pixel unit body; the pixel unit body is provided with a sidewall isolation spacer layer, the sidewall isolation spacer layer is located on the sidewall of the pixel unit body, and the outer surface of the sidewall isolation spacer layer is an arc-shaped structure; the pixel unit body is also provided with a metal reflective layer, the metal reflective layer includes a planar reflective layer and a side reflective layer, the planar reflective layer is located on the top of the pixel unit body, the side reflective layer conformally covers the arc-shaped outer surface of the sidewall isolation spacer layer, and the planar reflective layer and the side reflective layer are connected to form a three-dimensional surround reflective structure.

[0010] According to one embodiment of the present invention, the material of the metal reflective layer is silver.

[0011] According to one embodiment of the present invention, the material of the sidewall isolation spacer layer is silicon dioxide.

[0012] According to one embodiment of the present invention, the radius of curvature of the arc-shaped structure is 50-100 nm, and the sidewall inclination angle is 70°-80°.

[0013] According to one embodiment of the present invention, the pixel unit body further includes a transparent conductive layer, which is made of indium tin oxide.

[0014] According to one embodiment of the present invention, the pixel unit body further includes an epitaxial stack, which sequentially includes an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer along the direction away from the substrate.

[0015] According to one embodiment of the present invention, the pixel unit body further includes a first insulating layer, a second insulating layer, a third insulating layer, an n-contact metal layer, and a p-contact metal layer; a first groove is provided on both sides of the pixel unit body, and a sidewall isolation spacer layer, a first insulating layer, a metal reflective layer, and a second insulating layer are sequentially provided on the sidewall of the first groove from the inside to the outside; an n-contact metal layer is provided in the first groove and contacts the n-type semiconductor layer; a second groove is provided in the middle of the pixel unit body, and the second groove extends downward through the third insulating layer, the second insulating layer, and the first insulating layer; a p-contact metal layer is provided in the second groove and contacts the transparent conductive layer; the first insulating layer is disposed between the transparent conductive layer and the metal reflective layer, the second insulating layer is disposed between the metal reflective layer and the n-contact metal layer, and the third insulating layer covers the second insulating layer.

[0016] The present invention also provides a method for fabricating a pixel unit, comprising the following steps: S1. Provide a substrate, and grow an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer sequentially on the substrate using MOCVD process to obtain an epitaxial stack; deposit a transparent conductive layer on the side of the epitaxial stack away from the substrate using magnetron sputtering. S2. Deposit a SiO2 hard mask layer on the surface of the transparent conductive layer, form a pattern by photolithography and transfer it to the SiO2 hard mask layer; use inductively coupled plasma etching process to etch the transparent conductive layer, p-type semiconductor layer and light-emitting layer until the n-type semiconductor layer is exposed to form a trench; then remove the SiO2 hard mask layer and photoresist residue. S3. SiO2 thin films are deposited in the trench and on the surface of the transparent conductive layer using plasma-enhanced chemical vapor deposition. SiO2 on the surface of the transparent conductive layer and the bottom of the trench is removed by a combination of isotropic wet etching and dry etching, while SiO2 on the sidewall of the trench is retained and formed into a sidewall isolation spacer layer with an arc-shaped outer surface. S4. A first insulating layer is deposited on the surface of the structure obtained in step S3. After defining the reflective layer pattern by photolithography, a metal reflective layer is sputtered and deposited so that the metal reflective layer conformally covers the surface of the first insulating layer above the edge region of the transparent conductive layer and the surface of the first insulating layer on the arc-shaped outer surface of the sidewall isolation spacer layer. There is no metal reflective layer in the middle region of the transparent conductive layer and the bottom region of the trench, forming a connected planar reflective layer and a side reflective layer. S5. Deposit the second insulating layer and etch the second insulating layer until the n-type semiconductor layer is exposed at the bottom of the trench, forming an n-contact via; S6. Deposit an n-contact metal layer, so that the n-contact metal layer contacts the n-type semiconductor layer in the n-contact via and extends upward along the trench sidewall; S7. Deposit the third insulating layer, etch the third insulating layer, the second insulating layer and the first insulating layer until the transparent conductive layer is exposed to form a p-contact via; S8. Deposit the p-contact metal layer so that the p-contact metal layer contacts the transparent conductive layer within the p-contact via; then etch the third insulating layer to expose the n-contact metal layer.

[0017] According to one embodiment of the present invention, in step S2, the etching gas of the inductively coupled plasma etching process is a mixed gas containing Ar, Cl2 and BCl3, the radio frequency power is 250-350W, the gas pressure is 10-20Pa, and the etching temperature is 25-30℃.

[0018] According to one embodiment of the present invention, in step S3, the thickness of the deposited SiO2 film is 100-200 nm; after step S3 and before step S4, an annealing step is further included: under a nitrogen atmosphere, the temperature is raised to 400-450°C at a heating rate of 3-8°C / min and held for 30-60 min.

[0019] The beneficial effects of this invention are as follows: the integrated three-dimensional surround-type reflective structure formed by connecting the planar reflective layer and the side reflective layer, along with the arc-shaped sidewall Spacer layer, increases the effective reflective area and reduces photon scattering caused by sharp corners of the sidewalls, allowing photons generated by the light-emitting layer to be reflected to the light-emitting surface more efficiently; the side reflective layer surrounds the pixel sidewall to form a closed-loop blocking structure, which can effectively absorb and block photons leaked from adjacent pixels; the arc-shaped silicon dioxide Spacer layer located on the sidewall is annealed, which can effectively reduce the interface trap density and fixed charge density on the sidewall surface, suppress non-radiative recombination of charge carriers at the sidewall, and further improve the internal quantum efficiency and luminous stability of the device; the preparation method of this application is entirely based on the standard process of existing MicroLED production lines, requiring no additional special equipment, with strong process compatibility, facilitating large-scale production. Attached Figure Description

[0020] Figure 1 This is a flowchart of the pixel unit fabrication method for the back-emitting Micro LED of the present invention; Figure 2 It is a reflectance curve of commonly used metals in the wavelength range of 200 to 2000 nanometers; Figure 3 This is a schematic diagram of the process flow of the present invention. Figure 1 ; Figure 4 This is a schematic diagram of the process flow of the present invention. Figure 2 ; Figure 5 This is a schematic diagram of the process flow of the present invention. Figure 3 ; Figure 6 This is a schematic diagram of the process flow of the present invention. Figure 4 ; Figure 7 This is a schematic diagram of the process flow of the present invention. Figure 5 ; Figure 8 This is a schematic diagram of the process flow of the present invention. Figure 6 ; Figure 9 This is a schematic diagram of the process flow of the present invention. Figure 7 ; Figure 10 This is a schematic diagram of the process flow of the present invention. Figure 8 . Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example 1: This embodiment provides a pixel unit for back-emitting Micro LEDs, including a pixel unit body. The pixel unit body has a sidewall isolation spacer layer and a metal reflective layer. The sidewall isolation spacer layer is located on the sidewall of the pixel unit body, and the outer surface of the sidewall isolation spacer layer has an arc-shaped structure, which is used to improve the deposition uniformity of the side reflective layer, while optimizing the photon reflection path and improving the reflection effect. The sidewall isolation spacer layer covers the sidewall of the pixel unit (i.e., the trench sidewall between adjacent pixel units), which is used to achieve electrical isolation between the metal reflective layer and the epitaxial layer, and at the same time can reduce the interface trap density and fixed charge density of the pixel unit sidewall. The metal reflective layer includes a planar reflective layer and a side reflective layer. The planar reflective layer is located on the top of the pixel unit body, and the side reflective layer conformally covers the arc-shaped outer surface of the sidewall isolation spacer layer. The planar reflective layer and the side reflective layer are connected to form a three-dimensional surround reflective structure. Specifically, the planar reflective layer is disposed on the side of the epitaxial layer away from the light-emitting layer, and the side reflective layer surrounds the sidewall of the pixel unit to isolate the outer surface of the Spacer layer to form a closed-loop structure. The planar reflective layer and the side reflective layer constitute a three-dimensional surrounding reflective structure, which is used to reflect the photons leaked from the light-emitting layer to the light-emitting surface in all directions.

[0023] Example 2: This embodiment provides a pixel unit for a back-emitting Micro LED, including a pixel unit body. The pixel unit body has a substrate as its bottom, the substrate being a sapphire substrate, and an epitaxial stack and a transparent conductive layer are sequentially disposed along a direction away from the substrate. The epitaxial stack includes an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer sequentially disposed from bottom to top. The light-emitting layer has a multiple quantum well (MQW) structure, and the well layer and barrier layer are made of group III nitride materials.

[0024] The pixel unit body has symmetrically arranged first grooves on both sides. The first grooves penetrate downwards through the transparent conductive layer, the p-type semiconductor layer, and the light-emitting layer, and extend into the n-type semiconductor layer. The sidewalls of the first grooves are arranged sequentially from the inside to the outside as a sidewall isolation spacer layer, a first insulating layer, a metal reflective layer, and a second insulating layer. The outer surface of the sidewall isolation spacer layer has an arc-shaped structure.

[0025] A U-shaped n-contact metal layer is provided in the first groove, and the bottom of the n-contact metal layer contacts the n-type semiconductor layer at the bottom of the first groove. The n-contact metal layer covers the side of the second insulating layer away from the sidewall of the first groove in the sidewall region of the first groove, and extends upward along the sidewall of the first groove to the top of the pixel unit body.

[0026] A second groove is provided in the middle of the pixel unit body. The second groove extends downward through the third insulating layer, the second insulating layer, and the first insulating layer, and the bottom of the second groove exposes a transparent conductive layer. A p-contact metal layer is provided inside the second groove, and the p-contact metal layer is in direct contact with the transparent conductive layer at the bottom of the second groove.

[0027] Above the edge region of the transparent conductive layer, from bottom to top, a first insulating layer, a metal reflective layer, a second insulating layer, and a third insulating layer are sequentially disposed. Above the middle region of the transparent conductive layer, from bottom to top, a first insulating layer, a second insulating layer, and a third insulating layer are sequentially disposed.

[0028] The insulating layer structure consists of a sidewall isolation spacer layer, a first insulating layer, a second insulating layer, and a third insulating layer; the electrode structure consists of an n-contact metal layer and a p-contact metal layer; and the metal reflective layer, the insulating layer structure, and the electrode structure are arranged in a staggered manner to achieve coordinated adaptation between electrical isolation and photon reflection.

[0029] The first insulating layer is used to achieve electrical isolation between the n-type semiconductor layer and the p-type semiconductor layer; the second insulating layer is used to achieve electrical isolation between the side reflective layer and the n-contact metal layer; the n-contact metal layer and the n-type semiconductor layer form an ohmic contact; the third insulating layer is used to achieve electrical isolation between the n-contact metal layer and the p-contact metal layer; the p-contact metal layer and the p-type semiconductor layer form an ohmic contact; the planar reflective layer and the p-contact metal layer are staggered to avoid short circuits between them and to ensure that the entire area of ​​the planar reflective layer can serve as an effective reflective area.

[0030] The material of the metal reflective layer is silver (Ag), the material of the sidewall isolation spacer layer is silicon dioxide (SiO2), the radius of curvature of the arc structure is 50-100nm, the sidewall tilt angle is 70°-80°, the material of the transparent conductive layer is indium tin oxide (ITO), the n-type semiconductor layer is n-GaN, the light-emitting layer is MQW, the p-type semiconductor layer is p-GaN, the material of the n-contact metal layer is Ti-based metal including but not limited to Ti / Al / Ti / Au multilayer composite structure, and the material of the p-contact metal layer is Ni-based metal including but not limited to Ni / Au bilayer composite structure.

[0031] Example 3: The difference between this embodiment and Embodiment 2 is as follows: In addition to sapphire, substrate materials can also be silicon or silicon-on-insulator.

[0032] In addition to indium tin oxide, the transparent conductive layer can also be selected from at least one of aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), graphene, or metal nanowires.

[0033] In addition to the multi-quantum-well (MQW) structure, the light-emitting layer can also adopt at least one of the single-quantum-well structure, quantum wire structure, or quantum dot structure.

[0034] The doping ions in the n-type semiconductor layer can be Si 4+ 、Ge 4+ Sn 4+ Se 4+ Or Te 4+ At least one of them.

[0035] The doping ions in the p-type semiconductor layer can be Mg 2+ Zn 2+ Ca 2+ 、Sr 2+ Or Ba 2+ At least one of them.

[0036] Besides silver, aluminum can also be used as a material for the metal reflective layer.

[0037] In addition to silicon dioxide, silicon nitride (SiNx) can also be used as the material for the sidewall isolation spacer layer, the first insulating layer, the second insulating layer and the third insulating layer.

[0038] Furthermore, the planar reflective layer and the p-contact metal layer are staggered to prevent them from contacting each other and thus ensure that the entire area of ​​the planar reflective layer can serve as an effective reflective area.

[0039] Example 4: See Figure 1This embodiment provides a method for fabricating a back-emitting Micro LED pixel unit, including the following steps: S1. Epitaxial growth and deposition of transparent conductive layer: like Figure 3 As shown, a substrate with a c-plane sapphire substrate is provided. An epitaxial stack is grown on the substrate using MOCVD technology, namely, an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer are grown sequentially to form a complete epitaxial stack. Specifically, the growth temperature is controlled at 700-1100℃, and trimethylgallium (TMGa), trimethylindium (TMIn), and ammonia (NH3) are used as precursors. First, a 2μm thick Si-doped n-type GaN layer (n-GaN) is grown; then, a multiple quantum well (MQW) light-emitting layer is grown, which consists of 5 InGaN / GaN quantum wells with a total thickness of 70nm; finally, a 70nm thick Mg-doped p-type GaN layer (p-GaN) is grown. Subsequently, a 20nm thick transparent conductive layer (ITO) is deposited on the surface of the p-type semiconductor layer using magnetron sputtering.

[0040] S2, Etching to form trenches: like Figure 4 As shown, a 1 μm thick SiO2 hard mask layer was deposited on the surface of the structure obtained in S1 using PECVD. A pattern was formed by UV lithography and transferred to the SiO2 hard mask layer. Using the SiO2 hard mask as a mask, inductively coupled plasma (ICP) etching was employed to etch the transparent conductive layer, p-type semiconductor layer, and light-emitting layer until the n-type semiconductor layer was exposed, forming trenches. The etching gas was a mixture of Ar, Cl2, and BCl3, with an RF power of 250-350 W, a pressure of 10-20 Pa, and an etching temperature of 25-30 °C. After etching, a combined cleaning method is used, consisting of O2 plasma (power 150-200W, pressure 20-30Pa, time 60-90s) and diluted HF solution (HF:H2O=1:50, soaking for 30-60s, followed by rinsing with deionized water for 2min and drying with nitrogen), to remove residual polymer and particulate impurities on the sidewalls, ensuring a sidewall surface roughness Ra≤1nm. Subsequently, the SiO2 hard mask layer and photoresist residue are removed.

[0041] S3, Forming a sidewall isolation spacer layer: like Figure 5As shown, SiO2 thin films were deposited in the trenches of the structure obtained in S2 and on the surface of the transparent conductive layer using PECVD. SiH4+N2O was selected as the reactant gas, and the deposition temperature was controlled at 250-350℃, the RF power at 200-300W, and the gas pressure at 100-200Pa. The deposition rate was 1-2nm / s to a thickness of 100-200nm, ensuring a film density ≥2.2g / cm³ and a refractive index of 1.45-1.47 in the visible light band. Then, the SiO2 on the surface of the transparent conductive layer and the bottom of the trench was removed by a combination of isotropic wet etching and dry etching, while the SiO2 located on the sidewalls of the trench was retained, forming a sidewall isolation spacer layer with an arc-shaped outer surface. The wet etching process uses BOE buffered oxide etching solution (HF:NH4F=1:6) and etching for 20-40 seconds at 25-30℃ and a stirring rate of 50-100 rpm. The dry etching process uses CF4+O2 as the etching gas and etching for 10-15 seconds at a radio frequency power of 100-150W and a gas pressure of 5-10 Pa, ultimately forming a uniform arc shape with a curvature radius of 50-100 nm and a tilt angle of 70°-80° on the sidewalls. Subsequently, nitrogen atmosphere annealing is performed, with the temperature increased to 400-450℃ at a heating rate of 5℃ / min and held for 30-60 minutes to eliminate residual stress in the film, improve adhesion to the epitaxial layer, and ensure that the interface trap density is ≤1×10¹¹cm. - ², Fixed charge density ≤ 5 × 10¹ 0 cm - ².

[0042] S4. Forming a metallic reflective layer: like Figure 6 As shown, a first insulating layer (SiO2) with a thickness of 150 nm is deposited on the surface of the structure obtained in S3 using a PECVD process. After defining the reflective layer pattern using a photolithography process, a metal reflective layer (Ag) with a thickness of 200 nm is sputtered and deposited. The metal reflective layer conformally covers the surface of the first insulating layer above the edge region of the transparent conductive layer and the surface of the first insulating layer on the arc-shaped outer surface of the sidewall isolation spacer layer. There is no metal reflective layer in the middle region of the transparent conductive layer and the bottom region of the trench, forming a connected planar reflective layer and a side reflective layer.

[0043] S5. Form n-contact through-hole: like Figure 7 As shown, a second insulating layer (SiO2) with a thickness of 150 nm was deposited on the surface of the structure obtained in S4 using a PECVD process. The second insulating layer was then etched in the bottom region of the trench using photolithography and RIE etching processes until the n-type semiconductor layer was exposed, forming an n-contact via.

[0044] S6, Deposition of n-contact metal layer: like Figure 8As shown, the n-contact electrode pattern is defined on the surface of the structure obtained in S5 using photolithography, and an n-contact metal layer is deposited using a sputtering process. The n-contact metal layer is Ti / Al / Ti / Au, so that the n-contact metal layer forms an ohmic contact with the n-type semiconductor layer in the n-contact via and extends upward along the trench sidewall to cover the surface of the second insulating layer.

[0045] S7. Forming a p-contact through-hole: like Figure 9 As shown, a third insulating layer (SiO2) with a thickness of 300 nm was deposited on the surface of the structure obtained in S6 using a PECVD process. The third insulating layer, the second insulating layer, and the first insulating layer were etched in the middle region of the pixel unit through photolithography and RIE etching processes until the transparent conductive layer (ITO) was exposed, forming a p-contact via.

[0046] S8. Deposit the p-contact metal layer and expose the n-contact metal layer: like Figure 10 As shown, the p-contact electrode pattern is defined on the surface of the structure obtained in S7 using photolithography. A p-contact metal layer of Ni / Au is deposited using a sputtering process, allowing the p-contact metal layer to contact the transparent conductive layer (ITO) within the p-contact via, forming an ohmic contact. Subsequently, the third insulating layer is etched using photolithography and RIE to expose the n-contact metal layer located in the sidewall region, completing the fabrication.

[0047] The back-emitting Micro LED pixel unit prepared by the above steps has a three-dimensional surrounding reflective structure composed of a planar reflective layer and a side reflective layer, as well as an arc-shaped sidewall isolation spacer layer, which can effectively increase the reflective area, improve the light extraction efficiency and suppress light crosstalk between adjacent pixels.

[0048] To further verify the technical effects of the embodiments of the present invention, the performance of the present invention solution is compared with that of existing structures. The comparison data is shown in Table 1: Table 1 Performance comparison data between the present invention and existing structures

[0049] As shown in Table 1, the present invention, through the synergistic effect of the three-dimensional surrounding reflective structure composed of the planar reflective layer and the side reflective layer, and the arc-shaped sidewall isolation spacer layer, improves the light extraction efficiency by 83%-100% and reduces the light crosstalk rate of adjacent pixels by 20%-25% compared with the control group 2, which fully verifies the significant advantages of the present invention in improving luminous performance and display contrast.

[0050] Compared to existing technologies, the pixel unit and its fabrication method for back-emitting Micro LEDs provided by this invention, through the synergistic design of a three-dimensional surrounding reflective structure formed by connecting a planar reflective layer and a side reflective layer, and an arc-shaped surface structure of a sidewall isolation spacer layer, achieve the following significant technical effects by addressing the shortcomings of existing technologies, such as low photon recovery efficiency, severe light loss, and significant inter-pixel crosstalk, thereby greatly improving the overall performance of back-emitting Micro LEDs: (1) Increase the effective reflective area and improve the light extraction efficiency. The present invention adopts a three-dimensional surround reflective structure, which expands the effective reflective area of ​​the metal reflective layer from the planar area of ​​the prior art to an all-round area of ​​the plane and the side. By capturing photons leaked from the multi-quantum well active layer in all directions, the photon recovery efficiency is improved, the light extraction efficiency and device brightness of the back-emitting Micro LED are improved, and the device power consumption is reduced, so as to achieve a balance between high brightness and low power consumption.

[0051] (2) Suppressing inter-pixel crosstalk and improving display contrast. The side reflective layer forms a closed-loop structure around the side of the pixel unit. The silver material used in this invention has a higher reflectivity in the blue light band than the gold material used in the trench bump in the prior art, which can efficiently recover leaked photons in the pixel gap area. It can not only capture photons leaked from the side of this pixel unit, but also effectively block photons leaked from adjacent pixels from entering this pixel unit, effectively suppressing inter-pixel crosstalk, improving the display contrast of the back-emitting Micro LED, and significantly improving the clarity and color purity of the displayed image.

[0052] (3) The arc-shaped Spacer layer reduces light loss and improves internal quantum efficiency. The arc-shaped surface structure of the sidewall isolation Spacer layer can optimize the sharp corner structure of the trench gap in the existing technology into an arc-shaped structure that is conducive to diffuse reflection. This effectively changes the propagation path of photons leaking from the side, and reflects more photons leaking into the pixel gap and deep sidewall to the back light-emitting surface, reducing the scattering loss of photons at the interface between the sidewall and the reflective layer. This arc-shaped structure works synergistically with the three-dimensional surrounding reflective structure to further improve the light extraction efficiency, while also helping to suppress light crosstalk between adjacent pixels, achieving dual optimization of luminous efficiency and display contrast. In addition, the sidewall isolation Spacer layer can also effectively reduce the interface trap density and fixed charge density on the sidewall surface of the pixel unit, significantly suppress the nonradiative recombination of sidewall carriers, improve the internal quantum efficiency of the Micro LED chip, and comprehensively protect the light-emitting performance of the device.

[0053] (4) Process compatibility reduces production costs and facilitates mass production. The preparation process of this invention is fully compatible with existing back-emitting MicroLED processes such as epitaxial growth, dielectric deposition, metal evaporation, and photolithography. No new dedicated production equipment is required, and no changes are needed to the existing production process. The process complexity is only slightly increased, which facilitates large-scale mass production and has extremely high industrial application value.

[0054] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A pixel unit for emitting Micro LEDs from the back, characterized in that, Including the pixel unit itself; The pixel unit body is provided with a sidewall isolation spacer layer, which is located on the sidewall of the pixel unit body, and the outer surface of the sidewall isolation spacer layer is an arc-shaped structure. The pixel unit body is also provided with a metal reflective layer, which includes a planar reflective layer and a side reflective layer. The planar reflective layer is located on the top of the pixel unit body, and the side reflective layer conformally covers the arc-shaped outer surface of the sidewall isolation spacer layer. The planar reflective layer and the side reflective layer are connected to form a three-dimensional surround reflective structure.

2. The pixel unit according to claim 1, characterized in that, The material of the metal reflective layer is silver.

3. The pixel unit according to claim 1, characterized in that, The material of the sidewall isolation spacer layer is silicon dioxide.

4. The pixel unit according to claim 1, characterized in that, The radius of curvature of the arc-shaped structure is 50-100 nm, and the inclination angle of the sidewall is 70°-80°.

5. The pixel unit according to claim 1, characterized in that, The pixel unit body also includes a transparent conductive layer, which is made of indium tin oxide.

6. The pixel unit according to claim 1, characterized in that, The pixel unit body further includes an epitaxial stack, which sequentially includes an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer along the direction away from the substrate.

7. The pixel unit according to claim 1, characterized in that, It also includes a first insulating layer, a second insulating layer, a third insulating layer, an n-contact metal layer, and a p-contact metal layer; The pixel unit body has a first groove on both sides. The sidewall of the first groove is provided with the sidewall isolation spacer layer, the first insulating layer, the metal reflective layer and the second insulating layer in sequence from the inside to the outside. The first groove is provided with the n-contact metal layer, which is in contact with the n-type semiconductor layer. The pixel unit body has a second groove in the middle, the second groove penetrates downward through the third insulating layer, the second insulating layer and the first insulating layer, and the p-contact metal layer is provided in the second groove, the p-contact metal layer is in contact with the transparent conductive layer; The first insulating layer is disposed between the transparent conductive layer and the metal reflective layer, the second insulating layer is disposed between the metal reflective layer and the n-contact metal layer, and the third insulating layer covers the second insulating layer.

8. A method for fabricating a pixel unit as described in any one of claims 1-7, characterized in that, Includes the following steps: S1. Provide a substrate, and grow an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer sequentially on the substrate using MOCVD process to obtain an epitaxial stack; A transparent conductive layer is deposited on the side of the epitaxial stack opposite to the substrate using magnetron sputtering. S2. A SiO2 hard mask layer is deposited on the surface of the transparent conductive layer, a pattern is formed by photolithography and transferred to the SiO2 hard mask layer; the transparent conductive layer, p-type semiconductor layer and light-emitting layer are etched by inductively coupled plasma etching process until the n-type semiconductor layer is exposed to form a trench. The SiO2 hard mask layer and photoresist residue were then removed. S3. A SiO2 thin film is deposited in the trench and on the surface of the transparent conductive layer using a plasma-enhanced chemical vapor deposition process. The SiO2 on the surface of the transparent conductive layer and the bottom of the trench is removed by a combination of isotropic wet etching and dry etching, while the SiO2 on the sidewall of the trench is retained and formed into a sidewall isolation spacer layer with an arc-shaped outer surface. S4. A first insulating layer is deposited on the surface of the structure obtained in step S3. After defining the reflective layer pattern by photolithography, a metal reflective layer is sputtered and deposited so that the metal reflective layer conformally covers the surface of the first insulating layer above the edge region of the transparent conductive layer and the surface of the first insulating layer on the arc-shaped outer surface of the sidewall isolation spacer layer. The middle region of the transparent conductive layer and the bottom region of the trench do not have the metal reflective layer, forming a connected planar reflective layer and a side reflective layer. S5. Deposit a second insulating layer and etch the second insulating layer until the n-type semiconductor layer is exposed at the bottom of the trench, forming an n-contact via; S6. Deposit an n-contact metal layer, such that the n-contact metal layer contacts the n-type semiconductor layer in the n-contact via and extends upward along the trench sidewall; S7. Deposit the third insulating layer, and etch the third insulating layer, the second insulating layer and the first insulating layer until the transparent conductive layer is exposed to form a p-contact via; S8. Deposit a p-contact metal layer so that the p-contact metal layer contacts the transparent conductive layer within the p-contact via; then etch the third insulating layer to expose the n-contact metal layer.

9. The preparation method according to claim 8, characterized in that, In step S2, the etching gas in the inductively coupled plasma etching process is a mixed gas containing Ar, Cl2 and BCl3, with a radio frequency power of 250-350W, a gas pressure of 10-20Pa, and an etching temperature of 25-30℃.

10. The preparation method according to claim 8, characterized in that, In step S3, the thickness of the SiO2 film deposited is 100-200 nm; after step S3 and before step S4, an annealing process is also included: under a nitrogen atmosphere, the temperature is raised to 400-450°C at a heating rate of 3-8°C / min and held for 30-60 min.

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