A display panel, a display panel preparation method and a display device

Abstract

The application provides a display panel, a display panel preparation method and a display device, and relates to the technical field of display. The display panel comprises: an array substrate; a sacrifice layer arranged on one side of the array substrate; a first electrode layer arranged on a side of the sacrifice layer away from the array substrate, and comprising a plurality of patterned first electrodes; a pixel definition layer arranged on a side of the first electrode layer away from the sacrifice layer, and comprising a plurality of pixel definition structures, wherein the pixel definition structure comprises a pixel opening and a pixel definition part arranged around the pixel opening, and the pixel opening exposes the first electrode; the sacrifice layer is provided with a first break between adjacent pixel definition structures; and a light-emitting functional layer arranged on a side of the pixel definition layer and the first electrode away from the array substrate, and filled in the first break. The lateral leakage of sub-pixels can be inhibited, and the display effect is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the display panel, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are widely used in consumer electronics. With the iteration of display technology and the upgrading of user demands for image quality, the industry's requirements for pixel density in display panels continue to increase. High-resolution OLED display panels have very small distances between subpixels. Because OLED light-emitting devices contain a low-resistance film layer, when the light-emitting device emits light, the luminous current can flow laterally through this low-resistance film layer into adjacent subpixels, causing abnormal luminescence in adjacent subpixels.

[0003] Therefore, the sub-pixels of the display panel have a problem of abnormal light emission due to lateral leakage, which affects the display effect of the display panel. Summary of the Invention

[0004] This application provides a display panel, a method for manufacturing the display panel, and a display device, aiming to solve the lateral leakage problem of sub-pixels in the display panel and improve the display effect of the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including:

[0006] Array substrate; A sacrificial layer is disposed on one side of the array substrate; A first electrode layer is disposed on the side of the sacrificial layer away from the array substrate, and includes a plurality of patterned first electrodes; A pixel defining layer is disposed on the side of the first electrode layer away from the sacrificial layer, and includes a plurality of pixel defining structures. Each pixel defining structure includes a pixel opening and a pixel defining portion disposed around the pixel opening. The pixel opening exposes the first electrode. The sacrificial layer has a first break between adjacent pixel defining structures. A light-emitting functional layer is disposed on the side of the pixel limiting layer and the first electrode away from the array substrate, and fills the first break.

[0007] In one possible implementation, a first gap is provided between the pixel defining portions of adjacent pixel defining structures, and the first gap is located on the side of the first break away from the array substrate; The width of the first break is greater than the minimum width of the first gap, the width of the first gap gradually increases along the light emission direction of the display panel, or the width of the first break is greater than the width of the first gap, and the sidewall of the pixel limiting portion near the first gap is perpendicular to the plane of the array substrate.

[0008] In one possible implementation, the edge of the first electrode projected onto the array substrate is located within the range of the sacrificial layer projected onto the array substrate. The pixel defining portion covers the edge side of the first electrode and extends in a direction away from the edge side of the first electrode to cover the sacrificial layer; Preferably, the thickness of the sacrificial layer ranges from 20 nm to 500 nm; Preferably, the thickness of the sacrificial layer is in the range of 50nm-100nm; Preferably, the sacrificial layer is an inorganic material layer.

[0009] In one possible implementation, at the first break, the pixel defining portion covering the sacrificial layer extends toward the first break, and the orthographic projection of the pixel defining portion on the array substrate covers the edge side of the orthographic projection of the first break on the array substrate.

[0010] In one possible implementation, a plurality of first breaks are provided on the periphery of any of the pixel-defining structures, and the plurality of first breaks are either disconnected from each other or connected to each other.

[0011] In one possible implementation, a conductive layer and a planarization layer are further disposed between the array substrate and the sacrificial layer. The display panel includes a plurality of first vias, the first vias penetrating the conductive layer and the planarization layer. The orthographic projection of the first electrode on the array substrate, the orthographic projection of the first via on the array substrate, and the orthographic projection of the conductive layer on the array substrate at least partially overlap. The first electrode is connected to the conductive layer through the first via.

[0012] Secondly, embodiments of this application provide a method for manufacturing a display panel, the method comprising: Provide an array substrate; A sacrificial layer is prepared on one side of the array substrate; A first electrode layer is prepared on one side of the sacrificial layer, and the first electrode layer is patterned to form a plurality of first electrodes; A pixel defining layer is formed on one side of the sacrificial layer, and the pixel defining layer is patterned to form a plurality of pixel defining structures. The pixel defining structure includes a pixel opening and a pixel defining portion disposed around the pixel opening. The pixel opening exposes the first electrode. The sacrificial layer is etched to remove the sacrificial layer between adjacent pixel-defined structures, forming a first break.

[0013] In one possible implementation, a pixel-defining layer is formed on one side of the sacrificial layer, and the pixel-defining layer is patterned to form multiple pixel-defining structures, including: The pixel-defining layer is subjected to halftone mask exposure processing, so that the pixel-defining layer between adjacent pixel-defining structures is fully exposed, while the pixel-defining layer at the pixel opening is half-exposed; The pixel defining layer is developed to remove the pixel defining layer between adjacent pixel defining structures and to thin the pixel defining layer at the pixel opening.

[0014] In one possible implementation, the method further includes: While etching the sacrificial layer, the pixel limiting layer at the pixel opening is also etched, thereby exposing the first electrode layer at the pixel opening.

[0015] Thirdly, this application provides a display device including a display panel as described in the first aspect above.

[0016] This embodiment of the application forms a physical barrier by setting a first break in the sacrificial layer between adjacent pixel-defining structures and filling the first break with a light-emitting functional layer. In this embodiment, the presence of the first break hollows out the bottom region of the adjacent pixel-defining portion, forcing the subsequently deposited light-emitting functional layer to extend downwards and then upwards at the first break. Alternatively, the discontinuous structure at the bottom of the first break makes the coverage of the light-emitting functional layer discontinuous or extremely thin, thereby effectively severing the conductive path of the light-emitting functional layer between adjacent pixels. This significantly suppresses lateral leakage current, thereby improving the display effect. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is an exemplary cross-sectional schematic diagram of a display panel provided in an embodiment of this application; Figure 2 An exemplary cross-sectional schematic diagram of another display panel provided in an embodiment of this application; Figure 3 An exemplary top view of a display panel provided in an embodiment of this application; Figure 4 An exemplary top view schematic diagram of another display panel provided in an embodiment of this application; Figure 5 An exemplary top view schematic diagram of another display panel provided in an embodiment of this application; Figure 6 A schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application; Figure 7 A cross-sectional schematic diagram of a display panel manufacturing process provided in an embodiment of this application; Figure 8 A cross-sectional schematic diagram of another display panel manufacturing process provided in this application embodiment; Figure 9 This is a cross-sectional schematic diagram of another display panel manufacturing process provided in an embodiment of this application.

[0019] Explanation of reference numerals in the attached figures: Array substrate 100; Sacrificial layer 200, first fracture 210; First electrode layer 300, first electrode 310; Pixel limiting layer 400, pixel limiting structure 410, pixel opening 411, pixel limiting part 412, first gap 430; 500-layer luminescent functional layer; Planarization layer 600; Conductive layer 700; First through hole K. Detailed Implementation

[0020] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0021] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0022] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0023] The inventors discovered the following problems in the related technology.

[0024] The light-emitting functional layer of an OLED display panel is usually formed using a vapor deposition process. The light-emitting functional layer includes multiple film layers. Some of these film layers are formed in the pixel openings through pixel-level alignment vapor deposition using a mask, while other film layers are formed by full-surface vapor deposition. In other words, on an OLED display panel, there are shared film layers formed by full-surface vapor deposition between sub-pixels. The light-emitting current of a sub-pixel can leak through the shared film layer to adjacent sub-pixels, causing adjacent sub-pixels to emit light incorrectly, thus affecting the display effect of the display panel.

[0025] To address the aforementioned technical problems, embodiments of this application provide a display panel, such as... Figure 1 As shown, the display panel includes an array substrate 100, a sacrificial layer 200, a first electrode layer 300, a pixel defining layer 400, and a light-emitting functional layer 500.

[0026] The array substrate 100 includes a sacrificial layer 200 disposed on one side of the sacrificial layer 200. A first electrode layer 300 is disposed on the side of the sacrificial layer 200 away from the array substrate 100, and the first electrode layer 300 includes a plurality of patterned first electrodes 310. A pixel defining layer 400 is disposed on the side of the first electrode layer 300 away from the sacrificial layer 200. The pixel defining layer 400 includes a plurality of pixel defining structures 410, each pixel defining structure 410 including a pixel opening 411 and a pixel defining portion 412 surrounding the pixel opening 411, the pixel opening 411 exposing the first electrodes 310. The sacrificial layer 200 has a first break 210 between adjacent pixel defining structures 410. A light-emitting functional layer 500 is disposed on the side of the pixel defining layer 400 and the first electrodes 310 away from the array substrate 100, and fills the first break 210.

[0027] The array substrate 100 includes a thin-film transistor array layer. The thin-film transistor array layer includes multiple thin-film transistors, each containing conventional structures such as a source layer, a gate insulating layer, a gate, an interlayer dielectric layer, a source, and a drain, used to provide drive current and control signals for the light-emitting device. The surface of the array substrate is typically covered with a planarization layer 600 to provide a flat fabrication surface.

[0028] A sacrificial layer 200 is disposed on one side of the array substrate 100. In this embodiment, the sacrificial layer 200 is formed directly on the planarization layer 600. A first electrode layer 300 is disposed on the side of the sacrificial layer 200 away from the array substrate 100. The first electrode layer 300 is typically made of a transparent conductive oxide (such as ITO, i.e., indium tin oxide; IZO, i.e., indium zinc oxide) or a metal material with high reflectivity (such as silver, aluminum) or a stack thereof. By performing patterning processes such as photolithography and etching on the first electrode layer 300, a plurality of first electrodes 310 separated from each other are formed. The first electrode 310 can be the anode or cathode of a sub-pixel of the display panel, and each first electrode 310 is electrically connected to the drain of a corresponding thin-film transistor in the array substrate 100 through a via penetrating the planarization layer 600 and the sacrificial layer 200.

[0029] A pixel defining layer 400 is disposed on the side of the first electrode layer 300 away from the sacrificial layer 200. The pixel defining layer 400 is typically made of a photosensitive organic material (such as polyimide or acrylic resin). The pixel defining layer 400 is patterned through processes such as coating, exposure, and development to form multiple pixel defining structures 410. Each pixel defining structure 410 includes a pixel opening 411 and a pixel defining portion 412 surrounding the pixel opening 411. The pixel opening 411 precisely exposes a portion of the corresponding area of ​​the first electrode 310 below; this exposed area is the actual light-emitting area. The pixel defining portion 412 covers the edge of the first electrode 310, and its sidewalls form the boundary of the pixel opening 411.

[0030] The key aspect of this embodiment is that the sacrificial layer 200 has a first break 210 between adjacent pixel defining structures 410. Specifically, after the pixel defining layer 400 is patterned, an additional etching process is used to selectively remove the sacrificial layer 200 exposed between adjacent pixel defining structures 410. Since the pixel defining portion 412 and the first electrode layer 300 cover and protect the sacrificial layer 200 below the pixel defining structure 410, the etching process only occurs in the gap region between adjacent pixel defining structures 410. The sacrificial layer 200 is completely removed in this region, forming the first break 210.

[0031] A light-emitting functional layer 500 is disposed on the side of the pixel defining layer 400 and the first electrode 310 away from the array substrate 100, and fills the first break 210. The light-emitting functional layer 500 can be formed by high-precision metal mask evaporation, open mask evaporation, or solution printing (such as inkjet printing). The light-emitting functional layer 500 includes multiple layers of organic electroluminescent materials. For example, the light-emitting functional layer 500 may include a stack of hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer. During evaporation or printing, the material of the light-emitting functional layer 500 is deposited not only on the first electrode 310 within the pixel opening 411, but also on the top surface and sidewalls of the pixel defining portion 412. In this embodiment, since the sacrificial layer 200 provides a first break 210 between adjacent pixel defining structures 410, a recessed structure is formed in the vertical direction in this area. When the material of the light-emitting functional layer 500 is deposited, this material will fill the first break 210 accordingly.

[0032] This embodiment of the application forms a physical barrier by setting a first break 210 in the sacrificial layer 200 between adjacent pixel defining structures 410 and filling the first break 210 with the light-emitting functional layer 500. In existing display panels, the light-emitting functional layers 500 of different sub-pixels, especially laterally conductive films such as hole transport layers, are easily deposited continuously on the surface or sidewalls of the pixel defining portion 412, thereby forming conductive channels. When a pixel emits light, charge carriers may migrate laterally to adjacent non-emitting pixels through these continuous conductive channels, causing adjacent pixels to emit light incorrectly, i.e., generating serious lateral leakage current and pixel crosstalk problems. In this embodiment, the presence of the first break 210 hollows out the bottom region of the adjacent pixel defining portion 412, forcing the subsequently deposited light-emitting functional layer 500 to extend downwards and then climb upwards at the first break 210, or the discontinuous structure at the bottom of the first break 210 makes the coverage of the light-emitting functional layer 500 discontinuous or extremely thin, thereby effectively cutting off the conductive path of the light-emitting functional layer 500 between adjacent pixels. It significantly suppresses lateral leakage current, thereby improving the display effect.

[0033] In another embodiment of this application, such as Figure 1 and Figure 2 As shown, a first gap 430 is provided between the pixel limiting portions 412 of the adjacent pixel limiting structure 410, and the first gap 430 is located on the side of the first break 210 away from the array substrate 100. like Figure 3 As shown, Figure 3 This application provides a top view of a partial sub-pixel structure on a display panel, wherein adjacent pixel structures include a first gap 430. Figure 1 and Figure 2 This is a cross-sectional diagram along the imaginary straight line, where the imaginary curve represents the edge contour of the first electrode 310. It should be noted that... Figure 3 The example shown is based solely on the circular shape of the subpixel opening. The shape of the subpixel opening in this embodiment is not limited to a circle. For example, the subpixel opening can also be formed in other shapes such as rectangle or ellipse.

[0034] like Figure 1 As shown, the width of the first break 210 is greater than the minimum width of the first gap 430, and the width of the first gap 430 gradually increases along the light emission direction of the display panel. Alternatively, as... Figure 2 As shown, the width of the first fracture 210 is greater than the width of the first gap 430, and the sidewall of the first gap 430 is perpendicular to the plane of the array substrate 100. The widths of the first fracture and the first gap are along... Figure 3 The width of the dashed line in the middle.

[0035] Specifically, a first gap 430 is provided between the pixel defining portions 412 of two adjacent pixel defining structures 410. This first gap 430 is the space between the sidewalls of two adjacent pixel defining portions 412 after the pixel defining layer 400 is patterned. From a vertical perspective, the first gap 430 is located on the side of the first break 210 away from the array substrate 100. In other words, viewed from a cross-section of the display panel, from top to bottom, the sequence is: first gap 430, first break 210, and the array substrate 100 or planarization layer 600 below.

[0036] In the embodiments of this application, such as Figure 1As shown, the width of the first break 210 is greater than the minimum width of the first gap 430, and the width of the first gap 430 gradually increases along the light emission direction of the display panel (i.e., from the array substrate 100 to the light-emitting functional layer 500). This means that, in terms of cross-sectional shape, the first gap 430 presents an inverted trapezoidal shape. The width of the first break 210, i.e., the lateral dimension of the area where the sacrificial layer 200 is removed, is greater than the minimum width of the first gap 430. The first gap 430 is located on the side of the first break 210 away from the array substrate 100; that is, the lower base of the inverted trapezoidal first gap 430 is set on the first break 210, forming an undercut structure.

[0037] Or, such as Figure 2 As shown, the width of the first cut 210 is greater than the width of the first gap 430, and the sidewall of the pixel limiting layer 400 near the first gap 430 is perpendicular to the plane of the array substrate 100. The first gap 430 itself is a rectangular opening with steep sidewalls. The width of the first cut 210 is also designed to be greater than the width of the first gap 430, that is, the rectangular first cut 210 is set on the first cut 210, forming an undercut structure.

[0038] The "large bottom, small top" structure formed by the above embodiment can more reliably break the lateral continuity of the light-emitting functional layer 500 between adjacent pixels. In conventional structures, for example, when the width of the first break 210 and the first gap 430 are equal, the material of the light-emitting functional layer 500 may uniformly cover along the sidewall during deposition. Although the path becomes longer, it is still possible to form a continuous film layer. However, in this embodiment, since the first break 210 is significantly wider than the first gap 430 in the lateral direction, the bottom edge of the pixel limiting portion 412 above the first break 210 is suspended. When the light-emitting functional layer 500 is formed by vapor deposition or inkjet printing, when material particles or droplets are deposited on the sidewall of this area, due to the presence of a sharp corner and discontinuity, the light-emitting functional layer 500 will break at the corner and discontinuity, failing to form a continuous film layer or forming an extremely thin film layer, which can effectively prevent leakage current from passing through.

[0039] In another embodiment of this application, such as Figure 1 and Figure 2 As shown, the edge of the first electrode 310 projected onto the array substrate 100 is located within the range of the sacrificial layer 200 projected onto the array substrate 100; the pixel limiting portion 412 covers the edge side of the first electrode 310 and extends in a direction away from the edge side of the first electrode 310 to cover the sacrificial layer 200.

[0040] This embodiment further defines the coverage relationship between the sacrificial layer 200 and the first electrode 310 and the pixel limiting portion 412, and optimizes the material and thickness of the sacrificial layer 200, aiming to further simplify the process and improve the dimensional accuracy of the pixel opening.

[0041] Specifically, in the display panel of this embodiment, the edge of the orthographic projection of the first electrode 310 onto the array substrate 100 is located within the range of the orthographic projection of the sacrificial layer 200 onto the array substrate 100; that is, the edge of the orthographic projection of the sacrificial layer 200 onto the array substrate 100 covers the edge of the orthographic projection of the first electrode 310 onto the array substrate 100. The first electrode 310 is fabricated above the sacrificial layer 200. The sacrificial layer 200 serves as an intermediate transition layer.

[0042] Simultaneously, the pixel defining portion 412 covers the edge side of the first electrode 310 and extends away from the edge side of the first electrode 310, covering the sacrificial layer 200. After the pixel defining layer 400 is patterned, the edge of the pixel opening 411 is defined by the sidewall of the pixel defining portion 412. This sidewall is located above the inner region of the first electrode 310, ensuring that the edge of the first electrode 310 is covered by the pixel defining portion 412, thereby preventing leakage or short circuit caused by electric field concentration at the edge. More importantly, the main body of the pixel defining portion 412 extends outward from the edge of the first electrode 310 and covers the sacrificial layer 200 below it.

[0043] In a preferred implementation, the thickness of the sacrificial layer 200 ranges from 20nm to 500nm. For example, the thickness of the sacrificial layer 200 can be 20nm, 50nm, 100nm, 200nm, 300nm, 400nm, 450nm, 490nm, or 500nm. This thickness range ensures that the sacrificial layer 200 can provide sufficient height difference to form an effective fracture, while not being too thick, which would lead to excessively long etching processes or stress problems. If the thickness is less than 20nm, the depth of the first fracture 210 is too shallow, and the subsequently deposited light-emitting functional layer 500 is not easy to break, and the effect of preventing lateral leakage current will be greatly reduced. If the thickness is greater than 500nm, it will significantly increase the process time, and the excessively high step may cause poor coverage or cracks in the upper pixel limiting layer 400 and the light-emitting functional layer 500.

[0044] More preferably, the thickness of the sacrificial layer 200 is in the range of 50nm-100nm. For example, the thickness of the sacrificial layer 200 can be 20nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm. Within this range, the sacrificial layer 200 can form a first fracture 210 with a clear undercut profile within a reasonable time through an etching process.

[0045] In a preferred implementation, the sacrificial layer 200 is an inorganic material layer. Specifically, the sacrificial layer 200 may be silicon oxide (SiO2) or silicon nitride (SiN). xAlternatively, the sacrificial layer 200 can be made of silicon oxynitride (SiON), or it can be indium zinc oxide (IZO), indium gallium oxide (IGO), or indium zinc gallium oxide (IGZO). Compared to organic materials, inorganic materials have better thermal and chemical stability. Before the subsequent fabrication of the light-emitting functional layer 500, the display panel typically needs to undergo high-temperature baking to remove moisture and residual solvents; the inorganic sacrificial layer 200 will not deform or decompose during this process.

[0046] This embodiment constructs a stable three-layer stack by defining the edge of the sacrificial layer 200 to completely cover the edge of the first electrode 310 in the planar direction, and by having the pixel defining portion 412 extend outward to cover the sacrificial layer 200. This allows the first break 210 to be formed at a location away from the edge of the first electrode 310, thereby cutting off lateral leakage current while avoiding the risk that chemicals used to etch the sacrificial layer 200 (such as etching solution) may seep in along the interface and corrode the first electrode 310. Since the pixel defining portion 412 covers the sacrificial layer 200, the formation area of ​​the first break 210 is defined by the first gap 430 between the pixel defining portions 412, resulting in a larger process window that is easier to control. By selecting the inorganic sacrificial layer 200 and its thickness range of 20-500nm (especially 50-100nm), an optimal balance is achieved between structural stability, process compatibility, and electrical performance. The embodiments of this application not only improve the performance of preventing crosstalk, but also improve the manufacturing yield. Due to the function of the pixel limiting part 412, the sacrificial layer 200 below it is partially hollowed out, forming the first break 210. The pixel limiting part 412 can still maintain its shape by its own strength and will not collapse or peel off.

[0047] In another embodiment of this application, at the first break 210, the pixel limiting portion 412 covering the sacrificial layer 200 extends in the direction of the first break 210, and the orthographic projection of the pixel limiting portion 412 on the array substrate 100 covers the edge side of the orthographic projection of the first break 210 on the array substrate 100.

[0048] Specifically, in the display panel of this embodiment, viewed from a top view or cross-sectional view, the first break 210 is formed in the sacrificial layer 200. The bottom edge of the pixel defining portion 412 located above the first break 210 is not exactly aligned with the edge of the first break 210, but extends horizontally a short distance into the interior (i.e., in the center direction) of the first break 210, creating a misalignment between the first break 210 and the bottom edge of the upper pixel defining portion 412. Therefore, viewed from directly above the array substrate 100, the projection of the pixel defining portion 412 completely covers the edge portion of the first break 210. The boundary of the first break 210 is not exposed, but is obscured by the extended portion of the upper pixel defining portion 412.

[0049] In this embodiment, the structure extending from the pixel limiting portion 412 to above the edge of the first break 210 creates an extremely steep surface profile, even with a negative angle, for the subsequently deposited light-emitting functional layer 500. When the material of the light-emitting functional layer 500 is deposited in an approximately perpendicular direction, the light-emitting functional layer 500 is broken at the junction of the first break 210 and the edge of the pixel limiting portion 412, preventing the formation of a continuous film layer. This structural design can reliably eliminate lateral leakage current and pixel crosstalk problems.

[0050] In another embodiment of this application, or in any of the above embodiments, a plurality of first breaks 210 are provided on the periphery of any pixel-defined structure 410, and the plurality of first breaks 210 are either disconnected from each other or connected to each other.

[0051] As mentioned earlier, the first break 210 is disposed between adjacent pixel defining structures 410 to sever the lateral connectivity of the light-emitting functional layer 500. Multiple first breaks 210 are disposed around the periphery of any pixel defining structure 410. This means that for a sub-pixel, a first break 210 is disposed between that sub-pixel and all its surrounding adjacent sub-pixels, possibly including adjacent sub-pixels in the top, bottom, left, right, and diagonal directions. For example, in a standard RGB strip arrangement, a red sub-pixel has an independent first break 210 disposed between it and the green sub-pixel to its left, the blue sub-pixel to its right, the green sub-pixel above it, and the green sub-pixel below it.

[0052] like Figure 4 As shown, multiple first breaks 210 are disconnected from each other. Each first break 210 surrounding a sub-pixel is separate and unconnected. Each first break 210 exists only between that pixel and one specific adjacent pixel. The first break 210 between two adjacent pixels is an independent closed region. This design offers greater strength because the sacrificial layer 200 remains continuous at the four corners of the pixel, providing robust support for the overlying pixel-defining portion 412 and avoiding the risk of the pixel-defining layer 400 collapsing entirely due to a large area of ​​missing sacrificial layer 200. This structure is particularly suitable for high-resolution, small-sized display panels.

[0053] Or, such as Figure 5As shown, multiple first breaks 210 are interconnected. In this layout, multiple first breaks 210 surrounding a sub-pixel are connected together to form a "ring trench" around the pixel. For example, all the first breaks 210 around the pixel can be connected into a ring through the continuous removal regions of the sacrificial layer 200. This design maximizes the effect of lateral isolation because the sacrificial layer 200 below the pixel defining portion 412 is continuously removed, completely cutting off the possibility of the light-emitting functional layer 500 flowing to adjacent pixels from any direction. This structure is particularly excellent in preventing pixel crosstalk in the diagonal direction. It should be noted that... Figure 5 The example shown is only of the shape formed by connecting the first break 210 into a hexagon. The actual shape formed by connecting the first break 210 is not limited to hexagon. It can also be other shapes that surround the pixel opening, such as quadrilateral, pentagon or circle.

[0054] This embodiment ensures that each light-emitting unit is electrically isolated by setting multiple first breaks 210 around the periphery of any pixel. Neither adjacent pixels, whether horizontally, vertically, or diagonally, can form a conductive path through the continuous light-emitting functional layer 500. This provides a comprehensive and thorough solution for eliminating lateral leakage current.

[0055] In another embodiment of this application, a conductive layer 700 and a planarization layer 600 are further disposed between the array substrate 100 and the sacrificial layer 200. The display panel includes a plurality of first vias K, which penetrate the conductive layer 700 and the planarization layer 600. The orthographic projection of the first electrode 310 on the array substrate 100, the orthographic projection of the first via K on the array substrate 100, and the orthographic projection of the conductive layer 700 on the array substrate 100 overlap at least partially. The first electrode 310 is connected to the conductive layer 700 through the first via K.

[0056] The conductive layer 700 is typically a metal trace fabricated on the same layer as the source and drain metal layers, or an additional transparent electrode layer. This conductive layer 700 forms part of the driving circuit of the array substrate 100, and its function is to provide a driving signal to the first electrode 310.

[0057] The planarization layer 600 covers the conductive layer 700 and is used to planarize the uneven surface caused by the thin-film transistors and metal traces, providing a highly flat substrate for the fabrication of upper-layer devices.

[0058] The key connection structure in this embodiment is that the planarization layer 600 and the sacrificial layer 200 are provided with a plurality of first vias K. These vias are formed by photolithography and etching processes, sequentially penetrating the sacrificial layer 200 and the planarization layer 600, and their bottoms expose the underlying conductive layer 700 (e.g., the drain of a thin-film transistor or a dedicated connection pad).

[0059] Furthermore, the orthographic projections of the first electrode 310, the first via K, and the conductive layer 700 on the array substrate 100 at least partially overlap. This means that the first electrode 310, the first via K, and the conductive layer 700 are aligned with each other in the vertical direction. In the actual structure, the opening of the first via K is located above the conductive layer 700, while the first electrode 310 completely covers the area of ​​the first via K and extends around the via, enabling the first electrode 310 to achieve reliable physical contact and electrical connection with the conductive layer 700 through the first via K.

[0060] To ensure connection stability and reduce contact resistance, the deposition of the first electrode 310 material needs to have good step coverage, and the first electrode 310 will fill the first via K. Before forming the first electrode layer 300, an additional transparent conductive oxide layer can be deposited as an adhesion and barrier layer.

[0061] This embodiment ensures that the first electrode 310 and the pixel defining layer 400 are on a flat surface by setting a planarization layer 600, which is crucial for forming a uniform light-emitting layer and preventing bright spots and dark spots. Secondly, a sacrificial layer 200 is set on top of the planarization layer 600, and the first via K passes through both the sacrificial layer 200 and the planarization layer 600 simultaneously, which is a highly integrated and efficient process. It avoids the complex step of individually creating holes for each pixel on the already patterned sacrificial layer 200. During fabrication, the planarization layer 600 and the sacrificial layer 200 can be deposited sequentially, and then the first via K can be created on both layers simultaneously through a single photolithography and etching process. Afterwards, the first electrode layer 300 is deposited, and the material of the first electrode 310 naturally fills the via and contacts the conductive layer 700. Finally, the first electrode layer 300 is patterned to form mutually isolated first electrodes 310. Since the sacrificial layer 200 will eventually be partially removed in a subsequent step to form the first break 210, the sacrificial layer 200 around the first via K region will not be etched away because it is covered and protected by the first electrode 310 and the pixel defining portion 412 above it. This ensures that the connection point between the first electrode 310 and the conductive layer 700 is always completely preserved and undamaged. This design ensures that even after the first break 210 is formed, the driving signal path of each pixel remains intact, achieving perfect compatibility between pixel isolation and circuit connection.

[0062] Based on the same inventive concept, embodiments of this application also provide a method for manufacturing a display panel, such as... Figure 6 As shown, the method includes: S601, Provide an array substrate.

[0063] S602. Prepare a sacrificial layer on one side of the array substrate.

[0064] S603. A first electrode layer is prepared on one side of the sacrificial layer, and the first electrode layer is patterned to form multiple first electrodes.

[0065] S604. A pixel-limiting layer is formed on one side of the sacrificial layer, and the pixel-limiting layer is patterned to form multiple pixel-limiting structures.

[0066] The pixel defining structure includes a pixel opening and a pixel defining portion disposed around the pixel opening, wherein the pixel opening exposes a first electrode.

[0067] S605. The sacrificial layer is etched to remove the sacrificial layer between adjacent pixel-defined structures, forming the first break.

[0068] In one specific implementation, if the sacrificial layer is made of SiNx, SiO2, or SiNO, it can be etched using a dry etching method.

[0069] In another specific implementation, if the sacrificial layer is made of IZO, IGO, or IGZO, the sacrificial layer can be etched using a wet etching method.

[0070] The fabrication method provided in this application only requires adding a deposition sacrificial layer and an etching sacrificial layer after the pixel-defining layer to the conventional display panel manufacturing process to achieve a complex and efficient anti-crosstalk structure. This method is fully compatible with existing mainstream OLED manufacturing equipment (such as PECVD and PVD for deposition, and coating and etching machines for photolithography) without requiring additional high-cost equipment (such as expensive fine metal mask replacements or alignment systems). By selectively etching, the pixel-defining layer itself is cleverly used as an etching mask to achieve a self-aligned undercut structure, avoiding additional photolithography alignment steps. The first fracture surface prepared by this method is precisely located between the pixel-defining structures, enabling a significant improvement in display panel performance at extremely low cost.

[0071] In another embodiment of this application, in step S604, a pixel-defining layer is formed on one side of the sacrificial layer, and the pixel-defining layer is patterned to form multiple pixel-defining structures. Specifically, this can be implemented as follows: Step 1: Perform halftone mask exposure processing on the pixel confinement layer so that the pixel confinement layer between adjacent pixel confinement structures is fully exposed, while the pixel confinement layer at the pixel opening is half exposed. like Figure 7 As shown, the pixel confinement layer 400 can be exposed using a halftone mask, and the pixel confinement layer at the pixel opening is half-exposed.

[0072] Step 2: The pixel-defining layer is developed to remove the pixel-defining layer between adjacent pixel-defining structures and to thin the pixel-defining layer at the pixel opening.

[0073] like Figure 8 As shown, after developing the pixel-defining layer, the pixel-defining layer between adjacent pixel-defining structures is removed, and the pixel-defining layer at the pixel opening is thinned.

[0074] Following step two above, the process also includes step three: while etching the sacrificial layer, etching the pixel limiting layer at the pixel opening to expose the first electrode layer at the pixel opening.

[0075] like Figure 9 As shown, the pixel-defining layer 400 at the pixel opening and the sacrificial layer 200 between adjacent pixel-defining structures are both etched away. This application embodiment uses halftone exposure to precisely leave a thin layer of photoresist at the pixel opening. This residual photoresist layer can serve as a protective layer for the first electrode in subsequent steps, such as wet or dry etching of the sacrificial layer to form the first fracture, preventing accidental damage to the first electrode from the etching solution or plasma. After the first fracture is formed, the thin layer of photoresist at the pixel opening can be removed simultaneously, exposing the first electrode. This design improves the robustness of the process and the electrical performance of the final product.

[0076] This application also provides a display device, including the display panel described in any of the above embodiments, wherein the display device can be an electronic device such as a smartphone, tablet computer, or laptop computer.

[0077] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: Array substrate; A sacrificial layer is disposed on one side of the array substrate; A first electrode layer is disposed on the side of the sacrificial layer away from the array substrate, and includes a plurality of patterned first electrodes; A pixel defining layer is disposed on the side of the first electrode layer away from the sacrificial layer, and includes a plurality of pixel defining structures. Each pixel defining structure includes a pixel opening and a pixel defining portion disposed around the pixel opening. The pixel opening exposes the first electrode. The sacrificial layer has a first break between adjacent pixel-defined structures; A light-emitting functional layer is disposed on the side of the pixel limiting layer and the first electrode away from the array substrate, and fills the first break.

2. The display panel according to claim 1, characterized in that, A first gap is provided between the pixel defining portions of adjacent pixel defining structures, and the first gap is located on the side of the first break away from the array substrate; The width of the first break is greater than the minimum width of the first gap, the width of the first gap gradually increases along the light emission direction of the display panel, or the width of the first break is greater than the width of the first gap, and the sidewall of the pixel limiting portion near the first gap is perpendicular to the plane of the array substrate.

3. The display panel according to claim 2, characterized in that, The edge of the first electrode projected onto the array substrate is located within the range of the sacrificial layer projected onto the array substrate; The pixel defining portion covers the edge side of the first electrode and extends in a direction away from the edge side of the first electrode to cover the sacrificial layer; Preferably, the thickness of the sacrificial layer ranges from 20 nm to 500 nm; Preferably, the thickness of the sacrificial layer ranges from 50 nm to 100 nm; Preferably, the sacrificial layer is an inorganic material layer.

4. The display panel according to claim 3, characterized in that, At the first fracture, the pixel defining portion covering the sacrificial layer extends toward the first fracture, and the orthographic projection of the pixel defining portion on the array substrate covers the edge side of the orthographic projection of the first fracture on the array substrate.

5. The display panel according to any one of claims 1-4, characterized in that, The periphery of any of the pixel-defining structures is provided with a plurality of first breaks, which are either disconnected from each other or connected to each other.

6. The display panel according to claim 5, characterized in that, A conductive layer and a planarization layer are further disposed between the array substrate and the sacrificial layer. The display panel includes a plurality of first vias, the first vias penetrating the conductive layer and the planarization layer. The orthographic projection of the first electrode on the array substrate, the orthographic projection of the first via on the array substrate, and the orthographic projection of the conductive layer on the array substrate overlap at least partially. The first electrode is connected to the conductive layer through the first via.

7. A method for manufacturing a display panel, characterized in that, The method includes: Provide an array substrate; A sacrificial layer is prepared on one side of the array substrate; A first electrode layer is prepared on one side of the sacrificial layer, and the first electrode layer is patterned to form a plurality of first electrodes; A pixel defining layer is formed on one side of the sacrificial layer, and the pixel defining layer is patterned to form a plurality of pixel defining structures. The pixel defining structure includes a pixel opening and a pixel defining portion disposed around the pixel opening. The pixel opening exposes the first electrode. The sacrificial layer is etched to remove the sacrificial layer between adjacent pixel-defined structures, forming a first break.

8. The preparation method according to claim 7, characterized in that, A pixel-defining layer is formed on one side of the sacrificial layer, and the pixel-defining layer is patterned to form multiple pixel-defining structures, including: The pixel-defining layer is subjected to halftone mask exposure processing, so that the pixel-defining layer between adjacent pixel-defining structures is fully exposed, while the pixel-defining layer at the pixel opening is half-exposed; The pixel defining layer is developed to remove the pixel defining layer between adjacent pixel defining structures and to thin the pixel defining layer at the pixel opening.

9. The preparation method according to claim 8, characterized in that, The method further includes: While etching the sacrificial layer, the pixel limiting layer at the pixel opening is also etched, thereby exposing the first electrode layer at the pixel opening.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-6.

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