Display panel and display device

Abstract

The application discloses a display panel and a display device. The second source-drain metal layer comprises an auxiliary cathode line extending along a second direction. The third source-drain metal layer comprises a partition portion extending along the second direction. A undercut groove extending along the second direction is formed between the partition portion and the auxiliary cathode line. The first barrier wall and the second barrier wall are cross-connected to form a plurality of pixel openings. The second barrier wall is provided with a lap joint extending along the second direction. The lap joint is communicated with the undercut groove and exposes part of the auxiliary cathode line and at least part of the partition portion. The length of the lap joint and the length of the undercut groove are both greater than the width of the pixel opening. The cathode extends into the undercut groove through the lap joint and is connected with the auxiliary cathode line. The embodiment of the application reduces the depth of the lap joint to improve the stability of the cathode lap joint with the auxiliary cathode line. The lap joint can expose more area of the auxiliary cathode line, the area of the cathode lap joint with the auxiliary cathode line is improved, and the voltage drop of the cathode is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the rapid development of display technology, users have increasingly higher requirements for display effects, and the industry has maintained a high level of attention to display effect research. Among them, organic light-emitting diode (OLED) display panels have advantages such as high brightness, thin and light size, fast response speed, and ease of achieving color display and large-screen display, and have broad application prospects. However, existing display panels have the problem of poor brightness uniformity.

[0003] To address this issue, an auxiliary cathode is typically connected to the primary cathode to reduce the cathode voltage drop. However, for OLED panels with pixel circuits consisting of seven or more transistors, the circuitry is quite complex, especially for discrete pixel circuits. The traces in the first source / drain metal layer are primarily used to control the switching of the transistors in the pixel circuit and also to form the connection structure between the source and drain of the transistors. Since the auxiliary cathode is located in the first source / drain metal layer, and because the auxiliary cathode is a horizontal trace, the opening for connecting the primary cathode to the secondary cathode can only be located at the intersection of the horizontal and vertical barriers. This opening is small in size and deep, which is detrimental to the stability of the connection between the primary and secondary cathodes. Furthermore, the available wiring space for the secondary cathode is extremely limited, resulting in a limited effect on reducing the cathode voltage drop. Summary of the Invention

[0004] This application provides a display panel and a display device to at least partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising: Substrate; A pixel circuit layer is disposed on the substrate. The pixel circuit layer includes a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on opposite layers. The second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate. The third source / drain metal layer is disposed on the side of the second source / drain metal layer away from the substrate. The second source / drain metal layer includes an auxiliary cathode line extending along a second direction. The third source / drain metal layer includes a partition portion extending along the second direction. An undercut groove extending along the second direction is formed between the partition portion and the auxiliary cathode line. A pixel definition layer is disposed on the side of the pixel circuit layer away from the substrate. The pixel definition layer includes a first barrier and a second barrier. The first barrier extends along a first direction intersecting the second direction, and the second barrier extends along the second direction. The first barrier and the second barrier are intersected and connected to form a plurality of pixel openings. The second barrier is provided with an interface extending along the second direction. The interface connects to the undercut groove and exposes a portion of the auxiliary cathode line and at least a portion of the partition. The length of the interface and the length of the undercut groove are both greater than the width of the pixel opening. A cathode is disposed on the side of the pixel definition layer away from the substrate, and the cathode extends into the undercut groove through the interface and is connected to the auxiliary cathode line.

[0006] Optionally, in some embodiments of this application, in the second direction, the length of the overlapping joint and the length of the bottom groove are both equal to the distance between two adjacent first retaining walls.

[0007] Optionally, in some embodiments of this application, in the first direction, the width of the auxiliary cathode line is greater than the width of the partition, and a portion of the auxiliary cathode line extends beyond the partition.

[0008] Optionally, in some embodiments of this application, in the first direction, the width of the portion of the auxiliary cathode line that extends beyond the partition and is close to the bottom groove is greater than the width of the partition.

[0009] Optionally, in some embodiments of this application, in the first direction, the opposite sides of the auxiliary cathode wires extend beyond the partition portion, and the width of the portion of the auxiliary cathode wires that extends beyond the partition portion and is far from the bottom groove is smaller than the width of the partition portion.

[0010] Optionally, in some embodiments of this application, in the first direction, the width of the auxiliary cathode line is greater than the width of the second retaining wall forming the interface.

[0011] Optionally, in some embodiments of this application, in the second direction, a plurality of the bonding interfaces are spaced apart, and the cathode is connected to an auxiliary cathode line through the plurality of the bonding interfaces.

[0012] Optionally, in some embodiments of this application, in the first direction, the width of the interface is smaller than the width of each pixel opening.

[0013] Optionally, in some embodiments of this application, the pixel circuit layer further includes a first planarization layer, a passivation layer, and a second planarization layer. The first planarization layer is disposed between the first source / drain metal layer and the second source / drain metal layer, the passivation layer is disposed between the second source / drain metal layer and the third source / drain metal layer, the second planarization layer covers the third source / drain metal layer and the passivation layer, the pixel definition layer is disposed on the side of the second planarization layer away from the substrate, and the interface also penetrates through the second planarization layer and the passivation layer. Wherein, the width of the portion of the interface at the pixel definition layer is greater than the width of the portion of the interface at the second flat layer, the width of the portion of the interface at the second flat layer is greater than the width of the portion of the interface at the passivation layer, and the portion of the interface at the passivation layer is connected to the bottom notch.

[0014] Optionally, in some embodiments of this application, the display panel includes a plurality of pixels, a pixel includes at least three sub-pixels, and a sub-pixel is correspondingly disposed within an opening area of ​​a pixel; In the first direction, the auxiliary cathode line is disposed between two adjacent sub-pixels, and each N consecutive pixels form a repeating unit. Each repeating unit is provided with one auxiliary cathode line, where 2≤N≤5 and N is an integer.

[0015] Optionally, in some embodiments of this application, at least three of the sub-pixels of the pixel include a red sub-pixel, a green sub-pixel, and a blue sub-pixel; In the repeating unit, the auxiliary cathode line is disposed adjacent to the first blue sub-pixel, and the width of the first blue sub-pixel is smaller than the width of the other blue sub-pixels.

[0016] Optionally, in some embodiments of this application, at least three of the sub-pixels of the pixel include a red sub-pixel, a green sub-pixel, and a blue sub-pixel; In the repeating unit, the width of the red sub-pixel, the width of the green sub-pixel, and the width of the blue sub-pixel are the same; Alternatively, in the repeating unit, in the first direction, the widths of the N red sub-pixels increase, the widths of the N green sub-pixels increase, and the widths of the N blue sub-pixels increase. Alternatively, in the repeating unit, N is greater than 2, the widths of the N red sub-pixels are equal, the widths of the N green sub-pixels are equal, the width of the first blue sub-pixel is less than the widths of the other blue sub-pixels, and the widths of the other blue sub-pixels except the first blue sub-pixel are equal. Alternatively, in the repeating unit, the width of the red sub-pixel is smaller than the width of the green sub-pixel, the width of the green sub-pixel is smaller than the width of the blue sub-pixel, and in the first direction, the widths of the N blue sub-pixels show an increasing trend; Alternatively, in the repeating unit, the width of the red sub-pixel is less than the width of the green sub-pixel, the width of the green sub-pixel is less than the width of the blue sub-pixel, all the red sub-pixels have equal widths, all the green sub-pixels have equal widths, and all the blue sub-pixels have equal widths.

[0017] According to a second aspect of this application, a display device is provided, which includes the display panel described in any of the above embodiments.

[0018] The display panel and display device of this application embodiment include a pixel circuit layer comprising a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on opposite layers. The second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate, and the third source / drain metal layer is disposed on the side of the second source / drain metal layer away from the substrate. The second source / drain metal layer includes an auxiliary cathode line extending along a second direction, and the third source / drain metal layer includes a partition portion extending along the second direction. An undercut groove extending along the second direction is formed between the partition portion and the auxiliary cathode line. The pixel definition layer includes a first barrier wall and a second barrier wall. The first barrier wall extends along a first direction intersecting the second direction, and the second barrier wall extends along the second direction. The first barrier wall and the second barrier wall are intersected and connected to form a plurality of pixel openings. The second barrier wall is provided with an interface extending along the second direction. The interface connects to the undercut groove and exposes a portion of the auxiliary cathode line and at least a portion of the partition portion. The length of the interface and the length of the undercut groove are both greater than the width of the pixel opening. The cathode extends into the undercut groove through the interface and connects to the auxiliary cathode line.

[0019] It is understood that, in this embodiment of the application, by setting the auxiliary cathode line in the second source / drain metal layer, the auxiliary cathode line is closer to the cathode, reducing the depth of the overlap joint, thereby improving the stability of the cathode overlapping the auxiliary cathode line; secondly, the auxiliary cathode line, the overlap joint, and the bottom cut groove all extend along the second direction, and the length of the overlap joint and the bottom cut groove is greater than the width of the pixel opening, so that the overlap joint can expose a larger area of ​​the auxiliary cathode line, increasing the area of ​​the cathode overlapping the auxiliary cathode line, thereby reducing the cathode voltage drop.

[0020] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0023] Figure 1 This is an equivalent circuit diagram of the pixel circuit provided in the exemplary embodiments of this disclosure; Figure 2 This is a cross-sectional structural diagram of the display panel provided in an exemplary embodiment of this disclosure; Figure 3 This is a top view of the first source / drain metal layer, the second source / drain metal layer, and the first barrier wall in the display panel provided in an exemplary embodiment of this disclosure. Figure 4 This is a top view of the second source / drain metal layer, the third source / drain metal layer, the anode, and the pixel definition layer in the display panel provided in an exemplary embodiment of this disclosure. Figure 5 This is a schematic diagram of a first structure of a repeating unit area in a display panel provided in an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram of a second structure of a repeating unit area in a display panel provided in an exemplary embodiment of this disclosure; Figure 7 This is a schematic diagram of a third structure of a repeating unit area in a display panel provided in an exemplary embodiment of this disclosure; Figure 8 This is a schematic diagram of a fourth structure of a repeating unit area in a display panel provided in an exemplary embodiment of this disclosure; Figure 9 This is a schematic diagram of the fifth structure of the repeating unit area in the display panel provided in the exemplary embodiments of this disclosure; Figure 10-1 This is a schematic diagram of step ST01 of the method for manufacturing a display panel provided in an exemplary embodiment of this disclosure; Figure 10-2 This is a schematic diagram of step ST02 of the method for manufacturing a display panel provided in an exemplary embodiment of this disclosure; Figure 10-3 This is a schematic diagram of step ST03 of the method for manufacturing a display panel provided in an exemplary embodiment of this disclosure; Figure 10-4This is a schematic diagram of step ST04 of the method for manufacturing a display panel provided in an exemplary embodiment of this disclosure; Figure 10-5 This is a schematic diagram of step ST05 of the method for manufacturing a display panel provided in an exemplary embodiment of this disclosure; Figure 10-6 This is a schematic diagram of step ST06 of the method for manufacturing a display panel provided in an exemplary embodiment of this disclosure; Figure 11 This is a schematic diagram of the structure of a display device provided in an exemplary embodiment of this disclosure.

[0024] Explanation of reference numerals in the attached figures: Display panel 100; pixel circuit Px; sub-pixel EL; driving transistor T0; first transistor T1; second transistor T2; third transistor T3; fourth transistor T4; fifth transistor T5; sixth transistor T6; first storage capacitor C1; second storage capacitor C2; first node C; second node Q; third node A; fourth node B; fifth node D; data line 053; power line 052; first reset line V01; second reset line V02; third reset line V03; second scan line S02; third scan line S03; fourth scan line S04; substrate 11; pixel circuit layer 12; light-emitting device layer 13; buffer layer 121; active layer 122; first insulating layer 123; first metal layer 101; second insulating layer 124; second metal layer 102; third insulating layer 125; third metal layer 103 Fourth insulating layer 126; First source / drain metal layer 104; First planarization layer 128; Second source / drain metal layer 105; Passivation layer 127; Third source / drain metal layer 106; Second planarization layer 129; Pixel opening K1; Anode 131; Light-emitting layer 132; Cathode 133; Pixel definition layer 134; First barrier B01; Second barrier B02; First direction F1; Second direction F2; Auxiliary cathode line 051; Partition 061; Interlocking interface K2; Bottom groove ud1; Pixel P1; Repeating unit U1; Red sub-pixel ps1; Green sub-pixel ps2; Blue sub-pixel ps3; First adapter 054; First opening kk1; First via gk1; Second opening kk2; Second via gk2; Second adapter 062; Third opening kk3; Photoresist layer PR; Fourth opening kk4; Display device 1000. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0026] This application provides a display panel 100, wherein the pixel circuit Px of the display panel 100 in this embodiment consists of seven or more transistors. The pixel circuit Px is configured to control the emission of light from the sub-pixels EL of the display panel 100. An example is... Figure 1 As shown, but not limited to, other embodiments such as 7T2C or 7T1C, or 9T1C and 9T2C, etc.

[0027] exist Figure 1 In the pixel circuit Px, there are driving transistor T0, first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, first storage capacitor C1 and second storage capacitor C2.

[0028] The gate of driving transistor T0, the second terminal of the third transistor T3, one end of the first storage capacitor C1, and the second terminal of the fourth transistor T4 are connected to the second node Q. The first terminal of driving transistor T0 and one end of the second storage capacitor C2 are connected to the third node A. The second terminal of driving transistor T0, the first terminal of the third transistor T3, and the first terminal of the first transistor T1 are connected to the fourth node B. The second terminal of the first transistor T1 and the second terminal of the second transistor T2 are connected. The other end of the first storage capacitor C1, the other end of the second storage capacitor C2, the second terminal of the fifth transistor T5, and the second terminal of the sixth transistor T6 are connected to the fifth node D.

[0029] The gate of the first transistor T1 is configured to receive the light emission control signal EM. The gate of the second transistor T2 is configured to receive the first scan signal SN1. The gate of the third transistor T3 is configured to receive the second scan signal SN2. The gate of the fourth transistor T4 is configured to receive the third scan signal SN3. The gate of the fifth transistor T5 is configured to receive the second scan signal SN2. The gate of the sixth transistor T6 is configured to receive the fourth scan signal SN4.

[0030] The first terminal of the second transistor T2 is configured to receive the first reset signal VI1. The first terminal of the fourth transistor T4 is configured to receive the second reset signal VI2. The first terminal of the fifth transistor T5 is configured to receive the third reset signal VI3. The first terminal of the sixth transistor T6 is configured to receive the data signal DA. The third node A is configured to receive the power supply signal VDD.

[0031] Sub-pixel EL, the second terminal of the first transistor T1, and the second terminal of the second transistor T2 are connected to the first node C.

[0032] Specifically, the signal line connected to the data signal DA is data line 053. The signal line connected to the power signal VDD is power line 052. The signal line connected to the light emission control signal EM is the light emission control line. The signal line connected to the first reset signal VI1 is the first reset line V01. The signal line connected to the second reset signal VI2 is the second reset line V02. The signal line connected to the third reset signal VI3 is the third reset line V03. The signal line connected to the first scan signal SN1 is the first scan line. The signal line connected to the second scan signal SN2 is the second scan line S02. The signal line connected to the third scan signal SN3 is the third scan line S03. The signal line connected to the fourth scan signal SN4 is the fourth scan line S04.

[0033] Optionally, the driving transistor T0 is used to output a driving current corresponding to the data signal, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be switching transistors for transmitting signals. The first terminal of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be either a source or a drain, and the second terminal of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a different terminal from the first terminal. For example, if the first terminal is a drain, the second terminal can be a source.

[0034] In one embodiment, at least one of the driving transistors T0, T1, T2, T3, T4, T5, and T6 can be a P-channel field-effect transistor (PMOS), and the other transistors can be N-channel field-effect transistors (NMOS). For example, T1 can be a PMOS, and T0, T5, T2, T3, T4, and T6 can be NMOS. In another embodiment, all of the driving transistors T0, T1, T2, T3, T4, T5, and T6 can be NMOS.

[0035] For example, the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all PMOS transistors that include silicon semiconductors. However, this is not the case. For example, some of the driving transistors T0, T1, T2, T3, T4, T5, and T6 may be PMOS transistors that include silicon semiconductors, while the other transistors may be NMOS transistors that include oxide semiconductors. Alternatively, all of the driving transistors T0, T1, T2, T3, T4, T5, and T6 may be NMOS transistors that include oxide semiconductors.

[0036] Please refer to Figure 2 ,exist Figure 2 In the display panel 100, there are a substrate 11, a pixel circuit layer 12, and a light-emitting device layer 13. The pixel circuit layer 12 is disposed on the substrate 11, and the light-emitting device layer 13 is disposed on the side of the pixel circuit layer 12 away from the substrate 11. The pixel circuit layer 12 includes a plurality of pixel circuits Px.

[0037] The pixel circuit layer 12 includes a buffer layer 121, an active layer 122, a first insulating layer 123, a first metal layer 101, a second insulating layer 124, a second metal layer 102, a third insulating layer 125, a third metal layer 103, a fourth insulating layer 126, a first source / drain metal layer 104, a first planarization layer 128, a second source / drain metal layer 105, a passivation layer 127, a third source / drain metal layer 106, and a second planarization layer 129, which are stacked sequentially.

[0038] In some embodiments of this application, the light-emitting device layer 13 includes a pixel definition layer 134 and sub-pixels EL. The pixel definition layer 134 is disposed on the side of the second planarization layer 129 away from the substrate 11. The pixel definition layer 134 is provided with a pixel opening K1.

[0039] Optionally, the sub-pixel EL may include an anode 131, a light-emitting layer 132, and a cathode 133 on the pixel circuit layer 12. The light-emitting layer 132 is disposed within the pixel opening K1.

[0040] The light-emitting layer 132 may include an emission layer. The emission layer may be formed within the pixel opening K1 using inkjet printing. In some embodiments, the light-emitting layer 132 may further include an emission layer and a functional layer. The functional layer may include a hole transport layer, a hole injection layer, an electron transport layer, and / or an electron injection layer. In some other embodiments, the light-emitting layer 132 may include a first stack containing an emission layer and a functional layer, a second stack containing an emission layer and a functional layer, and a charge generation layer located between the first and second stacks. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The negative and positive charge generation layers can further improve the emission efficiency of a series-connected light-emitting diode with an emission layer.

[0041] Optionally, in some embodiments, the pixel definition layer 134 includes a first barrier wall B01 and a second barrier wall B02 disposed in different or the same layers. A plurality of first barrier walls B01 extend along a first direction F1 and are arranged along a second direction F2. A plurality of second barrier walls B02 extend along a second direction F2 and are arranged along a first direction F1. The plurality of first barrier walls B01 and the plurality of second barrier walls B02 are cross-connected to form a plurality of pixel openings K1.

[0042] For example, the second barrier wall B02 and the first barrier wall B01 are disposed in different layers, and the second barrier wall B02 is disposed on the side of the first barrier wall B01 away from the substrate 11. Based on the linear inkjet printing process, the sub-pixels EL in the same column have the same color, and the thickness of the second barrier wall B02 is greater than the thickness of the first barrier wall B01 to avoid overflow and mixing of ink materials of different colors.

[0043] Please refer to Figure 3 , Figure 3 This is a top view of the first source / drain metal layer 104, the second source / drain metal layer 105, and the first barrier wall B01 in the display panel 100 provided in the exemplary embodiment of this disclosure.

[0044] The first source / drain metal layer 104 includes a first reset line V01, a second reset line V02, a third reset line V03, a second scan line S02, a third scan line S03, and a fourth scan line S04 extending along a first direction F1.

[0045] The second source / drain metal layer 105 includes a data line 053, a power line 052, and an auxiliary cathode line 051 extending along the second direction F2.

[0046] Optionally, the first direction F1 and the second direction F2 intersect. For example, the first direction F1 is perpendicular to the second direction F2.

[0047] Understandably, given the complex routing of the pixel circuit Px, many horizontally extending scan lines and reset lines are placed in the first source-drain metal layer 104, while the vertically extending data lines 053, power lines 052, and auxiliary cathode lines 051 are placed in the second source-drain metal layer 105 to reduce the layout area of ​​the pixel circuit Px.

[0048] Please refer to Figure 4 And combined Figure 2 , Figure 4 This is a top view of the second source / drain metal layer 105, anode 131, and pixel definition layer 134 in the display panel 100 provided in an exemplary embodiment of this disclosure.

[0049] This application provides a display panel 100, which includes a substrate 11, a pixel circuit layer 12, a pixel definition layer 134, and a cathode 133.

[0050] The pixel circuit layer 12 includes a first source / drain metal layer 104, a second source / drain metal layer 105, and a third source / drain metal layer 106 disposed on opposite layers. The second source / drain metal layer 105 is located on the side of the first source / drain metal layer 104 away from the substrate 11, and the third source / drain metal layer 106 is disposed on the side of the second source / drain metal layer 105 away from the substrate 11. The second source / drain metal layer 105 includes an auxiliary cathode line 051 extending along a second direction F2, and the third source / drain metal layer 106 includes a partition portion 061 extending along the second direction F2. An undercut groove ud1 extending along the second direction F2 is formed between the partition portion 061 and the auxiliary cathode line 051.

[0051] A pixel definition layer 134 is disposed on the side of the pixel P1 circuit layer away from the substrate 11. The pixel definition layer 134 includes a first barrier B01 and a second barrier B02. The first barrier B01 extends along a first direction F1 intersecting a second direction F2, and the second barrier B02 extends along the second direction F2. The first barrier B01 and the second barrier B02 are intersected and connected to form a plurality of pixel openings K1. The second barrier B02 is provided with an interface K2 extending along the second direction F2. The interface K2 connects to the undercut groove ud1 and exposes a portion of the auxiliary cathode line 051 and at least a portion of the partition portion 061. The length L1 of the interface K2 and the length L2 of the undercut groove ud1 are both greater than the width N4 of the pixel openings K1.

[0052] The cathode 133 is disposed on the side of the pixel definition layer 134 away from the substrate 11. The cathode 133 extends into the bottom notch ud1 through the interface K2 and is connected to the auxiliary cathode line 051.

[0053] It is understood that, in this embodiment of the application, by setting the auxiliary cathode line 051 in the second source / drain metal layer 105, the auxiliary cathode line 051 is closer to the cathode 133, reducing the depth of the overlap interface K2, thereby improving the stability of the cathode 133 overlapping the auxiliary cathode line 051; secondly, the auxiliary cathode line 051, the undercut groove ud1, and the overlap interface K2 all extend along the second direction F2, and the lengths of the overlap interface K2 and the undercut groove ud1 are greater than the width of the pixel opening K1, so that the overlap interface K2 can expose more area of ​​the auxiliary cathode line 051, increasing the area of ​​the cathode 133 overlapping the auxiliary cathode line 051, thereby reducing the voltage drop of the cathode 133.

[0054] Optionally, in some embodiments of this application, the pixel P1 circuit layer further includes a first planarization layer 128, a passivation layer 127, and a second planarization layer 129. The first planarization layer 128 is disposed between the first source / drain metal layer 104 and the second source / drain metal layer 105, the passivation layer 127 is disposed between the second source / drain metal layer 105 and the third source / drain metal layer 106, and the second planarization layer 129 covers the third source / drain metal layer 106 and the passivation layer 127. The pixel definition layer 134 is disposed on the side of the second planarization layer 129 away from the substrate 11. The interface K2 also penetrates through the second planarization layer 129 and the passivation layer 127.

[0055] In the first direction F1, the width of the portion of interface K2 in the pixel definition layer 134 is greater than the width of the portion of interface K2 in the second planarization layer 129, the width of the portion of interface K2 in the second planarization layer 129 is greater than the width of the portion of interface K2 in the passivation layer 127, and the portion of interface K2 in the passivation layer 127 is connected to the bottom cut groove ud1.

[0056] Understandably, the width of the interface K2 decreases layer by layer, resulting in an inclined stepped slope on the sidewall of the interface K2, in order to reduce the risk of the cathode 133 and the light-emitting layer 132 breaking off on the sidewall of the interface K2.

[0057] Optionally, in some embodiments of this application, in the second direction F2, the length L1 of the overlapping interface K2 and the length L2 of the bottom groove ud1 are both equal to the distance between two adjacent first retaining walls B01.

[0058] It is understandable that the length L1 of the overlap interface K2 and the length L2 of the bottom groove ud1 are equal to the distance between the two adjacent first retaining walls B01, so that the length L1 of the overlap interface K2 and the length L2 of the bottom groove ud1 are maximized as much as possible, thereby increasing the overlap area of ​​the cathode 133 and the auxiliary cathode line 051 and reducing the voltage drop of the cathode 133.

[0059] Optionally, in some embodiments of this application, in the first direction F1, the width N1 of the auxiliary cathode line 051 is greater than the width N2 of the partition portion 061, and a portion of the auxiliary cathode line 051 extends beyond the partition portion 061.

[0060] It is understandable that the width of the auxiliary cathode line 051 is greater than that of the partition 061 and extends beyond the partition 061, making the width of the auxiliary cathode line 051 larger and increasing the area of ​​the auxiliary cathode line 051, thereby reducing the voltage drop of the cathode 133.

[0061] Optionally, in some embodiments of this application, in the first direction F1, the width of the portion of the auxiliary cathode line 051 that extends beyond the partition portion 061 and is close to the bottom groove ud1 is greater than the width N2 of the partition portion 061.

[0062] It is understandable that the width of the portion of the auxiliary cathode line 051 that extends beyond the partition 061 is greater than the partition 061, so as to further increase the width N1 of the auxiliary cathode line 051, thereby reducing the voltage drop of the cathode 133.

[0063] Optionally, in some embodiments of this application, in the first direction F1, the opposite sides of the auxiliary cathode line 051 extend beyond the partition portion 061, and the width of the portion of the auxiliary cathode line 051 that extends beyond the partition portion 061 and is far from the bottom groove ud1 is less than the width N2 of the partition portion 061.

[0064] Understandably, the auxiliary cathode line 051 extends beyond the partition portion 061 on both sides to further increase its width, thereby reducing the voltage drop of the cathode 133. Secondly, the portion of the auxiliary cathode line 051 furthest from the bottom groove ud1 has a smaller width to prevent it from becoming too wide, thus achieving high resolution.

[0065] Optionally, in some embodiments of this application, in the first direction F1, the width N1 of the auxiliary cathode line 051 is greater than the width N3 of the second retaining wall B02 forming the overlapping interface K2.

[0066] Understandably, the auxiliary cathode line 051 has a larger width, while the second barrier wall B02 forming the interface K2 has a smaller width, in order to reduce the voltage drop of the cathode 133 and at the same time reduce the size of the second barrier wall B02 to facilitate the achievement of high resolution.

[0067] Optionally, in some embodiments of this application, multiple interfaces K2 are spaced apart on the second direction F2, and the cathode 133 is connected to an auxiliary cathode line 051 through the multiple interfaces K2.

[0068] It is understandable that the cathode 133 is connected to an auxiliary cathode line 051 through multiple interface K2, so that the cathode 133 and the auxiliary cathode line 051 are connected in parallel to reduce the voltage drop of the cathode 133.

[0069] Optionally, in some embodiments of this application, the width of the interface K2 in the first direction F1 is smaller than the width of the opening K1 of each pixel, so as to achieve high resolution.

[0070] Optionally, in some embodiments of this application, the display panel 100 includes a plurality of pixels P1, and each pixel P1 includes at least three sub-pixels EL. Each sub-pixel EL is correspondingly disposed within the area of ​​a pixel opening K1.

[0071] In the first direction F1, an auxiliary cathode line 051 is set between two adjacent sub-pixels EL, and every N consecutive pixels P1 form a repeating unit U1. Each repeating unit U1 is provided with one auxiliary cathode line 051, where 2≤N≤5, and N is an integer.

[0072] It is understandable that, compared to inserting an auxiliary cathode line 051 in each pixel P1, the embodiments of this application insert an auxiliary cathode line 051 in at least two pixels P1 to achieve higher resolution.

[0073] For example, an auxiliary cathode line 051 may be inserted in every two pixels P1, or in every three pixels P1, or in every four pixels P1, or in every five pixels P1.

[0074] Optionally, such as Figure 7 and Figure 8 In some embodiments of this application, at least three sub-pixels EL of pixel P1 include red sub-pixel ps1, green sub-pixel ps2, and blue sub-pixel ps3.

[0075] In the repeating unit U1, the auxiliary cathode line 051 is set adjacent to the first blue sub-pixel ps3, and the width of the first blue sub-pixel ps3 is smaller than the width of the other blue sub-pixels ps3.

[0076] It is understandable that, given the equal arrangement area of ​​the pixel circuit Px corresponding to each blue sub-pixel ps3, the blue sub-pixel ps3 with the smallest width has more unused space. Therefore, in this embodiment, the auxiliary cathode line 051 is positioned adjacent to the column of blue sub-pixels ps3 with the smallest width. This utilizes the unused area of ​​the smallest blue sub-pixel ps3 to set up the auxiliary cathode line 051, saving layout area, increasing aperture ratio, and thus facilitating high resolution. Secondly, the human eye is not very sensitive to blue light; therefore, positioning the auxiliary cathode line 051 adjacent to the blue sub-pixels ps3 reduces the impact of reflection from the auxiliary cathode line 051 on the display effect.

[0077] Optionally, in some embodiments of this application, such as Figure 5 As shown, in the repeating unit U1, the width of the red sub-pixel ps1, the width of the green sub-pixel ps2, and the width of the blue sub-pixel ps3 are the same.

[0078] Understandably, the red subpixel ps1, green subpixel ps2, and blue subpixel ps3 have the same width to achieve high resolution. Optionally, the width of the red subpixel ps1, green subpixel ps2, and blue subpixel ps3 can be greater than or equal to 14.3 micrometers, such as 14.3 micrometers, 14.5 micrometers, 15 micrometers, etc.

[0079] Alternatively, in some embodiments, such as Figure 6 As shown, in the repeating unit U1, in the first direction F1, the widths of the N red sub-pixels ps1 increase, the widths of the N green sub-pixels ps2 increase, and the widths of the N blue sub-pixels ps3 increase.

[0080] It is understandable that increasing the width of the sub-pixel EL can reduce power consumption at the same brightness.

[0081] Alternatively, in some embodiments, such as Figure 7 As shown, in the repeating unit U1, N is greater than 2, the widths of the N red sub-pixels ps1 are equal, and the widths of the N green sub-pixels ps2 are equal. The width of the first blue sub-pixel ps3 is smaller than the widths of the other blue sub-pixels ps3, and the widths of the other blue sub-pixels ps3 are equal.

[0082] Alternatively, in some embodiments, such as Figure 8 As shown, in the repeating unit U1, the width of the red sub-pixel ps1 is smaller than the width of the green sub-pixel ps2, the width of the green sub-pixel ps2 is smaller than the width of the blue sub-pixel ps3, and in the first direction F1, the widths of the N blue sub-pixels ps3 show an increasing trend.

[0083] Alternatively, in some embodiments, such as Figure 9 As shown, in the repeating unit U1, the width of the red sub-pixel ps1 is smaller than the width of the green sub-pixel ps2, the width of the green sub-pixel ps2 is smaller than the width of the blue sub-pixel ps3, and in the first direction F1, the widths of the N blue sub-pixels ps3 show an increasing trend.

[0084] Alternatively, in repeating unit U1, the width of red sub-pixel ps1 is less than the width of green sub-pixel ps2, the width of green sub-pixel ps2 is less than the width of blue sub-pixel ps3, the width of all red sub-pixels ps1 is equal, the width of all green sub-pixels ps2 is equal, and the width of all blue sub-pixels ps3 is equal.

[0085] It should be noted that the method for manufacturing the display panel 100 in this embodiment includes the following steps: For step ST01, please refer to... Figure 10-1 A buffer layer 121, a patterned active layer 122, a first insulating layer 123, a patterned first metal layer 101, a second insulating layer 124, a patterned second metal layer 102, a third insulating layer 125, a patterned third metal layer 103, a fourth insulating layer 126, a patterned first source / drain metal layer 104, a first planarization layer 128, a second patterned second source / drain metal layer 105, a patterned passivation layer 127, and a third source / drain metal layer 106 are sequentially formed on the substrate 11.

[0086] Optionally, the patterned passivation layer 127 has a first opening kk1. The first opening kk1 includes an auxiliary cathode line 051 and a first transition portion 054. The third source / drain metal layer 106 includes a partition portion 061 and a second transition portion 062, with the partition portion 061 disposed adjacent to the first opening kk1. The first transition portion 054 is connected to the second transition portion 062 through a first via gk1, and the second transition portion 062 is connected to the pixel circuit Px.

[0087] Optionally, the third source / drain metal layer 106 can be patterned using a photolithography process, wherein wet etching can be used for patterning.

[0088] Then proceed to step ST02.

[0089] For step ST02, please refer to... Figure 10-2 A patterned first planarization layer 128 is formed on the passivation layer 127.

[0090] The patterned first planarization layer 128 is provided with a second opening kk2 and a second via gk2. The width of the second opening kk2 is greater than the width of the first opening kk1. The second opening kk2 connects to the first opening kk1 and exposes the portion of the partition 061 near the first opening kk1. The second via gk2 exposes the second transition portion 062.

[0091] Optionally, the first planarization layer 128 can be patterned using a photolithography process.

[0092] Then proceed to step ST03.

[0093] For step ST03, please refer to... Figure 10-3 An anode 131 and a pixel definition layer 134 are sequentially formed on the first planarization layer 128. The pixel definition layer 134 has a pixel opening K1 and a third opening Kk3. The third opening Kk3, the second opening Kk2, and the first opening Kk1 are connected to form an interface K2. The width of the third opening Kk3 is greater than the width of the second opening Kk2.

[0094] Then proceed to step ST04.

[0095] For step ST04, please refer to... Figure 10-4 A patterned photoresist layer PR is formed on the pixel definition layer 134 and a passivation layer 127 is etched to form an undercut groove ud1. Finally, the photoresist layer PR is removed.

[0096] The photoresist layer PR has a fourth opening kk4, which includes the sidewall of the partition portion 061, the sidewall of the first opening kk1 near the partition portion 061, and a portion of the auxiliary cathode line 051. The sidewall of the other side of the first opening kk1 is covered by the photoresist layer PR. Subsequently, a wet etching process is used to etch the passivation layer 127 exposed to the first opening kk1 to form an undercut groove ud1.

[0097] Then proceed to step ST05.

[0098] For step ST05, please refer to... Figure 10-5 An emissive layer 132 is formed on the pixel definition layer 134.

[0099] The light-emitting material layer of the light-emitting layer 132 is formed by inkjet printing. The hole functional layer and the electron functional layer can be formed by vapor deposition. However, it is not limited to this; in some other embodiments, the light-emitting material layer can be formed by vapor deposition. The light-emitting layer 132 is broken at the partition 061, and the light-emitting layer 132 does not enter the bottom groove ud1.

[0100] Then proceed to step ST06.

[0101] For step ST06, please refer to... Figure 10-6 A cathode 133 is formed on the light-emitting layer 132.

[0102] The cathode 133 is disconnected at the partition and extends into the bottom groove ud1 and connects to the auxiliary cathode line 051.

[0103] Optionally, the cathode 133 can be prepared using a sputtering process.

[0104] Based on this, steps ST01 to ST06 complete the process of connecting the cathode 133 to the auxiliary cathode wire 051.

[0105] Please refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of a display device 1000 provided in an exemplary embodiment of the present disclosure. According to a second aspect of this application, a display device 1000 is provided, which includes a display panel 100 as described in any of the above embodiments.

[0106] It should be noted that the structure of the display panel 100 of the display device 1000 provided in this application embodiment is the same as the structure of the display panel 100 provided in the above embodiments of this application. For details, please refer to... Figures 1 to 10-6 Therefore, the relevant explanations will not be repeated here.

[0107] Display device 1000 can be at least one of the following: smartphone, tablet, mobile phone, video phone, e-book reader, desktop computer, laptop, netbook, workstation, server, personal digital assistant, portable media player, MP3 player, television, mobile medical device, camera, game console, digital camera, car navigation system, in-vehicle display screen, electronic billboard, ATM, or wearable device, VR device, AR device.

[0108] The display panel 100 and display device 1000 of this application embodiment include a pixel circuit layer 12 comprising a first source / drain metal layer 104, a second source / drain metal layer 105, and a third source / drain metal layer 106 disposed on opposite layers. The second source / drain metal layer 105 is located on the side of the first source / drain metal layer 104 away from the substrate 11, and the third source / drain metal layer 106 is disposed on the side of the second source / drain metal layer 105 away from the substrate 11. The second source / drain metal layer 105 includes an auxiliary cathode line 051 extending along a second direction F2, and the third source / drain metal layer 106 includes a partition portion 061 extending along the second direction F2. A space is formed between the partition portion 061 and the auxiliary cathode line 051. A bottom-cut groove ud1 extends along a second direction F2; the pixel definition layer 134 includes a first barrier B01 and a second barrier B02. The first barrier B01 extends along a first direction F1 intersecting the second direction F2, and the second barrier B02 extends along the second direction F2. The first barrier B01 and the second barrier B02 are intersected and connected to form a plurality of pixel openings K1. The second barrier B02 is provided with an interface K2 extending along the second direction F2. The interface K2 connects to the bottom-cut groove ud1 and exposes a portion of the auxiliary cathode line 051 and at least a portion of the partition 061. The length of the interface K2 and the length of the bottom-cut groove ud1 are both greater than the width of the pixel openings K1. The cathode 133 extends into the bottom-cut groove ud1 through the interface K2 and connects to the auxiliary cathode line 051.

[0109] It is understood that, in this embodiment of the application, by setting the auxiliary cathode line 051 in the second source / drain metal layer 105, the auxiliary cathode line 051 is closer to the cathode 133, reducing the depth of the overlap interface K2, thereby improving the stability of the cathode 133 overlapping the auxiliary cathode line 051; secondly, the auxiliary cathode line 051, the overlap interface K2, and the bottom cut groove ud1 all extend along the second direction F2, and the lengths of the overlap interface K2 and the bottom cut groove ud1 are greater than the width of the pixel opening K1, so that the overlap interface K2 can expose more area of ​​the auxiliary cathode line 051, increasing the area of ​​the cathode 133 overlapping the auxiliary cathode line 051, thereby reducing the voltage drop of the cathode 133.

[0110] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0111] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0112] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0113] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: Substrate; A pixel circuit layer is disposed on the substrate. The pixel circuit layer includes a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on opposite layers. The second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate. The third source / drain metal layer is disposed on the side of the second source / drain metal layer away from the substrate. The second source / drain metal layer includes an auxiliary cathode line extending along a second direction. The third source / drain metal layer includes a partition portion extending along the second direction. An undercut groove extending along the second direction is formed between the partition portion and the auxiliary cathode line. A pixel definition layer is disposed on the side of the pixel circuit layer away from the substrate. The pixel definition layer includes a first barrier and a second barrier. The first barrier extends along a first direction intersecting the second direction, and the second barrier extends along the second direction. The first barrier and the second barrier are intersected and connected to form a plurality of pixel openings. The second barrier is provided with an interface extending along the second direction. The interface connects to the undercut groove and exposes a portion of the auxiliary cathode line and at least a portion of the partition. The length of the interface and the length of the undercut groove are both greater than the width of the pixel opening. A cathode is disposed on the side of the pixel definition layer away from the substrate, and the cathode extends into the undercut groove through the interface and is connected to the auxiliary cathode line.

2. The display panel according to claim 1, characterized in that, In the second direction, the length of the overlapping joint and the length of the bottom groove are both equal to the distance between two adjacent first retaining walls.

3. The display panel according to claim 1, characterized in that, In the first direction, the width of the auxiliary cathode line is greater than the width of the partition, and a portion of the auxiliary cathode line extends beyond the partition.

4. The display panel according to claim 3, characterized in that, In the first direction, the width of the portion of the auxiliary cathode line that extends beyond the partition and is close to the bottom groove is greater than the width of the partition.

5. The display panel according to claim 4, characterized in that, In the first direction, the opposite sides of the auxiliary cathode line extend beyond the partition, and the width of the portion of the auxiliary cathode line that extends beyond the partition and is far from the bottom groove is smaller than the width of the partition.

6. The display panel according to claim 5, characterized in that, In the first direction, the width of the auxiliary cathode line is greater than the width of the second retaining wall forming the interface.

7. The display panel according to any one of claims 1-6, characterized in that, In the second direction, a plurality of the contact joints are spaced apart, and the cathode is connected to an auxiliary cathode line through the plurality of contact joints.

8. The display panel according to any one of claims 1-6, characterized in that, The pixel circuit layer further includes a first planarization layer, a passivation layer, and a second planarization layer. The first planarization layer is disposed between the first source / drain metal layer and the second source / drain metal layer. The passivation layer is disposed between the second source / drain metal layer and the third source / drain metal layer. The second planarization layer covers the third source / drain metal layer and the passivation layer. The pixel definition layer is disposed on the side of the second planarization layer away from the substrate. The interface also penetrates through the second planarization layer and the passivation layer. Wherein, the width of the portion of the interface at the pixel definition layer is greater than the width of the portion of the interface at the second flat layer, the width of the portion of the interface at the second flat layer is greater than the width of the portion of the interface at the passivation layer, and the portion of the interface at the passivation layer is connected to the bottom notch.

9. The display panel according to any one of claims 1-6, characterized in that, The display panel includes a plurality of pixels, and each pixel includes at least three sub-pixels, and each sub-pixel is correspondingly disposed within the opening area of ​​the pixel. In the first direction, the auxiliary cathode line is disposed between two adjacent sub-pixels, and each N consecutive pixels form a repeating unit. Each repeating unit is provided with one auxiliary cathode line, where 2≤N≤5 and N is an integer.

10. The display panel according to claim 9, characterized in that, The pixel's at least three sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel; In the repeating unit, the auxiliary cathode line is disposed adjacent to the first blue sub-pixel, and the width of the first blue sub-pixel is smaller than the width of the other blue sub-pixels.

11. The display panel according to claim 9, characterized in that, The pixel's at least three sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel; In the repeating unit, the width of the red sub-pixel, the width of the green sub-pixel, and the width of the blue sub-pixel are the same; Alternatively, in the repeating unit, in the first direction, the widths of the N red sub-pixels increase, the widths of the N green sub-pixels increase, and the widths of the N blue sub-pixels increase. Alternatively, in the repeating unit, N is greater than 2, the widths of the N red sub-pixels are equal, the widths of the N green sub-pixels are equal, the width of the first blue sub-pixel is less than the widths of the other blue sub-pixels, and the widths of the other blue sub-pixels except the first blue sub-pixel are equal. Alternatively, in the repeating unit, the width of the red sub-pixel is smaller than the width of the green sub-pixel, the width of the green sub-pixel is smaller than the width of the blue sub-pixel, and in the first direction, the widths of the N blue sub-pixels show an increasing trend; Alternatively, in the repeating unit, the width of the red sub-pixel is less than the width of the green sub-pixel, the width of the green sub-pixel is less than the width of the blue sub-pixel, all the red sub-pixels have equal widths, all the green sub-pixels have equal widths, and all the blue sub-pixels have equal widths.

12. A display device, characterized in that, Includes the display panel as described in any one of claims 1-11.

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