Display device

Abstract

A display device includes a substrate including a through-hole; a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer over the substrate; a first metal layer over the thin film transistor; a second metal layer over the first metal layer; a light-emitting layer over the second metal layer; a protective film over the light-emitting layer; a wiring region surrounding the through-hole; a first signal line formed in a same layer as the first metal layer and provided in the wiring region; and a weir portion provided between the through-hole and the first signal line, wherein the semiconductor layer includes an oxide semiconductor material.

Description

[0001] Cross-references to related applications

[0002] This application is a divisional application of the invention patent application filed on December 22, 2021, with application number 202111581179.0 and title "Display Device". Technical Field

[0003] The present invention relates to a display device, and more specifically, to a display device comprising a through hole in a display area for displaying an image. Background Technology

[0004] Recently, with the advent of the information society, the field of display technology that visually presents electrical signals has developed rapidly. As a result, various flat panel display devices with excellent performance such as thin shape, light weight and low power consumption have been developed, and these flat panel display devices have replaced traditional cathode ray tubes (CRTs).

[0005] Specific examples of flat panel display devices include liquid crystal display (LCD), plasma display panel (PDP), field-emitting diode (FED) display, and organic light-emitting diode (OLED).

[0006] Organic light-emitting displays (OLEDs) are self-emissive devices with excellent viewing angles. Therefore, OLEDs have attracted considerable attention as a next-generation display technology.

[0007] Organic light-emitting display devices are used in a variety of electronic devices, such as televisions, smartphones, e-books, monitors, and laptops.

[0008] As organic light-emitting display devices are used in various electronic devices, there is an increasing demand for technology that increases the proportion of the display area used to provide images and relatively reduces the peripheral area that does not provide images when designing the form of organic light-emitting display devices.

[0009] Therefore, organic light-emitting display devices include holes in the display area where electronic components (such as cameras, light-sensing elements, and / or heat-sensing elements) are located. Since the holes are formed in the display area, a hole bezel is formed around the holes where the electronic components are located, serving as dead space for various lines.

[0010] Recently, there has been a demand for technologies to reduce the bezel size of holes. Summary of the Invention

[0011] Therefore, the present invention aims to provide a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of related technologies.

[0012] One advantage of the present invention is that it provides an organic light-emitting display device that can reduce the aperture border of the display device (which includes holes in the display area where electronic components are located) and improve current deviation, thereby improving brightness uniformity and reliability.

[0013] Additional features and advantages of the invention will be set forth in part in the description which follows, some of which will become apparent upon study of the following or may be learned by practice of the invention. These and other advantages of the invention may be realized and obtained by means of the structures specifically pointed out in the specification, its claims, and the accompanying drawings.

[0014] To achieve these and other advantages and in accordance with the intent of the invention, as embodied and broadly described herein, a display device includes: a substrate including a through-hole; a thin-film transistor on the substrate including a gate, a source, a drain, and a semiconductor layer; a first metal layer on the thin-film transistor; a second metal layer on the first metal layer; a light-emitting layer on the second metal layer; a protective film on the light-emitting layer; a line region surrounding the through-hole; a first signal line formed in the same layer as the first metal layer and disposed in the line region; and a weir disposed between the through-hole and the first signal line, wherein the semiconductor layer comprises an oxide semiconductor material.

[0015] On the other hand, a display device includes: a through-hole; a line region surrounding the through-hole; a display region surrounding the line region; a first layer line, a second layer line, a third layer line, and a fourth layer line located in the line region and in different layers; a plurality of auxiliary layer lines located below the first layer line or on the fourth layer line; a plurality of pixels located in the display region; a plurality of first signal lines electrically connected to the pixels and arranged along a first direction; and a plurality of second signal lines electrically connected to the pixels and arranged along a second direction intersecting the first direction, wherein the auxiliary layer lines are electrically connected to one of the second signal lines.

[0016] It should be understood that the foregoing general description and the following detailed description of the invention are illustrative and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0017] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and form a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0018] Figure 1 This is a schematic diagram illustrating an organic light-emitting display device according to an embodiment of the present invention;

[0019] Figure 2It is a schematic diagram. Figure 1 A view of region A;

[0020] Figure 3 This is a schematic cross-sectional view illustrating the through hole and hole frame area according to an embodiment of the present invention;

[0021] Figure 4 This is a cross-sectional view of the pixel structure and the hole frame region of the organic light-emitting display device according to the first embodiment of the present invention.

[0022] Figure 5 This is a cross-sectional view of the pixel structure and the hole frame region of the organic light-emitting display device according to the second embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram illustrating the structure of the hole frame region and the auxiliary electrode according to the second embodiment of the present invention. Detailed Implementation

[0024] The description now refers in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The same reference numerals are used throughout the drawings to refer to the same or similar parts.

[0025] Figure 1 This is a schematic diagram illustrating an organic light-emitting display device according to an embodiment of the present invention.

[0026] Before proceeding with the detailed description, a portable terminal is shown as an example of the application of the organic light-emitting display device 100 according to this embodiment. The portable terminal may be a tablet PC, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a game console, a watch-type electronic device, etc.

[0027] However, the present invention is not limited to the specific electronic devices to which the organic light-emitting display device 100 is applied. For example, in another embodiment of the present invention, the organic light-emitting display device 100 can be used in large-sized electronic devices such as televisions or outdoor billboards, or in small or medium-sized electronic devices such as personal computers, laptops, vehicle navigation devices, smartwatches, or cameras.

[0028] Reference Figure 1 According to an embodiment of the present invention, an organic light-emitting display device may include a display area AA for displaying an image and a non-display area NA located outside the display area AA.

[0029] The display area AA can be composed of multiple pixels. Figure 2 A pixel P is an area used to display an image. A pixel P may include pixel circuitry and an organic light-emitting diode that is energized to emit light.

[0030] The non-display area NA can be the area surrounding the display area AA. Within the non-display area NA, a gate driving unit (not shown) and a data driving unit (not shown) can be provided for providing corresponding signals to each of the plurality of pixels P. The gate driving unit can be a component that applies gate signals and can be provided on one or both sides in the lateral (or horizontal) direction relative to the display area AA. The data driving unit can be a component that applies data signals and can be provided on one or both sides in the longitudinal (vertical) direction relative to the display area AA.

[0031] The through hole 210 may be located in the display area AA. At least one electronic component may be placed in the through hole 210. The electronic component may be a camera, a speaker, a light sensor, a heat sensor, a microphone, etc.

[0032] exist Figure 1 The diagram illustrates, by way of example, a circular through-hole 210 formed in the center of the upper part of the display area AA. However, the position, shape, and number of through-holes 210 are not limited. Through-holes 210 can have one of various shapes, including polygonal shapes such as quadrilaterals and ellipses.

[0033] The hole bezel region HA can be formed around the through hole 210.

[0034] The hole border area HA can be the area surrounding the through hole 210, the area between the through hole 210 and the display area AA adjacent to the through hole 210, or the area surrounded by the display area AA.

[0035] In the aperture border region HA, multiple gate lines can be provided for providing signals to the pixel P located around the via 210. Figure 2 (GL) and multiple data lines ( Figure 2 DL).

[0036] The following will refer to Figure 2 The through hole 210 and the hole border area HA are described in more detail.

[0037] Figure 2 It is a diagram Figure 1 A view of region A. Region A includes the through hole 210, the hole border region HA, and a portion of the display region AA.

[0038] Reference Figure 2The via frame region HA may include a circumference region RA and a line region LA. The circumference region RA may be the inner region of the via frame region HA surrounding the periphery of the via 210, and the gate line GL (or the first signal line) and the data line DL (or the second signal line) may not be located in the circumference region RA.

[0039] The circumferential region RA can be an area used to prevent damage to lines GL and DL when laser irradiation is performed to form the through hole 210, and therefore the minimum width needs to be kept constant.

[0040] The line region LA can be the area surrounding the periphery of the via 210, outside (or the rest) of the hole frame region HA, and multiple gate lines GL and multiple data lines DL can be located in the line region LA.

[0041] The gate lines GL and data lines DL can be formed as semi-circular structures along the outer circumferential surface of the via 210 and bypass the via 210. Multiple gate lines GL can extend around the via 210 in a first direction, such as a lateral direction. The multiple gate lines GL can be configured as scan lines, light emission control lines, initialization voltage lines, etc., according to the signal.

[0042] Multiple data lines DL can extend around the through-hole 210 along a second direction, such as the longitudinal direction, intersecting the first direction. The multiple data lines DL can be configured as drive voltage lines, drive low voltage lines, etc., depending on the signal configuration.

[0043] According to embodiments of the present invention, the gate line GL and data line DL can be formed as multiple lines located in different layers, wherein the insulating layer ( Figure 3 (109a, 109b, 109c, 109d, and 109e) are inserted therein. See below for further details. Figure 3 The circumferential region RA and the line region LA surrounding the through hole 210 are described in more detail.

[0044] Figure 3 This is a schematic cross-sectional view illustrating the through hole and hole border area according to an embodiment of the present invention.

[0045] Reference Figure 3 A via 210 may be formed on the substrate 101, and a circumferential region RA and a line region LA may be defined in a hole border region HA around the via 210.

[0046] In the line region LA of the substrate 101, multiple signal lines M1, M2, M3, M4, and M5 can be provided. The multiple signal lines M1, M2, M3, M4, and M5 can be via lines passing near the via 210, and can include a first layer line M1, a second layer line M2, a third layer line M3, a fourth layer line M4, and a fifth layer line M5.

[0047] A portion of the first to fifth layer lines M1 to M5 can be electrically connected to the gate line GL, and another portion of the first to fifth layer lines M1 to M5 can be electrically connected to the data line DL.

[0048] The first layer line M1 and the second layer line M2 may include a gate line GL. Multiple first layer lines M1 and multiple second layer lines M2 may be configured as scan lines to which scan signals are applied, light emission control lines to which light emission control signals are applied, initialization voltage lines to which initialization voltages are applied, etc.

[0049] The third to fifth layer lines M3 to M5 may include data lines GL. Multiple third to fifth layer lines M3 to M5 may be configured as data lines to which data voltage is applied, drive voltage lines to which drive voltage is applied, and drive low voltage lines to which drive low voltage is applied, etc. Furthermore, the third to fifth layer lines M3 to M5 may be configured with thin-film transistors (TFTs). Figure 4 The source of DTr) Figure 4 111a) or drain ( Figure 4 (111b).

[0050] The first interlayer insulation layer 109a can be disposed between the first layer line M1 and the second layer line M2. The second interlayer insulation layer 109b can be disposed between the second layer line M2 and the third layer line M3. The third interlayer insulation layer 109c can be located between the third layer line M3 and the fourth layer line M4. The fourth interlayer insulation layer 109d can be located between the fourth layer line M4 and the fifth layer line M5 or the anode 121.

[0051] This will be explained in more detail later.

[0052] The opening may be confined within the bank insulating layer 109e located on the fifth layer line M5. The opening may expose the space used to form an organic light-emitting diode (OLED). Figure 4 The anode of E) Figure 4 At least a part of (121).

[0053] The light-emitting layer 123 of the organic light-emitting diode E may be located on the insulating layer 109e and correspond to the opening defined by the insulating layer 109e. The cathode 125 may be located on the light-emitting layer 123.

[0054] A protective film 130 in the form of a thin film may be located on the cathode 125. The organic light-emitting display device 100 can be encapsulated by attaching the protective film 130 to the substrate 101.

[0055] The protective film 130 may use at least two inorganic protective films 131a and 131b to prevent external oxygen or moisture from penetrating the organic light-emitting display device 100. In this case, preferably, an organic protective film 133 is inserted between the two inorganic protective films 131a and 131b to supplement impact resistance.

[0056] Therefore, the organic light-emitting display device 100 can prevent external oxygen or moisture from penetrating the organic light-emitting display device 100.

[0057] A dam (DAM) may be disposed outside the first to fourth interlayer insulating layers 109a, 109b, 109c, and 109d. The dam DAM may completely surround the through-hole 210. The dam DAM may confine the organic protective film 133 of the protective film 130, which protects the components of the organic light-emitting display device 100 (e.g., thin-film transistors DTr and organic light-emitting diodes E) from the influence of particles that can penetrate from the outside, thereby stably positioning them within the internal region of the dam DAM.

[0058] The weir section DAM can be formed by stacking the first to fourth interlayer insulation layers 109a, 109b, 109c and 109d and the embankment insulation layer 109e.

[0059] A cover layer 135 may be formed between the through-hole 210 and the weir section DAM. The cover layer 135 may cover the uneven surface formed through the weir section DAM and provide a uniform surface 135-SH. The uniform surface 135-SH defined by the cover layer 135 may define the same plane as the uniform surface 130-S defined by the protective film 130.

[0060] In the organic light-emitting display device 100 according to an embodiment of the present invention, since the line region LA of the hole frame region HA is configured using the first to fifth layer lines M1, M2, M3, M4 and M5, the width of the line region LA can be reduced.

[0061] In other words, since lines M1, M2, M3, M4 and M5, which were originally in the same layer, are now in different layers, the width of the line region LA can be reduced.

[0062] Since the width of the line area LA can be reduced, the hole bezel area HA can also be reduced. Therefore, a display device 100 with a narrower hole bezel can be provided to meet recent needs.

[0063] <First Implementation Method>

[0064] Figure 4 This is a cross-sectional view of the pixel structure and the hole frame region of an organic light-emitting display device according to a first embodiment of the present invention.

[0065] Reference Figure 4 In the organic light-emitting display device 100, the display area AA and the aperture border area HA can be defined on the substrate 101. Multiple pixels can be arranged in the display area AA. Figure 2 (P), and can display images through multiple pixels P.

[0066] For illustrative purposes, each pixel P of the display area AA may include a light-emitting area EA having an organic light-emitting diode E and actually displaying an image, and a non-light-emitting area NEA located around the edge of the light-emitting area EA and including a switching area TrA in which a driving thin-film transistor DTr is formed.

[0067] The buffer layer BUF may be located on the substrate 101. In the switching region TrA located in the non-light-emitting region NEA of each pixel P, the semiconductor layer 103 may be disposed on the buffer layer BUF.

[0068] The semiconductor layer 103 may be formed of silicon. The semiconductor layer 103 may include an active region 103a in which a channel is formed in its central portion, and a source region 103c and a drain region 103b on both sides of the active region 103a, which are doped with a high concentration of impurities.

[0069] The semiconductor layer 103 can be formed from one of polycrystalline silicon, low-temperature polycrystalline silicon, and oxide semiconductor materials. In the case of a top-gate structure, a light-blocking layer LS can be formed below the semiconductor layer 103 to prevent external light from affecting the characteristics of the driving thin-film transistor DTr.

[0070] A gate insulating layer 105 may be formed on a substrate 101 having a light-blocking layer LS and a semiconductor layer 103. The gate 107 and gate line correspond to the active region 103a of the semiconductor layer 103. Figure 2 The gate (GL) can be formed on the gate insulating layer 105. The gate 107 can be connected to one electrode of the storage capacitor.

[0071] In the line region LA of the aperture border region HA, multiple first-layer lines M1 may be located on the gate insulating layer 105 and separated from each other by a predetermined interval. The first-layer lines M1 may be located in the same layer as the gate line GL and the gate 107, and may be electrically connected to the gate line GL.

[0072] A first interlayer insulating layer 109a may be formed on the gate 107, the gate line GL, and the first layer line M1. An upper electrode 108 may be located on the first interlayer insulating layer 109a corresponding to the gate 107. The upper electrode 108 may be connected to the other electrode of the storage capacitor.

[0073] In the line region LA of the aperture border region HA, multiple second-layer lines M2 can be located on the first interlayer insulating layer 109a and can be separated from each other at predetermined intervals. The second-layer lines M2 can be electrically connected to the light-emitting control lines.

[0074] In the first embodiment, the light emission control line can be omitted. In this case, the first layer line M1 can be electrically connected to a gate line GL, and the second layer line M2 can be electrically connected to another gate line GL.

[0075] In the switching region TrA, the first and second interlayer insulating layers 109a and 109b and the gate insulating layer 105 may include a first semiconductor contact hole 116a and a second semiconductor contact hole 116b that expose the source region 103c and the drain region 103b located on both sides of the active region 103a, respectively.

[0076] The source 111a and drain 111b may be located on a second interlayer insulating layer 109b having a first semiconductor contact hole 116a and a second semiconductor contact hole 116b. The source 111a and drain 111b may be separated from each other and contact the source region 103c and drain region 103b exposed through the first semiconductor contact hole 116a and the second semiconductor contact hole 116b, respectively.

[0077] In the line region LA of the aperture border region HA, multiple third-layer lines M3 may be located on the second interlayer insulating layer 109b and may be separated from each other by a predetermined interval. The third-layer lines M3 may be located in the same layer as the data lines DL and the sources 111a and 111b, and may be electrically connected to the data lines DL.

[0078] The third interlayer insulation layer 109c may be located on the source 111a, the drain 111b, and the third layer line M3.

[0079] The source 111a and drain 111b, the semiconductor layer 103 including the source region 103c and drain region 103b that contact the source 111a and drain 111b, the gate insulating layer 105 on the semiconductor layer 103, and the gate 107 can form a driving thin film transistor DTr.

[0080] A drain contact hole PH1 may be formed in the third interlayer insulating layer 109c and expose the drain electrode 111b. A connecting electrode GNT may be formed on the third interlayer insulating layer 109c and contact the drain electrode 111b exposed through the drain contact hole PH1.

[0081] In the line region LA of the hole frame region HA, multiple fourth layer lines M4 may be located on the third interlayer insulating layer 109c and separated from each other by a predetermined interval. The fourth layer lines M4 may be made of the same material as the connecting electrode GNT and located in the same layer as the connecting electrode GNT.

[0082] The fourth layer line M4 can be electrically connected to a different data line DL than the data line DL connected to the third layer line M3.

[0083] In the switching region TrA, the fourth interlayer insulating layer 109d may be located on the connection electrode GNT and includes a connection contact hole PH2 that exposes the connection electrode GNT. The anode 121 of the organic light-emitting diode E may be located on the fourth interlayer insulating layer 109d and connected to the connection electrode GNT via the connection contact hole PH2.

[0084] The anode 121 may be formed of a metallic material with high reflectivity. For example, the anode 121 may have a stacked structure of aluminum (Al) and titanium (Ti) (e.g., Ti / Al / Ti), a stacked structure of aluminum (Al) and ITO (e.g., ITO / Al / ITO), an APC alloy structure (e.g., Ag / Pd / Cu), or a stacked structure of APC alloy and ITO (e.g., ITO / APC / ITO).

[0085] Anode 121 can be located in each pixel P. Dike insulating layer 109e can be located between anodes 121 of pixels P. In other words, using dike insulating layer 109e as the boundary of each pixel P, anode 121 can be separated by pixel P.

[0086] In the organic light-emitting display device 100, multiple fifth-layer lines M5 may be located on the fourth interlayer insulating layer 109d in the line region LA of the aperture frame region HA, and separated from each other by a predetermined interval. The fifth-layer lines M5 may be located in the same layer as the anode 121.

[0087] The fifth layer line M5 can be electrically connected to a different data line DL than the data line DL connected to the third layer line M3 and the fourth layer line M4.

[0088] The dam insulation layer 109e can be located on the fifth layer line M5.

[0089] The light-emitting layer 123 may be integrally located on the substrate 101 having an anode 121 and an insulating layer 109e. The light-emitting layer 123 may be a common layer formed together on the pixel P. The light-emitting layer 123 may be a white light-emitting layer that emits white light.

[0090] In this configuration, the light-emitting layer 123 can be formed as a tandem structure having two or more stacks. Each stack may include a hole transport layer, at least one light-emitting layer, and an electron transport layer. Charge generation layers may be formed between the stacks. The charge generation layers may include an n-type charge generation layer adjacent to the lower stack and a p-type charge generation layer formed on the n-type charge generation layer and adjacent to the upper stack.

[0091] Furthermore, the n-type charge generation layer can inject electrons into the lower stack, while the p-type charge generation layer can inject holes into the upper stack. The n-type charge generation layer can be an organic layer, wherein the organic matrix material with electron transport capability is doped with alkali metals such as Li, Na, K, or Cs, or with alkaline earth metals such as Mg, Sr, Ba, or Ra. The p-type charge generation layer can comprise an organic matrix material doped with dopants, possessing hole transport capability.

[0092] The cathode 125 may be integrally located on the light-emitting layer 123. Similar to the light-emitting layer 123, the cathode 125 may be a common layer formed together on the pixel P. The cathode 125 may be formed of a transparent conductive material (TCO) such as ITO or IZO, or a semi-transparent conductive material such as Mg, Ag, or an alloy of Mg and Ag.

[0093] When the cathode 125 is formed of a semi-transmissive conductive material, the light output efficiency can be improved due to the microcavity effect.

[0094] A capping layer may be formed on the cathode 125.

[0095] Regarding the organic light-emitting diode E, when a predetermined voltage is applied to the anode 121 and the cathode 125 according to the selected signal, holes from the anode 121 and electrons from the cathode 125 are transferred to the light-emitting layer 123 to form excitons, and when the excitons transition from the excited state to the ground state, light is generated and emitted.

[0096] The emitted light can pass through the cathode 125 and be output to the outside, thereby enabling the organic light-emitting display device 100 to ultimately display an image.

[0097] A thin-film protective film 130 may be located on the driving thin-film transistor DTr and the organic light-emitting diode E, thereby allowing the organic light-emitting display device 100 to be packaged.

[0098] As described above, in the organic light-emitting display device 100 of the first embodiment of the present invention, the fifth layer line M5 can be formed in the same layer as the anode 121 of the organic light-emitting diode E and formed in the line region LA of the aperture frame region HA using the same material as the anode 12. Therefore, the line region LA of the aperture frame region HA can be formed with the first to fifth layers of lines M1, M2, M3, M4 and M5. Therefore, the width of the line region LA can be reduced.

[0099] Because the width of the line area LA is reduced, the hole bezel area HA can be reduced, and a display device 100 with a narrower hole bezel can be provided to meet recent needs.

[0100] The first to fifth layer lines M1, M2, M3, M4, and M5 can overlap alternately. In other words, the first layer line M1 and the second layer line M2 do not overlap with each other in the plan view, but are arranged alternately; similarly, the second layer line M2 and the third layer line M3 do not overlap with each other in the plan view, but are arranged alternately.

[0101] Furthermore, the third-layer line M3 and the fourth-layer line M4 do not overlap in the plan view, but are arranged alternately; similarly, the fourth-layer line M4 and the fifth-layer line M5 do not overlap in the plan view, but are arranged alternately.

[0102] Therefore, as the width of the line region LA decreases, the parasitic capacitance generated between the first layer line M1 and the second layer line M2 connected to the gate line GL can be reduced, and the parasitic capacitance generated between the third to fifth layer lines M3 to M5 connected to the data line DL can also be reduced.

[0103] Therefore, it can prevent the reduction in display quality caused by parasitic capacitance.

[0104] <Second Implementation Method>

[0105] To avoid repetition, components that have the same or similar functions as those in the first embodiment are referred to by the same reference numerals. The features of the second embodiment will be described below.

[0106] Figure 5 This is a cross-sectional view of the pixel structure and the hole frame region of the organic light-emitting display device according to the second embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the structure of the hole frame region and the auxiliary electrode according to the second embodiment of the present invention.

[0107] The buffer layer BUF may be located on the substrate 101. In the switching region TrA located in the non-light-emitting region NEA of each pixel P, the semiconductor layer 103 may be located on the buffer layer BUF.

[0108] The semiconductor layer 103 may be formed of silicon. The semiconductor layer 103 may include an active region 103a in which a channel is formed in its central portion, and a source region 103c and a drain region 103b on both sides of the active region 103a, which are doped with a high concentration of impurities.

[0109] A light-blocking layer LS can be formed below the semiconductor layer 103 to prevent external light from affecting the characteristics of the driving thin-film transistor DTr.

[0110] The light-blocking layer LS can be formed from an opaque conductive material with low resistance to block light. For example, the light-blocking layer LS can be formed from aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), or titanium (Ti).

[0111] In the line area LA of the hole border area HA, multiple auxiliary layer lines MS can be located on the buffer layer BUF and can be separated from each other at predetermined intervals. The auxiliary layer lines MS can be electrically connected to the data lines DL.

[0112] A gate insulating layer 105 may be formed on a substrate 101 having a light-blocking layer LS and a semiconductor layer 103. A gate 107 corresponding to the active region 103a of the semiconductor layer 103 and a gate line GL may be formed on the gate insulating layer 105. The gate 107 may be connected to one electrode of a storage capacitor.

[0113] In the line region LA of the aperture border region HA, multiple first-layer lines M1 may be located on the gate insulating layer 105 and separated from each other by a predetermined interval. The first-layer lines M1 may be located in the same layer as the gate line GL and the gate 107, and may be electrically connected to the gate line GL.

[0114] A first interlayer insulating layer 109a may be formed on the gate 107, the gate line GL, and the first layer line M1. An upper electrode 108 may be located on the first interlayer insulating layer 109a corresponding to the gate 107. The upper electrode 108 may be connected to the other electrode of the storage capacitor.

[0115] In the line region LA of the aperture border region HA, multiple second-layer lines M2 may be located on the first interlayer insulating layer 109a and may be separated from each other by a predetermined interval. The second-layer lines M2 may be electrically connected to the light-emitting control line, or may be electrically connected to a gate line GL that is different from the gate line GL connected to the first-layer line M1.

[0116] In the switching region TrA, the first and second interlayer insulating layers 109a and 109b and the gate insulating layer 105 may include a first semiconductor contact hole 116a and a second semiconductor contact hole 116b that expose the source region 103c and the drain region 103b located on both sides of the active region 103a, respectively.

[0117] The source 111a and drain 111b may be located on a second interlayer insulating layer 109b having a first semiconductor contact hole 116a and a second semiconductor contact hole 116b. The source 111a and drain 111b may be separated from each other and contact the source region 103c and drain region 103b exposed through the first semiconductor contact hole 116a and the second semiconductor contact hole 116b, respectively.

[0118] In the line region LA of the hole frame region HA, multiple third-layer lines M3 may be located on the second interlayer insulating layer 109b and may be separated from each other at predetermined intervals. The third-layer lines M3 may be located in the same layer as the data line DL and the source 111a and drain 111b, and may be electrically connected to the data line DL.

[0119] The third interlayer insulation layer 109c may be located on the source 111a, the drain 111b, and the third layer line M3.

[0120] A drain contact hole PH1 may be formed in the third interlayer insulating layer 109c and expose the drain electrode 111b. A connecting electrode GNT may be formed on the third interlayer insulating layer 109c and contact the drain electrode 111b exposed through the drain contact hole PH1.

[0121] In the line region LA of the hole border region HA, multiple fourth-layer lines M4 may be located on the third interlayer insulating layer 109c and separated from each other by a predetermined interval. The fourth-layer lines M4 may be located in the same layer as the connecting electrode GNT.

[0122] The fourth layer line M4 can be electrically connected to a different data line DL than the data line DL connected to the third layer line M3.

[0123] In the switching region TrA, the fourth interlayer insulating layer 109d may be located on the connection electrode GNT and includes a connection contact hole PH2 that exposes the connection electrode GNT. The anode 121 of the organic light-emitting diode E may be located on the fourth interlayer insulating layer 109d and connected to the connection electrode GNT via the connection contact hole PH2.

[0124] Anode 121 may be located in each pixel P. Dike insulating layer 109e may be located between anodes 121 of pixels P.

[0125] The light-emitting layer 123 may be integrally located on the substrate 101 having an anode 121 and an insulating layer 109e. The light-emitting layer 123 may be a common layer formed together on the pixel P. The light-emitting layer 123 may be a white light-emitting layer that emits white light.

[0126] The cathode 125 may be integrally located on the light-emitting layer 123. Similar to the light-emitting layer 123, the cathode 125 may be a common layer formed together on the pixel P. The cathode 125 may be formed of a transparent conductive material (TCO) such as ITO or IZO, or a semi-transparent conductive material such as Mg, Ag, or an alloy of Mg and Ag.

[0127] A thin-film protective film 130 may be located on the driving thin-film transistor DTr and the organic light-emitting diode E, thereby allowing the organic light-emitting display device 100 to be packaged.

[0128] As described above, in the organic light-emitting display device 100 of the second embodiment of the present invention, the auxiliary layer line MS can be formed in the same layer as the light-blocking layer LS and formed in the line region LA of the aperture frame region HA using the same material as the light-blocking layer LS. Therefore, the line region LA of the aperture frame region HA can be formed with the first to fourth layer lines M1, M2, M3 and M4 and the auxiliary layer line MS. Therefore, the width of the line region LA can be reduced.

[0129] Because the width of the line area LA is reduced, the hole bezel area HA can be reduced, and a display device 100 with a narrower hole bezel can be provided to meet recent needs.

[0130] In particular, in the organic light-emitting display device 100 according to the second embodiment of the present invention, the auxiliary electrode 300 may be formed in the same layer as the light blocking layer LS and the auxiliary layer line MS and is formed of the same material as the light blocking layer LS and the auxiliary layer line MS.

[0131] Therefore, the problems of current deviation and brightness non-uniformity caused by the increased resistance of the driving low-voltage line can be solved.

[0132] In other words, the driving voltage line to which a driving voltage is applied and the driving low voltage line to which a driving low voltage is applied can be formed in the same layer as the data line DL, and the driving voltage line and the driving low voltage line can be parallel to the data line DL and formed between adjacent pixels P.

[0133] The driving low-voltage line can be connected to the cathode 125 of the organic light-emitting diode E and transmit a low-potential voltage (i.e., VSS voltage).

[0134] The reason for forming the cathode 125 as a double-layer structure instead of a single-layer structure is that the cathode 125 is formed as a very thin film to be transparent. Therefore, due to the properties of the metal forming the cathode 125, the very thin film itself has very high resistance.

[0135] This cathode 125 can produce current deviations, which in turn cause non-uniformity of brightness on pixel P.

[0136] In the organic light-emitting display device 100 according to the second embodiment of the present invention, the auxiliary electrode 300 may be formed in the same layer as the light blocking layer LS and the auxiliary layer line MS and is formed of the same material as the light blocking layer LS and the auxiliary layer line MS, may correspond to the display area AA, and may be electrically connected to the driving low voltage line.

[0137] Reference Figure 6 The auxiliary electrode 300 can be formed into a mesh structure in the display area AA. Since the auxiliary electrode 300 and the cathode 125 can be in contact with each other, the resistance of the cathode 125 can be reduced.

[0138] In the above description, a first layer line M1 and a second layer line M2 are shown by way of example connected to the gate line GL and the light-emitting control line, respectively. However, the first layer line M1 and the second layer line M2 can be electrically connected to the data line DL, the drive voltage line, and the drive low voltage line.

[0139] Furthermore, the third layer line M3 and the fourth layer line M4 are shown as examples, respectively connected to the data line DL, the drive voltage line, and the drive low voltage line. However, the third layer line M3 and the fourth layer line M4 can be electrically connected to the gate line DL and the light-emitting control line. The auxiliary layer line MS and the first layer line M1 can be arranged alternately and repeatedly in the plan view without overlapping each other.

[0140] In the second embodiment described above, it is possible for the auxiliary layer line MS to be electrically connected to the data line and for the first to fourth layer lines to be electrically connected to the gate line GL.

[0141] As described above, in the line region of the aperture bezel area of ​​the organic light-emitting display device according to embodiments of the present invention, the fifth layer line may be formed in the same layer as the anode of the organic light-emitting diode and made of the same material as the anode of the organic light-emitting diode, or the auxiliary layer line may be formed in the same layer as the light-blocking layer and made of the same material as the light-blocking layer. Therefore, the line region of the aperture bezel area may include the first to fourth layers of lines, and the fifth layer line or auxiliary layer line. Therefore, the width of the line region can be reduced.

[0142] Therefore, the bezel area can also be reduced, enabling the provision of display devices with narrower bezels to meet recent needs.

[0143] Furthermore, the auxiliary electrode can be formed in the same layer as the auxiliary layer line in the display area using the same material. Therefore, it has the advantage of resolving issues such as current deviation and brightness non-uniformity caused by increased resistance in the driving low-voltage line.

[0144] Various modifications and variations may be made to this invention without departing from the spirit or scope thereof, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover any modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: Substrates including through holes; A thin-film transistor comprising a gate, a source, a drain, and a semiconductor layer on the substrate; The first metal layer on the thin-film transistor; A second metal layer on top of the first metal layer; A light-emitting layer on the second metal layer; The protective film on the light-emitting layer; The line region surrounding the through hole; A first signal line formed in the same layer as the first metal layer and disposed in the line region; and A weir is provided between the through hole and the first signal line. The semiconductor layer comprises an oxide semiconductor material.

2. The display device according to claim 1, further comprising a covering layer on the protective film.

3. The display device according to claim 1, wherein the light-emitting layer comprises a hole transport layer and an electron transport layer, and The hole transport layer and the electron transport layer extend into the line region.

4. The display device according to claim 3, wherein the hole transport layer and the electron transport layer are disposed on the upper part of the weir.

5. The display device according to claim 1, further comprising a second signal line formed in the same layer as the second metal layer and disposed in the line region.

6. The display device according to claim 1, further comprising a third metal layer between the light-emitting layer and the protective film, The third metal layer is disposed on the upper part of the weir.

7. The display device according to claim 1 further includes an auxiliary layer line, the auxiliary layer line being formed of the same material as the light-blocking layer in the same layer as the light-blocking layer.

8. The display device according to claim 7, wherein the light blocking layer is disposed below the semiconductor layer.

9. The display device according to claim 8, further comprising an auxiliary electrode, the auxiliary electrode being formed in the display area in the same layer as the auxiliary layer line using the same material. The auxiliary electrode is electrically connected to the cathode on the light-emitting layer.

10. The display device according to claim 1, further comprising: The first layer of lines is formed of the same material as the gate in the same layer as the gate; as well as The second layer of lines is formed in the same layer as the upper electrode of the thin-film transistor, using the same material. The first layer lines and the second layer lines do not overlap in the plan view, and the first layer lines and the second layer lines are arranged alternately and repeatedly.

11. The display device of claim 10, further comprising an auxiliary layer line, the auxiliary layer line being formed of the same material as the light-blocking layer beneath the semiconductor layer in the same layer as the light-blocking layer. The auxiliary layer lines and the first layer lines do not overlap in the plan view, and the auxiliary layer lines and the first layer lines are arranged alternately and repeatedly.

12. The display device according to claim 1, further comprising: The third layer line is formed of the same material as the source and the drain in the same layer as the source and the drain; as well as The fourth layer of lines is formed of the same material as the first metal layer within the same layer as the first metal layer. The third and fourth layer lines do not overlap in the plan view, and the third and fourth layer lines are arranged alternately and repeatedly.

13. The display device of claim 12, further comprising an auxiliary layer line, the auxiliary layer line being formed of the same material as the second metal layer in the same layer as the second metal layer. The auxiliary layer lines and the fourth layer lines do not overlap in the plan view, and the auxiliary layer lines and the fourth layer lines are arranged alternately and repeatedly.

14. The display device according to claim 1, further comprising: The first layer of lines is formed of the same material as the gate in the same layer as the gate; as well as The second layer of lines is formed in the same layer as the upper electrode of the thin-film transistor, using the same material. A first interlayer insulating layer is provided between the gate and the upper electrode; a second interlayer insulating layer is provided between the upper electrode and the source and the drain; a third interlayer insulating layer is provided between the source and the drain and the first metal layer; a fourth interlayer insulating layer is provided between the first metal layer and the second metal layer; or a gate insulating layer is provided between the gate and the auxiliary layer line below the gate.

15. The display device according to claim 14, wherein the weir is disposed outside the first interlayer insulating layer, the second interlayer insulating layer, the third interlayer insulating layer and the fourth interlayer insulating layer to completely surround the through hole.

16. The display device of claim 1, wherein the source and the drain are electrically connected to a corresponding one of the first signal lines.

17. The display device according to claim 1, further comprising a light-emitting diode, the light-emitting diode comprising an anode electrically connected to the drain electrode, and a light-emitting layer and a cathode sequentially disposed on the anode.

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