Multiple exposure process method

Abstract

The application discloses a multiple exposure process method, comprising: performing pattern splitting, using a baking step of a cycle step of a photolithography process to diffuse a boron-containing doped region in previous cycle steps and to reduce a feature of an effective pattern area, separately splitting a minimum size pattern into a splitting mask with the latest process, and uniformly splitting each pattern with a size greater than the minimum size into each splitting mask with a process later than the latest process. An amorphous silicon layer is formed on a bottom structure. Each splitting mask is used to perform the following cycle steps: performing a photolithography process, comprising: coating an SOC layer, a SiARC layer and a photoresist in sequence, performing exposure and development on the photoresist using the selected splitting mask to pattern the photoresist. Performing etching and ion implantation, comprising: etching the SiARC layer and the SOC layer in sequence, and performing ion implantation to form a boron-containing doped region in the surface-exposed amorphous silicon layer. Removing the photoresist, the SiARC layer and the SOC layer. Performing an amorphous silicon removal process. The application can improve CDU.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a multiple exposure process method. Background Technology

[0002] As semiconductor manufacturing processes shrink, when the distance between patterns exceeds the resolution limit of photolithography, multiple exposure techniques are employed. This involves splitting all patterns onto multiple photomasks, increasing the distance between patterns on individual photomasks, and then performing multiple lithography-etching-lithography-etching processes (LELE). For example, in some patterning processes, without using more advanced photolithography techniques, it is necessary to split the pattern into four photomasks to form a special pattern, thereby increasing the process window.

[0003] Meanwhile, some multi-exposure processes, unlike typical LELE processes, define patterns using Litho-Etch ion implantation (IMP). Finally, a wet etching process with NH3OH removes the non-patterned amorphous silicon (A-Si) film. In this wet etching, the ratio of amorphous silicon in the patterned to non-patterned regions is approximately 1:5, leaving the remaining amorphous silicon as the final desired pattern structure. However, existing multi-exposure processes exhibit poor critical dimension (CD) uniformity in the patterns they form. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a multi-exposure process method that achieves patterning of the amorphous silicon layer by defining boron-doped regions formed in the amorphous silicon layer through multiple split photomasks. This reduces the adverse effect of boron diffusion in the boron-doped regions caused by the cycle steps corresponding to each split photomask on the critical dimension uniformity (CDU), thereby improving the CDU.

[0005] To solve the above-mentioned technical problems, the multi-exposure process method provided by the present invention includes: Provide a photomask to be split, the photomask having a pattern before splitting; perform pattern splitting to split the pattern before splitting into multiple split photomasks.

[0006] An amorphous silicon layer is formed on the underlying structure.

[0007] The following cyclic steps are performed using each of the aforementioned split photomasks: The photolithography process includes: sequentially coating a SOC layer, a SiARC layer, and a photoresist, and then patterning the photoresist by exposure and development using the selected split photomask.

[0008] The etching (ET) and ion implantation (IM) processes include: sequentially etching the SiARC layer and the SOC layer using the pattern of the photoresist as a mask to expose the surface of the amorphous silicon layer, and then performing ion implantation to form a boron-doped region in the exposed amorphous silicon layer.

[0009] Remove the photoresist, the SiARC layer, and the SOC layer.

[0010] The photolithography process also includes a baking step, which causes the boron-doped regions from the preceding cycles to diffuse, thereby reducing the effective pattern area defined by the boron-doped regions. Based on the characteristic that the baking step reduces the effective pattern area of ​​the boron-doped regions, the pattern splitting includes: The split masks are sorted according to the order in which the cyclic steps are performed. At the same time, according to the relative size of the patterns, the smallest pattern is split into the split mask with the latest process, and the patterns with a size larger than the smallest size are evenly split into the split masks with the next later process, so as to improve the CDU of the patterns.

[0011] After all the cycle steps corresponding to the split photomask are completed, an amorphous silicon removal (A-Si RM) process is performed to remove the amorphous silicon layer outside the effective patterned area of ​​the boron-doped region, thereby forming an amorphous silicon pattern.

[0012] A further improvement is that the impurities implanted by the ions include boron.

[0013] A further improvement is that, after all the cyclic steps corresponding to the split photomask are completed and before the amorphous silicon removal process, the process further includes: A boron diffusion process is performed to reduce the effective patterned area of ​​the boron-doped region formed in the final cycle step, thereby further improving the CDU of the pattern.

[0014] A further improvement is that the baking step includes pre-baking and / or post-baking.

[0015] A further improvement is that the boron diffusion process includes cyclic external baking, wherein the temperature of the cyclic external baking is greater than or equal to the highest temperature in the baking step.

[0016] A further improvement is that the maximum temperature of the baking step includes 250°C.

[0017] The temperature of the external baking cycle is 250°C and the time is 60 seconds.

[0018] A further improvement is that the amorphous silicon pattern is a truncated pattern of the zeroth metal layer.

[0019] A further improvement is that the underlying structure includes a first dielectric layer and a hard mask layer formed on a semiconductor substrate.

[0020] A further improvement is that the first dielectric layer includes an oxide layer.

[0021] A further improvement is that the hard mask layer comprises a second TiN layer and a third oxide layer stacked sequentially.

[0022] A further improvement is that the amorphous silicon removal process employs wet etching, and the etching solution used in the wet etching includes NH3OH.

[0023] A further improvement is that the number of split photomasks includes four.

[0024] A further improvement is that, before the pattern splitting, the OPC pre-coloring is performed on the pattern in the photomask, which marks the patterns of different sizes and types with different colors; in the pattern splitting, the pattern is split into the corresponding split photomask according to the color of the pattern.

[0025] This invention achieves patterning of amorphous silicon layers by defining boron-doped regions formed within the amorphous silicon layer through multiple split photomasks. It leverages the unavoidable baking step in photolithography. In multiple cycles, except for the final cycle, the boron-doped regions formed in subsequent cycles are affected by the baking process. This effect causes the boron (B) concentration in the surrounding area of ​​the boron-doped region to expand outwards, thus reducing the B concentration and hindering selective etching between the boron-doped region and the surrounding boron-free amorphous silicon layer. Therefore, the effective patterned area of ​​the boron-doped region is actually smaller than the boron-doped region itself. Utilizing this characteristic, the smallest pattern size is separated into the latest split photomask, while larger patterns are further separated into different split photomasks. The pattern is uniformly split into the split masks before the next process step. This reduces the CD difference caused by process variations, thereby significantly improving the CDU of the same pattern. For example, in this invention, the smallest pattern is split into the split mask at the end of the process. Compared with the existing method where patterns of various sizes are uniformly split into different split masks, the smallest pattern in this invention is obviously not affected by the differences between split masks in different processes, thus improving the CDU. For patterns larger than the smallest size, since they are uniformly split into the split masks before the next process step, the boron-doped regions of the split masks before the next process step are affected by the baking step. Therefore, the differences between patterns larger than the smallest size are also smaller, thus also improving the CDU.

[0026] Furthermore, this invention can add a boron diffusion process after all the corresponding cyclic steps for photomask splitting are completed and before the amorphous silicon removal process. The boron diffusion process is typically achieved through external baking, but can also be achieved using any other process capable of boron diffusion. Adding the boron diffusion process reduces the effective pattern area of ​​the boron-doped region formed in the final cyclic step, thereby further improving the pattern's CDU. Moreover, in this invention, a single baking step is usually sufficient to saturate the diffusion of the boron-doped region; therefore, adding a boron diffusion process ensures that the diffusion of the boron-doped region formed in different cyclic steps tends to saturate, thus further improving the pattern's CDU.

[0027] In addition, by adding the boron diffusion process, the present invention can reduce the effective pattern area of ​​all boron-doped regions, thus reducing the CD of patterns, especially small-sized patterns, while keeping the etching and ion implantation process windows unchanged. Attached Figure Description

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figures 1-4 This is a schematic diagram of the device structure in each step of the existing multiple exposure process; Figure 5 This is a top view of the boron-doped region after ion implantation in an existing multiple exposure process. Figure 6 This is a top view of the boron-doped region after the baking step in the photolithography process in the existing multiple exposure process. Figure 7 This is a flowchart of the multiple exposure process method according to an embodiment of the present invention; Figure 8 It is the photomask pattern after OPC pre-coloring in the existing comparative multiple exposure process; Figure 9 This is the photomask pattern after OPC pre-coloring in the multiple exposure process of this invention. Detailed Implementation

[0029] The multiple exposure process method of this invention is derived based on the analysis of existing multiple exposure processes. Before describing the multiple exposure process method of this invention in detail, the existing multiple exposure processes are first introduced as follows: like Figures 1 to 4 The diagram shown is a schematic representation of the device structure in each step of an existing multiple exposure process. The existing multiple exposure process includes: After splitting the pattern to form a split photomask, an amorphous silicon layer 104 is formed on the underlying structure. For example... Figure 1As shown, the underlying structure includes a first dielectric layer 101 and a hard mask layer formed on a semiconductor substrate (not shown).

[0030] The first dielectric layer 101 includes an oxide layer. Figure 1 The oxide layer shown is PEOX, which is an oxide layer formed by PECVD.

[0031] The hard mask layer comprises a second TiN layer 102 and a third oxide layer 103 stacked sequentially. Figure 1 In this design, the second TiN layer 102 and the third oxide layer 103 are further represented as HM TiN and HM OX, respectively. The amorphous silicon layer 104 is represented as A-Si, and 300A indicates that the thickness of the amorphous silicon layer 104 is 300 Å.

[0032] The following cyclic steps are performed using each of the aforementioned split photomasks: like Figure 1 As shown, the photolithography process includes: sequentially coating a SOC layer 105, a SiARC layer 106, and a photoresist 107; and patterning the photoresist 107 by exposure and development using the selected split photomask. Figure 1 In this process, the openings 108 formed by the patterning of the photoresist 107 define the subsequent etching and ion implantation regions. Figure 1 In the diagram, the SOC layer 105, the SiARC layer 106, and the photoresist 107 are also represented by SOC, SiARC, and PR, respectively.

[0033] The photolithography process includes a baking step. The baking step includes pre-baking and / or post-baking. Pre-baking is performed after the photoresist 107 is coated, and the pre-baking temperature is, for example, 250°C.

[0034] like Figure 2 As shown, etching and ion implantation are performed, including: using the pattern of the photoresist 107 as a mask to sequentially etch the SiARC layer 106 and the SOC layer 105 and expose the surface of the amorphous silicon layer 104. After etching, the opening 108 is deepened and the surface of the amorphous silicon layer 104 is exposed.

[0035] Then, ion implantation, as indicated by arrow 109, is performed to form a boron-doped region 104a in the exposed amorphous silicon layer 104. The impurities implanted include boron.

[0036] like Figure 3 As shown, the photoresist 107, the SiARC layer 106, and the SOC layer 105 are removed.

[0037] like Figure 4As shown, after all the cycle steps corresponding to the photomask splitting are completed, an amorphous silicon removal process is performed to remove the amorphous silicon layer 104 outside the effective patterned area of ​​the boron-doped region 104a, thereby forming the amorphous silicon pattern 104a. Typically, the amorphous silicon removal process employs wet etching, and the etching solution used in the wet etching includes NH3OH.

[0038] Figure 4 In the designation, the amorphous silicon pattern is also denoted by 104a. However, in reality, the size of the amorphous silicon pattern 104a is not exactly equal to the boron-doped region 104a formed during ion implantation, but rather equal to the effective pattern area of ​​the boron-doped region 104a. Furthermore, in each cycle, the baking step in the photolithography process diffuses the boron in the boron-doped regions 104a formed in previous cycles, thereby reducing the effective pattern area.

[0039] like Figure 5 The image shown is a top view of the boron-doped region after ion implantation in an existing multiple exposure process. Figure 5 The image shown is a top view of the boron-doped region 104a after ion implantation. Figure 6 The image shown is a top view of the boron-doped region after the baking step in the photolithography process in the existing multiple exposure process. Figure 6 In the diagram, 104a is designated as the effective patterned region of the boron-doped region 104a. The periphery of the effective patterned region of the boron-doped region 104a has regions 104b and 104c with reduced boron doping concentration, with region 104c having an even lower boron concentration. Region 104c is formed by boron diffusion from region 104b. Finally, in the amorphous silicon removal process, the over-etch (OE) resistance of the amorphous silicon in regions 104b and 104c is weakened, and the A-Si loss increases; for example, the amorphous silicon in regions 104b and 104c will also be removed. Therefore, due to… Figure 5 and Figure 6 By comparison, it can be seen that Figure 6 The critical dimension (CD) of the amorphous silicon pattern 104a formed by the effective patterned region of the boron-doped region 104a in the process will be smaller than that formed by the process. Figure 5 The key dimensions of the amorphous silicon pattern 104a formed by the boron-doped region 104a are such that CDs of the same pattern will differ, thus the CD uniformity (CDU) will deteriorate.

[0040] Furthermore, regarding the boron diffusion in the boron-doped region 104a, experiments show that the boron diffusion tends to saturate after one bake, resulting in a significant reduction in the CD value; however, the CD variation values ​​corresponding to multiple bakes with varying numbers of bakes are relatively smaller. Therefore, in existing multi-exposure processes, before the amorphous silicon removal process, the top view structure of the boron-doped region 104a formed in the last cycle step and... Figure 5 Correspondingly; the top view structure of the boron-containing diffusion region 104a formed in each of the other cyclic steps and Figure 6 Correspondingly, the CD of the amorphous silicon pattern 104a formed by the boron-containing diffusion region 104a formed in the last cycle step is larger than the CD of the amorphous silicon pattern 104a formed by the boron-containing diffusion region 104a formed in other cycle steps, so the CDU deteriorates.

[0041] like Figure 7 The diagram shown is a flowchart of the multiple exposure process method according to an embodiment of the present invention; please also refer to the schematic diagram of the device structure in each step of the multiple exposure process method according to an embodiment of the present invention. Figures 1 to 4 As shown, the multiple exposure process method of this invention includes: Step S101: Provide a photomask to be split, the photomask having a pattern before splitting; perform pattern splitting to split the pattern before splitting into multiple split photomasks.

[0042] In this embodiment of the invention, a baking step is also included in the photolithography process of subsequent cycles. This baking step causes diffusion of the boron-doped regions 104a in the preceding cycles, thereby reducing the effective pattern area defined by the boron-doped regions 104a. Based on the characteristic that the baking step reduces the effective pattern area of ​​the boron-doped regions 104a, the pattern splitting includes: The split masks are sorted according to the order in which the cyclic steps are performed. At the same time, according to the relative size of the patterns, the smallest pattern is split into the split mask with the latest process, and the patterns with a size larger than the smallest size are evenly split into the split masks with the next later process, so as to improve the CDU of the patterns.

[0043] In this embodiment of the invention, before pattern splitting, the process further includes OPC pre-coloring of the unsplit pattern in the photomask, wherein the OPC pre-coloring assigns different colors to patterns of different sizes and types; during pattern splitting, the pattern is split into the corresponding split photomask according to its color. Figure 9The image shown is a photomask layout after OPC pre-coloring in the multiple exposure process of this invention. In photomask layout 201b, patterns of the same color are split into the same split photomask. In photomask layout 201b, the smallest pattern 205, i.e., the small island, is split into the split photomask with the latest process. Patterns 202, 203, and 204 of other sizes are evenly split into the split photomasks with the next latest process. Patterns 202, 203, and 204 correspond to the large island, the fat island, and the medium island, respectively.

[0044] and Figure 8 This is the photomask layout after OPC pre-coloring in the existing comparative multiple exposure process. It can be seen that in the photomask layout 201a, patterns of various sizes are uniformly set in each of the split photomasks. Obviously, under the diffusion effect of the corresponding baking step on the boron-doped region in the previous cycle step, the CD of each pattern of the same size will be different, so the CDU will be reduced.

[0045] In some embodiments, the number of split photomasks includes four.

[0046] Step S102: Form an amorphous silicon layer 104 on the underlying structure.

[0047] In this embodiment of the invention, the amorphous silicon layer 104 is used to form a cut-out pattern of the zeroth metal layer.

[0048] like Figure 1 As shown, the underlying structure includes a first dielectric layer 101 and a hard mask layer formed on a semiconductor substrate (not shown).

[0049] The first dielectric layer 101 includes an oxide layer. Figure 1 The oxide layer shown is PEOX, which is an oxide layer formed by PECVD.

[0050] The hard mask layer comprises a second TiN layer 102 and a third oxide layer 103 stacked sequentially. Figure 1 In this design, the second TiN layer 102 and the third oxide layer 103 are further represented as HM TiN and HM OX, respectively. The amorphous silicon layer 104 is represented as A-Si, and 300A indicates that the thickness of the amorphous silicon layer 104 is 300 Å.

[0051] Step S103: Perform the following cyclic steps using each of the described split photomasks: Step S103a, as Figure 1 As shown, the photolithography process includes: sequentially coating a SOC layer 105, a SiARC layer 106, and a photoresist 107; and patterning the photoresist 107 by exposure and development using the selected split photomask. Figure 1In this process, the openings 108 formed by the patterning of the photoresist 107 define the subsequent etching and ion implantation regions. Figure 1 In the diagram, the SOC layer 105, the SiARC layer 106, and the photoresist 107 are also represented by SOC, SiARC, and PR, respectively.

[0052] In this embodiment of the invention, the photolithography process includes a baking step. The baking step includes pre-baking and / or post-baking.

[0053] Step S103b, as follows Figure 2 As shown, etching and ion implantation are performed, including: using the pattern of the photoresist 107 as a mask to sequentially etch the SiARC layer 106 and the SOC layer 105 and expose the surface of the amorphous silicon layer 104. After etching, the opening 108 is deepened and the surface of the amorphous silicon layer 104 is exposed.

[0054] Then, ion implantation, as indicated by arrow 109, is performed to form a boron-doped region 104a in the surface-exposed amorphous silicon layer 104.

[0055] In this embodiment of the invention, the impurity implanted by the ion includes boron.

[0056] Step S103c, as Figure 3 As shown, the photoresist 107, the SiARC layer 106, and the SOC layer 105 are removed.

[0057] In this embodiment of the invention, after all the cyclic steps corresponding to the split photomask have been completed and before the subsequent amorphous silicon removal process, the following steps are also included: A boron diffusion process is performed to reduce the effective patterned area of ​​the boron-doped region 104a formed in the final cycle step, thereby further improving the CDU of the pattern.

[0058] The boron diffusion process includes cyclic external baking, wherein the temperature of the cyclic external baking is greater than or equal to the highest temperature in the baking step. In some embodiments, the highest temperature of the baking step includes 250°C. The cyclic external baking temperature is 250°C, and the time is 60 seconds.

[0059] Step S104, as follows Figure 4 As shown, after all the cycle steps corresponding to the split photomask are completed, an amorphous silicon removal process is performed to remove the amorphous silicon layer 104 outside the effective pattern area of ​​the boron-doped region 104a and thereby form the amorphous silicon pattern 104a.

[0060] Figure 4In this context, the amorphous silicon pattern is also designated as 104a, meaning that the retained boron-doped region 104a serves as the amorphous silicon pattern. In practice, the retained boron-doped region 104a is located within the effective pattern area. After the baking step in the subsequent photolithography processes, the effective pattern area of ​​the boron-doped region 104a shrinks to less than the initial ion-implanted area. Please also consider... Figure 5 and Figure 6 As shown, Figure 5 The image shown is a top view of the boron-doped region 104a after ion implantation. Figure 6 This is a top view of the boron-doped region 104a after the baking step in the photolithography process. Figure 6 In the diagram, 104a is designated as the effective patterned region of the boron-doped region 104a. The periphery of the effective patterned region of the boron-doped region 104a has regions 104b and 104c with reduced boron doping concentration, where region 104c has an even lower boron concentration. Finally, in the amorphous silicon removal process, the amorphous silicon in regions 104b and 104c is also removed.

[0061] In this embodiment of the invention, the amorphous silicon removal process employs wet etching, and the etching solution used in the wet etching includes NH3OH.

[0062] This invention achieves patterning of the amorphous silicon layer 104 by defining boron-doped regions 104a formed in the amorphous silicon layer 104 through multiple split photomask steps. Utilizing the unavoidable baking step in the photolithography process, and considering that in multiple cycles, except for the last cycle, the boron-doped regions 104a formed in each subsequent cycle are affected by the baking step, causing the boron concentration (B) in the surrounding area of ​​the boron-doped regions 104a to expand outwards. This reduces the B concentration in the surrounding area, making selective etching between the boron-doped regions and the surrounding boron-free areas of the amorphous silicon layer 104 impossible. Therefore, the effective patterned area of ​​the boron-doped regions 104a is actually smaller than the boron-doped regions 104a themselves. Using this characteristic, the smallest pattern size is individually split into the latest split photomask step. In this invention, patterns larger than the minimum size are uniformly split into separate photomasks before the next step. This reduces CD differences caused by process variations, thereby significantly improving the CDU of the same pattern. For example, in this embodiment, the smallest size pattern is split into the final photomask of the process. Compared with the existing method where patterns of various sizes are uniformly split into different photomasks, the smallest size pattern in this embodiment is obviously not affected by the differences between photomasks in different processes, thus improving the CDU. Since the patterns larger than the minimum size are uniformly split into separate photomasks before the next step, the boron-doped region 104a of each photomask before the next step is affected by the baking step, so the differences between the patterns larger than the minimum size are also smaller, thus also improving the CDU.

[0063] Furthermore, this embodiment of the invention can add a boron diffusion process after all the cycle steps corresponding to the photomask splitting are completed and before the amorphous silicon removal process. The boron diffusion process is usually achieved by external baking in the cycle, but any other process capable of achieving boron diffusion can also be used. After adding the boron diffusion process, the effective pattern area of ​​the boron-doped region 104a formed in the last cycle step can be reduced, thereby further improving the CDU of the pattern. Moreover, in this embodiment of the invention, the diffusion of the boron-doped region 104a is usually saturated by one baking step. Therefore, after adding a boron diffusion process in this embodiment of the invention, the diffusion of the boron-doped region 104a formed in the cycle steps of different processes can be saturated, thus further improving the CDU of the pattern.

[0064] In addition, by adding the boron diffusion process, the effective pattern area of ​​all boron-doped regions 104a can be reduced in the embodiments of the present invention. Therefore, the CD of the pattern, especially the small-sized pattern, can be reduced while keeping the etching and ion implantation process windows unchanged.

[0065] In this embodiment of the invention, it is possible to further miniaturize and optimize the CDU of small node patterns. By using OPC pre-color, high-quantity patterns such as SRAM large islands / fat islands are evenly distributed on the first three masks, and small islands are separately distributed on the fourth mask. This can reduce CD difference caused by process differences and significantly improve the CDU of the same pattern.

[0066] Meanwhile, an additional 250℃ Bake 60s step, i.e., the aforementioned cyclic external baking, is added before A-Si RM to ensure edge B diffusion in all patterns. This allows for the reduction of island CD and improvement of CDU while maintaining the ET-IMP window, i.e., the process window for etching and ion implantation.

[0067] The embodiments of the present invention solve the problems of worsened CDU due to process differences in existing small process nodes, and the difficulty that the CD cannot be further reduced by reducing the ET opening in extremely small size patterns. It can significantly improve the MOC CDU and reduce the final CD.

[0068] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A multiple exposure process method, characterized in that, include: Provide a photomask to be split, the photomask having a pattern before splitting; perform pattern splitting to split the pattern before splitting into multiple split photomasks; An amorphous silicon layer is formed on the underlying structure; The following cyclic steps are performed using each of the aforementioned split photomasks: The photolithography process includes: sequentially coating a SOC layer, a SiARC layer, and a photoresist, and then patterning the photoresist by exposure and development using the selected split photomask; Etching and ion implantation include: using the pattern of the photoresist as a mask to sequentially etch the SiARC layer and the SOC layer and expose the surface of the amorphous silicon layer, and then performing ion implantation to form a boron-doped region in the exposed amorphous silicon layer; Remove the photoresist, the SiARC layer, and the SOC layer; The photolithography process also includes a baking step, which causes the boron-doped regions from the preceding cycles to diffuse, thereby reducing the effective pattern area defined by the boron-doped regions. Based on the characteristic that the baking step reduces the effective pattern area of ​​the boron-doped regions, the pattern splitting includes: The split masks are sorted according to the order in which the cyclic steps are performed. At the same time, according to the relative size of the patterns, the smallest pattern is split into the split mask with the latest process, and the patterns with a size larger than the smallest size are evenly split into the split masks with the next later process, so as to improve the CDU of the patterns. After all the cycle steps corresponding to the split photomask are completed, an amorphous silicon removal process is performed to remove the amorphous silicon layer outside the effective patterned area of ​​the boron-doped region, thereby forming an amorphous silicon pattern.

2. The multiple exposure process method as described in claim 1, characterized in that: The impurities implanted by the ions include boron.

3. The multiple exposure process method as described in claim 1, characterized in that: After all the cyclic steps corresponding to the photomask splitting are completed and before the amorphous silicon removal process, the process further includes: A boron diffusion process is performed to reduce the effective patterned area of ​​the boron-doped region formed in the final cycle step, thereby further improving the CDU of the pattern.

4. The multiple exposure process method as described in claim 3, characterized in that: The baking steps include pre-baking and / or post-baking.

5. The multiple exposure process method as described in claim 4, characterized in that: The boron diffusion process includes cyclic external baking, wherein the temperature of the cyclic external baking is greater than or equal to the highest temperature in the baking step.

6. The multiple exposure process method as described in claim 5, characterized in that: The maximum temperature for the baking step includes 250°C; The temperature of the external baking cycle is 250°C and the time is 60 seconds.

7. The multiple exposure process method as described in claim 1, characterized in that: The amorphous silicon pattern is a cut-off pattern of the zeroth metal layer.

8. The multiple exposure process method as described in claim 7, characterized in that: The underlying structure includes a first dielectric layer and a hard mask layer formed on a semiconductor substrate.

9. The multiple exposure process method as described in claim 8, characterized in that: The first dielectric layer includes an oxide layer.

10. The multiple exposure process method as described in claim 9, characterized in that: The hard mask layer comprises a second TiN layer and a third oxide layer stacked sequentially.

11. The multiple exposure process method as described in claim 1, characterized in that: The amorphous silicon removal process employs wet etching, and the etching solution used in the wet etching process includes NH3OH.

12. The multiple exposure process method as described in claim 7, characterized in that: The number of split photomasks includes four.

13. The multiple exposure process method as described in claim 1, characterized in that: Before the pattern splitting, the process also includes OPC pre-coloring of the pattern in the photomask, whereby the OPC pre-coloring assigns different colors to patterns of different sizes and types; during the pattern splitting, the pattern is split into the corresponding split photomask according to its color.

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