Method for forming trench isolation structure and semiconductor device

Abstract

The application relates to the technical field of semiconductor devices, in particular to a trench isolation structure forming method and a semiconductor device. The trench isolation structure forming method comprises the following steps: providing a substrate, the substrate comprises a plurality of trenches and a fin part between two adjacent trenches, a patterned mask layer is formed on the fin part, the trench is filled with a trench isolation material, and the top surface of the trench isolation material is substantially flush with the top surface of the patterned mask layer; etching part of the trench isolation material, so that the recessed bottom of the trench isolation material and the bottom of the patterned mask layer form a height difference; removing the patterned mask layer; and etching the trench isolation material to obtain a trench isolation structure. The application can at least alleviate the problem that the current process is prone to cause a dished recess of the dielectric isolation layer, can reduce or avoid the problem of the dished recess or abnormal recess, and thus improves the electrical performance of the semiconductor device and the product yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a method for forming a trench isolation structure and a semiconductor device. Background Technology

[0002] With the continuous development of semiconductor manufacturing technology, the geometric dimensions of semiconductor structures are constantly shrinking, and the size of the isolation region between semiconductor devices is also decreasing accordingly. Currently, shallow trench isolation (STI) structures are mostly used to achieve isolation between devices.

[0003] Shallow trench isolation is a key process module in integrated circuit manufacturing used to achieve active region electrical isolation. Its typical process flow includes: etching a silicon substrate to form trenches, depositing dielectric materials such as high-density plasma silicon oxide (HDP oxide) or fluidized silicon oxide (F-CVD) to fill the trenches, removing excess dielectric material through chemical mechanical polishing (CMP) to expose the silicon nitride stop layer, and subsequent oxide retrieval process to adjust the final height of the isolation dielectric, preparing for subsequent gate structure formation or epitaxial growth.

[0004] However, in the traditional process flow, abnormal grooves are easily formed during CMP and subsequent etching of the isolation dielectric material, resulting in dish-shaped depressions in the final STI dielectric isolation layer. This dish-shaped depression structure will cause problems in the subsequent contact area manufacturing and affect the performance of semiconductor devices. Summary of the Invention

[0005] The purpose of this invention is to provide a method for forming a trench isolation structure and a semiconductor device, which can at least alleviate the problem of dish-shaped depressions in the dielectric isolation layer that are easily generated in the current process, and is beneficial to improving the electrical performance of the semiconductor device and the product yield.

[0006] In a first aspect, the present invention discloses a method for forming a trench isolation structure, the method comprising: A substrate is provided, the substrate including a plurality of trenches and fins located between adjacent trenches, a patterned mask layer is formed on the fins, the trenches are filled with trench isolation material, and the top surface of the trench isolation material is substantially flush with the top surface of the patterned mask layer; The trench isolation material is etched in such a way that a height difference is formed between the bottom of the trench isolation material and the bottom of the patterned mask layer; Remove the patterned mask layer; The trench isolation material is etched to obtain a trench isolation structure.

[0007] In an optional embodiment, in the step of etching the trench isolation material, the trench isolation material has a recess in the patterned mask layer, the bottom of the recess being higher than the bottom of the patterned mask layer.

[0008] In an optional embodiment, the height difference between the bottom of the recess and the bottom of the patterned mask layer is A, and the depth of the recess is B, wherein A and B satisfy: A = (1~5) × B.

[0009] In an optional embodiment, the method of etching a portion of the trench isolation material includes: removing a portion of the trench isolation material using a wet etching process.

[0010] In an optional embodiment, the step of etching the trench isolation material to obtain the trench isolation structure includes: An isotropic etching process is used to perform a first etching process on the trench isolation material exposed on the substrate, so that the trench isolation material located on the substrate forms a convex structure. A second etching process is performed on the trench isolation material located on the substrate and within the trench to obtain a trench isolation structure.

[0011] In an optional embodiment, the step of etching the trench isolation material to obtain the trench isolation structure includes: An isotropic etching process is used to etch the trench isolation material located on the substrate and within the trench to obtain a trench isolation structure.

[0012] In an optional embodiment, the step of providing the substrate includes the following steps: A transition layer, a mask layer, and a patterned layer with an isolation pattern are sequentially formed on the substrate; Using the patterned layer as a mask, the mask layer, the transition layer, and a portion of the substrate are etched sequentially to form a patterned mask layer, a patterned transition layer, and an initial trench structure; The initial trench structure is filled with trench isolation material, the top surface of which is higher than the top surface of the patterned mask layer; The trench isolation material is planarized so that the top surface of the trench isolation material is approximately flush with the top surface of the patterned mask layer.

[0013] In an optional embodiment, the method of filling the initial trench structure with trench isolation material includes: filling the initial trench structure with trench isolation material using a flowable chemical vapor deposition process.

[0014] In an optional embodiment, the planarization process includes treating the trench isolation material using a chemical mechanical polishing process.

[0015] In an optional embodiment, the trench isolation material includes at least one of silicon oxide, silicon oxycarbonitride, or a low-k dielectric material.

[0016] In a second aspect, the present invention discloses a semiconductor device, the semiconductor device comprising a trench isolation structure formed by the aforementioned trench isolation structure forming method.

[0017] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects: The trench isolation structure formation method of this application first forms a trench isolation material in the trenches of the substrate and within the patterned mask layer, and then etches the trench isolation material. Specifically, during the etching process, a height difference is created between the bottom of the trench isolation material's depression and the bottom of the patterned mask layer. This allows the trench isolation material to form a convex structure on the substrate after the patterned mask layer is removed. Further etching of the trench isolation material within the substrate based on this convex structure utilizes the central protrusion as a mask layer to resist etching, thus mitigating the dishing problem during the etching process. Furthermore, this method avoids the damage to the fins caused by CMP processes in related technologies, ultimately improving device performance and chip yield.

[0018] In addition, the method of forming this application is simple to implement, low in cost, and has significant effects, making it suitable for widespread application.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a shallow trench membrane structure in related technologies. Figure 2A This is a schematic diagram of the first part of a method for fabricating a shallow trench isolation structure provided in related technologies; Figure 2BThis is a second part of a schematic diagram illustrating a method for fabricating a shallow trench isolation structure provided in related technologies; Figure 2C This is a schematic diagram of the third part of a method for fabricating a shallow trench isolation structure provided in related technologies; Figure 3A This is a first-part schematic diagram of another method for fabricating a shallow trench isolation structure provided in the related technology; Figure 3B This is a second part of a schematic diagram illustrating another method for fabricating a shallow trench isolation structure provided in the related technology; Figure 4 A schematic flowchart illustrating the method for forming a trench isolation structure according to an embodiment of the present invention; Figure 5 This is a flowchart illustrating steps S110 to S130 in the method for forming a trench isolation structure provided in an embodiment of the present invention. Figure 6 A flowchart illustrating steps S410 to S420 in the method for forming a trench isolation structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of step S110 in the method for forming a trench isolation structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of step S120 in the method for forming a trench isolation structure provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of step S130 in the method for forming a trench isolation structure provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of step S200 in the method for forming a trench isolation structure provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of step S300 in the method for forming a trench isolation structure provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of step S410 in the method for forming a trench isolation structure provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of step S420 in the method for forming a trench isolation structure provided in an embodiment of the present invention.

[0022] Explanation of reference numerals in the attached figures: Figures 1 to 3B middle: 1-Silicon substrate; 2-Transition layer; 3-Hard mask layer; 4-Dielectric layer; Figures 4 to 13 middle: 100-substrate; 200 - Graphical transition layer; 300 - Patterned mask layer; 400 - Graphical layer; 500 - Groove isolation material; 510 - Convex structure. Detailed Implementation

[0023] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0025] refer to Figure 1 As shown, in related technologies, the film structure used to form a shallow trench isolation (STI) structure typically includes a silicon substrate 1, a transition layer 2, and a hard mask layer 3 arranged sequentially from bottom to top. In some cases, the fabrication process of this shallow trench isolation structure typically includes the following steps: First, it is formed through steps such as photolithography, multiple etching processes, sidewall deposition, and cleaning. Figure 1 The trench structure is shown in the figure; then the trench is filled with a dielectric material, such as by flowing chemical vapor deposition (FCVD) to fill the dielectric layer 4; after filling, a CMP process is performed to mechanically and chemically polish the dielectric layer 4 until it stops at the top surface of the hard mask layer 3; then an etching process is used to remove the dielectric layer 4 on the basis of CMP, and by controlling the etching time, the dielectric etching stops exactly at the level of the bottom of the dielectric layer, forming a structure as shown in the figure. Figure 2A The structure shown is then removed by high-selectivity etching to form a hard mask layer 3, as shown. Figure 2B The structure shown is then subjected to a final dielectric etching process to expose the fins, forming the STI structure of a fin field-effect transistor (FinFET), as shown below. Figure 2C As shown. However, in this process flow, CMP and subsequent dielectric layer etch-back processes are prone to producing dishing, which leads to severe dishing in the final STI dielectric isolation layer, such as... Figure 2C The structure is shown. If there are severe depressions on the surface of the dielectric layer of STI, the depressed areas will form unexpected cavities or morphological distortions, which will damage the crystal quality of epitaxial growth. In addition, the height difference between the edge and bottom of the depression will cause unevenness of the epitaxial growth substrate, resulting in misalignment or uneven thickness of subsequent nanosheet stacking, which will directly affect the electrical performance of the device, that is, affect the product quality.

[0026] In related technologies, to alleviate the above situation, the fabrication of shallow trench isolation structures has been optimized. For example, another fabrication process for a shallow trench isolation structure provided in related technologies includes the following steps: First, it is formed through steps such as photolithography, multiple etching processes, sidewall deposition, and cleaning. Figure 1 The trench structure is shown in the diagram; then, the trench is filled with a dielectric material, such as by flowing chemical vapor deposition (FCVD); after filling, a first CMP process is performed to mechanically and chemically polish the dielectric layer 4 until it stops at the top surface of the hard mask layer; then, an etching process is used to remove the dielectric layer 4 on top of the CMP process, controlling the etching time so that the etching stops exactly at the bottom of the dielectric layer 4, and then the hard mask layer is removed by high-selectivity etching; then, a second CMP process is added to planarize the surface of the dielectric layer 4, such as... Figure 3A As shown, a final dielectric back etching is performed to expose the fins, forming the STI structure of the fin field-effect transistor (FinFET), as follows. Figure 3B As shown, this method, by adding a CMP (Chemical Motion Processing) step, can mitigate the dish-shaped recess to some extent. However, CMP requires precise positioning on the fin. Because the fin width is very small in advanced processes, it is difficult for CMP to precisely stop at the fin tip, and the grinding process easily damages the fin structure, even causing breakage, leading to decreased device performance and reduced product yield. Therefore, the fabrication method for shallow trench isolation structures in this technology still needs improvement.

[0027] In view of this, the present invention discloses a method for forming a trench isolation structure and a semiconductor device. The present invention mainly optimizes the current STI fabrication process and provides a novel process method for forming STI, so as to alleviate the problem of severe dish-shaped depressions on the surface of the isolation dielectric layer in the current related technologies, or to alleviate the problem that the newly added CMP process is very easy to damage the Fin structure, or even directly cause Fin fracture, ultimately affecting device performance and product yield.

[0028] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses a method for forming a trench isolation structure, such as... Figure 4 As shown, the forming method includes: S100, a substrate 100 is provided, the substrate 100 includes a plurality of trenches and fins located between two adjacent trenches, a patterned mask layer 300 is formed on the fins, the trenches are filled with trench isolation material 500, and the top surface of the trench isolation material 500 is substantially flush with the top surface of the patterned mask layer 300. S200, Etch a portion of the trench isolation material 500 to create a height difference between the bottom of the recessed trench isolation material 500 and the bottom of the patterned mask layer 300; S300, Remove the patterned mask layer 300; S400, etching trench isolation material 500, to obtain a trench isolation structure.

[0029] To mitigate the severe dish-shaped depression problem caused by CMP processes and subsequent dielectric etch-back processes in related technologies, which affects device performance and chip yield, or to address the issue of CMP processes being added to the fabrication process, the small critical dimension (CD) of the active region (Fin) makes the Fin structure highly susceptible to damage or even breakage during CMP, leading to degraded device performance and extremely low yield. This embodiment provides a method for forming a trench isolation structure that can improve the formation of dish-shaped depressions and avoids the need for additional CMP processes, thereby improving device performance and chip yield.

[0030] In this embodiment, during the etching process of the trench isolation material 500 in step S200, a height difference is formed between the bottom of the trench isolation material 500 and the bottom of the patterned mask layer 300. Thus, unlike the conventional method of making the bottom of the trench isolation material 500 flush with the patterned mask layer 300, this embodiment creates a height difference between the bottom of the trench isolation material 500 and the bottom of the patterned mask layer 300. This allows the trench isolation material 500 on the substrate 100 to form a convex structure 510 in subsequent processing. That is, during the etching of the trench isolation material 500 in step S400, a convex structure 510 can be formed on the substrate 100. Based on this convex structure 510, the trench isolation material 500 within the substrate 100 is further etched. The central protrusion acts as a mask layer to resist etching, thus offsetting the dishing problem during the etching process of the trench isolation material 500 within the substrate 100. In other words, the dish-shaped depression is mainly caused by the fact that the etching rate on both sides of the trench isolation material 500 in the trench is less than the etching rate in the middle. That is, after the etching gas diffuses into the trench, the gas at the edge of the fin is in single-sided contact, while the center of the trench is in overall contact, resulting in a faster etching rate in the center and causing the trench isolation material 500 to form an abnormal depression in the trench. In this embodiment, the trench isolation material 500 is formed into a convex structure 510 (i.e., a protrusion) on the substrate 100. Due to the presence of the protrusion, during the etching process of the trench isolation material 500, since the etching rate on both sides of the trench isolation material 500 is less than the etching rate in the middle, and the etching rate at the edge is less than the etching rate in the middle, the protrusion can compensate for the difference in etching rates between the edge and the middle, making the etching rates of the edge and the middle compatible. Therefore, after etching, it is beneficial to form a trench isolation structure with a flat surface, thus avoiding the formation of dish-shaped depressions.

[0031] Therefore, this embodiment can avoid the formation of disc-shaped depressions and reduce the damage to the fins that can easily occur during chemical mechanical polishing (CMP). Furthermore, this embodiment avoids the damage to the fins caused by the increased CMP process in related technologies, ultimately improving device performance and chip product yield.

[0032] In some embodiments, a patterned transition layer 200 is further provided between the fin of the substrate 100 and the patterned mask layer 300. As an example, the patterned transition layer 200 and the patterned mask layer 300 are sequentially provided on the fin of the substrate 100.

[0033] The method in this embodiment can avoid the damage to the fins caused by the CMP process in related technologies and reduce the problem of disc-shaped depressions.

[0034] Specifically, such as Figure 5 As shown, in some embodiments, step S100, the process of providing a substrate, specifically includes the following steps: S110. A transition layer, a mask layer (such as a hard mask layer), and a patterned layer 400 with an isolation pattern are sequentially formed on the substrate 100. Using the patterned layer 400 as a mask, the hard mask layer, the transition layer, and part of the substrate 100 are sequentially etched to form a patterned mask layer 300, a patterned transition layer 200, and an initial trench structure. S120. Fill the initial trench structure with trench isolation material 500 (i.e., isolation material or dielectric material used to form the bottom dielectric isolation layer), the top surface of the trench isolation material 500 being higher than the top surface of the patterned mask layer 300. S130. The trench isolation material 500 is planarized so that the top surface of the trench isolation material 500 is approximately flush with the top surface of the patterned mask layer 300. It should be understood that during or after the planarization process of the trench isolation material 500, the patterned layer 400 with the isolation pattern is removed, the top surface of the patterned mask layer 300 is exposed, and then a portion of the trench isolation material 500 is removed so that the top surface of the trench isolation material 500 is approximately flush with the top surface of the patterned mask layer 300.

[0035] In this embodiment, in step S110, during the process of providing the substrate, a semiconductor structure can be provided first. This semiconductor structure includes a substrate 100, a transition layer formed on the surface of the substrate 100, a hard mask layer formed on the surface of the transition layer, and a patterned layer 400 with isolation patterns formed on the hard mask layer. Using the patterned layer 400 as a mask, the hard mask layer, the transition layer, and a portion of the substrate 100 are sequentially etched to form an initial trench structure, i.e., shallow trenches. The areas between adjacent shallow trenches are active regions, such as... Figure 7 As shown.

[0036] It should be understood that the structure formed in step S110 has several trenches (shallow trenches). The number of trenches can be one, two, or more. The present invention does not limit the specific number of trenches, and can be selected and set according to needs. The substrate 100 between adjacent trenches forms fins, which can also be called active regions (Fin). That is, the sidewalls of the trenches form fins, and the upper end of the fins has a patterned transition layer 200. The patterned transition layer 200 has a patterned mask layer 300. Several trenches can be formed by sequentially etching the hard mask layer, the transition layer, and a portion of the substrate 100.

[0037] It should be noted that the above semiconductor structure may include shallow trenches with a width of more than 200 μm, and may also include shallow trenches with a width of less than 200 μm. Shallow trenches of different widths are suitable for distribution in different regions of the semiconductor structure, and can be selected as needed without special restrictions.

[0038] In the above semiconductor structure, the substrate 100 can provide an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as a bare die or a wafer processed by epitaxial growth process.

[0039] Optionally, the substrate 100 can be made of silicon, such as a silicon substrate or a silicon substrate on an insulator. In other embodiments of the present invention, the substrate 100 may also be selected from other semiconductor materials such as silicon carbide, germanium, gallium arsenide, or silicon-germanium compounds. Those skilled in the art can select the type of semiconductor substrate according to the semiconductor device formed on the substrate, therefore the type of substrate should not limit the scope of protection of the present invention.

[0040] Optionally, the substrate 100 can be circular, square, or other regular or irregular shaped substrates. This application does not limit the specific shape and structure of the substrate 100, which can be circular, square, or other shaped substrates.

[0041] Optionally, the transition layer can be an oxide layer, for example, the material of the transition layer can be, but is not limited to, silicon dioxide (SiO2).

[0042] In this embodiment, a transition layer is formed on the substrate 100. The transition layer can serve as a buffer layer to improve the stress between the substrate 100 and the subsequently formed hard mask layer. The transition layer can be, for example, a dense silicon oxide material. Optionally, the transition layer can be formed by methods such as dry oxidation, wet oxidation, or in-situ water vapor growth, and there is no limitation on the method.

[0043] Optionally, the mask layer is a hard mask layer, and the material of the hard mask layer may include, but is not limited to, silicon nitride (SiN).

[0044] In this embodiment, a transition layer is formed on the substrate 100, and then a hard mask layer is formed on the transition layer. The hard mask layer can be, for example, silicon nitride. The hard mask layer can serve as a hard mask layer during trench etching to protect the substrate 100 from damage. Optionally, the hard mask layer can be formed using methods such as low-pressure chemical vapor deposition, and there are no limitations on this.

[0045] In this embodiment, a patterned layer 400 with an isolation pattern is formed on the hard mask layer. The isolation pattern can be used to define the distribution area of ​​the shallow trench isolation structure. For example, photoresist is first formed on the hard mask layer to cover the upper surface of the hard mask layer. After exposure and development, an isolation pattern with an exposed portion of the hard mask layer is formed on the photoresist. The position of the exposed portion of the hard mask layer on the photoresist corresponds to the position of the shallow trench isolation structure.

[0046] Then, using a photoresist with an isolation pattern as a mask, a hard mask layer, a transition layer, and a portion of the substrate 100 are sequentially etched to form a patterned mask layer 300, a patterned transition layer 200, and an initial trench structure. Optionally, in this embodiment, dry etching can be used to form the initial trench structure, for example.

[0047] In this embodiment, the semiconductor device formed by the above-described semiconductor structure includes, but is not limited to, a fin field-effect transistor.

[0048] Optionally, the method of filling the initial trench structure with trench isolation material 500 includes filling the initial trench structure with trench isolation material 500 using a flowable chemical vapor deposition (FCVD) process.

[0049] In this embodiment, as Figure 8 As shown, in step S120, the trench isolation material 500 can be filled using FCVD, and the filling needs to be overfilled, that is, the top of the trench isolation material 500 needs to be higher than the top surface of the patterned mask layer 300, so that the initial trench structure is filled and the top is flat, that is, the surface flatness is guaranteed, thereby ensuring the isolation effect and reducing the difficulty of subsequent chemical mechanical polishing (CMP). Then, an annealing process can be performed to densify it.

[0050] Furthermore, the flowable chemical vapor deposition filling method can meet the requirements of small openings and large depth-to-width ratio of shallow trench isolation structures.

[0051] Optionally, such as Figure 9 As shown, in step S130, the planarization process includes: treating the trench isolation material 500 using a chemical mechanical polishing (CMP) process.

[0052] In step S130, CMP is used to planarize the trench isolation material 500, stopping at the hard mask layer, so that the top surface of the trench isolation material 500 is flush with the top surface of the hard mask layer, forming a shape as shown in the image. Figure 9 The structure shown is as follows. That is, the trench isolation material 500 is subjected to CMP process and stopped at the hard mask layer.

[0053] In some embodiments, the trench isolation material 500 (i.e., the isolation material used to form the bottom dielectric isolation layer) includes, but is not limited to, silicon oxide (SiO2). x The trench isolation material 500 may be any one or more of silicon nitride, silicon oxynitride (SiOCN), or a low-k dielectric material. Furthermore, the trench isolation material 500 may also be one or more combinations of silicon nitride, silicon oxynitride, or ultra-low-k dielectric materials. The trench isolation material 500 may include silicon dioxide or other materials that can separate the active regions of the device. In this embodiment, as an example, the trench isolation material 500 is selected from silicon oxide (SiO2). x ).

[0054] In this embodiment, both the patterned transition layer 200 and the trench isolation material 500 are made of silicon oxide.

[0055] In some embodiments, such as Figure 10 As shown, in step S200, in the step of etching a portion of the trench isolation material 500, the trench isolation material 500 has a recess in the patterned mask layer 300, and the bottom of the recess is higher than the bottom of the patterned mask layer 300.

[0056] In this embodiment, an etching process is used to etch the trench isolation material 500. By controlling the etching time, the trench isolation material 500 stops above the bottom of the hard mask layer, forming a shape as shown. Figure 10 The structure shown. For example, during the etching process of the trench isolation material 500, the etching time can be controlled so that the etching of the trench isolation material 500 stops just above the bottom of the hard mask layer.

[0057] It should be understood that by controlling etching conditions such as etching time, the trench isolation material 500 can be made slightly higher than the bottom of the hard mask layer. This height difference depends on the amount of dish-shaped depressions formed by normal etching. The more severe the dish-shaped depressions, the higher the height difference, in order to counteract the dish-shaped depressions.

[0058] In some embodiments, the method of etching a portion of the trench isolation material 500 in step S200 includes: removing a portion of the trench isolation material 500 using a phosphoric acid wet etching process.

[0059] The operating conditions of this phosphoric acid wet etching process include etching time, which is determined based on the height difference between the bottom of the trench isolation material (more than 500mm) and the bottom of the hard mask layer. For example, the etching time can be 1s to 60s, or 1s to 30s, or 1s to 10s, etc., without much restriction.

[0060] In addition, other operating conditions of the phosphoric acid wet etching process can be selected and set according to the actual situation, as long as the trench isolation material 500 is etched just above the bottom of the hard mask layer and does not limit the purpose of the present invention.

[0061] Optionally, the height difference between the bottom of the recess and the bottom of the patterned mask layer 300 is A, and the depth of the recess is B. A and B satisfy: A = (1~5) × B.

[0062] It should be understood that the height difference between the bottom of the groove isolation material 500 and the bottom of the hard mask layer is related to the degree of the groove isolation material 500. The greater the degree of the groove isolation material 500, that is, the more severe the dish-shaped depression, the greater the height difference. This can offset the dish-shaped depression and make it easier to form a shallow groove isolation structure with a flat surface in the future.

[0063] As an example, the above A = (1~5) × B. Further, A = (1~3) × B. Further, A = (1~2) × B. For example, A can be 1 times B, or A can be 2 times B, or A can be 3 times B, etc.

[0064] In this embodiment, the patterned mask layer 300 can be a patterned hard mask layer, that is, the mask layer can be a hard mask layer.

[0065] In some embodiments, such as Figure 11 As shown, in step S300, the patterned mask layer 300 is removed. A high selectivity etching process can be used to etch the patterned mask layer 300 to completely remove it, forming a layer as shown in the image. Figure 11 The structure shown.

[0066] In high-selectivity etching processes, the selectivity ratio of silicon nitride to silicon can be greater than 50:1, and the selectivity ratio of silicon oxide to silicon can also be greater than 50:1; for example, SiN:Si > 50:1, SiO x The ratio of Si to Si is greater than 50:1, in order to achieve selective etching of the transition layer and the hard mask layer.

[0067] It should be noted that other process conditions of this high selectivity etching process can be selected and set by those skilled in the art according to the actual situation, and there are no special restrictions on them, as long as the hard mask layer can be effectively removed.

[0068] In some embodiments, such as Figure 6 As shown, step S400, the step of etching the trench isolation material 500 to obtain the trench isolation structure includes: S410, The trench isolation material 500 exposed on the substrate 100 is subjected to a first etching process using an isotropic etching process, so that the trench isolation material 500 located on the substrate 100 forms a convex structure 510. S420, A second etching process is performed on the trench isolation material 500 located above and within the substrate 100 to obtain a trench isolation structure.

[0069] In this embodiment, after removing the patterned hard mask layer 300, an isotropic etching step is added, that is, step S410 is added, to perform a dielectric etching modification, etching the trench isolation material 500 into a convex structure 510, such as... Figure 12 As shown; then, after a further etching step of trench isolation material 500, i.e. step S420, the final shallow trench isolation structure, i.e., the STI structure, is formed, as shown. Figure 13 As shown.

[0070] Therefore, by adding an isotropic etching step to modify the morphology of the trench isolation material 500 (modifying it to a convex shape), the embodiment of the present invention offsets the dish-shaped depression problem in the final etching process of the trench isolation material 500. That is, when the convex morphology is subjected to isotropic etching, the convex morphology in the middle will act as a mask layer to resist etching, and finally eliminate the dish-shaped depression. In addition, this solution avoids the damage to the Fin during the CMP process, and can ultimately improve device performance and chip product yield.

[0071] The above step S420 can be performed using conventional processing methods, such as first etching the trench isolation material 500 to form a convex structure 510, and then using a dry etching process to etch back the trench isolation material 500 so that the remaining trench isolation material 500 after the back etching reaches the preset thickness, thereby completing the shallow trench isolation structure setting and obtaining a shallow trench isolation structure with a flat surface.

[0072] In other embodiments, step S400, the step of etching the trench isolation material 500 to obtain the trench isolation structure, includes: The trench isolation material 500 located above and within the substrate 100 is etched using an isotropic etching process to obtain a trench isolation structure.

[0073] Step S400 in this embodiment can be divided into two steps to perform the etching operation, or it can be performed in one step. For example, the final step of etching the trench isolation material 500 (dielectric etching) can also be done using isotropic etching, which can combine the etching of the trench isolation material 500 into one step.

[0074] In this embodiment, the specific shape and structure of the fin can take various forms. As one optional implementation, the upper end of the fin is smaller than the lower end, and the upper end of the fin is much smaller than the opening size of the upper end of the shallow trench. This increases the structural rigidity of the fin field-effect transistor and reduces the risk of fin deformation due to stress on the bottom of the fin.

[0075] Optionally, the size of the fin remains constant from top to bottom and then gradually increases; that is, the fin includes straight segments and arc segments. Correspondingly, the size of the shallow groove remains constant from top to bottom and then gradually decreases; that is, the shallow groove is a U-shaped groove, and the bottom of the U-shaped groove is an arc groove. With this configuration, the fin has an arc segment, which can reduce stress concentration at the bottom of the fin, thereby reducing the risk of breakage at the bottom of the fin; the corresponding arc groove bottom of the U-shaped groove can reduce the probability of void formation during medium filling, improving the quality of the isolation interface between the groove isolation material 500 and the shallow groove.

[0076] As another optional implementation of the present invention, embodiments of the present invention also disclose a semiconductor device comprising a trench isolation structure fabricated using the aforementioned method for forming a trench isolation structure. This trench isolation structure is used for physical isolation between adjacent devices.

[0077] In the embodiments of this application, the semiconductor devices include, but are not limited to, one or more of the following semiconductor devices: fin field-effect transistor, metal-oxide-semiconductor field-effect transistor, complementary metal-oxide-semiconductor, insulated-gate bipolar transistor, gate turn-off thyristor, or thyristor.

[0078] The trench isolation structure formation method of this application first forms a trench isolation material 500 in the trench of the substrate 100 and within the patterned mask layer 300, and then etches the trench isolation material 500. During the etching process, a height difference is formed between the bottom of the trench isolation material 500 and the bottom of the patterned mask layer 300. Thus, after the patterned mask layer 300 is removed, the trench isolation material 500 is etched again, which forms a convex structure 510 on the substrate 100. Based on this convex structure 510, the trench isolation material 500 within the substrate 100 is further etched. The convex structure in the middle acts as a mask layer to resist etching, which can offset the dishing problem during the etching process of the trench isolation material within the substrate. That is, it can improve the dish-shaped dishing problem of the trench isolation material, and ultimately improve device performance and chip product yield. This invention effectively overcomes some practical problems in the prior art, thus having high utilization value and significance.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for forming a trench isolation structure, characterized in that, The forming method includes: A substrate is provided, the substrate including a plurality of trenches and fins located between adjacent trenches, a patterned mask layer is formed on the fins, the trenches are filled with trench isolation material, and the top surface of the trench isolation material is substantially flush with the top surface of the patterned mask layer; The trench isolation material is etched in such a way that a height difference is formed between the bottom of the trench isolation material and the bottom of the patterned mask layer; Remove the patterned mask layer; The trench isolation material is etched to obtain a trench isolation structure.

2. The method for forming the trench isolation structure according to claim 1, characterized in that, In the step of etching the trench isolation material, the trench isolation material has a recess in the patterned mask layer, and the bottom of the recess is higher than the bottom of the patterned mask layer.

3. The method for forming the trench isolation structure according to claim 2, characterized in that, The height difference between the bottom of the recess and the bottom of the patterned mask layer is A, and the depth of the recess is B, wherein A and B satisfy: A = (1~5) × B.

4. The method for forming the trench isolation structure according to claim 1, characterized in that, The method for etching the trench isolation material includes: removing a portion of the trench isolation material using a wet etching process.

5. The method for forming the trench isolation structure according to claim 1, characterized in that, The step of etching the trench isolation material to obtain the trench isolation structure includes: An isotropic etching process is used to perform a first etching process on the trench isolation material exposed on the substrate, so that the trench isolation material located on the substrate forms a convex structure. A second etching process is performed on the trench isolation material located on the substrate and within the trench to obtain a trench isolation structure.

6. The method for forming a trench isolation structure according to claim 1, characterized in that, The step of etching the trench isolation material to obtain the trench isolation structure includes: An isotropic etching process is used to etch the trench isolation material located on the substrate and within the trench to obtain a trench isolation structure.

7. The method for forming a trench isolation structure according to any one of claims 1 to 6, characterized in that, The step of providing the substrate includes the following steps: A transition layer, a mask layer, and a patterned layer with an isolation pattern are sequentially formed on the substrate; Using the patterned layer as a mask, the mask layer, the transition layer, and a portion of the substrate are etched sequentially to form a patterned mask layer, a patterned transition layer, and an initial trench structure; The initial trench structure is filled with trench isolation material, the top surface of which is higher than the top surface of the patterned mask layer; The trench isolation material is planarized so that the top surface of the trench isolation material is approximately flush with the top surface of the patterned mask layer.

8. The method for forming the trench isolation structure according to claim 7, characterized in that, The method of filling the initial trench structure with trench isolation material includes: filling the initial trench structure with trench isolation material using a flowable chemical vapor deposition process; And / or, the planarization process includes: treating the trench isolation material using a chemical mechanical polishing process.

9. The method for forming a trench isolation structure according to any one of claims 1 to 6, characterized in that, The trench isolation material includes at least one of silicon oxide, silicon oxycarbonitrile, or low-k dielectric material.

10. A semiconductor device, characterized in that, The semiconductor device includes a trench isolation structure fabricated using the trench isolation structure formation method according to any one of claims 1 to 9.

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