A method for manufacturing an fd-soi substrate structure by hydrogen, carbon, germanium ion implantation process
Patent Information
- Application Number
- CN202511781479.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-04-30
- Filing Date
- 2025-11-29
- Publication Date
- 2026-10-13
AI Technical Summary
[0003]基于现有技术存在的技术问题，本发明提供一种FD-SOI衬底结构通过氢、碳、锗离子注入工艺的制备方法，解决现有技术难以生产先进工艺要求的高品质FD-SOI衬底结构的问题，实现所制备的FD-SOI衬底结构顶层硅薄膜能够更薄且尺寸精度更高，并且工艺一致性稳定
[0032]本发明的FD-SOI衬底结构通过氢、碳、锗离子注入工艺的制备方法中，采用离子注入与湿法刻蚀工艺相结合的方式；首先通过注入氢离子，在晶圆表面一定深度位置处形成较为平整的弱化层，以便于后续进行剥离；接着注入碳离子和锗离子，在相对较浅的另两个深度位置处，形成两层较为平整的阻挡层，利用碳、锗离子较大的特点阻挡氢离子向晶圆表面的扩散，同时碳、锗离子不会对顶层硅薄膜造成器件上的改变；在后续进行湿法刻蚀工艺时，当刻蚀到阻挡层时，刻蚀速度会变慢很多，出现此现象即说明已刻蚀至对应的阻挡层位置，实现通过宏观现象了解微观尺度的变化；刻蚀速度先在经过最靠近表面的一层阻挡层时发生降低，起到提示作用、以便做好停止刻蚀的准备，在完全刻蚀过该层后，刻蚀速度又会升高，经过相对较短的一段时间后，将继续刻蚀到下一阻挡层，刻蚀速度再次变慢，此时停止刻蚀即可保留所需薄膜厚度；如此能够实现有效控制顶层硅薄膜达到所需的超薄厚度，氢离子注入以外的两道离子注入形成了两道刻蚀减速作用，进一步提高了表面减薄进程的可控性，保证了工艺一致性；并且湿法刻蚀工艺使得薄膜均匀度一致，可实现厚度落差低于2％，以及表面无缺陷；采用本发明方法制备的FD-SOI衬底结构表面比较平整，表面及结构内部缺陷少，能够保持较好的单晶性；本发明的方法尤其适用于先进工艺要求顶层硅薄膜达到纳米级的超薄厚度的情况，能够形成所需的高品质的纳米级超薄膜，对于FD-SOI技术在特征尺寸更小的半导体器件中的应用具有重大意义。
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Figure CN122910031A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor design and manufacturing technology, and specifically relates to a method for preparing an FD-SOI substrate structure by hydrogen, carbon, and germanium ion implantation. Background Technology
[0002] Currently, FD-SOI (Fully Depleted Silicon on Insulator) technology is gradually becoming a solution for advanced chips. In transistors fabricated using FD-SOI technology, the silicon thin film defines the source-drain junction depth and depletion region, which can improve short-channel effects such as DIBL (Drain Induced Barrier Lowering), further improving the subthreshold characteristics of the device and reducing the static power consumption of the circuit. Furthermore, FD-SOI transistors do not require channel doping, thus avoiding effects such as RDF (Random Dopants Fluctuation) and carrier mobility reduction, maintaining a stable threshold voltage (Vth). Unlike the 3D transistor structure used in FinFET technology, FD-SOI is a planar process technology, which can effectively reduce the complexity of the manufacturing process. Compared with traditional Bulk Silicon technology, FD-SOI provides better transistor electrostatic characteristics, and the buried oxide layer reduces the parasitic capacitance between the source and drain. In addition, this technology can effectively restrict the electron flow between the source and drain, significantly reducing the leakage current performance of the device. Besides the gate, FD-SOI can also control the transistor behavior through the bottom substrate of the device to achieve back bias control. However, to obtain semiconductor devices with sufficiently small feature sizes, an ultra-thin top silicon film needs to be formed in the FD-SOI substrate structure. Existing FD-SOI technology uses chemical mechanical polishing to form this top film structure, which tends to have large thickness differences (e.g., more than 10%) at the wafer edge and can also cause surface scratches. In existing FD-SOI substrate structures, the top silicon film is relatively thick, so the aforementioned defects do not have a significant impact on performance. However, for ultrathin top silicon films, such as those at the nanometer scale, these defects will significantly affect performance. Furthermore, when thinning the top silicon film through grinding or other processes, mechanical errors or the timing of process termination become apparent at the nanometer scale, making it difficult to precisely control the thickness of the retained top silicon film and resulting in poor process consistency. Summary of the Invention
[0003] Based on the technical problems existing in the prior art, the present invention provides a method for preparing FD-SOI substrate structure by hydrogen, carbon and germanium ion implantation process, which solves the problem that the prior art is difficult to produce high-quality FD-SOI substrate structure with advanced process requirements, and realizes that the top silicon film of the prepared FD-SOI substrate structure can be thinner and have higher dimensional accuracy, and the process consistency is stable.
[0004] According to the technical solution of the present invention, the present invention provides a method for preparing an FD-SOI substrate structure by hydrogen, carbon, and germanium ion implantation, comprising the following steps performed sequentially:
[0005] Step S1: Prepare the first wafer and the second wafer, both of which are wafer substrate bare dies;
[0006] Step S2: Perform thermal oxidation treatment on the surface of the first wafer to form an insulating oxide layer on the surface of the first wafer;
[0007] Step S3: First, hydrogen ion implantation is performed on the first wafer to form a hydrogen implantation layer under the insulating oxide layer; then carbon ion implantation and germanium ion implantation are performed. Carbon ion implantation is performed before or after germanium ion implantation. The first implanted ion of carbon ions and germanium ions forms a first implantation layer between the hydrogen implantation layer and the insulating oxide layer, and the second implanted ion of carbon ions and germanium ions forms a second implantation layer between the first implantation layer and the insulating oxide layer.
[0008] Step S4: After cleaning the surfaces of the first wafer and the second wafer, the surface of the insulating oxide layer of the first wafer is bonded to the second wafer using a bonding process.
[0009] Step S5: The first wafer is peeled off along the hydrogen implantation layer. The remaining first wafer forms the top silicon film on the second wafer in the part outside the insulating oxide layer. The top silicon film is then recrystallized by thermal annealing.
[0010] Step S6: The top silicon film is etched below the second implantation layer by wet etching process, so that the top silicon film reaches the required thickness.
[0011] In some embodiments, the insulating oxide layer is a silicon dioxide layer.
[0012] In some embodiments, in step S3, the dose of hydrogen ion implantation is higher than the dose of carbon ion implantation, and the dose of hydrogen ion implantation is higher than the dose of germanium ion implantation.
[0013] In some embodiments, the process parameters for hydrogen ion implantation in step S3 include: implantation energy: 50 keV to 200 keV, and implantation dose: 1 × 10⁻⁶. 16 atoms / cm 2 ~1×1018 atoms / cm 2 ;
[0014] And / or, the process parameters for carbon ion implantation include: implantation energy: 50 eV to 30 keV, implantation dose: 1 × 10⁻⁶. 13 atoms / cm 2 ~1×10 16 atoms / cm 2 ;
[0015] And / or, the process parameters for germanium ion implantation include: implantation energy: 50 eV to 10 keV, implantation dose: 1 × 10⁻⁶. 14 atoms / cm 2 ~1×10 16 atoms / cm 2 .
[0016] In some embodiments, the temperature condition for hydrogen ion implantation in step S3 is ≤60°C;
[0017] And / or, the temperature condition for carbon ion implantation is ≤0℃;
[0018] And / or, the temperature condition for germanium ion implantation is ≤0℃.
[0019] In some embodiments, the process parameters for hydrogen ion implantation in step S3 include: implantation energy: 10keV~200keV, and implantation dose: 1×10⁻⁶. 16 atoms / cm 2 ~1×10 18 atoms / cm 2 ;
[0020] And / or, the process parameters for carbon ion implantation include: implantation energy: 50 eV to 50 keV, implantation dose: 1 × 10⁻⁶. 13 atoms / cm 2 ~5×10 16 atoms / cm 2 ;
[0021] And / or, the process parameters for germanium ion implantation include: implantation energy: 50 eV to 50 keV, implantation dose: 1 × 10⁻⁶. 14 atoms / cm 2 ~5×10 16 atoms / cm 2 .
[0022] In some embodiments, the temperature condition for hydrogen ion implantation in step S3 is ≤100°C;
[0023] And / or, the temperature conditions for carbon ion implantation are ≤-10℃;
[0024] And / or, the temperature condition for germanium ion implantation is ≤-10℃.
[0025] In some implementations, in step S3, the spacing between the first injection layer and the second injection layer is less than or equal to 5 nm.
[0026] In some implementations, in step S4, the bonding process is a low-temperature bonding process with a bonding temperature of ≤200°C.
[0027] In some embodiments, in step S5, the thermal annealing process is a high-temperature thermal annealing process, and the temperature of the thermal annealing process is ≥500°C.
[0028] In some implementations, in step S4, the bonding process is a low-temperature bonding process with a bonding temperature of ≤350°C.
[0029] In some embodiments, in step S5, the thermal annealing process is a high-temperature thermal annealing process, and the temperature of the thermal annealing process is ≥400°C.
[0030] In some implementations, after step S6, the top silicon film reaches the desired ultrathin thickness, which is ≤20nm.
[0031] Compared with the prior art, the beneficial technical effects of the present invention are as follows:
[0032] The FD-SOI substrate structure of this invention is fabricated using a hydrogen, carbon, and germanium ion implantation process, which combines ion implantation with wet etching. First, hydrogen ions are implanted to form a relatively flat weakening layer at a certain depth on the wafer surface, facilitating subsequent stripping. Then, carbon and germanium ions are implanted to form two relatively flat barrier layers at two shallower depths. The larger size of carbon and germanium ions prevents the diffusion of hydrogen ions to the wafer surface, while also preventing them from altering the top silicon film. During the subsequent wet etching process, the etching rate slows significantly when the barrier layers are reached. This indicates that the corresponding barrier layer has been etched, allowing for observation of microscopic changes through macroscopic observations. The etching rate initially decreases when passing through the barrier layer closest to the surface, serving as an indication to prepare for stopping the etching process. After completely etching this layer… The etching rate increases again, and after a relatively short period, it continues etching to the next barrier layer. The etching rate slows down again, and at this point, etching is stopped to retain the required film thickness. This allows for effective control of the top silicon film to reach the required ultrathin thickness. The two ion implantations, in addition to hydrogen ion implantation, create two etching deceleration effects, further improving the controllability of the surface thinning process and ensuring process consistency. Furthermore, the wet etching process ensures uniform film uniformity, achieving a thickness difference of less than 2% and a defect-free surface. The FD-SOI substrate structure prepared using the method of this invention has a relatively flat surface with few surface and internal defects, maintaining good single crystallinity. The method of this invention is particularly suitable for advanced processes requiring the top silicon film to reach nanometer-level ultrathin thickness, enabling the formation of the required high-quality nanometer-level ultrathin films. This is of great significance for the application of FD-SOI technology in semiconductor devices with smaller feature sizes. Attached Figure Description
[0033] Figure 1 This is a flowchart of the method provided by the present invention.
[0034] Figures 2 to 9 This is a schematic diagram of the process of gradually obtaining the FD-SOI substrate structure using the method of the invention.
[0035] Explanation of reference numerals in the attached figures:
[0036] A. First wafer; B. Second wafer; 1. Insulating oxide layer; 2. Hydrogen implantation layer; 3. First implantation layer; 4. Second implantation layer; 5. Top silicon film; 6. Substrate. Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0038] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0039] It should be noted that the concepts of "first" and "second" mentioned in this invention are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.
[0040] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".
[0041] This invention provides a method for fabricating an FD-SOI substrate structure using hydrogen, carbon, and germanium ion implantation processes. In other words, it is a method for fabricating an FD-SOI substrate structure that includes hydrogen, carbon, and germanium ion implantation processes. It belongs to the field of semiconductor design and manufacturing. A typical fabrication method includes: (1) preparing two wafer substrates, A and B; (2) performing thermal oxidation treatment on the surface of wafer A; (3) performing hydrogen ion implantation (room temperature conditions), carbon ion implantation, and germanium ion implantation (low temperature conditions) on wafer A, wherein the carbon ion and germanium ion implantation depths should be similar, and the order of carbon ion and germanium ion implantation can be interchanged; (4) cleaning the surfaces of wafers A and B first, and then performing low-temperature bonding; (5) peeling wafer A to form a top silicon film, and then recrystallizing the top silicon film by high-temperature thermal annealing; (6) etching the top silicon film to an ultrathin film using wet etching. This invention improves the preparation method of FD-SOI without changing the FD-SOI substrate structure, solving the problem that existing technologies are unable to produce high-quality FD-SOI substrate structures that meet the requirements of advanced processes. The invention enables the prepared FD-SOI substrate structure to have a thinner top silicon film with higher dimensional accuracy and stable process consistency.
[0042] Please see Figures 1 to 9The present invention discloses a method for preparing an FD-SOI substrate structure by hydrogen, carbon, and germanium ion implantation, comprising the following steps performed sequentially.
[0043] Step S1 involves preparing a first wafer A and a second wafer B, both of which are bare wafer substrates. This step S1 corresponds to... Figure 2 The initial state is shown.
[0044] Step S2 involves performing a thermal oxidation treatment on the surface of the first wafer A to form an insulating oxide layer 1. In this embodiment, the insulating oxide layer 1 is a silicon dioxide layer. The state after step S2 is as follows: Figure 3 As shown.
[0045] Step S3: First, hydrogen ion implantation is performed on the first wafer A to form a hydrogen implantation layer 2 below the insulating oxide layer 1. Then, carbon ion implantation and germanium ion implantation are performed to form a first implantation layer 3 between the hydrogen implantation layer 2 and the insulating oxide layer 1, and a second implantation layer 4 between the first implantation layer 3 and the insulating oxide layer 1. More specifically, carbon ion implantation is performed before or after germanium ion implantation; in other words, the order of carbon ion implantation and germanium ion implantation can be interchanged. The first implanted carbon ion or germanium ion forms the first implantation layer 3 (shallower than the hydrogen implantation layer 2) between the hydrogen implantation layer 2 and the insulating oxide layer 1, and the later implanted carbon ion or germanium ion forms the second implantation layer 4 (further shallower than the first implantation layer 3) between the first implantation layer 3 and the insulating oxide layer 1. Both carbon ions and germanium ions are positive ions. In this embodiment, a high dose of hydrogen ions (room temperature conditions) is implanted first, followed by a low dose of carbon ions (low temperature conditions) and a low dose of germanium ions (low temperature conditions) implanted sequentially. The state of hydrogen ion implantation in step S3 is as follows: Figure 4 As shown, the state of carbon ion implantation is as follows: Figure 5 As shown, the state of germanium ion implantation is as follows: Figure 6 As shown.
[0046] Step S4: After cleaning the surfaces of the first wafer A and the second wafer B, the surface of the insulating oxide layer 1 of the first wafer A is bonded to the second wafer B using a bonding process. In this embodiment, the bonding process involves flipping the first wafer A over and placing it upside down on the upper surface of the second wafer B. Preferably, the bonding process is a low-temperature bonding process, with a bonding temperature of, for example, ≤200°C. In another preferred embodiment, the bonding process is a low-temperature bonding process, with a bonding temperature of, for example, ≤350°C. The state after step S4 is as follows: Figure 7 As shown.
[0047] In step S5, the first wafer A is peeled off along the hydrogen implantation layer 2 (i.e., based on the precise location of the weakening layer formed in the previous step). The remaining portion of the first wafer A, excluding the insulating oxide layer 1, forms the top silicon film 5 on the second wafer B. The top silicon film 5 is then recrystallized through thermal annealing. Preferably, the thermal annealing is a high-temperature thermal annealing, for example, at a temperature ≥500°C. In another preferred embodiment, the thermal annealing is a high-temperature thermal annealing, for example, at a temperature ≥400°C. The peeling process in step S5 is as follows: Figure 8 As shown.
[0048] Step S6 involves wet etching to etch the top silicon film 5 down to below the second implantation layer 4, achieving the desired thickness. The wet etching and the second implantation layer 4 formed in the preceding process allow for precise control of the thickness of the top silicon film 5. It should be noted that the wet etching is performed from top to bottom (from the surface inwards), with the etching surface moving downwards from the surface, first passing through the first implantation layer 3, and then etching to the second implantation layer 4. Preferably, after step S6, the top silicon film 5 reaches the desired ultrathin thickness, ≤20nm. The state after step S6 is as follows... Figure 9 As shown, the FD-SOI substrate structure is obtained, which consists of a substrate 6 (formed from the second wafer B), an insulating oxide layer 1, and a top silicon thin film 5 stacked sequentially.
[0049] The key concepts and principles of this invention are as follows.
[0050] In step S3, hydrogen ions are first implanted. The small size of the hydrogen ions allows them to penetrate deeper into the wafer, forming a bubble-like structure, which is the weakening layer of the wafer structure, or hydrogen implantation layer 2. Since this layer is a weak point in the wafer, it can be peeled off in step S5 to initially obtain the top layer structure of FD-SOI. Preferably, high-dose hydrogen ion implantation is used. Compared to low-dose implantation, high-dose implantation makes hydrogen implantation layer 2 smoother, resulting in a smoother surface after peeling.
[0051] After hydrogen ion implantation, carbon ions and germanium ions are implanted (the order can be interchanged), forming two barrier layers: the first implantation layer 3 and the second implantation layer 4. The implanted hydrogen diffuses, forming the first implantation layer 3 and the second implantation layer 4 above the hydrogen implantation layer. Because carbon and germanium ions are relatively large, they can block hydrogen diffusion, ensuring that the portion above the second implantation layer 4 (i.e., the final top silicon film 5) is free of hydrogen and boron, thus avoiding any impact on device performance. Carbon and germanium ion implantation is preferably performed at low doses. Small amounts of carbon and germanium have virtually no impact on the performance of silicon substrate devices, but they are still considered dopants; a sufficient amount is enough, as excessive amounts can have negative effects, such as negative electrical effects, significant lattice damage, and interference with subsequent recrystallization repair processes during thermal annealing.
[0052] In subsequent wet etching in step S6, the wet etching is performed from top to bottom (from the surface inwards). The etching surface moves downwards from the surface. The etching rate above the first implantation layer 3 (i.e., the etching rate for the wafer) is very fast. When the first implantation layer 3 is etched, the etching rate decreases significantly. After the first implantation layer 3 is completely etched away, the etching rate increases again as the wafer continues to be etched. Then, when the second implantation layer 4 is etched, the etching rate decreases again. Therefore, the etching rate (which is directly reflected in the corresponding etching equipment or can be obtained in real time through data processing) can be used to determine which layer the wafer has been etched to. Preferably, the depths of the first implantation layer 3 and the second implantation layer 4 are close. For example, the interval between the first implantation layer 3 and the second implantation layer 4 is less than or equal to 5 nm, and this interval is controlled by the implantation energy. The first implantation layer 3 serves as a clear reminder that after etching to the first implantation layer 3, etching to the second implantation layer 4 will soon follow. This allows for manual or automatic control to stop etching after reaching the second implantation layer 4, ensuring that the top silicon film 5 retains the required ultrathin thickness. In the preferred case where the depths of the first implantation layer 3 and the second implantation layer 4 are close, it also forms a "double insurance," significantly reducing the etching rate and ensuring that etching is "blocked," preventing excessive etching of the top silicon film 5.
[0053] It is worth noting that the first implantation layer 3 and the second implantation layer 4 are generally thinner (i.e., narrower in area) to avoid affecting the structure of other parts of the wafer and to ensure process efficiency. Consequently, the etching rate changes at the first implantation layer 3 and the second implantation layer 4 are relatively rapid and the duration is relatively short. Without the first implantation layer 3, the etching rate would only decrease at the second implantation layer 4, and after the decrease, etching would need to be stopped immediately (or after a set short time). For example, manual control might not be able to react quickly enough to this change. Therefore, the presence of the first implantation layer 3 can play a beneficial role in both manual and automated identification and control processes.
[0054] As a supplementary explanation, the depths of the hydrogen implantation layer 2, the first implantation layer 3, and the second implantation layer 4 are based on the implantation energy. For the same type of ions, the greater the implantation energy, the deeper the ions penetrate below the wafer surface. When the implanted ions have consistent energy, a layer structure of a specific depth will be formed. The implantation depths and corresponding implantation energies of the hydrogen implantation layer 2, the first implantation layer 3, and the second implantation layer 4 are designed to achieve the desired effect. In particular, the position of the second implantation layer 4 is directly related to the thickness of the final top silicon film 5.
[0055] Preferably, in step S3, the hydrogen ion implantation dose is higher than the carbon ion implantation dose, and the hydrogen ion implantation dose is higher than the germanium ion implantation dose. Further, the process parameters for hydrogen ion implantation include: implantation energy: 50keV~200keV, and implantation dose: 1×10⁻⁶. 16 atoms / cm 2 ~1×10 18 atoms / cm 2 ; and / or, the process parameters for carbon ion implantation include, implantation energy: 50 eV to 30 keV, and implantation dose: 1 × 10⁻⁶. 13 atoms / cm 2 ~1×10 16 atoms / cm 2 ; and / or, the process parameters for germanium ion implantation include: implantation energy: 50 eV to 10 keV, implantation dose: 1 × 10⁻⁶. 14 atoms / cm 2 ~1×10 16 atoms / cm 2 In another preferred embodiment, the hydrogen ion implantation dose is higher than the carbon ion implantation dose, and the hydrogen ion implantation dose is higher than the germanium ion implantation dose. Further, the process parameters for hydrogen ion implantation include: implantation energy: 10keV~200keV, and implantation dose: 1×10⁻⁶. 16 atoms / cm 2 ~1×10 18 atoms / cm 2 ; and / or, the process parameters for carbon ion implantation include, implantation energy: 50 eV to 50 keV, and implantation dose: 1 × 10⁻⁶. 13 atoms / cm 2 ~5×10 16 atoms / cm 2 ; and / or, the process parameters for germanium ion implantation include: implantation energy: 50 eV to 50 keV, implantation dose: 1 × 10⁻⁶. 14 atoms / cm 2 ~5×1016 atoms / cm 2 .
[0056] Preferably, in step S3, the temperature condition for hydrogen ion implantation is ≤60℃; and / or, the temperature condition for carbon ion implantation is ≤0℃; and / or, the temperature condition for germanium ion implantation is ≤0℃. In another preferred embodiment, in step S3, the temperature condition for hydrogen ion implantation is ≤100℃; and / or, the temperature condition for carbon ion implantation is ≤-10℃; and / or, the temperature condition for germanium ion implantation is ≤-10℃. Wherein, carbon ion and germanium ion implantation preferably employ a low-temperature ion implantation process, which can avoid ion diffusion during ion implantation, control the ions to be uniformly implanted to a specific location within the wafer, resulting in precise positioning and a narrow distribution range, thus forming a precisely positioned and flat implantation layer. Similarly, the hydrogen ion implantation temperature should not be too high; furthermore, when using low-temperature implantation, a lower dose can be selected for implantation, further avoiding lattice damage and reducing defects.
[0057] In summary, the FD-SOI substrate structure of this invention, fabricated using hydrogen, carbon, and germanium ion implantation, employs a combination of ion implantation and wet etching. First, hydrogen ions are implanted to form a relatively flat weakening layer at a certain depth on the wafer surface, facilitating subsequent stripping. Then, carbon and germanium ions are implanted to form two relatively flat barrier layers at two shallower depths. The larger size of carbon and germanium ions prevents the diffusion of hydrogen ions to the wafer surface, while simultaneously preventing carbon and germanium ions from altering the top silicon film. During subsequent wet etching, the etching rate slows significantly when the barrier layer is reached, indicating that the corresponding barrier layer has been reached, allowing for observation of microscopic changes through macroscopic observations. The etching rate initially decreases when passing the barrier layer closest to the surface, serving as an indication to prepare for stopping the etching process. The etching rate continues until the barrier layer is completely etched. After the first layer, the etching rate increases again. After a relatively short period, etching continues to the next barrier layer, where the etching rate slows down again. At this point, etching is stopped to retain the required film thickness. This allows for effective control of the top silicon film to achieve the desired ultrathin thickness. The two ion implantations, in addition to hydrogen ion implantation, create two etching deceleration effects, further improving the controllability of the surface thinning process and ensuring process consistency. Furthermore, the wet etching process ensures uniform film uniformity, achieving a thickness difference of less than 2% and a defect-free surface. The FD-SOI substrate structure prepared using the method of this invention has a relatively flat surface with few surface and internal defects, maintaining good single crystallinity. The method of this invention is particularly suitable for advanced processes requiring the top silicon film to achieve nanometer-level ultrathin thickness, enabling the formation of the required high-quality nanometer-level ultrathin films. This is of great significance for the application of FD-SOI technology in semiconductor devices with smaller feature sizes.
[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for preparing an FD-SOI substrate structure via hydrogen, carbon, and germanium ion implantation, characterized in that, This includes the following steps performed sequentially: Step S1: Prepare the first wafer (A) and the second wafer (B), both of which are wafer substrate dies; Step S2: Perform thermal oxidation treatment on the surface of the first wafer (A) to form an insulating oxide layer (1) on the surface of the first wafer (A); Step S3: First, hydrogen ion implantation is performed on the first wafer (A) to form a hydrogen implantation layer (2) under the insulating oxide layer (1); then carbon ion implantation and germanium ion implantation are performed. Carbon ion implantation is performed before or after germanium ion implantation. The first implanted ion of carbon ions and germanium ions forms a first implantation layer (3) between the hydrogen implantation layer (2) and the insulating oxide layer (1), and the second implanted ion of carbon ions and germanium ions forms a second implantation layer (4) between the first implantation layer (3) and the insulating oxide layer (1). Step S4: After cleaning the surfaces of the first wafer (A) and the second wafer (B), the surface of the insulating oxide layer (1) of the first wafer (A) is bonded to the second wafer (B) by a bonding process. Step S5: The first wafer (A) is peeled off along the hydrogen implantation layer (2). The remaining first wafer (A) forms the top silicon film (5) on the second wafer (B) in the part other than the insulating oxide layer (1). The top silicon film (5) is then recrystallized by thermal annealing. Step S6: The top silicon film (5) is etched below the second implantation layer (4) by wet etching process, so that the top silicon film (5) reaches the required thickness.
2. The method for preparing the FD-SOI substrate structure according to claim 1 using hydrogen, carbon, and germanium ion implantation, characterized in that... The insulating oxide layer (1) is a silicon dioxide layer.
3. The method for preparing the FD-SOI substrate structure according to claim 1 using hydrogen, carbon, and germanium ion implantation, characterized in that... In step S3, the process parameters for hydrogen ion implantation include: implantation energy: 50keV~200keV, and implantation dose: 1×10⁻⁶. 16 atoms / cm 2 ~1×10 18 atoms / cm 2 ; And / or, the process parameters for carbon ion implantation include: implantation energy: 50 eV to 30 keV, implantation dose: 1 × 10⁻⁶. 13 atoms / cm 2 ~1×10 16 atoms / cm 2 ; And / or, the process parameters for germanium ion implantation include: implantation energy: 50 eV to 10 keV, implantation dose: 1 × 10⁻⁶. 14 atoms / cm 2 ~1×10 16 atoms / cm 2 .
4. The method for preparing the FD-SOI substrate structure according to claim 1 using hydrogen, carbon, and germanium ion implantation, characterized in that... In step S3, the temperature condition for hydrogen ion implantation is ≤60℃; And / or, the temperature condition for carbon ion implantation is ≤0℃; And / or, the temperature condition for germanium ion implantation is ≤0℃.
5. The method for preparing the FD-SOI substrate structure according to claim 1 using hydrogen, carbon, and germanium ion implantation, characterized in that... In step S3, the spacing between the first injection layer (3) and the second injection layer (4) is less than or equal to 5 nm.
6. The method for preparing the FD-SOI substrate structure according to claim 1 using hydrogen, carbon, and germanium ion implantation, characterized in that... In step S5, the hot annealing treatment is a high-temperature hot annealing treatment, and the temperature of the hot annealing treatment is ≥500℃.
7. The method for preparing the FD-SOI substrate structure according to claim 1 using hydrogen, carbon, and germanium ion implantation, characterized in that... In step S3, the process parameters for hydrogen ion implantation include: implantation energy: 10keV~200keV, and implantation dose: 1×10¹⁶ atoms / cm²~1×10¹⁸ atoms / cm². And / or, the process parameters for carbon ion implantation include, implantation energy: 50 eV to 50 keV, and implantation dose: 1 × 10¹³ atoms / cm² to 5 × 10¹⁶ atoms / cm². And / or, the process parameters for germanium ion implantation include implantation energy: 50 eV to 50 keV, and implantation dose: 1 × 10¹⁴ atoms / cm² to 5 × 10¹⁶ atoms / cm².
8. The method for preparing the FD-SOI substrate structure according to claim 1 using hydrogen, carbon, and germanium ion implantation, characterized in that... In step S3, the temperature condition for hydrogen ion implantation is ≤100℃; And / or, the temperature conditions for carbon ion implantation are ≤-10℃; And / or, the temperature condition for germanium ion implantation is ≤-10℃.
9. The method for preparing the FD-SOI substrate structure according to claim 1 using hydrogen, carbon, and germanium ion implantation, characterized in that... In step S4, the bonding process is a low-temperature bonding process with a bonding temperature of ≤350℃.
10. The method for preparing the FD-SOI substrate structure according to claim 1 using hydrogen, carbon, and germanium ion implantation, characterized in that... In step S5, the hot annealing treatment is a high-temperature hot annealing treatment, and the temperature of the hot annealing treatment is ≥400℃.