A method of repairing yield loss from semiconductor process defects

Abstract

The present application belongs to the field of semiconductor core particle manufacturing, and relates to a method for repairing yield loss of semiconductor process defects, comprising: providing a wafer with particle defects, the wafer surface being formed with metal structures and metal residues generated by the particle defects, sequentially performing surface medium layer deposition, chemical mechanical polishing, photolithography, etching, secondary medium layer deposition and secondary chemical mechanical polishing on the wafer, so as to remove the particle defects and the metal residues, and complete medium filling between the metal structures after the metal residues are removed. The present application has universality and ease of use, regardless of the shape of the structure and the process node, the method of the present application does not require additional processes, additional equipment and new photomasks, and is aimed at appropriate process sites, i.e. after the initial CMP, performing photolithography, metal etching, medium filling and CMP processes again, so as to save the wafer yield reduced by the particle defects and avoid economic losses caused by wafer scrapping.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor chip manufacturing and relates to a method for repairing semiconductor process defects and yield loss. Background Technology

[0002] Semiconductor chips typically integrate millions of semiconductor devices, each of which often comprises dozens to hundreds of structural layers from bottom to top. Each layer is defined by photolithography and etching processes. For non-copper metal structures, the typical process sequence is metal thin film deposition, photolithography, and metal etching, such as... Figure 1 As shown. However, during chip manufacturing, particle contamination in the environment or equipment cavities is difficult to completely avoid. Once these particles land on the metal thin film or the developed photolithographic pattern, they cannot be removed by the etching gas, and these particle defects will directly affect the formation of the metal structure in subsequent etching processes, such as... Figure 2 As shown, the shape abnormalities caused by such defects cannot be repaired in subsequent conventional processes.

[0003] Yield testing shows that the impact of such defects is far greater than their own size, causing short-circuit failures in all devices on multiple adjacent bit lines (BLs). Each BL typically connects 512 or 1024 devices, with an adjacent bit line spacing of approximately 300 nm. In other words, in this metal etching process, a single particle defect of only about 300 nm in size can cause the failure of thousands of devices, resulting in severe yield losses, or even rendering the entire chip unusable. The root cause of this failure is that during the etching process, the particle defect blocks the metal film that should have been removed underneath, leaving metal residue and thus creating a conductive path between two or more originally independent bit lines.

[0004] Furthermore, although mature fab wafer fabs can control the density of particle defects to a low level, occasional abnormal shipments from process equipment may cause a sharp increase in the density of particle defects on the wafer. There is currently no way to salvage such accidents, and in severe cases, the wafer can only be scrapped. Summary of the Invention

[0005] To address the aforementioned technical problems in the existing technology, this invention proposes a method for repairing yield losses due to semiconductor process defects. This method can repair large-scale yield failures caused by residual etching of metal or dielectric films due to particle defects. The specific technical solution is as follows: A method for repairing semiconductor process defect yield loss provides a wafer with particle defects, the surface of which has a metal structure and metal residues generated by the particle defects. The wafer is subjected to surface dielectric layer deposition, chemical mechanical polishing, photolithography, etching, secondary dielectric layer deposition, and secondary chemical mechanical polishing in sequence to remove particle defects and metal residues, and to complete the dielectric filling between the metal structures after the removal of metal residues.

[0006] Furthermore, the metal structure includes a magnetic tunnel junction, a ferroelectric memory or a resistive switching memory film structure, and related electrode structures.

[0007] Furthermore, the metal residue is formed by particle defects that prevent the metal film from being etched, and creates conductive pathways between the metal structures.

[0008] Furthermore, the surface dielectric layer is deposited, and chemical mechanical polishing is used to remove all dielectric material on top of the metal structure, the metal layer on the surface of the metal structure, and the particle defects, thereby exposing the surface of the metal residue.

[0009] Furthermore, the wafer with the exposed metal residue is subjected to photolithography and metal etching again.

[0010] Furthermore, when performing photolithography again on the wafer that has exposed the metal residue, the photolithography process parameters are adjusted to increase the size of the photolithographic pattern, increase the window for photolithographic alignment, and protect the formed metal structure.

[0011] Furthermore, the dielectric filling between the metal structures is completed by secondary dielectric layer deposition, and the dielectric layer on top of the metal structure is removed by secondary chemical mechanical polishing to expose the top surface of the metal structure.

[0012] Beneficial effects: This invention is universal and easy to use. Regardless of the shape of the structure or the process node, the method proposed in this invention does not require additional processes, additional equipment, or new photomasks. It aims to salvage the wafer yield reduced by particles and avoid the economic losses caused by wafer scrap by performing photolithography, metal etching, dielectric filling, and CMP processes again at appropriate process stations, i.e., after the initial CMP (chemical mechanical polishing).

[0013] For metal structure residues that primarily function as conductors, theoretically, failures caused by metal residues can be 100% repaired. For resistive devices such as MTJs, ferroelectric memories, and resistive switching memories, film layer residues are crucial to device resistance and performance. Using the method proposed in this invention, since the device size within the film layer residue range is difficult to match the normal device size even after repair, device failures within the film layer residue range are irreversible. However, normal devices spanning multiple black bars (BLs) can function normally. The method proposed in this invention can recover at least 95% of failures caused by metal residues. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the photolithography and metal etching process performed after a metal thin film is formed on the wafer surface, under conditions where there are no particle defects. Figure 2 This is a schematic diagram of the photolithography and metal etching process under conditions of particle defects after a metal thin film is formed on the wafer surface. Figure 3 This is a schematic diagram of an MTJ (magnetic tunnel junction) memory chip with residual metal in this embodiment; Figure 4 This is a schematic diagram of the process for removing particulate defects in this embodiment; Figure 5 This is a schematic diagram of the process of removing metal residues and performing media deposition and chemical mechanical polishing in this embodiment.

[0015] In the figure, 1: TEOS substrate; 2: dielectric layer; 3: metal structure; 4: metal thin film; 401: electrode structure; 5: first photoresist; 501: second photoresist; 6: particle defects. Detailed Implementation

[0016] To make the objectives, technical solutions, and technical effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0017] This embodiment provides a method for repairing yield loss due to semiconductor process defects, specifically including: A wafer is provided, employing a TEOS substrate 1. Metal structures 3 are formed on the surface of the wafer. Metal residues exist between the metal structures 3 due to particle defects 6 obstructing the etching of metal films 4. These metal residues cause conductive paths, i.e., short circuits, between adjacent metal structures 3. (Refer to...) Figure 2As shown. To further illustrate the impact of metal residue, this embodiment uses the read / write process of an MTJ (Magnetic Tunnel Junction) memory chip as an example: each word line (WL) connects to multiple MTJ devices, and similarly, each bit line also connects to multiple MTJ devices. During normal read / write, only one word line and one bit line are energized at a time, and only the unique MTJ cell connected to both lines is selected for operation. However, when metal residue causes adjacent bit lines BL2 and BL3 to connect, such as... Figure 3 As shown, applying a voltage to BL2 indirectly powers BL3. At this time, if the MTJ at the WL5–BL2 intersection is read or written, the MTJs on WL5–BL3 will also be in a conducting state, significantly increasing the total current in the circuit to the sum of the two branches. Therefore, all MTJs on these two bit lines will be considered short-circuited and fail. As chips follow Moore's Law towards higher integration levels and device spacing continues to shrink, the critical particle size that can cause such high yield losses is becoming smaller and smaller, making it more difficult to avoid, and resulting in increasingly severe yield and economic losses.

[0018] To address the presence of particle defects 6, a dielectric layer 2 is deposited on the wafer surface, followed by chemical mechanical polishing to remove the particle defects 6, exposing the surface where the metal residue exists. (Refer to...) Figure 4 As shown. The chemical mechanical polishing removes all the medium on top of the metal structure 3 and a certain thickness of metal layer on the surface of the metal structure 3. At the same time, the particle defects 6 are also removed and disappear in the process, exposing a smooth metal residue.

[0019] Subsequently, the wafer with exposed metal residue is subjected to photolithography and metal etching again to remove the metal residue and disconnect the conductive path. A dielectric layer 2 is then deposited again to complete the dielectric filling between the metal structures 3, followed by chemical mechanical polishing to remove the dielectric layer 2 on top of the metal structures 3, exposing the top surface of the metal structures 3. (Refer to...) Figure 5 As shown.

[0020] During the second photolithography process, the photolithography process parameters are adjusted to increase the size of the photolithographic pattern, raise the window for photolithographic alignment, and protect the already formed metal structure. Alternatively, other suitable photomasks can be selected for the second photolithography, as long as they meet the requirement that the photoresist, after development, can completely cover the already formed normal metal structure and expose the residual metal layer.

[0021] The metal structure 3 includes a film structure of a magnetic tunnel junction, a ferroelectric memory, or a resistive switching memory, as well as an associated electrode structure 401.

[0022] It is understood that the method of the present invention can be used as a segment of the complete chip manufacturing process, or as an emergency treatment method, and is very suitable for repairing yield loss caused by a sharp increase in particle defect density on the wafer due to process equipment malfunction.

[0023] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the implementation process of the present invention has been described in detail above, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for repairing yield loss due to defects in semiconductor processes, characterized in that: A wafer with particle defects is provided. The surface of the wafer has a metal structure and metal residues caused by the particle defects. The wafer is subjected to surface dielectric layer deposition, chemical mechanical polishing, photolithography, etching, secondary dielectric layer deposition and secondary chemical mechanical polishing in sequence to remove particle defects and metal residues, and to complete the dielectric filling between the metal structures after the removal of metal residues.

2. The method for repairing semiconductor process defect yield loss as described in claim 1, characterized in that: The metal structure includes a magnetic tunnel junction, a ferroelectric memory or a resistive switching memory film structure, and related electrode structures.

3. The method for repairing semiconductor process defect yield loss as described in claim 1, characterized in that: The metal residue is formed by particle defects that prevent the metal film from being etched, and creates conductive pathways between metal structures.

4. The method for repairing semiconductor process defect yield loss as described in claim 1, characterized in that: The surface dielectric layer is deposited, and chemical mechanical polishing is used to remove all dielectric material on top of the metal structure, the metal layer on the surface of the metal structure, and the particle defects, thereby exposing the surface of the metal residue.

5. The method for repairing semiconductor process defect yield loss as described in claim 4, characterized in that: The wafer, which has exposed the metal residue, is then subjected to photolithography and metal etching again.

6. The method for repairing semiconductor process defect yield loss as described in claim 1, characterized in that: During the next photolithography process, the photolithography process parameters are adjusted to increase the size of the photolithographic pattern, raise the window for photolithographic alignment, and protect the already formed metal structure.

7. The method for repairing semiconductor process defect yield loss as described in claim 1, characterized in that: The dielectric filling between the metal structures is completed by secondary dielectric layer deposition, and the dielectric layer on top of the metal structure is removed by secondary chemical mechanical polishing to expose the top surface of the metal structure.

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