A three-dimensional capacitive resistor sheet integrated system

Abstract

The application discloses a three-dimensional capacitive and resistive sheet integrated system, which comprises a silicon substrate, one or more three-dimensional capacitive units arranged on the silicon substrate, each three-dimensional capacitive unit comprising a first through-silicon via, a through-hole capacitive electrode part, a first side capacitive electrode part and a second side capacitive electrode part, and one or more three-dimensional resistive units arranged on the silicon substrate, each three-dimensional resistive unit comprising a second through-silicon via, a through-hole resistive part, a first side resistive part and a second side resistive part, wherein an insulating medium layer is arranged between the first side resistive part, the second side resistive part and the through-hole resistive part and the silicon substrate. The application adopts a through-silicon via vertical integration process, is adjustable in multiple gears, has the characteristics of low parasitic, high integration, multiple gears, process compatibility and high reliability, and is suitable for radio frequency communication, optical communication, high-speed digital circuit and power management scenes.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically silicon-based integrated passive device (IPD) technology, and particularly relates to a single capacitor-resistor parallel integrated on-chip system based on through-silicon via (TSV) technology. Background Technology

[0002] As radio frequency and high-speed circuits develop towards higher frequencies, miniaturization, and higher integration, RC parallel passive networks have become the core unit for power supply decoupling, RF damping, impedance matching, and signal termination. Traditional solutions use discrete resistors and capacitors for surface mounting, which has drawbacks such as large parasitic inductance of leads, large footprint, numerous solder joints, low reliability, and fixed, non-adjustable resistor values.

[0003] While existing silicon-based integrated passive devices can integrate resistors and capacitors on the chip, they generally have the following problems: they only support fixed resistance values, lack multi-level switching capability, and cannot adapt to the damping and impedance adjustment requirements under different operating conditions; they mostly adopt planar thin film structures, resulting in large parasitic parameters and limited high-frequency performance. Traditional silicon capacitors use U-shaped deep trench blind vias, which result in poor etching uniformity, large capacitance deviation, high fabrication stress, and easy breakage; they also fail to achieve parallel topology optimization and common pad architecture design for single capacitors and multi-level resistors.

[0004] The applicant's prior patent CN202510164294.X discloses a double-sided open silicon through-hole capacitor, which adopts a cylindrical / prismatic / dumbbell-shaped through-hole structure, solving the problems of poor capacitance uniformity and stress breakage in blind-hole capacitors, with capacitance uniformity <1.3%. However, this patent only implements a single capacitor device and does not involve resistor integration, RC parallel network, or multi-level adjustable design, thus failing to meet the application requirements of on-chip RC adjustable networks.

[0005] Therefore, considering the aforementioned technical problems, it is necessary to provide a new technical solution. Summary of the Invention

[0006] To address at least one of the technical problems existing in the prior art, this invention aims to provide a three-dimensional capacitor-resistor on-chip integrated system based on through-silicon vias (TSVs). Utilizing vertical TSV technology, capacitors and resistors are integrated in three-dimensional space, and a common bottom electrode and independent pad architecture are introduced. The specific technical solution is as follows: This invention discloses a three-dimensional capacitor-resistor on-chip integrated system, comprising: a three-dimensional capacitor-resistor on-chip integrated system, characterized in that it comprises: silicon substrate; One or more 3D capacitor cells are disposed on the silicon substrate. Each 3D capacitor cell includes one or more first silicon vias penetrating the silicon substrate, a via capacitor electrode portion formed in the first silicon via, a first side capacitor electrode portion formed on a first side of the silicon substrate and electrically connected to the via capacitor electrode portion, and a second side capacitor electrode portion formed on a second side of the silicon substrate. The via capacitor electrode portion and the first side capacitor electrode portion form the first capacitor electrode of the 3D capacitor cell, and the silicon substrate and the second side capacitor electrode portion form the second capacitor electrode of the 3D capacitor cell. An insulating dielectric layer is filled between the first capacitor electrode and the second capacitor electrode. One or more three-dimensional resistive units disposed on the silicon substrate, each three-dimensional resistive unit including one or more second silicon vias penetrating the silicon substrate, a via resistor portion formed in the second silicon via, a first-side resistor portion formed on a first side of the silicon substrate and electrically connected to the via resistor portion, and a second-side resistor portion formed on a second side of the silicon substrate and electrically connected to the via resistor portion, wherein an insulating dielectric layer is disposed between the first-side resistor portion, the second-side resistor portion and the via resistor portion and the silicon substrate.

[0007] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, each three-dimensional capacitor unit further includes: A first capacitor pad is formed on the outside of the first side capacitor electrode portion and is electrically connected to the first side capacitor electrode portion; A second capacitor pad is formed on the outside of the second side capacitor electrode portion and is electrically connected to the second side capacitor electrode portion.

[0008] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, each three-dimensional resistor unit further includes: A first resistor pad is formed on the outside of the first-side resistor portion and is electrically connected to the first-side resistor portion; A second resistor pad is formed on the outside of the second-side resistor section and is electrically connected to the second-side resistor section.

[0009] As a preferred embodiment of the three-dimensional capacitor-resistor on-chip integrated system described in this invention, the second capacitor pad and the second resistor pad are electrically connected as a common resistor-capacitor pad.

[0010] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, each three-dimensional capacitor unit further includes: An end capacitor electrode portion formed on the second side of the silicon substrate and electrically connected to the through-hole capacitor electrode portion. The through-hole capacitor electrode portion, the first side capacitor electrode portion, and the end capacitor electrode portion form the first capacitor electrode of the three-dimensional capacitor unit.

[0011] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, the resistance range of the three-dimensional resistor unit can be configured in multiple ranges by the size of the second through-silicon via and the density of the second through-silicon via.

[0012] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, the resistance value of the three-dimensional resistor unit is in the range of 1Ω to 10KΩ.

[0013] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, the first through-silicon via and / or the second through-silicon via is a double-sided opening structure.

[0014] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, the first through-silicon via and / or the second through-silicon via is selected from one or more combinations of cylindrical, prismatic and dumbbell shapes.

[0015] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, the opening diameter of the first through-silicon via and / or the second through-silicon via is 2 μm to 20 μm.

[0016] As a preferred embodiment of the three-dimensional capacitor-resistor on-chip integrated system described in this invention, the first-side resistor portion is disposed on the outer surface of the insulating dielectric layer covering the first-side surface of the silicon substrate; The second-side resistor is disposed on the outer surface of the insulating dielectric layer covering the second-side surface of the silicon substrate.

[0017] As a preferred embodiment of the three-dimensional capacitor-resistor on-chip integrated system described in this invention, the first-side resistor portion and the second-side resistor portion are both disposed on the outside of the insulating dielectric layer, and the first-side resistor portion and the second-side resistor portion connect the through-hole resistor portions in a plurality of second silicon vias to form a three-dimensional series network.

[0018] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, the resistivity of the silicon substrate is 0.001~0.01 Ω·cm, the thickness is 50~300 μm, and the crystal orientation is [missing information]. <100> .

[0019] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, the insulating dielectric layer is selected from one or more combinations of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide.

[0020] As a preferred embodiment of the on-chip integrated system of three-dimensional capacitors and resistors described in this invention, the thickness of the insulating dielectric layer is 1 nm to 2000 nm.

[0021] As a preferred embodiment of the three-dimensional capacitor-resistor on-chip integrated system described in this invention, the through-hole resistor section, the first-side resistor section and / or the second-side resistor section are one of heavily doped polycrystalline silicon, tantalum nitride, titanium nitride, gold, platinum, aluminum and copper.

[0022] As a preferred embodiment of the three-dimensional capacitor-resistor on-chip integrated system described in this invention, the thickness of the first-side resistor portion and / or the second-side resistor portion is 10 nm to 2000 nm.

[0023] As a preferred embodiment of the three-dimensional capacitor-resistor on-chip integrated system described in this invention, the first capacitor pad, the second capacitor pad, the first resistor pad, and the second resistor pad are independently selected from one or more combinations of gold, aluminum, copper, titanium, nickel, and palladium.

[0024] As a preferred embodiment of the three-dimensional capacitor-resistor on-chip integrated system described in this invention, the thickness of the first capacitor pad, the second capacitor pad, the first resistor pad and / or the second resistor pad is 1000 nm to 10000 nm.

[0025] Compared with the prior art, the technical solution described in this application has at least one or more of the following beneficial effects: First, it achieves extreme miniaturization and high integration by utilizing the TSV vertical structure to transform the traditional planar wire-wound resistor into a three-dimensional series resistor, reducing the area occupied by more than 90% compared to planar resistors of the same specifications.

[0026] Secondly, it boasts excellent high-frequency performance. The vertical structure reduces the overlap area with the substrate, significantly reducing parasitic capacitance and inductance. The common bottom electrode design shortens the current loop, significantly improving high-frequency characteristics and making it suitable for RF applications above 10GHz.

[0027] Third, it is multi-level adjustable. By setting different numbers of resistor units or different sizes of resistor layers, multiple resistor levels from 1Ω to 10KΩ can be achieved on the same chip to meet the impedance matching requirements of different circuits.

[0028] Fourth, it features high uniformity and high reliability. Inheriting the double-sided opening through-silicon via (TSV) process, it solves the problem of uneven depth in blind via etching, with capacitance uniformity of <1.3%. The double-sided opening releases the stress of deep silicon etching, preventing wafer breakage.

[0029] Fifth, high power density, the three-dimensional heat dissipation path is superior to the planar structure, and the heat dissipation power density is increased by more than 4 times.

[0030] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0031] To more clearly illustrate the technical solution of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A cross-sectional structural diagram of the on-chip integrated system of a three-dimensional capacitor and resistor provided in this patent embodiment. Figure 2 The top view of the on-chip integrated system of three-dimensional capacitor and resistor provided in this embodiment of the patent shows the layout of the first capacitor pad on the three-dimensional capacitor unit and the first resistor pads of multiple three-dimensional resistor units. Figure 3 This is the electrical equivalent circuit diagram of the capacitor unit and the resistor unit in the embodiment of this patent.

[0033] Wherein, 1-silicon substrate, 101-resistor-capacitor common pad, 111-first silicon via, 112-insulating dielectric layer, 113-via capacitor electrode portion, 114-first side capacitor electrode portion, 115-second side capacitor electrode portion, 116-first capacitor pad, 117-end capacitor electrode portion, 121-second silicon via, 122-via resistor portion, 123-first side resistor portion, 124-second side resistor portion, 125-first resistor pad. Detailed Implementation

[0034] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0035] In the description of this invention, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," "outer," "front end," "rear end," "both ends," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0036] In the description of this invention, unless otherwise explicitly specified and limited, the terms "provided with," "equipped with," "connected," "installed," "sleeved," "opened," and "fixed," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] A three-dimensional capacitor-resistor on-chip integrated system includes a silicon substrate 1 and a silicon substrate 2. One or more 3D capacitor cells are disposed on the silicon substrate 1. Each 3D capacitor cell includes one or more first silicon vias 111 penetrating the silicon substrate 1, a via capacitor electrode portion 113 formed in the first silicon via 111, a first side capacitor electrode portion 114 formed on a first side of the silicon substrate 1 and electrically connected to the via capacitor electrode portion 113, and a second side capacitor electrode portion 115 formed on a second side of the silicon substrate. The via capacitor electrode portion 113 and the first side capacitor electrode portion 114 form the first capacitor electrode of the 3D capacitor cell, and the silicon substrate 1 and the second side capacitor electrode portion 115 form the second capacitor electrode of the 3D capacitor cell. An insulating dielectric layer 112 is filled between the first capacitor electrode and the second capacitor electrode. One or more three-dimensional resistive units are disposed on the silicon substrate. Each three-dimensional resistive unit includes one or more second silicon vias 121 penetrating the silicon substrate 1, a via resistor 122 formed in the second silicon via 121, a first-side resistor 123 formed on a first side of the silicon substrate 1 and electrically connected to the via resistor 122, and a second-side resistor 124 formed on a second side of the silicon substrate 1 and electrically connected to the via resistor 122. An insulating dielectric layer 112 is disposed between the first-side resistor 123, the second-side resistor 124 and the via resistor 122 and the silicon substrate 1.

[0038] Preferably, the silicon substrate 1 is a low-resistivity silicon substrate. In the example, the resistivity of the silicon substrate 1 is 0.001~0.01 Ω·cm, its thickness is 50~300 μm, and its crystal orientation is [missing information]. <100> .

[0039] Preferably, an insulating dielectric layer 112 is also filled between the first capacitor electrode and the silicon substrate.

[0040] Preferably, one end of the second-side capacitor electrode portion 115 is connected to the silicon substrate 1. In the example, one end of the second-side capacitor electrode portion 115 is electrically connected to the silicon substrate 1.

[0041] Preferably, the other end of the second-side capacitor electrode portion 115 is electrically connected to the second-side resistor portion 124.

[0042] In the example, the length direction of the second side capacitor electrode portion 115 is consistent with the length direction of the first through-silicon via 111.

[0043] Preferably, the second-side resistive portion 124 completely covers the outer side of the insulating dielectric layer 112 on the second-side outer surface of the silicon substrate 1, and the fully covered second-side resistive portion 124 also serves as the common lower electrode. More preferably, the second-side capacitive electrode portion 115 is located between the silicon substrate 1 and the common lower electrode. In the example, the resistor-capacitor common pad covers the outer surface of the common lower electrode.

[0044] In the example, the three-dimensional capacitor unit C is connected in parallel with all the three-dimensional resistor units R.

[0045] In a preferred embodiment, each three-dimensional capacitor unit further includes: A first capacitor pad 116 is formed on the outside of the first side capacitor electrode portion 114 and is electrically connected to the first side capacitor electrode portion 114; A second capacitor pad is formed on the outside of the second side capacitor electrode portion and is electrically connected to the second side capacitor electrode portion; In a preferred embodiment, each 3D resistive unit further includes: A first resistor pad 125 is formed on the outside of the first side resistor portion and is electrically connected to the first side resistor portion; A second resistor pad is formed on the outside of the second-side resistor section and is electrically connected to the second-side resistor section; More preferably, the second capacitor pad and the second resistor pad are electrically connected as a resistor-capacitor common pad 101, which is formed on the outside of the common lower electrode.

[0046] In a preferred embodiment, each three-dimensional capacitor unit further includes: An end capacitor electrode portion 117 is formed on the second side of the silicon substrate 1 and is electrically connected to the through-hole capacitor electrode portion 113. The through-hole capacitor electrode portion 113, the first side capacitor electrode portion 114, and the end capacitor electrode portion 117 form the first capacitor electrode of the three-dimensional capacitor unit.

[0047] Preferably, the end capacitor electrode portion 117 is disposed opposite to the second side capacitor electrode portion 115 of the second capacitor electrode.

[0048] In a preferred embodiment, the resistance range of the three-dimensional resistor unit can be configured in multiple levels by adjusting the size and density of the second through-silicon via 121. The size of the second through-silicon via 121 includes its aperture, length, etc., and / or In the example, the resistance value of each 3D resistor unit ranges from 1Ω to 10KΩ.

[0049] In a preferred embodiment, the first through-silicon via 111 and / or the second through-silicon via 121 are double-sided opening structures.

[0050] In the example, the first through-silicon via 111 and / or the second through-silicon via 121 is selected from one or more combinations of cylindrical, prismatic and dumbbell shapes.

[0051] In the example, the opening diameter of the first through-silicon via 111 and / or the second through-silicon via 121 is 2 μm to 20 μm.

[0052] In a preferred embodiment, the first-side resistor portion 123 is disposed on the outer surface of the insulating dielectric layer 112 covering the first-side surface of the silicon substrate 1; The second-side resistor 124 is disposed on the outer surface of the insulating dielectric layer 112 covering the second-side surface of the silicon substrate 1.

[0053] More preferably, the first-side resistor 123 and the second-side resistor 124 are both disposed on the outside of the insulating dielectric layer, and the first-side resistor 123 and the second-side resistor 124 connect the through-hole resistors 122 in the plurality of second silicon vias to form a three-dimensional series network.

[0054] In a preferred embodiment, the insulating dielectric layer 112 is selected from one or more combinations of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide.

[0055] In the example, the thickness of the insulating dielectric layer 112 is 1 nm to 2000 nm.

[0056] Preferably, within the three-dimensional capacitor unit, the insulating dielectric layer 112 outside the first side of the silicon substrate is a first capacitor insulating dielectric layer, and the insulating dielectric layer 112 outside the second side of the silicon substrate includes a second capacitor insulating dielectric layer and a third capacitor insulating dielectric layer. The insulating dielectric layer 112 on the side of the end capacitor electrode portion closest to the silicon substrate is the second capacitor insulating dielectric layer, and the insulating dielectric layer 112 on the side of the end capacitor electrode portion away from the silicon substrate is the third capacitor insulating dielectric layer. Preferably, within the three-dimensional capacitor unit, the insulating dielectric layer 112 outside the first side of the silicon substrate is a first resistive insulating dielectric layer, and the insulating dielectric layer 112 outside the second side of the silicon substrate includes a second resistive insulating dielectric layer and a third resistive insulating dielectric layer. The second resistive insulating dielectric layer has the same thickness as the second capacitor insulating dielectric layer, and the third resistive insulating dielectric layer is the sum of the thickness of the end capacitor electrode portion and the thickness of the third capacitor insulating dielectric layer.

[0057] In a preferred embodiment, the through-hole resistor 122, the first-side resistor 123, and / or the second-side resistor 124 are one of heavily doped polycrystalline silicon, tantalum nitride, titanium nitride, gold, platinum, aluminum, and copper.

[0058] Preferably, the thickness of the first-side resistor portion 123 and / or the second-side resistor portion 124 is 10 nm to 2000 nm.

[0059] In a preferred example, the first capacitor pad 116, the second capacitor pad, the first resistor pad 125, and the second resistor pad are independently selected from one or more combinations of gold, aluminum, copper, titanium, nickel, and palladium.

[0060] Preferably, the thickness of the first capacitor pad 116, the second capacitor pad, the first resistor pad 125, and / or the second resistor pad is 1000 nm to 10000 nm. In the example, the second capacitor pad and the second resistor pad are electrically connected to form a resistor-capacitor common pad, and the thickness of the resistor-capacitor common pad is 1000 nm to 10000 nm. Example

[0061] An RF matching network integrated chip was fabricated according to the technical solution of the three-dimensional capacitor-resistor on-chip integrated system of this patent, and its various structural parameters are as follows: The silicon substrate 1 is selected from low-resistivity silicon with a resistivity of 0.001 Ω·cm and a thickness of 200 μm.

[0062] 3D capacitor unit: The first through-silicon via 111 is a cylindrical through-silicon via (TSV) with an opening diameter of 10 μm and a depth of 200 μm. The insulating dielectric layer on the first side of the silicon substrate, the insulating dielectric layer within the TSV, and the insulating dielectric layer on the second side of the silicon substrate are all deposited using a thermal oxidation process to deposit silicon oxide (SiO2), each with a thickness of 30 nm. The capacitor electrode portion 114 on the first side is made of copper (Cu) with a thickness of 2 μm.

[0063] 3D resistor unit: The second through-silicon via 121 is a rectangular via, and multiple second through-silicon vias 121 are arranged in a 3x3 array. The opening side length of the second through-silicon via is 5 μm. The third resistive insulating dielectric layer is thermally oxidized SiO2 with a thickness of 50 nm. The first-side resistive section, the through-hole resistive section, and the second-side resistive section are all heavily doped polycrystalline silicon, with a thickness of 150 nm and a resistivity of 1.2 mΩ·cm. The through-hole resistors of the nine through-silicon vias are connected in series through resistor leads.

[0064] Pads: The first capacitor pad 110, the first resistor pad 111, and the resistor-capacitor common pad 109 all adopt a Ti / Cu / Ni / Au composite structure, and their thickness is 8 μm.

[0065] The performance metrics of the RF matching network integrated chip were measured as follows: The capacitance of the three-dimensional capacitor unit is 100 pF.

[0066] The resistance range of the three-dimensional resistor unit: the total resistance of the 9 through-hole resistors connected in series is 47 kΩ (accuracy ±0.5%).

[0067] Parasitic parameters: Equivalent series resistance ESR < 0.1 Ω, parasitic capacitance < 1 fF.

[0068] The RF matching network integrated chip is suitable for high-precision analog integrated circuits and 10GHz RF front-end matching. Example

[0069] A power management decoupling chip was fabricated according to the technical solution of the three-dimensional capacitor-resistor on-chip integrated system of this patent. Its various structural parameters are as follows: The silicon substrate 1 is selected from low-resistivity silicon with a resistivity of 0.01 Ω·cm and a thickness of 150 μm.

[0070] 3D capacitor unit: The first through-silicon via 111 is a cylindrical through-silicon via array, and the opening diameter of the first through-silicon via 111 is 15 μm. The insulating dielectric layer on the first side of the silicon substrate, the insulating dielectric layer inside the through-silicon via, and the insulating dielectric layer on the second side of the silicon substrate are all hafnium oxide (HfO2), and their thickness is 20 nm. The capacitor electrode portion 114 on the first side is aluminum (Al).

[0071] 3D resistor unit: The second through-silicon via 121 is an octagonal via with an opening-to-side distance of 5 μm. The first, second, and third resistive insulating dielectric layers are all made of tantalum nitride (TaN), each with a thickness of 50 nm and a resistivity of 5 mΩ·cm. The via resistance of the second through-silicon via can be set to a single through-hole (low resistance, approximately 1 kΩ), or it can be set to nine via resistors connected in series (high resistance, approximately 12 kΩ).

[0072] Pads: The first capacitor pad 110, the first resistor pad 111, and the resistor-capacitor common pad 109 are all made of aluminum metal and have a thickness of 6 μm.

[0073] The performance metrics of the power management decoupling chip were measured as follows: The capacitance of the three-dimensional capacitor unit is 1nF.

[0074] The resistance settings of the 3D resistor unit are adjustable to 1 kΩ and 12 kΩ.

[0075] Temperature coefficient (TCR): ≤ ±40 ppm / ℃.

[0076] Heat dissipation capability: Power density is increased by 4 times compared to planar structures.

[0077] Power management decoupling chips are suitable for decoupling and damping regulation of power rails, effectively suppressing power ripple.

[0078] It should be noted that, unless otherwise specified, all features in the above embodiments or embodiments described herein can be freely combined.

[0079] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "preferred embodiments," "other embodiments," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0080] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications and variations to the above embodiments within the scope of the present invention.

Claims

1. A three-dimensional capacitor-resistor on-chip integrated system, characterized in that, It includes: Silicon substrate (1); One or more three-dimensional capacitor units disposed on the silicon substrate (1), each three-dimensional capacitor unit including one or more first silicon vias (111) penetrating the silicon substrate (1), a via capacitor electrode portion (113) formed in the first silicon via (111), a first side capacitor electrode portion (114) formed on a first side of the silicon substrate (1) and electrically connected to the via capacitor electrode portion (113), and a second side capacitor electrode portion (115) formed on a second side of the silicon substrate, wherein the via capacitor electrode portion (113) and the first side capacitor electrode portion (114) form the first capacitor electrode of the three-dimensional capacitor unit, and the silicon substrate (1) and the second side capacitor electrode portion (115) form the second capacitor electrode of the three-dimensional capacitor unit, and an insulating dielectric layer (112) is filled between the first capacitor electrode and the second capacitor electrode. One or more three-dimensional resistor units disposed on the silicon substrate, each three-dimensional resistor unit including one or more second silicon vias (121) penetrating the silicon substrate (1), via resistor portion (122) formed in the second silicon via (121), first side resistor portion (123) formed on a first side of the silicon substrate (1) and electrically connected to the via resistor portion (122), and second side resistor portion (124) formed on a second side of the silicon substrate (1) and electrically connected to the via resistor portion (122), wherein an insulating dielectric layer (112) is disposed between the first side resistor portion (123), the second side resistor portion (124) and the via resistor portion (122) and the silicon substrate (1).

2. The on-chip integrated system of three-dimensional capacitors and resistors according to claim 1, characterized in that, Each 3D capacitor unit also includes: A first capacitor pad (116) is formed on the outside of the first side capacitor electrode portion (114) and electrically connected to the first side capacitor electrode portion (114). A second capacitor pad is formed on the outside of the second side capacitor electrode portion (115) and electrically connected to the second side capacitor electrode portion (115); and / or Each 3D resistive unit also includes: A first resistor pad (125) is formed on the outside of the first side resistor portion (123) and is electrically connected to the first side resistor portion (123). A second resistor pad is formed on the outside of the second side resistor portion (124) and electrically connected to the second side resistor portion (124).

3. The on-chip integrated system of three-dimensional capacitors and resistors according to claim 2, characterized in that, The second capacitor pad and the second resistor pad are electrically connected as a common resistor-capacitor pad (101).

4. The on-chip integrated system of three-dimensional capacitors and resistors according to claim 1, characterized in that, Each 3D capacitor unit also includes: An end capacitor electrode (117) is formed on the second side of the silicon substrate (1) and electrically connected to the through-hole capacitor electrode (113). The through-hole capacitor electrode portion (113), the first side capacitor electrode portion (114), and the end capacitor electrode portion (117) form the first capacitor electrode of the three-dimensional capacitor unit.

5. The on-chip integrated system of three-dimensional capacitors and resistors according to claim 1, characterized in that, The resistance range of the three-dimensional resistor unit can be configured in multiple levels by the size of the second through-silicon via (121) and the arrangement density of the second through-silicon via (121); and / or The resistance value of the three-dimensional resistor unit ranges from 1Ω to 10KΩ.

6. The on-chip integrated system of three-dimensional capacitors and resistors according to claim 1, characterized in that, The first through-silicon via (111) and / or the second through-silicon via (121) are double-sided opening structures; and / or The first through-silicon via (111) and / or the second through-silicon via (121) are selected from one or more combinations of cylindrical, prismatic, and dumbbell shapes; and / or The opening diameter of the first through-silicon via (111) and / or the second through-silicon via (121) is 2 μm to 20 μm.

7. The on-chip integrated system of three-dimensional capacitors and resistors according to claim 1, characterized in that, The first-side resistor (123) is disposed on the outer surface of the insulating dielectric layer (112) covering the first-side surface of the silicon substrate (1); The second-side resistor (124) is disposed on the outer surface of the insulating dielectric layer (112) covering the second side surface of the silicon substrate (1).

8. The on-chip integrated system of three-dimensional capacitors and resistors according to claim 7, characterized in that, The first-side resistor (123) and the second-side resistor (124) are both disposed on the outside of the insulating dielectric layer. The first-side resistor (123) and the second-side resistor (124) connect the through-hole resistors (122) in the multiple second silicon vias to form a three-dimensional series network.

9. The on-chip integrated system of three-dimensional capacitors and resistors according to claim 1, characterized in that, The silicon substrate (1) has a resistivity of 0.001~0.01 Ω·cm, a thickness of 50~300 μm, and a crystal orientation of [missing information]. <100> ; and / or The insulating dielectric layer (112) is selected from one or more combinations of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide; and / or The thickness of the insulating dielectric layer (112) is 1 nm to 2000 nm.

10. The three-dimensional capacitor-resistor on-chip integrated system according to claim 2 or 3, characterized in that, The through-hole resistor section (122), the first-side resistor section (123), and / or the second-side resistor section (124) are one of heavily doped polycrystalline silicon, tantalum nitride, titanium nitride, metallic gold, metallic platinum, metallic aluminum, and metallic copper; and / or The thickness of the first-side resistor section (123) and / or the second-side resistor section (124) is 10 nm to 2000 nm; and / or The first capacitor pad (116), the second capacitor pad, the first resistor pad (125), and the second resistor pad are independently selected from one or more combinations of gold, aluminum, copper, titanium, nickel, and palladium; and / or The thickness of the first capacitor pad (116), the second capacitor pad, the first resistor pad (125), and / or the second resistor pad is 1000 nm to 10000 nm.

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