Chip packaging method and packaging structure

Abstract

The chip packaging method and packaging structure provided by the embodiments of the present disclosure have the following advantages: the micro flow channel is formed in the glass substrate, the heat generated by the stacked chip packaging module is conducted to the micro flow channel of the glass substrate through the redistribution layer and the interposer in sequence, direct and efficient heat dissipation of the stacked chip packaging module is achieved, the heat dissipation path is greatly shortened, and the temperature control capability under the peak power is significantly improved; compared with the existing micro flow channel process which needs to dig holes first and then seal, the micro flow channel structure formed by the method is stable and has strong voltage resistance, and can directly bear high-flow-rate cooling liquid; the micro flow channel is formed in the glass substrate, so that an additional external heat sink is avoided, and miniaturization and thinning of the packaging body are facilitated; the pipeline interface is independently arranged in the non-welding area of the glass substrate, so that the electrical connection integrity of the welding area is ensured, and the electrical performance and the thermal management do not interfere with each other; the micro flow channel is formed in the single-layer glass substrate only, and a complex alignment step is not needed, so that the process is simple.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a chip packaging method and packaging structure. Background Technology

[0002] Artificial intelligence requires massive computing power, which in turn consumes a significant amount of energy. The greater the computing power of a single chip, the higher its energy consumption. Current chip power consumption is already in the 2000W range, and it will be even higher in the future. The greater the power consumption, the greater the heat generated, requiring stronger heat dissipation capabilities. To improve heat dissipation performance, the industry has begun using microfluidic liquid cooling technology, which involves creating microchannels on the back of the chip to rapidly remove heat through liquid flow.

[0003] Current microfluidic designs on the back of chips are helpful in improving heat dissipation, but they still have some shortcomings. The main issue is that high-performance chips are packaged using flip-chip technology, with the circuit layer on the front and facing down. Since the heat source is on the circuit layer, the microfluidic channels need to dissipate heat through the chip itself. The chip's thickness affects heat dissipation, especially since the chip doesn't heat up uniformly and has hot spots. Back-side heat dissipation is more like surface-level heat dissipation for these hot spots, lacking specificity. Furthermore, in future 3D stacked packaging, the heat dissipation path between the back microfluidic channels and the front of the chip involves multiple chips and multiple interfaces, making the heat dissipation path even more complex.

[0004] To address the aforementioned issues, it is necessary to propose a chip packaging method and structure that is rationally designed and effectively solves these problems. Summary of the Invention

[0005] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a chip packaging method and packaging structure.

[0006] One aspect of this disclosure provides a chip packaging method, the packaging method comprising: A glass substrate is formed and microchannels are formed within the glass substrate; A first chamber and a second chamber, penetrating the thickness of the glass substrate, are formed in the non-welding area of ​​the glass substrate. An inlet pipe interface connected to the microchannel inlet and an outlet pipe interface connected to the microchannel outlet are respectively provided in the first chamber and the second chamber. An intermediary is mounted and fixed to the welding area of ​​the glass substrate, wherein the intermediary is provided with a plurality of conductive pillars penetrating its thickness. A redistribution layer is formed on the surface of the intermediate body; The stacked chip package module is flip-chip fixed to the redistribution layer.

[0007] Optionally, forming a glass substrate and forming microchannels within the glass substrate includes: A first carrier board and a second carrier board are provided, wherein both the first carrier board and the second carrier board include a glass layer and a wiring layer; A first groove is patterned on the glass layer of the first carrier plate, and a second groove that matches the first groove is formed at the corresponding location of the first groove. The first and second carrier plates are anodized on the sides where grooves are formed to obtain the glass substrate, wherein the first and second grooves are aligned to form closed microchannels.

[0008] Optionally, forming a glass substrate and forming microchannels within the glass substrate further includes: Provide glass carrier plates; Interconnect wiring layers are formed on both sides of the glass carrier plate to form the glass substrate; wherein, The microchannels are formed within the interconnect wiring layer while forming the interconnect wiring layer on either side.

[0009] Optionally, the microchannels encased within the interconnect wiring layer are formed simultaneously with the formation of the interconnect wiring layer on either side; The interconnect wiring layer includes multiple metal layers formed by electroplating and multiple dielectric layers coated on the metal layers, wherein the metal layers and the dielectric layers are spaced apart. The bottom wall, side wall, and top wall of the microchannel are formed by electroplating while forming each of the metal layers, thereby forming the microchannel.

[0010] Optionally, a first chamber and a second chamber are formed throughout the thickness of the non-welding region of the glass substrate, including: The non-welded areas of the glass substrate at the corresponding microchannel inlet and microchannel outlet are etched along their thickness direction to form a first chamber and a second chamber, respectively; wherein the first chamber and the second chamber are respectively connected to the microchannel inlet and outlet.

[0011] Optionally, after providing an inlet pipe interface communicating with the microchannel inlet and an outlet pipe interface communicating with the microchannel outlet in the first chamber and the second chamber respectively, the method further includes: A sealant layer is filled between the first chamber and the inlet pipe interface, and between the second chamber and the outlet pipe interface.

[0012] Another aspect of this disclosure provides a chip packaging structure, including: A glass substrate, wherein microchannels are provided in the glass substrate, and an inlet pipe interface and an outlet pipe interface are respectively provided at the microchannel inlet and microchannel outlet in the non-welding area of ​​the glass substrate. An intermediary is disposed in the welding area of ​​the substrate, and the intermediary is provided with a plurality of conductive pillars penetrating its thickness; A redistribution layer is disposed on the surface of the intermediate body; The stacked chip package module is flip-chip mounted on the redistribution layer.

[0013] Optionally, the microchannels are S-shaped with their ends connected.

[0014] Optionally, the cross-section of the microchannel may be square, hexagonal, or circular.

[0015] Optionally, the non-welding area of ​​the glass substrate is provided with a first chamber and a second chamber at the corresponding microchannel inlet and microchannel outlet, respectively, and the first chamber and the second chamber are respectively provided with an inlet pipe interface and an outlet pipe interface; A sealant layer is provided in the first chamber and the second chamber, the sealant layer filling the space between the first chamber and the inlet pipe interface, and filling the space between the second chamber and the outlet pipe interface.

[0016] The chip packaging method and packaging structure disclosed herein involve forming a glass substrate and creating microchannels within it. The microchannels are embedded within the glass substrate, and the heat generated by the stacked chip packaging module is sequentially conducted to the microchannels in the glass substrate through a redistribution layer and an intermediary. This achieves direct and efficient heat dissipation of the stacked chip packaging module, significantly shortening the heat dissipation path and effectively solving the heat dissipation lag problem caused by traditional back-side microchannels needing to pass through the chip body and multiple interfaces. This significantly improves temperature control capabilities under peak power. Compared to existing microchannel processes that require drilling holes before sealing, the microchannel structure formed by this method is stable, has strong pressure resistance, and can directly support high-flow-rate coolant. Forming microchannels within the glass substrate avoids the need for additional external heat sinks or complex piping, facilitating miniaturization and thinning of the package. Independently setting pipe interfaces in the non-soldering area of ​​the glass substrate ensures the integrity of electrical connections in the soldering area, preventing interference between electrical performance and thermal management. Forming microchannels only within a single-layer glass substrate eliminates the need for complex alignment steps, simplifying the process. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a chip packaging method according to one embodiment of the present disclosure; Figures 2 to 9 This is a schematic diagram of the process of a chip packaging method according to another embodiment of this disclosure; Figure 10 This is a top view of a microchannel according to another embodiment of this disclosure; Figure 11 This is a schematic diagram of a chip packaging structure according to another embodiment of the present disclosure. Figure 9 (Cross-sectional view of AA') Figure 12 This is a schematic diagram of a chip packaging structure according to another embodiment of the present disclosure. Figure 9 (Cross-sectional view of BB'). Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0019] like Figure 1 As shown, one aspect of this disclosure provides a chip packaging method S100, which specifically includes: S110, Form a glass substrate and form microchannels within the glass substrate.

[0020] like Figure 2 and Figure 3 As shown, a glass substrate 170 is formed and microchannels 130 are formed within the glass substrate 170.

[0021] For example, in one embodiment, forming a glass substrate 170 and forming microchannels 130 within the glass substrate 170 includes: First, such as Figure 2 As shown, a first carrier board 171 and a second carrier board 172 are provided, wherein both the first carrier board 171 and the second carrier board 172 include a glass layer and a wiring layer.

[0022] Secondly, an etching process is used to pattern the first groove 173 on the glass layer of the first carrier plate 171, and an etching process is used to pattern the second groove 174 on the glass layer of the second carrier plate 172, so as to form a second groove 174 that matches the first groove 173 at the corresponding location of the first groove 173.

[0023] Specifically, wet etching is used on the glass layers of the first substrate 171 and the second substrate 172 to etch semi-circular grooves with a depth of more than 10 μm. That is, a semi-circular first groove 173 is etched on the first substrate 171, and a semi-circular second groove 174 is etched on the second substrate 172, wherein the position, shape and size of the first groove 173 and the second groove 174 are the same.

[0024] Finally, as Figure 3As shown, the first carrier plate 171 and the second carrier plate 172 with grooves are anodicly bonded to obtain the glass substrate 170, wherein the first groove 173 and the second groove 174 are aligned to form a closed microchannel 130.

[0025] Specifically, after aligning the first carrier plate 171 and the second carrier plate 172, an anodic bonding process is used to align the semi-circular first groove 173 and the second groove 174 to form a cavity microchannel 130 with a circular cross-section.

[0026] It should be noted that this embodiment does not specifically limit the shape of the first groove and the second groove. In addition to semi-circle, it can also be square or trapezoidal, etc., and can be selected according to actual needs.

[0027] In this embodiment, the grooves of two glass layers are aligned and bonded by anodic bonding to form an integrated closed cavity microchannel. The channel wall is made of glass body. Compared with the existing microchannel preparation method that uses a thin sealing layer to cover the groove, the wall thickness and structural strength are significantly improved. It can withstand coolant with higher flow rate and pressure without leakage or deformation, thus improving stability.

[0028] For example, in another embodiment, forming a glass substrate 170 and forming microchannels 130 within the glass substrate 170 further includes: First, a glass substrate is provided.

[0029] Next, interconnect wiring layers are formed on both sides of the glass carrier plate to form the glass substrate 170.

[0030] Specifically, forming the microchannel encapsulated within the interconnect wiring layer while forming the interconnect wiring layer on any one side may include: The interconnect wiring layer is formed by electroplating multiple metal layers and coating multiple dielectric layers onto the metal layers, wherein the metal layers and the dielectric layers are spaced apart; while forming each of the metal layers, the bottom wall, side wall, and top wall of the microchannel are electroplated to form the microchannel. That is, the microchannel 130 is integrally formed by electroplating during the formation of the wiring layer.

[0031] In this embodiment, the fabrication of microchannels is embedded in the molding process of the double-sided wiring layer of the glass substrate, eliminating the need for an additional independent flow channel processing process. This simplifies the production process, reduces manufacturing costs, and facilitates more precise alignment between the microchannels and the electrical interconnect structure. The microchannels are encased in the metal and dielectric layers of the interconnect wiring layer and can be directly connected to the conductive pillars of the intermediate through the metal pillars in the wiring layer. The heat generated by the stacked chip packaging module is transferred to the flow channel wall through the redistribution layer and the intermediate through a very short path with low thermal resistance, which greatly improves the heat dissipation efficiency of the chip.

[0032] For example, in this embodiment, such as Figure 10 As shown, the microchannel 130 is S-shaped with its ends connected.

[0033] In this embodiment, the microchannels are configured as an S-shaped structure with the ends connected, which can significantly extend the flow path of the coolant within a limited plane area of ​​the intermediate body, increasing the heat exchange area and time between the coolant and the intermediate body. This allows the coolant to absorb heat more fully, effectively improving the heat carrying capacity of the coolant per unit volume. Thus, without increasing the external fluid flow rate or pressure, the overall heat exchange efficiency and temperature control effect of the heat dissipation system are significantly improved.

[0034] S120. A first chamber and a second chamber are formed in the non-welding area of ​​the glass substrate, extending through its thickness. An inlet pipe interface connected to the microchannel inlet and an outlet pipe interface connected to the microchannel outlet are respectively provided in the first chamber and the second chamber.

[0035] For example, a first chamber and a second chamber extending through the thickness of the non-welding region of the glass substrate are formed, which may specifically include: like Figure 4 As shown, the non-soldering areas of the glass substrate 170 at the corresponding microchannel inlet and microchannel outlet are etched along their thickness direction to form a first chamber 178 and a second chamber, respectively, so that the first chamber 178 and the second chamber are respectively connected to the microchannel inlet and the microchannel outlet. That is, the glass layer or wiring layer of the glass substrate 170 at the microchannel inlet and microchannel outlet is removed to connect the chamber to the inlet or outlet of the microchannel.

[0036] In this step, the first chamber and the second chamber can be precisely and with low resistance connected to the inlet and outlet of the microchannel, respectively, ensuring that the external coolant can flow smoothly into and out of the microchannel inside the package. This avoids flow loss and increased pressure drop caused by misalignment or blockage of the channel interface, thereby ensuring the working stability and cooling efficiency of the microchannel heat dissipation system.

[0037] For example, such as Figure 4 and Figure 9As shown, an inlet pipe interface 175 connected to the microchannel inlet and an outlet pipe interface 176 connected to the microchannel outlet are respectively provided in the first chamber 178 and the second chamber. Then, a sealant layer 177 is filled between the first chamber and the inlet pipe interface 175 and between the second chamber and the outlet pipe interface 176.

[0038] In this step, the inner walls of the first and second chambers are filled with a sealant layer and pipe interfaces are installed simultaneously. This ensures a secure and sealed connection between the pipe interfaces and the encapsulation body, while effectively preventing coolant leakage during operation. The sealant layer not only provides fixation and sealing but also buffers the stress between the external pipes and the rigid encapsulation structure, improving the reliability and service life of the overall encapsulation structure under long-term thermal cycling and liquid pressure fluctuations.

[0039] S130. The intermediate body is fixed to the welding area of ​​the glass substrate, wherein the intermediate body is provided with a plurality of conductive pillars penetrating its thickness.

[0040] like Figure 5 As shown, an intermediary 110 is mounted and fixed to the soldering area of ​​a glass substrate 170. The intermediary 110 is provided with a plurality of conductive pillars 111 penetrating its thickness. The conductive pillars 111 can be copper pillars, serving a vertical interconnecting function. In this embodiment, the intermediary 110 can be a silicon wafer or a glass sheet, and the choice can be made according to actual needs; this embodiment does not impose a specific limitation.

[0041] For example, after forming the conductive pillars 111, a plurality of conductive bumps 112 can be formed on the side of the intermediary 110 facing the glass substrate 170, and the intermediary 110 is fixed to the glass substrate 170 by the plurality of conductive bumps 112. An underfill layer encapsulating the plurality of conductive bumps 112 is also provided between the intermediary 110 and the glass substrate 170 to further fix the intermediary 110 to the glass substrate 170.

[0042] S140, A redistribution layer is formed on the surface of the intermediate.

[0043] like Figure 6 As shown, a redistribution layer 120 is formed on the side of the interposer 110 facing away from the glass substrate 170, which increases the interconnect density of the chip. The redistribution layer 120 includes multiple layers of metal and dielectric layers stacked at intervals.

[0044] S150. The stacked chip packaging module is flip-chip fixed to the redistribution layer.

[0045] like Figure 7 and Figure 8As shown, the stacked chip package module 150 is flip-chip connected to the redistribution layer 120 via multiple thermal bumps 151. An underfill layer encapsulating the multiple thermal bumps 151 is formed between the stacked chip package module 150 and the redistribution layer 120.

[0046] The stacked chip packaging module 150 includes multiple chips stacked sequentially in flip-chip configuration and a molding compound encapsulating the chips. The stacked chip packaging module 150 is a pre-formed chip module; the specific structural composition of the stacked chip packaging module 150 is not limited in this embodiment and can be selected according to actual needs.

[0047] For example, the method further includes: like Figure 7 and Figure 8 As shown, a plurality of solder balls 180 are formed on the side of the glass substrate 170 away from the intermediary 110, and the electrical signals of the entire package structure are led out through the plurality of solder balls 180.

[0048] The chip packaging method of this disclosure forms a glass substrate and forms microchannels within the glass substrate. The microchannels are embedded inside the glass substrate, and the heat generated by the stacked chip packaging module is conducted sequentially through the redistribution layer and the intermediary to the microchannels in the glass substrate, achieving direct and efficient heat dissipation of the stacked chip packaging module. The heat dissipation path is significantly shortened, effectively solving the heat dissipation lag problem caused by the traditional back-side microchannels needing to pass through the chip body and multiple interfaces, and significantly improving the temperature control capability under peak power. Compared with the existing microchannel process that requires drilling holes before sealing, the microchannel structure formed by this method is stable and has strong pressure resistance, and can directly carry high-flow-rate coolant. Forming microchannels within the glass substrate avoids additional external heat sinks or complex pipelines, which is conducive to miniaturization and thinning of the package. By independently setting the pipe interface in the non-soldering area of ​​the glass substrate, the electrical connection integrity of the soldering area is ensured, so that electrical performance and thermal management do not interfere with each other. The microchannels are formed only in a single-layer glass substrate, eliminating the need for complex alignment steps, and the process is simple.

[0049] like Figure 11 and Figure 12 As shown, another aspect of the present disclosure provides a chip packaging structure 100, including an intermediary 110, a redistribution layer 120, a microchannel 130, a stacked chip packaging module 150, and a glass substrate 170.

[0050] The glass substrate 170 is provided with microchannels 130, wherein the non-welding area of ​​the glass substrate 170 is provided with an inlet pipe interface 175 and an outlet pipe interface 176 at the corresponding microchannel inlet and microchannel outlet, respectively.

[0051] An intermediary 110 is disposed in the welding area of ​​the glass substrate 170, and the intermediary 110 is provided with a plurality of conductive pillars 111 penetrating its thickness.

[0052] The intermediate body 110 is provided with a plurality of conductive pillars 111 penetrating its thickness. The conductive pillars 111 can be copper pillars, serving a vertical interconnecting function. Furthermore, in this embodiment, the intermediate body 110 can be a silicon wafer or a glass sheet, whichever is chosen according to actual needs; this embodiment does not impose a specific limitation.

[0053] The redistribution layer 120 is disposed on the surface of the interposer 110 to improve the interconnection density.

[0054] The stacked chip package module 150 is flip-chip mounted on the redistribution layer 120.

[0055] In this embodiment, the microchannel is located inside the glass substrate and is connected to the stacked chip packaging module above it through conductive pillars and conductive bumps in the intermediary and the redistribution layer. The heat generated by the stacked chip packaging module is conducted to the microchannel in the glass substrate through the redistribution layer and the intermediary, realizing direct and efficient heat dissipation of the stacked chip packaging module. The heat dissipation path is greatly shortened, effectively solving the heat dissipation lag problem caused by the traditional back-side microchannel having to pass through the chip body and multiple interfaces, and significantly improving the temperature control capability under peak power. The microchannel is integrally molded, with a stable structure and strong pressure resistance, and can directly carry high-flow-rate coolant. The microchannel is set inside the glass substrate, avoiding additional external heat sinks or complex pipelines, which is conducive to the miniaturization and thinning of the package. By setting the pipe interface independently in the non-welding area of ​​the glass substrate, the electrical connection integrity of the welding area is ensured, so that electrical performance and thermal management do not interfere with each other. The microchannel is set only in a single-layer glass substrate, eliminating the need for complex alignment steps and simplifying the process.

[0056] For example, such as Figure 10 As shown, in this embodiment, the microchannel 130 is S-shaped with its ends connected.

[0057] In this embodiment, the microchannels are configured as an S-shaped structure with the ends connected, which can significantly extend the flow path of the coolant within a limited plane area of ​​the intermediate body, increasing the heat exchange area and time between the coolant and the intermediate body. This allows the coolant to absorb heat more fully, effectively improving the heat carrying capacity of the coolant per unit volume. Thus, without increasing the external fluid flow rate or pressure, the overall heat exchange efficiency and temperature control effect of the heat dissipation system are significantly improved.

[0058] For example, the cross-section of the microchannel 130 may be square, hexagonal, or circular.

[0059] It should be noted that this embodiment does not specifically limit the shape of the cross-section of the microchannel, and it can be selected according to actual needs.

[0060] In this embodiment, the cross-section of the microchannel is set to hexagonal, square, and circular, which can flexibly adapt to different media materials and manufacturing processes (such as wet etching, dry etching, etc.). Among them, hexagonal and circular cross-sections have better structural stress dispersion capabilities, which helps to improve the structural stability of the microchannel under high-pressure fluid impact; square cross-sections facilitate integrated wiring and channel fabrication in rewiring processes. The selection of multiple cross-sectional shapes provides rich feasibility for optimizing channel design according to actual heat dissipation requirements and manufacturing conditions, which helps to balance heat dissipation performance, structural strength, and manufacturing yield.

[0061] For example, such as Figure 11 and 12 As shown, the interposer 110 has multiple conductive bumps 112 on the side opposite to the redistribution layer 120, and the interposer 110 is fixed to the glass substrate 170 through the multiple conductive bumps 112. The glass substrate 170 has multiple solder balls 180 on the side opposite to the interposer 110, and the electrical signals of the entire package structure are led out through the solder balls 180.

[0062] For example, an underfill layer covering conductive bumps is provided between the intermediary 110 and the glass substrate 170 to further fix the intermediary 110. An underfill layer covering multiple thermal bumps is provided between the stacked chip packaging module 150 and the redistribution layer 120 to further fix the multiple chips 150.

[0063] For example, such as Figure 12 As shown, the non-welding area of ​​the glass substrate 170 is provided with a first chamber 178 and a second chamber at the corresponding microchannel inlet and microchannel outlet, respectively. The first chamber and the second chamber are respectively provided with an inlet pipe interface 175 and an outlet pipe interface 176.

[0064] The coolant is delivered to the inlet pipe interface 175 through the inlet pipe, and then enters the microchannel 130 through the microchannel inlet. After heat exchange, it enters the outlet pipe interface 176 through the microchannel outlet and flows out through the outlet pipe, thus completing the heat exchange process.

[0065] In this embodiment, independent first and second chambers are provided, offering ample installation space and positioning references for the inlet and outlet pipe interfaces, facilitating subsequent pipe sealing and connection operations. The inlet pipe interface is connected to the microchannel inlet, and the outlet pipe interface is connected to the microchannel outlet, ensuring that the coolant flows completely through all microchannel paths without the risk of bypass leakage. The inlet and outlet pipe interfaces are integrated within the package, eliminating the need for additional substrate surface space and contributing to the miniaturization of the overall package size.

[0066] For example, such as Figure 12 As shown, a sealant layer 177 is provided in the first chamber and the second chamber. The sealant layer 177 fills the space between the first chamber and the inlet pipe interface 175, and fills the space between the second chamber and the outlet pipe interface 176.

[0067] In this embodiment, by setting a sealing layer, the sealing connection between the external coolant pipeline and the internal microchannel is ensured, preventing the risk of electrical short circuit caused by coolant leakage. At the same time, it provides structural buffer at the interface, reducing the interface stress caused by temperature changes or vibration.

[0068] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A chip packaging method, characterized in that, The encapsulation method includes: A glass substrate is formed and microchannels are formed within the glass substrate; A first chamber and a second chamber are formed in the non-welding area of ​​the glass substrate, extending through its thickness. An inlet pipe interface connected to the microchannel inlet and an outlet pipe interface connected to the microchannel outlet are respectively provided in the first chamber and the second chamber. An intermediary is mounted and fixed to the welding area of ​​the glass substrate, wherein the intermediary is provided with a plurality of conductive pillars penetrating its thickness. A redistribution layer is formed on the surface of the intermediate body; The stacked chip package module is flip-chip fixed to the redistribution layer.

2. The method according to claim 1, characterized in that, Forming a glass substrate and forming microchannels within the glass substrate includes: A first carrier board and a second carrier board are provided, wherein both the first carrier board and the second carrier board include a glass layer and a wiring layer; A first groove is patterned on the glass layer of the first carrier plate, and a second groove that matches the first groove is formed at the corresponding location of the first groove. The first and second carrier plates are anodized on the sides where grooves are formed to obtain the glass substrate, wherein the first and second grooves are aligned to form closed microchannels.

3. The method according to claim 1, characterized in that, The method of forming a glass substrate and forming microchannels within the glass substrate further includes: Provide glass carrier plates; Interconnect wiring layers are formed on both sides of the glass carrier plate to form the glass substrate; wherein, The microchannels are formed within the interconnect wiring layer while forming the interconnect wiring layer on either side.

4. The method according to claim 3, characterized in that, The microchannels encapsulated within the interconnect wiring layer are formed simultaneously with the formation of the interconnect wiring layer on either side; The interconnect wiring layer includes multiple metal layers formed by electroplating and multiple dielectric layers coated on the metal layers, wherein the metal layers and the dielectric layers are spaced apart. The bottom wall, side wall, and top wall of the microchannel are formed by electroplating while forming each of the metal layers, thereby forming the microchannel.

5. The method according to claim 1, characterized in that, A first chamber and a second chamber, extending through the thickness of the glass substrate, are formed in the non-welding region, including: The non-welded areas of the glass substrate at the corresponding microchannel inlet and microchannel outlet are etched along their thickness direction to form a first chamber and a second chamber, respectively; wherein the first chamber and the second chamber are respectively connected to the microchannel inlet and outlet.

6. The method according to claim 1, characterized in that, After providing inlet pipe interfaces connected to the microchannel inlet and outlet pipe interfaces connected to the microchannel outlet in the first chamber and the second chamber respectively, the method further includes: A sealant layer is filled between the first chamber and the inlet pipe interface, and between the second chamber and the outlet pipe interface.

7. A chip packaging structure, characterized in that, include: A glass substrate, wherein microchannels are provided in the glass substrate, and an inlet pipe interface and an outlet pipe interface are respectively provided at the microchannel inlet and microchannel outlet in the non-welding area of ​​the glass substrate. An intermediary is disposed in the welding area of ​​the glass substrate, and the intermediary is provided with a plurality of conductive pillars penetrating its thickness; A redistribution layer is disposed on the surface of the intermediate body; The stacked chip package module is flip-chip mounted on the redistribution layer.

8. The chip packaging structure according to claim 7, characterized in that, The microchannels are S-shaped with their ends connected.

9. The chip packaging structure according to claim 7, characterized in that, The cross-section of the microchannel can be square, hexagonal, or circular.

10. The chip packaging structure according to claim 7, characterized in that, The non-welding area of ​​the glass substrate is provided with a first chamber and a second chamber at the corresponding microchannel inlet and microchannel outlet, respectively. The first chamber and the second chamber are respectively provided with an inlet pipe interface and an outlet pipe interface. A sealant layer is provided in the first chamber and the second chamber, the sealant layer filling the space between the first chamber and the inlet pipe interface, and filling the space between the second chamber and the outlet pipe interface.

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