Chip and chip packaging method

Abstract

The application discloses a chip, comprising: a substrate comprising a first surface, a second surface and a side surface, the first surface and the second surface being opposite to each other, the side surface connecting the first surface and the second surface; a conductive terminal arranged on the first surface; a metal shielding layer connected with a grounding structure of the chip, the metal shielding layer covering the second surface and the side surface, the metal shielding layer extending from the side surface to the first surface, and the metal shielding layer covering a part of the first surface between the conductive terminal and the side surface.

Description

Technical Field

[0001] This application belongs to the field of semiconductor packaging technology, specifically relating to a chip and a chip packaging method. Background Technology

[0002] With the increasing integration of packages and the rise in operating frequencies, electromagnetic interference (EMI) has become a growing concern. On the one hand, high-speed signals between different chips within a package are prone to crosstalk, affecting signal integrity. On the other hand, when analog / RF circuits and digital circuits coexist in the same package, they are susceptible to external electromagnetic radiation, leading to a decline in system performance. Although existing technologies have attempted to introduce EMI shielding into packages, these methods are primarily based on traditional packaging. The shielding structure often only covers the back or four sides of the chip, resulting in limited shielding effectiveness and insufficient shielding efficiency, making it difficult to meet the needs of next-generation high-speed and high-frequency devices. Summary of the Invention

[0003] This application aims to provide a chip and a chip packaging method, which improves the shielding effect of the metal shielding layer by covering the first surface, second surface and side surface of the chip during packaging.

[0004] In a first aspect, this application provides a chip, comprising: a substrate including a first surface, a second surface, and a side surface, wherein the first surface and the second surface are opposite to each other, and the side surface is connected to the first surface and the second surface; a conductive terminal disposed on the first surface; and a metal shielding layer connected to the grounding structure of the chip, wherein the metal shielding layer covers the second surface and the side surface, the metal shielding layer extends from the side surface to the first surface, and the metal shielding layer covers the portion of the first surface located between the conductive terminal and the side surface.

[0005] Secondly, this application provides a chip packaging method for producing the chip as described above. The chip packaging method includes: providing a wafer substrate having a first groove on its surface; forming a second groove at the bottom of the first groove using a half-cutting process; sputtering a first metal layer on the wafer substrate; coating the wafer substrate with photoresist; removing the photoresist from the second groove area and the area between the conductive terminal adjacent to the second groove and the second groove using an exposure and development process; electroplating a metal shielding layer in the area where the photoresist was removed; removing the photoresist using an exposure and development process; removing the first metal layer outside the area covered by the metal shielding layer using an etching process; thinning the wafer substrate on the side opposite to the conductive terminal; when the wafer substrate is thinned to a target thickness, electroplating the metal shielding layer on the side of the wafer substrate opposite to the conductive terminal; and separating the wafer substrate to obtain the chip.

[0006] The technical solution adopted in this application can achieve the following technical effects:

[0007] The metal shielding layer in this application not only covers the first surface and side surfaces but also extends to the first surface, covering a portion of the first surface between the conductive terminals and the side surfaces. This structure effectively eliminates electromagnetic leakage gaps at the edges of the first surface, as is common in traditional shielding methods, improving the electromagnetic shielding effect of the chip, reducing signal crosstalk, and ensuring the chip's operational stability. Furthermore, the metal shielding layer is connected to the chip's grounding structure, allowing the electromagnetic interference energy absorbed by the metal shielding layer to be conducted to the ground wire through the grounding structure, ensuring the stable operation of the metal shielding layer. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the chip structure in one embodiment provided in this application;

[0009] Figure 2 This is a schematic diagram of the structure of a wafer substrate according to an embodiment of this application;

[0010] Figure 3 This is a schematic diagram of the structure of a wafer substrate according to an embodiment of this application;

[0011] Figure 4 This is a schematic diagram of the structure of a wafer substrate according to an embodiment of this application;

[0012] Figure 5 This is a schematic diagram of the structure of a wafer substrate according to an embodiment of this application;

[0013] Figure 6 This is a schematic diagram of the structure of a wafer substrate according to an embodiment of this application;

[0014] Figure 7 This is a schematic diagram of the structure of a wafer substrate according to an embodiment of this application;

[0015] Figure 8 This is a schematic diagram of the structure of a wafer substrate according to an embodiment of this application.

[0016] Explanation of reference numerals in the attached figures:

[0017] 10-Base, 11-First surface, 111-Clear area, 112-First side, 12-Second surface, 13-Side, 131-First connecting section, 1311-Connecting part, 1312-Inclined part, 132-Second connecting section, 133-Second side, 134-Step surface

[0018] 20-Second metal layer

[0019] 30 - Conductive terminal, 31 - Grounding structure

[0020] 40-Metallic shielding layer

[0021] 50-Conductive pad,

[0022] 61-First groove, 62-Second groove

[0023] 70-First metal layer

[0024] 80-photoresist,

[0025] 90 - wafer substrate, 91 - first side, 92 - second side. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0027] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] like Figure 1 As shown, this application provides a chip, which includes: a substrate 10, including a first surface 11, a second surface 12, and a side surface 13, wherein the first surface 11 and the second surface 12 are opposite to each other, and the side surface 13 is connected to the first surface 11 and the second surface 12; a conductive terminal 30 disposed on the first surface 11; and a metal shielding layer 40 connected to the chip's grounding structure 31, the metal shielding layer 40 covering the second surface 12 and the side surface 13, extending from the side surface 13 to the first surface 11, and covering the portion of the first surface 11 located between the conductive terminal 30 and the side surface 13. In this application, the metal shielding layer 40 not only covers the first surface 11 and the side surface 13, but also extends to the first surface 11, covering the portion of the first surface 11 located between the conductive terminal 30 and the side surface 13. This structure effectively eliminates the electromagnetic leakage gaps at the edge of the first surface 11 in traditional shielding methods, improves the electromagnetic shielding effect of the chip, reduces signal crosstalk, and ensures the chip's operational stability. In addition, the metal shielding layer 40 is connected to the grounding structure 31 of the chip, so that the electromagnetic interference energy absorbed by the metal shielding layer 40 can be conducted to the ground wire through the grounding structure 31, ensuring the stable operation of the metal shielding layer 40.

[0030] Traditional shielding structures typically involve adding a molding compound or metal shield after chip packaging, and these structures only cover the second surface 12 and side surface 13 of the chip. In this application, a metal shielding layer 40 is electroplated and deposited during the packaging process, resulting in better adhesion to the chip. This layer covers a portion of the second surface 12, side surface 13, and first surface 11, with improved integrity and continuity.

[0031] Furthermore, the metal shielding layer 40 completely covers the second surface 12 and side surface 13 of the chip, improving the shielding effect of the metal shielding layer 40 and preventing electromagnetic leakage.

[0032] The first surface 11 and the second surface 12 are disposed opposite to each other along the thickness direction of the substrate 10. The conductive terminal 30 can be a bump structure (such as a bump), and the bump can be formed by solder or conductive metal. The bump can be a spherical conductive structure.

[0033] like Figure 1As shown, in some embodiments, the conductive terminal 30 includes a ground terminal serving as a ground structure 31 for the chip, and the metal shielding layer 40 located on the first surface 11 extends to connect with the ground terminal. The ground terminal is located on the first surface 11 near the side 13. After the metal shielding layer 40 extends to the first surface 11, it connects with the ground terminal located on the first surface 11, which maximizes the coverage area of ​​the metal shielding layer 40 and enhances its shielding capability, thereby improving the electromagnetic shielding effect. Furthermore, by providing the ground terminal on the first surface 11, the need for a ground structure 31 inside the substrate 10 is avoided, simplifying the manufacturing process.

[0034] Optionally, a grounding layer is provided inside the substrate 10, and the metal shielding layer 40 is electrically connected to the grounding layer. Compared with grounding using a grounding terminal, providing a grounding layer can provide a larger grounding area and improve the efficiency of interference signal release.

[0035] like Figure 1 As shown, in some embodiments, the chip further includes a first metal layer 70 sandwiched between the substrate 10 and the metal shielding layer 40. The first metal layer 70 covers the side 13 and extends from the side 13 to the first surface 11, and covers the portion of the first surface 11 located between the conductive terminal 30 and the side 13. The metal shielding layer 40 covers the first metal layer 70. The first metal layer 70 is a seed layer and has strong adhesion to the substrate 10. Providing a first metal layer 70 between the metal shielding layer 40 and the substrate 10 can enhance the connection stability between the metal shielding layer 40 and the substrate 10, thereby improving the structural reliability of the chip.

[0036] like Figure 1 As shown, the first metal layer 70 is connected to the chip's grounding structure 31. The first metal layer 70 is firmly attached to the substrate 10, and its connection to the grounding structure 31 ensures the stability of the chip's overall grounding performance.

[0037] Optionally, the first metal layer 70 includes titanium and / or copper. The first metal layer 70 includes stacked titanium and copper metals, wherein the titanium metal is disposed on the side near the first surface 11, and the copper metal is disposed near the metal shielding layer 40. The titanium metal disposed on the side near the first surface 11 can provide extremely strong adhesion between the substrate 10 and the metal shielding layer 40, preventing the metal shielding layer 40 from delaminating.

[0038] Optionally, the first metal layer 70 is a sputtered metal layer. When the first metal layer 70 is a sputtered metal layer, a stable adhesion relationship between the first metal layer 70 and the substrate 10 can be ensured.

[0039] Optionally, the metal shielding layer 40 includes copper; or, the metal shielding layer 40 is an electroplated metal layer. The first metal layer 70 includes stacked titanium and copper metals, wherein the titanium metal is disposed on the side near the first surface 11, and the copper metal is disposed near the metal shielding layer 40. The titanium metal is between the metal shielding layer 40 and the substrate 10 to prevent the metal shielding layer 40 from delamination. The copper metal is made of the same material as the metal shielding layer 40, providing an excellent electroplating base, enabling the metal sheet shielding layer to be deposited "seamlessly" on the first metal layer 70, without a significant physical interface between the two, and eliminating the risk of galvanic corrosion between dissimilar metals. The electroplating process has a high metal deposition rate, and the required metal shielding layer 40 can be formed quickly through electroplating. In addition, compared with the metal shielding layer 40 formed by molding, the metal shielding layer 40 formed by electroplating can reduce the overall thickness of the chip and improve the electrical and thermal conductivity of the metal shielding layer 40.

[0040] like Figure 1 As shown, in some embodiments, the first surface 11 and the second surface 12 are spaced apart and disposed opposite to each other along the thickness direction of the substrate 10. The side surface 13 includes a first connecting segment 131 and a second connecting segment 132 connected together. The first connecting segment 131 and the second connecting segment 132 are disposed along the thickness direction. The second connecting segment 132 is connected to the first surface 11 through the first connecting segment 131. The metal shielding layer 40 covers the first connecting segment 131 and the second connecting segment 132. At least a portion of the first connecting segment 131 is inclined relative to the second connecting segment 132 toward the direction close to the conductive terminal 30. And / or, the orthographic projection of the first side 112 of the first connecting segment 131 for connecting the first surface 11 on the plane where the first surface 11 is located is within the range of the orthographic projection of the second side 133 of the first connecting segment 131 for connecting the second connecting segment 132 on the plane where the first surface 11 is located. The presence of the first connecting segment 131 eliminates the sharp angle at a junction in the path of the metal shielding layer 40 extending from the side 13 to the first surface 11, making the metal shielding layer 40 transition more smoothly from the side 13 to the first surface 11, effectively reducing the stress at the junction and improving the service life of the metal shielding layer 40.

[0041] Furthermore, the first connecting segment 131 includes an inclined portion 1312 that is inclined relative to the thickness direction, with the angle between the inclined portion 1312 and the thickness direction ranging from 15° to 90°; the side of the inclined portion 1312 near the first surface 11 is connected to the first surface 11, and the side of the inclined portion 1312 away from the first surface 11 is connected to the second connecting segment 132; or, the first connecting segment 131 further includes a connecting portion 1311 extending along the thickness direction, with one side of the connecting portion 1311 connected to the first surface 11 and the other side of the connecting portion 1311 connected to the inclined portion 1312; the angle between the inclined portion 1312 and the connecting portion 1311 ranges from 15° to 90°, and the second connecting segment 132 is connected to the connecting portion 1311 via the inclined portion 1312. The transition between an inclined portion 1312 or a section of the inclined portion 1312 and a section of the connecting portion 1311 avoids stress concentration in the metal shielding layer 40 and increases the service life of the metal shielding layer 40.

[0042] Understandable, such as Figure 3 As shown, the first connection segment 131 includes a stepped surface 134. During chip manufacturing, the provided wafer substrate 90 has a first groove 61, and a second groove 62 is cut out at the bottom of the first groove 61 using a half-cut process. The two cuts form the first connection segment 131, which includes the stepped surface 134. Using this cutting process, while the wafer substrate 90 remains in an integral state, the second groove 62 is formed at the future chip separation location by half-cutting. The depth of the second groove 62 exceeds the functional structure layer of the chip, but does not cut through the wafer substrate 90, so that the entire wafer substrate 90 still maintains a continuous structure. In this way, the four sidewalls of each chip are exposed in advance in the wafer state, thereby enabling the deposition of the sidewall metal shielding layer 40 and the construction of electrical connections at the wafer level.

[0043] like Figure 1 As shown, in some embodiments, the first surface 11 has a clearance area 111, the metal shielding layer 40 is located outside the clearance area 111, and the conductive terminal 30 is disposed inside the clearance area 111. By placing the conductive terminal 30 inside the clearance area 111 and the metal shielding layer 40 outside the clearance area 111, short circuits caused by contact between the metal shielding layer 40 and the conductive terminal 30 are prevented, reducing electromagnetic interference during operation and improving the overall operational stability of the chip.

[0044] Furthermore, a metal shielding layer 40 is disposed around a clearance region 111, which is located on the first surface 11 of the substrate 10. A conductive terminal 30 is disposed within the clearance region 111. The metal shielding layer 40 continuously and completely covers the portion between the conductive terminal 30 and the side surface 13 of the chip on the first surface 11, maximizing the electromagnetic shielding effect of the metal shielding layer 40 while preventing mutual interference between the conductive terminal 30 and the metal shielding layer 40.

[0045] like Figure 1 As shown, in some embodiments, the chip further includes: a second metal layer 20, which is sandwiched between the first surface 11 and the conductive terminal 30, the conductive terminal 30 being disposed on the side of the second metal layer 20 facing away from the substrate 10, and the portion of the second metal layer 20 exposed outside the chip being covered by the first metal layer 70.

[0046] Specifically, the second metal layer 20 is an Under Bump Metallurgy (UBM) layer, and the conductive terminal 30 is a conductive bump structure disposed on the UBM layer. The UBM layer contacts a conductive pad 50 formed of aluminum (Al), and the conductive pad 50 is formed on the first surface 11 of the substrate 10. The UBM layer can be formed of a material that provides good adhesion properties for forming the ball structure or an alloy including such a material, such as titanium, nickel, chromium, gold, etc.

[0047] In some embodiments, the first surface 11 and the second surface 12 are spaced apart and opposite to each other along the thickness direction of the substrate 10, and the thickness of the substrate 10 is less than 200 micrometers. In this application, the electroplating deposition of the metal shielding layer 40 is completed during the packaging process, increasing the total device thickness only by micrometers, almost maintaining the original die size. The chip thickness provided in this application embodiment can be controlled within the range of less than 200 micrometers. Traditional packaging methods, which add a molding layer and a metal shield, typically increase the thickness by hundreds of micrometers, resulting in chips manufactured using conventional processes with a thickness in the range of 300-500 micrometers. In comparison, this application can significantly reduce the overall thickness, improve system integration and packaging density, and better meet the miniaturization and high-performance requirements of mobile terminals, wearable devices, etc.

[0048] like Figures 2 to 8As shown, this application also provides a chip packaging method for producing the chip in the aforementioned embodiments. The chip packaging method includes: providing a wafer substrate 90, the surface of which has a first groove 61; forming a second groove 62 at the bottom of the first groove 61 using a half-cutting process; sputtering a first metal layer 70 on the wafer substrate 90; coating a photoresist 80 on the wafer substrate 90; removing the photoresist 80 from the area of ​​the second groove 62 and the area between the conductive terminal 30 adjacent to the second groove 62 and the second groove 62 by exposure and development processes; electroplating a metal shielding layer 40 in the area where the photoresist 80 has been removed; removing the photoresist 80 by exposure and development processes; removing the first metal layer 70 outside the area covered by the metal shielding layer 40 by etching processes; thinning the wafer substrate 90 on the side away from the conductive terminal 30; when the wafer substrate 90 is thinned to a target thickness, electroplating a metal shielding layer 40 on the side of the wafer substrate 90 away from the conductive terminal 30; and separating the wafer substrate 90 to obtain a chip.

[0049] like Figure 2 , Figure 3 As shown, a wafer substrate 90 is provided, and the surface of the wafer substrate 90 has a first groove 61; a second groove 62 is formed at the bottom of the first groove 61 using a half-cutting process. The radial dimension of the first groove 61 is larger than the radial dimension of the second groove 62. Therefore, after the second groove 62 is formed at the bottom of the first groove 61 using a half-cutting process, a first connecting segment 131 is formed from the groove opening of the first groove 61 to the groove opening of the second groove 62.

[0050] In the embodiments provided in this application, there is no molding material around the chip, which is a fan-in structure of the bare die. It is conventionally believed that deep trench cutting in this structure would significantly weaken the mechanical strength of the wafer substrate 90, easily causing edge chipping or complete breakage, thus making deep trench processing unsuitable. This application optimizes the trench depth range, blade type, and cutting parameters to achieve deep trench forming on the wafer substrate 90 while maintaining sufficient strength, thereby providing the necessary geometric conditions for subsequent sidewall metal deposition.

[0051] Specifically, the half-cut depth in this application is not simply limited to "greater than the final chip thickness and less than the wafer substrate 10 thickness," but is further limited to 60%–85% of the original thickness of the wafer substrate 90. Within this depth range, the half-cut second groove 62 can completely penetrate the active device layer of the chip and its overlying interconnect structure, forming continuously exposed silicon-based sidewalls on all four sides of the chip, providing a stable geometric boundary for the subsequent continuous deposition of the sidewall metal shielding layer 40. At the same time, a continuous silicon bridge structure is still retained at the bottom of the second groove 62, so that the wafer substrate 90 still has the mechanical strength required to withstand subsequent sputtering, electroplating, and back-side thinning processes without the introduction of molding material support.

[0052] If the depth of the second groove 62 is lower than the lower limit of the above range, the sidewall height will be insufficient, which will easily lead to the interruption of subsequent metal deposition in the sidewall area and make it difficult to form a complete shielding path in the thickness direction. If the depth of the second groove 62 exceeds the upper limit of the above range, the remaining silicon bridge thickness will be too thin, which will easily cause through cracks or the entire wafer substrate 90 to break in subsequent processes without molding support, making the process unfeasible.

[0053] To suppress the adverse effects on the overall strength of the wafer substrate 90 during the dicing process, this application specifies the use of ultra-thin diamond resin-bonded cutting blades in the Half-cut process. The blade thickness is preferably limited to 20–35 μm, and a continuous cutting edge structure is employed. Compared to conventional metal-bonded blades or thicker blades, this blade structure significantly reduces the cutting force per unit width and radial impact during dicing, resulting in lower stress concentration and effectively suppressing the propagation of microcracks at the bottom and sidewalls of the second groove 62. Furthermore, the continuous cutting edge structure makes the trench sidewall morphology more uniform, which is beneficial for the subsequent formation of a continuous coverage of the first metal layer 70 in the sidewall region. If unrestricted conventional cutting blades are used, under the same cutting depth conditions, radial cracks or latent cracks are easily induced at the bottom of the trench, leading to wafer breakage during subsequent sputtering, electroplating, or back grinding processes, making it impossible to complete the wafer-level continuous process.

[0054] In addition to the blade type, this application provides windowed limits for the cutting parameters during the Half-cut process, including but not limited to: limiting the spindle speed to 30,000–45,000 rpm to reduce instantaneous cutting impact and suppress anisotropic silicon fracture; limiting the feed rate to 1–3 mm / s to control the cutting energy input per unit length and reduce residual stress at the bottom of the second groove 62; and employing a multi-stage progressive cutting method with a single cut depth not exceeding 15–25 μm to avoid damaging the overall strength of the wafer substrate 90 with a single deep cut. Through the synergistic limitation of the above cutting parameters, the stress concentration level at the bottom and sidewalls of the second groove 62 can be effectively controlled while forming a high aspect ratio second groove 62 structure, allowing the wafer substrate 90 to maintain its integral state and smoothly enter subsequent wafer-level thinning and thinning processes even without molding and packaging.

[0055] like Figure 4 As shown, a first metal layer 70 is sputtered onto a wafer substrate 90. Specifically, the first metal layer 70 is formed on a first side 91 of the wafer substrate 90 and on the bottom and sidewalls of the second groove 62 by a sputtering process. The first side 91 of the wafer substrate 90 is the side of the wafer substrate 90 that has the conductive terminal 30.

[0056] Optionally, the first metal layer 70 includes titanium, or the first metal layer 70 includes copper, or the first metal layer 70 includes titanium and copper stacked together.

[0057] Photoresist 80 is coated on the wafer substrate 90. Specifically, during this step of coating the photoresist 80, the photoresist 80 covers the first side of the wafer substrate 90 where the conductive terminals 30 are disposed and the area of ​​the second groove 62.

[0058] like Figure 5 As shown, the photoresist 80 in the area of ​​the second groove 62 and the area between the conductive terminal 30 and the second groove 62 is removed by exposure and development processes. The photoresist 80 covering the area of ​​the second groove 62 and the area between the conductive terminal 30 and the second groove 62 is removed, and a clearance area 111 is formed in the area where the conductive terminal 30 is located by the photoresist 80.

[0059] like Figure 6 As shown, a metal shielding layer 40 is electroplated to form the area where the photoresist 80 is removed. The electroplated metal shielding layer 40 comprises copper. After electroplating, a metal shielding layer 40 is applied to the sidewalls and bottom of the second groove 62, as well as to the area between the conductive terminal 30 adjacent to the second groove 62 and the second groove 62. The metal shielding layer 40 covers the first metal layer 70. This application, by combining the deposition of the first metal layer 70, the opening design of the photoresist 80, and the electroplating filling in the wafer state, enables the metal shielding layer 40 to form a self-connected continuous coverage within the second groove 62, while simultaneously achieving a reliable electrical connection with the chip's grounding structure 31, thereby constructing a complete three-dimensional shielding path.

[0060] like Figure 7 As shown, the photoresist 80 is removed through exposure and development processes; the first metal layer 70 outside the area covered by the metal shielding layer 40 is removed through etching processes. All the photoresist 80 on the first side 91 of the wafer substrate 90 is removed, exposing the first metal layer 70 covering the first side 91 of the wafer substrate 90. Because the sputtering thickness of the first metal layer 70 is much smaller than the deposition thickness of the metal shielding layer 40, the first metal layer 70 on the first side 91 of the wafer substrate 90 can be removed through etching processes, while simultaneously preserving the first metal layer 70 covered by the metal shielding layer 40.

[0061] Thinning is performed on the side of the wafer substrate 90 opposite to the conductive terminal 30. This side of the wafer substrate 90 opposite to the conductive terminal 30 is the second side 92 of the wafer substrate 90. Before thinning on the second side 92 of the wafer substrate 90, a support structure is used to cover the first side 91 of the wafer substrate 90. The support structure includes a support layer and a soft adhesive layer. The support layer is harder than the soft adhesive layer. The soft adhesive layer covers the first side 91 of the wafer substrate 90. By providing the support structure, the wafer substrate 90 is prevented from separating during the thinning process. By introducing a support structure on the first side, the mechanical stress applied to local areas of the wafer substrate 90 during the thinning process can be effectively dispersed, avoiding local suspension or stress concentration caused by the second groove 62, thereby significantly reducing the risk of warping, collapse, or cracking of the wafer substrate 90 during the thinning process.

[0062] In some embodiments, the endpoint of thinning on the second side 92 of the wafer substrate 90 is not thinned to an arbitrary thickness, but is limited to thinning to the target thickness required for the chip. After the final thinning is completed, adjacent chips in the wafer substrate 90 are separated only through the bottom region of the second groove 62, thereby achieving the overall release of the chip without introducing an additional secondary dicing process.

[0063] With the second groove 62 already formed, significant thickness non-uniformity and stress concentration areas exist within the wafer substrate 90, making the high-pressure, high-removal-rate methods used in conventional back-grinding processes unsuitable for this structure. Therefore, in some embodiments of this application, the back-grinding pressure during the thinning process is controlled and limited to a low-pressure, gradual removal process window. By reducing the mechanical load applied per unit area to the second side 92 of the wafer substrate 90, stress concentration at the bottom and sidewall regions of the second groove 62 can be effectively suppressed, preventing crack propagation or silicon bridge instability during the thinning process.

[0064] like Figure 8 As shown, when the wafer substrate 90 is thinned to the target thickness, a metal shielding layer 40 is electroplated on the side of the wafer substrate 90 opposite to the conductive terminal 30. After thinning, a metal shielding layer 40 is electroplated on the second side 92 of the wafer substrate 90, completely covering the second side 92 of the wafer substrate 90. At the same time, the metal shielding layer 40 on the second side 92 of the wafer substrate 90 is connected to the metal shielding layer 40 located on the sidewall of the second groove 62 to form a continuous integral structure, ensuring the integrity and continuity of the metal shielding layer 40 coverage.

[0065] The wafer substrate 90 is separated to obtain the chip. During final separation, all chips can be released in one step, forming a complete second surface 12, side surface 13, and a continuous metal shielding layer 40 of the first surface 11. Specifically, the first side 91 of the wafer substrate 90 corresponds to the first surface 11 of the chip, the second side 92 of the wafer substrate 90 corresponds to the second surface 12 of the chip, and the sidewall of the second groove 62 corresponds to the side surface 13 of the chip.

[0066] The above embodiments of the present invention focus on describing the differences between the various embodiments. As long as the different optimization features of the various embodiments are not contradictory, they can be combined to form a better embodiment. For the sake of brevity, they will not be described in detail here.

[0067] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A chip, characterized in that, include: The substrate (10) includes a first surface (11), a second surface (12) and a side surface (13), wherein the first surface (11) and the second surface (12) are opposite to each other, and the side surface (13) connects the first surface (11) and the second surface (12). Conductive terminal (30), the conductive terminal (30) is disposed on the first surface (11); A metal shielding layer (40) is connected to the grounding structure (31) of the chip. The metal shielding layer (40) covers the second surface (12) and the side surface (13). The metal shielding layer (40) extends from the side surface (13) to the first surface (11), and the metal shielding layer (40) covers the portion of the first surface (11) located between the conductive terminal (30) and the side surface (13).

2. The chip according to claim 1, characterized in that, The conductive terminal (30) includes a ground terminal that serves as a ground structure (31) for the chip, and the metal shielding layer (40) located on the first surface (11) extends to be connected to the ground terminal.

3. The chip according to claim 1, characterized in that, It also includes a first metal layer (70) sandwiched between the substrate (10) and the metal shielding layer (40), the first metal layer (70) covering the side (13) and extending from the side (13) to the first surface (11), and the first metal layer (70) covering the portion of the first surface (11) located between the conductive terminal (30) and the side (13), and the metal shielding layer (40) covering the first metal layer (70).

4. The chip according to claim 3, characterized in that, The first metal layer (70) is connected to the grounding structure (31) of the chip.

5. The chip according to claim 3, characterized in that, The first metal layer (70) comprises titanium and / or copper; or, the first metal layer (70) is a sputtered metal layer.

6. The chip according to claim 1, characterized in that, The metal shielding layer (40) comprises copper; or, the metal shielding layer (40) is an electroplated metal layer.

7. The chip according to claim 1, characterized in that, The first surface (11) and the second surface (12) are spaced apart and disposed opposite to each other along the thickness direction of the substrate (10). The side surface (13) includes a first connecting segment (131) and a second connecting segment (132) connected together. The first connecting segment (131) and the second connecting segment (132) are disposed along the thickness direction. The second connecting segment (132) is connected to the first surface (11) through the first connecting segment (131). The metal shielding layer (40) covers the first connecting segment (131) and the second connecting segment (132). At least a portion of the first connecting segment (131) is inclined relative to the second connecting segment (132) toward the conductive terminal (30); and / or The orthographic projection of the first side (112) of the first connecting segment (131) for connecting the first surface (11) onto the plane of the first surface (11) is within the range of the orthographic projection of the second side (133) of the first connecting segment (131) for connecting the second connecting segment (132) onto the plane of the first surface (11).

8. The chip according to claim 7, characterized in that, The first connecting segment (131) includes an inclined portion (1312) that is inclined relative to the thickness direction, the angle between the inclined portion (1312) and the thickness direction being in the range of 15° to 90°; The side of the inclined portion (1312) closest to the first surface (11) is connected to the first surface (11), and the side of the inclined portion (1312) away from the first surface (11) is connected to the second connecting segment (132); or, The first connecting segment (131) further includes a connecting portion (1311) extending along the thickness direction, one side of the connecting portion (1311) being connected to the first surface (11), and the other side of the connecting portion (1311) being connected to the inclined portion (1312); the included angle between the inclined portion (1312) and the connecting portion (1311) is in the range of 15° to 90°, and the second connecting segment (132) is connected to the connecting portion (1311) through the inclined portion (1312).

9. The chip according to claim 1, characterized in that, The first surface (11) has a clearance area (111), the metal shielding layer (40) is located outside the clearance area (111), and the conductive terminal (30) is disposed inside the clearance area (111).

10. A chip packaging method, characterized in that, The chip packaging method for producing any one of claims 1 to 9 includes: A wafer substrate (90) is provided, the surface of which has a first groove (61); A second groove (62) is formed at the bottom of the first groove (61) using a half-cutting process. A first metal layer (70) is sputtered onto the wafer substrate (90); Photoresist (80) is coated on the wafer substrate (90); The photoresist (80) in the second groove (62) area and the area between the conductive terminal (30) adjacent to the second groove (62) and the second groove (62) is removed by exposure and development processes. The metal shielding layer (40) is formed by electroplating in the area where the photoresist (80) is removed. The photoresist (80) is removed by exposure and development processes. The first metal layer (70) outside the area covered by the metal shielding layer (40) is removed by an etching process. Thinning is performed on the side of the wafer substrate (90) opposite to the conductive terminal (30); When the wafer substrate (90) is thinned to the target thickness, the metal shielding layer (40) is formed by electroplating on the side of the wafer substrate (90) opposite to the conductive terminal (30). The wafer substrate (90) is separated to obtain the chip.

Images