Wide bandgap power device integrated package module and preparation method thereof

Abstract

The application discloses a wide-bandgap power device integrated package module and a preparation method thereof, and relates to the technical field of power electronic packaging. The package module comprises a multilayer co-fired ceramic co-fired main body provided with a groove and a metallized pad, a wide-bandgap power chip placed in the groove in a front-down manner, a bottom surface composite layer covering the back surface of the wide-bandgap power chip and the bottom surface of the multilayer co-fired ceramic co-fired main body, and a back electrode lead-out structure connected with a copper seed layer in the bottom surface composite layer; the bottom surface composite layer further comprises a thick copper layer located on the side of the copper seed layer away from the wide-bandgap power chip, and the thick copper layer forms a welding interface connected with an external heat dissipation structure. The back electrode lead-out structure can be formed by the thick copper layer electrically connected with the copper seed layer, or can be formed by a drain lead-out through hole connecting the copper seed layer and a drain lead-out pad on the top surface. The application realizes an integrated package with low parasitic inductance, low thermal resistance and high integration.

Description

Technical Field

[0001] This application relates to the fields of advanced power electronics packaging and multilayer co-fired electronic ceramic manufacturing technology, and in particular to an integrated packaging module for wide bandgap power devices and its preparation method. Background Technology

[0002] Wide-bandgap semiconductor power devices, such as silicon carbide metal-oxide-semiconductor field-effect transistors and gallium nitride high electron mobility transistors, can withstand high junction temperatures and high-frequency switching. However, further performance release is limited by packaging. Existing power packaging routes mainly suffer from three bottlenecks: First, the traditional multi-step heterogeneous integration scheme using active metal solder substrates and aluminum wire bonding typically has a parasitic inductance of 10 nH to 20 nH per chip loop, and there are up to four types of heterogeneous failure interfaces within the module; Second, the scheme of embedding power chips in organic printed circuit boards or organic laminates has an out-of-plane thermal conductivity of less than 1 W / (m·K), making it difficult to withstand kilowatt-level steady-state heat flow; Third, the scheme based on single-layer ceramic substrates with flip-chip connections cannot achieve multi-layer wiring and co-fired embedded passive components because the ceramic is a pre-formed single-layer structure.

[0003] While existing multilayer co-fired ceramic technology possesses the capability for multilayer wiring and co-fired embedded passive components, it primarily targets radio frequency and microwave integration. A key technical challenge in this field is how to achieve low-parasitic integration of recessed flip-chip wide-bandgap power chips on multilayer co-fired ceramic substrates, and how to achieve kilowatt-level heat dissipation via a copper-plated bottom plate directly connected to a cold plate. Summary of the Invention

[0004] The main purpose of this application is to propose an integrated packaging module for wide bandgap power devices and its fabrication method, aiming to solve the problems of large parasitic inductance, insufficient heat dissipation and low integration of existing packaging solutions.

[0005] To achieve the above objectives, in a first aspect, this application proposes an integrated package module for wide bandgap power devices, comprising: A multi-layer co-fired ceramic body is formed by stacking and co-firing multiple layers of green ceramic film. The multi-layer co-fired ceramic body has a groove, and the bottom of the groove has a metallized pad. At least one wide bandgap power chip, the wide bandgap power chip has a chip front pad on its front side, the wide bandgap power chip is placed in the groove with its front side facing down, the front pad is connected to the metallization pad, and the back side of the wide bandgap power chip is flush with the bottom surface of the multilayer co-fired ceramic body; A bottom composite layer covering the back surface of the wide bandgap power chip and the bottom surface of the multilayer co-fired ceramic body, the bottom composite layer including a copper seed layer connected to the back electrode of the wide bandgap power chip and a thick copper layer located on the side of the copper seed layer opposite to the wide bandgap power chip, the thick copper layer forming a welding interface for connection with an external heat dissipation structure; and A back electrode lead-out structure connected to the copper seed layer for leading out the back electrode of the wide bandgap power chip, the back electrode lead-out structure including the thick copper layer or a drain lead-out via penetrating the multilayer co-fired ceramic body; When the back electrode lead-out structure includes the thick copper layer, the copper seed layer is electrically connected to the thick copper layer, and the thick copper layer serves as both the lead-out terminal of the back electrode of the wide bandgap power chip and the soldering interface for connection with the external heat dissipation structure. When the back electrode lead-out structure includes the drain lead-out via, an insulating layer and a second copper seed layer are sequentially provided between the copper seed layer and the thick copper layer. The thick copper layer is located on the side of the second copper seed layer away from the insulating layer and is electrically isolated from the copper seed layer. The lower end of the drain lead-out via is connected to the copper seed layer, and the upper end is connected to the drain lead-out pad on the top surface of the multilayer co-fired ceramic body.

[0006] In some embodiments, the multilayer co-fired ceramic includes low-temperature co-fired ceramic or high-temperature co-fired ceramic; The co-firing temperature of the low-temperature co-fired ceramic is 800℃~1000℃; The co-firing temperature of the high-temperature co-fired ceramic is 1400℃~1700℃; The out-of-plane thermal conductivity of the multilayer co-fired ceramic body is ≥10 W / (m·K), and the total number of layers is ≥20. The height difference between the back surface of the wide bandgap power chip and the bottom surface of the multilayer co-fired ceramic body does not exceed ±20 μm.

[0007] In some embodiments, the metallized pads are composed of co-fired thick film conductors, the materials of which include at least one of silver-based, copper-based, tungsten-based, and molybdenum-based pastes; The wide bandgap power chip includes at least one of silicon carbide MOSFET, silicon carbide Schottky diode, and gallium nitride HEMT.

[0008] In some preferred embodiments, the wide bandgap power chip includes at least one of a 650 V or 1200 V silicon carbide metal-oxide-semiconductor field-effect transistor, a silicon carbide Schottky barrier diode, and a 100 V or 650 V gallium nitride high electron mobility transistor.

[0009] In some embodiments, at least one decoupling capacitor or at least one gate drive inductor is embedded in the multilayer co-fired ceramic body and connected to the gate circuit or source circuit of the wide bandgap power chip through internal wiring of the multilayer co-fired ceramic body.

[0010] In some embodiments, the back electrode lead-out structure includes the thick copper layer, the copper seed layer is electrically connected to the thick copper layer, and the thick copper layer serves as both the lead-out terminal of the back electrode of the wide bandgap power chip and the soldering interface connected to the external heat dissipation structure; the copper seed layer is a copper layer formed by sputter deposition, and the thick copper layer is an electroplated copper layer formed by electroplating with the copper seed layer as the seed. The thickness of the copper seed layer is 0.3 μm to 2 μm; The thickness of the thick copper layer is 100 μm to 500 μm.

[0011] In some embodiments, a filler adhesive is used to fill the space between the groove, the wide bandgap power chip, and the sidewall of the groove. The filler adhesive is used to fix the wide bandgap power chip, provide electrical insulation between the sidewall of the wide bandgap power chip and the sidewall of the groove, and buffer thermal cycling stress. The filler adhesive includes at least one of epoxy resin filler adhesive, silicone filler adhesive, and high thermal conductivity filler adhesive; the filler adhesive is doped with thermally conductive filler, which includes at least one of alumina, boron nitride, aluminum nitride, and magnesium oxide.

[0012] In some embodiments, an insulating layer and a second copper seed layer are provided between the copper seed layer and the thick copper layer, and the thick copper layer is disposed on the side of the second copper seed layer opposite to the insulating layer. The insulating layer is used to electrically isolate the back electrode of the wide bandgap power chip from the thick copper layer. The back electrode lead-out structure includes a drain lead-out via penetrating the multilayer co-fired ceramic body. The lower end of the drain lead-out via is connected to the copper seed layer, and the upper end is connected to the drain lead-out pad on the top surface of the multilayer co-fired ceramic body, so that the back electrode of the wide bandgap power chip is led out to the top surface of the multilayer co-fired ceramic body through the copper seed layer and the drain lead-out via. The insulating layer includes at least one of aluminum nitride ceramic dielectric layer, silicon nitride ceramic dielectric layer, alumina ceramic dielectric layer, polyimide high thermal conductivity insulating polymer layer containing ceramic filler, and epoxy resin high thermal conductivity insulating polymer layer containing ceramic filler, with a thickness of 5 μm to 100 μm. In some embodiments, there are multiple grooves, and a wide bandgap power chip is placed in each groove. The multiple wide bandgap power chips are connected in parallel or in a bridge topology through the back electrode lead-out structure. When the back electrode lead-out structure includes the thick copper layer, the back electrodes of at least two wide bandgap power chips are electrically connected through the copper seed layer and the thick copper layer to form a multi-chip parallel structure. When the back electrode lead-out structure includes the drain lead-out via, the back electrodes of each wide bandgap power chip are led out to the drain lead-out pad on the top surface of the multilayer co-fired ceramic body through the corresponding drain lead-out via, and form a half-bridge, full-bridge, multi-level inverter bridge or modular multi-level converter sub-module topology through the internal wiring of the multilayer co-fired ceramic body.

[0013] Secondly, this application also proposes a method for preparing the packaging module proposed in the first aspect of this application, comprising: S1. Provide a green ceramic film strip, wires are laid on the green ceramic film strip, through holes are filled and grooves are punched, and the strip is laminated to form a laminate. S2. Perform debinding and co-firing treatment on the laminated body to form a multi-layer co-fired ceramic co-fired body with grooves; S3. Place the wide bandgap power chip face down into the groove, and connect the front pads of the wide bandgap power chip to the metallized pads at the bottom of the groove. S4. Fill the groove with filler adhesive between the wide bandgap power chip and the sidewall of the groove and cure it. S5. A copper seed layer is sputtered and deposited on the bottom surface of the multilayer co-fired ceramic body and the back surface of the wide bandgap power chip. S6. When the back electrode lead-out structure includes the thick copper layer, the thick copper layer is grown by electroplating using the copper seed layer as a seed, so that the copper seed layer is electrically connected to the thick copper layer; when the back electrode lead-out structure includes a drain lead-out via, an insulating layer is formed and patterned on the copper seed layer, a second copper seed layer is sputtered and deposited on the insulating layer, the thick copper layer is grown by electroplating using the second copper seed layer as a seed, and the lower end of the drain lead-out via is connected to the copper seed layer.

[0014] In some embodiments, step S2, the debinding and co-firing process includes sequentially subjecting the laminate to a first heat treatment, a second heat treatment, and a third heat treatment; the first heat treatment is performed at a temperature of 80℃~120℃ for 2 h~4 h; the second heat treatment is performed at a temperature of 250℃~500℃ for 2 h~4 h; and the third heat treatment is performed at a temperature of 800℃~1700℃ for 4 h~10 h. In step S3, the front pad of the wide bandgap power chip is connected to the metallized pad at the bottom of the groove by sintering with metal-based paste or by transient liquid phase bonding. The sintering temperature of the metal-based paste is 200℃~300℃, the pressure is 5 MPa~40 MPa, and the holding time is 1 min~10 min. In step S4, the filler adhesive is applied by dispensing or vacuum injection, and the curing temperature is 80℃~180℃, and the time is 10 min~120 min.

[0015] In some preferred embodiments, in step S3, the metal-based sintering slurry includes at least one of nano-silver paste, nano-copper paste, silver paste, copper paste, and gold paste; the transient liquid-phase bonded alloy system is at least one of copper-tin, silver-tin, and gold-tin.

[0016] The beneficial effects of this application are: By placing a wide-bandgap power chip face-down into a pre-formed recess in a multilayer co-fired ceramic substrate and connecting it to the bottom metallized pads, low-parasitic, high-density interconnection between the chip and the substrate is achieved. The back side of the wide-bandgap power chip is flush with the bottom surface of the multilayer co-fired ceramic substrate and is covered by a sputtered copper seed layer and a thick copper layer. This thick copper layer serves a dual function as the back electrode lead-out of the chip and the external heat dissipation soldering interface, constructing an ultra-low thermal resistance path from the chip junction to the external heat dissipation structure. This structure effectively solves the problems of large parasitic inductance and numerous heterogeneous interfaces in traditional wire bonding schemes, achieving a significant reduction in loop parasitic inductance (down to below 5 nH). Simultaneously, since the thick copper layer directly serves as the heat dissipation interface, combined with the high thermal conductivity of the co-fired ceramic dielectric, the junction-to-case thermal resistance is significantly reduced (down to below 0.3 K / W), meeting the heat dissipation requirements of high power density. Furthermore, the integrated structure of multilayer co-fired ceramics reduces material interfaces, improves reliability, and supports embedded passive components and complex multi-chip topology integration, greatly enhancing the integration of the package and design flexibility. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1This is a longitudinal cross-sectional view of the integrated packaging module for wide bandgap power devices provided in the embodiments of this application. The figure also shows an external cold plate 14 connected to the bottom surface of the module. The external cold plate 14 is not part of the packaging module of this application and is only used to show the longitudinal heat dissipation path. Figure 2 This is a top view (half-bridge topology) of a wide bandgap power device integrated package module provided in an embodiment of this application. Figure 3 This is a longitudinal cross-sectional view of the multilayer co-fired ceramic body with grooves after S1 and S2 in the preparation method provided in the embodiments of this application; Figure 4 This is a longitudinal cross-sectional view of the process in which a flip-chip wide bandgap power chip is placed into a groove and sintered with a metal-based paste after step S3 in the preparation method provided in this application. Figure 5 This is a longitudinal cross-sectional view of the filling and curing process of the wide bandgap power chip and the sidewall of the groove after step S4 is completed in the preparation method provided in this application. Figure 6 This is a longitudinal cross-sectional view of the copper seed layer jointly sputtered and deposited on the bottom surface of the module and the back surface of the wide bandgap power chip after step S5 in the preparation method provided in the embodiments of this application. Figure 7 This is a longitudinal cross-sectional view of the thick copper layer formed after step S6 in the preparation method provided in this application. In the embodiment where the thick copper layer is directly conductive, the thick copper layer is grown by electroplating using a copper seed layer as a seed. In the embodiment where the thick copper layer is insulating and dissipates heat, an insulating layer and a second copper seed layer are sequentially disposed between the copper seed layer and the thick copper layer.

[0019] Figure label: 100. Wide bandgap power device integrated packaging module; 1. Multilayer co-fired ceramic body; 2. Groove; 3. Metallized pads; 4. Wide bandgap power chip; 5. Connector layer; 6. Copper seed layer; 7. Thick copper layer; 8. Drain lead-out pads; 9a. Decoupling capacitor; 9b. Gate drive inductor; 10. Internal wiring and vias; 11. Filler adhesive; 12. Insulating layer; 13. Drain lead-out vias; 14. External cold plate (shown only) Figure 1 15. Second copper seed layer (not part of the encapsulation module of this application).

[0020] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0023] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0024] The terminology used in this application is explained as follows: "Wide bandgap power chips" broadly refer to power discrete devices manufactured using wide bandgap semiconductor materials such as silicon carbide and gallium nitride. Their typical characteristics include high critical breakdown field strength and high operating junction temperature. "Multilayer co-fired ceramics" refers to the process and products of stacking multiple layers of unsintered ceramic films and sintering them in a single step, including low-temperature co-fired ceramics and high-temperature co-fired ceramics. "Sputter deposition" is a type of physical vapor deposition, referring to the process of using glow discharge to bombard a target material under vacuum conditions, causing target atoms to deposit on the substrate surface to form a thin film. "Front-down mounting" refers to a chip mounting method where the active area and pads face the substrate or carrier, i.e., flip-chip structure.

[0025] "Groove" generally refers to the opening structure formed on a multilayer co-fired ceramic body to accommodate wide-bandgap power chips. It includes blind-hole grooves that do not penetrate the co-fired body and window-type openings that penetrate the co-fired body. Both are functionally equivalent and can achieve chip embedding and contact with the metallization layer on the bottom surface.

[0026] Traditional aluminum wire bonding solutions have high parasitic inductance, organic dielectric solutions have poor heat dissipation, and single-layer ceramic solutions have low integration density. None of these three solutions can simultaneously achieve low parasitic inductance, efficient heat dissipation, and high-density three-dimensional integration.

[0027] Based on the above issues, please refer to Figure 1 , Figure 6 and Figure 7 This application provides an integrated packaging module for wide bandgap power devices. The integrated packaging module 100 includes: a multilayer co-fired ceramic body 1 formed by stacking and co-firing multiple layers of green ceramic film; a groove 2 on the multilayer co-fired ceramic body 1 for accommodating a wide bandgap power chip 4; a metallized pad 3 at the bottom of the groove 2; at least one wide bandgap power chip 4; a chip front pad on the front side of the wide bandgap power chip 4; the wide bandgap power chip 4 is placed face down in the groove 2; the chip front pad is connected to the metallized pad 3; and the wide bandgap power chip... The back surface of the wide-bandgap power chip 4 is flush with the bottom surface of the multilayer co-fired ceramic body 1. A bottom composite layer covers the back surface of the wide-bandgap power chip 4 and the bottom surface of the multilayer co-fired ceramic body 1. The bottom composite layer includes a copper seed layer 6 connected to the back electrode of the wide-bandgap power chip 4 and a thick copper layer 7 located on the side of the copper seed layer 6 away from the wide-bandgap power chip 4. The thick copper layer 7 forms a welding interface for connection with the external heat dissipation structure. A back electrode lead-out structure is also connected to the copper seed layer 6 for leading out the back electrode of the wide-bandgap power chip 4. The back electrode lead-out structure includes the thick copper layer 7 or a drain lead-out via 13 penetrating the multilayer co-fired ceramic body 1. When the back electrode lead-out structure includes the thick copper layer 7, the copper seed layer 6 and the thick copper layer 7 are electrically connected. The thick copper layer 7 simultaneously serves as the lead-out end of the back electrode of the wide-bandgap power chip 4 and the welding interface for connection with the external heat dissipation structure. When the back electrode lead-out structure includes a drain lead-out via 13, an insulating layer 12 and a second copper seed layer 15 are sequentially provided between the copper seed layer 6 and the thick copper layer 7. The thick copper layer 7 is disposed on the side of the second copper seed layer 15 away from the insulating layer 12, and the insulating layer 12 electrically isolates the copper seed layer 6 from the thick copper layer 7. The lower end of the drain lead-out via 13 is connected to the copper seed layer 6, and the upper end is connected to the drain lead-out pad 8 on the top surface of the multilayer co-fired ceramic co-fired body 1, so that the back electrode of the wide bandgap power chip 4 is led out to the top surface of the multilayer co-fired ceramic co-fired body 1 through the copper seed layer 6 and the drain lead-out via 13.

[0028] In the embodiment where the thick copper layer 7 is directly conductive, the copper seed layer 6 is electrically connected to the thick copper layer 7. The thick copper layer 7 simultaneously serves as the lead-out terminal of the back electrode of the wide bandgap power chip 4 and the welding interface for connection with the external heat dissipation structure. By matching the thickness of the wide bandgap power chip 4 with the depth of the groove 2, a continuous reference surface is formed between the back surface of the wide bandgap power chip 4 and the bottom surface of the multilayer co-fired ceramic body 1. The copper seed layer 6, subsequently sputtered, can span across the back surface of the wide bandgap power chip 4 and the bottom surface of the multilayer co-fired ceramic body 1, and provide a conductive substrate for the electroplating formation of the thick copper layer 7. The thick copper layer 7 and the copper seed layer 6 are metallurgically bonded, electrically forming a low-inductance lead-out terminal of the back electrode, and thermally forming a large-area heat dissipation interface that can be connected to the external cold plate 14.

[0029] In the embodiment where the thick copper insulating layer dissipates heat and the drain lead-out via is responsible for electrode lead-out, an insulating layer 12 and a second copper seed layer 15 are sequentially provided between the copper seed layer 6 and the thick copper layer 7. The insulating layer 12 is used to electrically isolate the back electrode of the wide bandgap power chip 4 from the thick copper layer 7. The lower end of the drain lead-out via 13 is connected to the copper seed layer 6, and the upper end is connected to the drain lead-out pad 8 on the top surface of the multilayer co-fired ceramic body 1, so that the back electrode of the wide bandgap power chip 4 is led out to the top surface of the multilayer co-fired ceramic body 1 through the copper seed layer 6 and the drain lead-out via 13. In this scheme, the thick copper layer 7 is an electrically neutral heat dissipation layer that can be connected to a grounded cold plate or a housing to achieve decoupling of electrical and thermal functions.

[0030] In some embodiments, the multilayer co-fired ceramic includes low-temperature co-fired ceramic or high-temperature co-fired ceramic; the co-firing temperature of the low-temperature co-fired ceramic is 800℃~1000℃; and the co-firing temperature of the high-temperature co-fired ceramic is 1400℃~1700℃.

[0031] By selecting low-temperature or high-temperature co-firing systems, silver / copper high-conductivity conductors or tungsten / molybdenum high-melting-point conductors can be adapted to meet the requirements of conductor resistivity and anti-electromigration capability for different voltage, current and frequency application scenarios.

[0032] In some implementations, the multilayer co-fired ceramic body 1 can be selected from ceramic material systems with different out-of-plane thermal conductivity depending on the different requirements for heat dissipation capacity and cost in the application scenario. For example, glass-based low-temperature co-fired ceramics (out-of-plane thermal conductivity of about 3~5 W / (m·K)) can be used to obtain lower dielectric loss and manufacturing cost; or high-temperature co-fired ceramics such as alumina, aluminum nitride, and silicon nitride (out-of-plane thermal conductivity of about 20~200 W / (m·K)) can be used to obtain lower longitudinal thermal resistance under the high heat flux density conditions of wide bandgap power chips, but the material and process costs are correspondingly higher. Since the out-of-plane (thickness direction) thermal conductivity determines the longitudinal heat dissipation path thermal resistance of the chip through the co-fired body to the bottom heat dissipation structure, the above material systems can be selected according to the target junction temperature and cost budget, taking into account both heat dissipation capacity and economy.

[0033] The number of layers in the multilayer co-fired ceramic body 1 can be set according to the wiring density of the gate, source, and drain lines, the integration requirements of embedded passive components, and the groove depth to accommodate wide bandgap power chips, thereby balancing the stack-up thickness and manufacturing cost while meeting the requirements of three-dimensional high-density interconnection and structure.

[0034] The height difference between the back surface of the wide bandgap power chip 4 and the bottom surface of the multilayer co-fired ceramic body 1 does not exceed ±20 μm. This coplanarity constraint ensures that the back surface of the chip and the bottom surface heat dissipation and interconnection structure are on approximately the same reference plane, guaranteeing that the copper seed layer 6 sputtered, the thick copper layer 7 electroplated, and the external cold plate 14 subsequently prepared on the bottom surface can be uniformly and gaplessly bonded, avoiding local air gaps, uneven plating, or bonding voids caused by excessive height difference, thereby maintaining a uniform longitudinal heat dissipation path and stable electrical / thermal connection quality on the bottom surface.

[0035] In some embodiments, the metallized pad 3 is composed of a co-fired thick-film conductor, the material of which includes at least one of silver-based, copper-based, tungsten-based, and molybdenum-based pastes. The metallized pad 3 at the bottom of the groove 2 needs to be co-fired with the multilayer ceramic green tape at high temperatures of several hundred or even thousands of degrees, therefore a thick-film conductor paste compatible with this co-firing temperature must be used.

[0036] In some embodiments, the wide bandgap power chip 4 includes at least one of a silicon carbide MOSFET, a silicon carbide Schottky diode, and a gallium nitride HEMT. Preferably, the wide bandgap power chip 4 includes at least one of a 650 V or 1200 V silicon carbide metal-oxide-semiconductor field-effect transistor, a silicon carbide Schottky barrier diode, and a 100 V or 650 V gallium nitride high electron mobility transistor.

[0037] In some embodiments, at least one decoupling capacitor 9a or at least one gate drive inductor 9b is co-fired and embedded in the multilayer co-fired ceramic body 1, and is connected to the gate circuit or source circuit of the wide bandgap power chip 4 through internal wiring of the multilayer co-fired ceramic body 1. For example, a high-frequency decoupling capacitor 9a is co-fired and embedded in the ceramic layer directly below the wide bandgap power chip 4, with one end directly connected to the source pad through internal wiring and via 10, and the other end connected to the reference ground of the gate circuit. This can physically minimize the area and parasitic inductance of the gate drive circuit, which is crucial for suppressing gate oscillations during high-frequency switching and preventing false turn-on.

[0038] In some embodiments, the copper seed layer 6 has a thickness of 0.3 μm to 2 μm; the thick copper layer 7 has a thickness of 100 μm to 500 μm. The selection of the thickness of the copper seed layer 6 balances the continuity of sputtering film deposition with production efficiency. When the thickness is less than 0.3 μm, discontinuities in coverage are likely to occur at the tiny gaps spanning the back of the chip and the ceramic surface, resulting in localized areas without copper growth after electroplating begins; when the thickness is greater than 2 μm, the sputtering time is too long, increasing costs, and stress accumulation may lead to film cracking. The 100 μm to 500 μm thick copper layer 7 has low in-plane resistivity and thermal resistance, which allows for effective heat diffusion, while providing sufficient physical thickness for soldering to the external cold plate to accommodate the solder layer and absorb mechanical stress caused by differences in thermal expansion coefficients, preventing cracking at the cold plate connection.

[0039] To improve long-term reliability, in some embodiments, a filler adhesive 11 is filled within the groove 2, between the wide-bandgap power chip 4 and the sidewall of the groove 2. The filler adhesive 11 is used to fix the wide-bandgap power chip 4, provide electrical insulation between the sidewall of the wide-bandgap power chip 4 and the sidewall of the groove 2, and buffer thermal cycling stress. The filler adhesive 11 includes at least one of epoxy resin filler adhesive, silicone filler adhesive, and high thermal conductivity filler adhesive. By providing the filler adhesive 11, the narrow gap between the wide-bandgap power chip 4 and the sidewall of the multilayer co-fired ceramic body 1 is filled. This gap is a high electric field concentration area, and the electrical insulation properties of the filler adhesive 11 can prevent lateral air discharge or creepage.

[0040] The high thermal conductivity filler adhesive refers to a filler adhesive with a matrix of polymers such as epoxy resin, silicone, polyimide, or modified bismaleimide, and in which thermally conductive fillers are doped to achieve a thermal conductivity of not less than 1 W / (m·K) after curing. The thermally conductive fillers include at least one of alumina, boron nitride, aluminum nitride, and magnesium oxide. As an example, the volume fraction of the thermally conductive filler in filler adhesive 11 is 30%~70%, the particle size is 0.5 μm~50 μm, and the filling density can be increased by using a gradation of large and small particle sizes. Correspondingly, the thermal conductivity of filler adhesive 11 after curing is 1 W / (m·K)~8 W / (m·K), the volume resistivity is not less than 1×10¹³ Ω·cm, the breakdown field strength is not less than 15 kV / mm, and the coefficient of thermal expansion is 15×10¹³ Ω·cm. -6 / K~40×10 -6 / K.

[0041] For example, in one specific example, filler 11 is an epoxy resin filler doped with approximately 55% by volume spherical alumina with particle sizes of 1 μm and 20 μm, and its thermal conductivity after curing is approximately 2.5 W / (m·K), and its glass transition temperature is approximately 155°C; in another specific example, filler 11 is an organosilicon filler doped with approximately 45% by volume hexagonal boron nitride, and its thermal conductivity after curing is approximately 1.8 W / (m·K), and its lower elastic modulus is more conducive to buffering thermal cycling stress; in yet another specific example, filler 11 is an epoxy resin filler doped with approximately 60% by volume aluminum nitride and surface passivated, and its thermal conductivity after curing is approximately 4 W / (m·K).

[0042] Compared to ordinary epoxy resin fillers without thermally conductive fillers (whose thermal conductivity is typically only 0.2 W / (m·K)~0.4 W / (m·K)), the high thermal conductivity filler doped with the aforementioned thermally conductive filler, while maintaining electrical insulation performance, provides an auxiliary lateral heat dissipation channel for the side of the wide bandgap power chip 4. This allows heat generated on the side and edge of the chip to be conducted through the filler 11 to the multilayer co-fired ceramic body 1 and further dissipated, thereby reducing the local temperature rise at the chip edge and alleviating the temperature gradient inside the chip. At the same time, the incorporation of thermally conductive fillers also reduces the coefficient of thermal expansion of the filler 11, making it closer to the coefficient of thermal expansion of the wide bandgap power chip 4 and the multilayer co-fired ceramic body 1. This reduces the shear stress generated between the chip side and the sidewall of the groove 2 during temperature cycling, suppresses interface cracking and delamination between the filler 11 and the chip side and ceramic sidewall, and helps improve the temperature cycling reliability of the module.

[0043] In some embodiments, an insulating layer 12 and a second copper seed layer 15 are sequentially disposed between the copper seed layer 6 and the thick copper layer 7, with the thick copper layer 7 located on the side of the second copper seed layer 15 facing away from the insulating layer 12. The insulating layer 12 is used to electrically isolate the back electrode of the wide bandgap power chip 4 from the thick copper layer 7; the insulating layer 12 includes at least one of aluminum nitride ceramic dielectric layer, silicon nitride ceramic dielectric layer, alumina ceramic dielectric layer, polyimide high thermal conductivity insulating polymer layer containing ceramic filler, and epoxy resin high thermal conductivity insulating polymer layer containing ceramic filler, with a thickness of 5 μm to 100 μm. After sputtering and patterning to form the copper seed layer 6, the insulating layer 12 is formed on the copper seed layer 6 by deposition, screen printing, or surface mount technology. Then, the second copper seed layer 15 is sputtered and deposited on the insulating layer 12, and the thick copper layer 7 is formed by electroplating using the second copper seed layer 15 as a seed. This structure makes the thick copper layer 7 an electrically neutral heat dissipation layer, which can be directly connected to the grounded cold plate or the housing over a large area.

[0044] In some embodiments, the multilayer co-fired ceramic body 1 has a drain lead-out via 13 penetrating its body. The lower end of the drain lead-out via 13 is connected to the copper seed layer 6, and the upper end is connected to the drain lead-out pad 8 on the top surface of the multilayer co-fired ceramic body 1, so that the back electrode of the wide bandgap power chip 4 is led out to the top surface of the multilayer co-fired ceramic body 1 through the copper seed layer 6 and the drain lead-out via 13. When the thick copper layer 7 is electrically isolated from the back electrode, the drain lead-out via 13 provides the back electrode with an electrical lead-out path independent of the thick copper layer 7.

[0045] In the embodiment where the thick copper layer 7 is directly conductive, there are multiple grooves 2, and a wide bandgap power chip 4 is placed in each groove 2. The back electrodes of at least two wide bandgap power chips 4 are electrically connected through the copper seed layer 6 and the thick copper layer 7 to form a multi-chip parallel structure.

[0046] In the embodiment where thick copper insulation dissipates heat and drain lead-out vias are used for electrode lead-out, there are multiple grooves 2. Wide bandgap power chips 4 are placed in each groove 2. The back electrodes of each wide bandgap power chip 4 are led out through corresponding drain lead-out vias 13 to the corresponding drain lead-out pads 8 on the top surface of the multilayer co-fired ceramic body 1. These electrodes are then routed through the internal wiring of the multilayer co-fired ceramic body 1 to form a half-bridge, full-bridge, multi-level inverter bridge, or modular multi-level converter sub-module topology. For example, please refer to... Figure 2 Two chips can form a half-bridge, four chips can form a full-bridge, and multiple chips can also be configured as needed to form a multi-level topology or a modular multi-level converter sub-module.

[0047] This application also provides a method for preparing the above-mentioned packaging module. For example... Figures 3 to 7 As shown, the method includes: S1. Provide a green ceramic film tape, wires are laid on the green ceramic film tape, through holes are filled and grooves 2 are punched, and the tape is laminated to form a laminate.

[0048] According to the multilayer co-fired ceramic process, the cast green ceramic film is cut to the required size, and through-holes for interlayer interconnection are punched using a laser or mechanical punching machine. Then, a thick film printer is used to fill the through-holes with conductive pastes such as silver, copper, or tungsten, and print wiring patterns. For schemes using drain lead-out through-holes 13, drain lead-out through-holes 13 are also formed and filled in the pre-set green ceramic film, and drain lead-out pads 8 are formed on the top surface connected to the upper end of the drain lead-out through-holes 13. Then, grooves 2 for accommodating the chip are machined on the pre-set green ceramic film layer using punching or laser cutting processes. Finally, all green ceramic film layers are stacked under a precision alignment fixture and isostatically laminated into a single ceramic green body stack under certain temperature and pressure.

[0049] S2. Perform debinding and co-firing treatment on the laminated body to form a multi-layer co-fired ceramic co-fired body 1 with grooves 2.

[0050] In some embodiments, the debinding and co-firing process includes sequentially subjecting the laminate to a first heat treatment, a second heat treatment, and a third heat treatment; the temperature of the first heat treatment is 80°C to 120°C, and the time is 2 h to 4 h; the temperature of the second heat treatment is 250°C to 500°C, and the time is 2 h to 4 h; the temperature of the third heat treatment is 800°C to 1700°C, and the time is 4 h to 10 h.

[0051] The laminated body undergoes a slow heating process in the co-firing furnace. First, at a temperature of about 80℃ to 120℃, the organic binder in the green ceramic film is fully oxidized, decomposed, and discharged (binder removal). Then, it is sintered at peak temperatures of 250℃ to 500℃ and 800℃ to 1700℃ to form a dense multilayer co-fired ceramic body 1 containing pre-set grooves 2 and internal three-dimensional metallized wiring.

[0052] S3. Place the wide bandgap power chip 4 face down into the groove 2, and connect the front pads of the wide bandgap power chip 4 to the metallized pads 3 at the bottom of the groove 2.

[0053] In some embodiments, the front pads of the wide bandgap power chip 4 are connected to the metallized pads 3 at the bottom of the groove 2 by metal-based paste sintering or transient liquid phase bonding, with the metal-based paste sintering temperature being 200°C to 300°C and the pressure being 5MPa to 40MPa.

[0054] For example, after co-firing, a layer of nano-silver paste is applied to the metallized pads 3 at the bottom of the groove 2 by dispensing or stencil printing. Then, a high-precision pick-and-place machine is used to lift the chip face down and place it into the groove 2, applying pressure of tens of megapascals while heating to about 250°C. This causes the nano-silver particles to sinter and form the bonding layer 5 under solid-phase diffusion. This sintering temperature is much lower than the co-firing temperature and will not cause secondary damage to the already co-fired multilayer co-fired ceramic.

[0055] S4. Fill the groove 2 with filler adhesive 11 between the wide bandgap power chip 4 and the sidewall of the groove 2 and cure it.

[0056] In some embodiments, the filler 11 is applied by dispensing or vacuum injection, and the curing temperature is 80°C to 180°C for 10 min to 120 min.

[0057] After the wide bandgap power chip 4 is soldered, adhesive is applied along the edge of the wide bandgap power chip 4. Using capillary action, low-viscosity epoxy resin or silicone filler is allowed to penetrate and fill the tiny gap between the wide bandgap power chip 4 and the sidewall of the multilayer co-fired ceramic body 1. Then, it is heated and cured to firmly anchor the wide bandgap power chip 4.

[0058] S5. A copper seed layer 6 is sputtered and deposited on the bottom surface of the multilayer co-fired ceramic body 1 and the back surface of the wide bandgap power chip 4.

[0059] For example, the module with the chip mounted and glue filled and cured is placed with its bottom side facing up in a magnetron sputtering device. First, the surface is bombarded with an ion beam to remove oxides and contaminants. Then, argon ions are used to bombard the copper target, sputtering out copper atoms that are uniformly deposited on the entire bottom surface, forming a copper seed layer of about 1 μm thick with excellent adhesion.

[0060] In the embodiment where the thick copper layer 7 is directly conductive, S6, the thick copper layer 7 is grown by electroplating using the copper seed layer 6 as a seed, so that the copper seed layer 6 and the thick copper layer 7 are electrically connected.

[0061] For example, the module with the sputtered copper seed layer 6 is used as the cathode and immersed in a copper sulfate electroplating solution. Electroplating is carried out for a long time at an appropriate current density, so that copper ions are reduced on the surface of the copper seed layer 6 and gradually grow to a thickness of one hundred to several hundred micrometers, forming a solid thick copper layer 7.

[0062] For the scheme of heat dissipation by insulating thick copper and electrode lead-out via responsible for electrode lead-out, an insulating layer 12 is formed and patterned on the copper seed layer 6 by deposition, screen printing or surface mount process, and then a second copper seed layer 15 is sputtered and deposited on the insulating layer 12. The thick copper layer 7 is grown by electroplating with the second copper seed layer 15 as seed. At the same time, the lower end of the drain lead-out via 13 is connected to the copper seed layer 6 and the upper end is connected to the drain lead-out pad 8 on the top surface of the multilayer co-fired ceramic body 1. Thus, the drain lead-out via 13 undertakes the electrical lead-out of the back electrode of the wide bandgap power chip 4, and the thick copper layer 7 undertakes the heat dissipation function of connecting with the external heat dissipation structure.

[0063] The following specific examples provide further details.

[0064] Example 1 A 650 V / 60 A silicon carbide metal oxide semiconductor field-effect transistor half-bridge power module is prepared using a high thermal conductivity low-temperature co-fired ceramic dielectric with an out-of-plane thermal conductivity of approximately 20 W / (m·K), a dielectric loss tangent of approximately 0.0002, and a thermal expansion coefficient of approximately 10 ppm / K. The metal-based paste can be nano-silver paste.

[0065] Example 2 Commercially available low-temperature co-fired ceramic media with an out-of-plane thermal conductivity of approximately 4 W / (m·K), a dielectric loss tangent of approximately 0.0003, and a thermal expansion coefficient of approximately 4 ppm / K are used. The remaining structure and method are the same as in Example 1. Silver paste can be used as the metal-based slurry.

[0066] Comparative Example 1 A 650 V / 60 A silicon carbide metal oxide semiconductor field-effect transistor half-bridge power module of the same class was prepared by using the industry's mainstream traditional active metal brazing substrate with silver sintering positive mounting and aluminum lead bonding process.

[0067] Performance tests were conducted on Examples 1, 2, and Comparative Example 1, and the main results are shown in Table 1.

[0068] Table 1. Performance Test Comparison of Embodiments and Comparative Examples of this Application

[0069] As shown in Table 1, in Embodiments 1 and 2 of this application, the back of the power chip is directly connected to the external cold plate via a sputtered copper seed layer and an electroplated thick copper layer. The multilayer co-fired ceramic dielectric does not participate in the main heat dissipation path from the back of the chip to the cold plate. The junction-to-case thermal resistance is determined by the chip body, the copper seed layer, the thick copper layer, and the external interface, and is approximately 0.25 K / W to 0.28 K / W. In Comparative Example 1, the main heat dissipation path needs to pass through an active metal brazing substrate, a base plate, and a thermally conductive interface material to the cold plate, and the junction-to-case thermal resistance is typically approximately 0.40 K / W. The parasitic inductance of the circuit in Comparative Example 1 is determined by the length of the aluminum lead and the circuit area, which is typically 10 nH to 20 nH in the industry, with a median value of approximately 15 nH. In Embodiments 1 and 2 of this application, a groove flip-chip combined with a multilayer co-fired ceramic internal thick film trace is used, resulting in a smaller circuit area of ​​approximately 4.2 nH to 4.5 nH.

[0070] The above description is merely an exemplary embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the technical concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A wide bandgap power device integrated packaging module, characterized in that, include: A multi-layer co-fired ceramic body is formed by stacking and co-firing multiple layers of green ceramic film. The multi-layer co-fired ceramic body has a groove, and the bottom of the groove has a metallized pad. At least one wide bandgap power chip, the wide bandgap power chip has a chip front pad on its front side, the wide bandgap power chip is placed in the groove with its front side facing down, the front pad is connected to the metallization pad, and the back side of the wide bandgap power chip is flush with the bottom surface of the multilayer co-fired ceramic body; A bottom composite layer covering the back surface of the wide bandgap power chip and the bottom surface of the multilayer co-fired ceramic body, the bottom composite layer including a copper seed layer connected to the back electrode of the wide bandgap power chip and a thick copper layer located on the side of the copper seed layer opposite to the wide bandgap power chip, the thick copper layer forming a welding interface for connection with an external heat dissipation structure; and A back electrode lead-out structure connected to the copper seed layer for leading out the back electrode of the wide bandgap power chip, the back electrode lead-out structure including the thick copper layer or a drain lead-out via penetrating the multilayer co-fired ceramic body; When the back electrode lead-out structure includes the thick copper layer, the copper seed layer is electrically connected to the thick copper layer, and the thick copper layer serves as both the lead-out terminal of the back electrode of the wide bandgap power chip and the soldering interface for connection with the external heat dissipation structure. When the back electrode lead-out structure includes the drain lead-out via, an insulating layer and a second copper seed layer are sequentially provided between the copper seed layer and the thick copper layer. The thick copper layer is located on the side of the second copper seed layer away from the insulating layer and is electrically isolated from the copper seed layer. The lower end of the drain lead-out via is connected to the copper seed layer, and the upper end is connected to the drain lead-out pad on the top surface of the multilayer co-fired ceramic body.

2. The packaging module as described in claim 1, characterized in that, The multilayer co-fired ceramic includes low-temperature co-fired ceramic or high-temperature co-fired ceramic; The co-firing temperature of the low-temperature co-fired ceramic is 800℃~1000℃; The co-firing temperature of the high-temperature co-fired ceramic is 1400℃~1700℃; The out-of-plane thermal conductivity of the multilayer co-fired ceramic body is ≥10 W / (m·K), and the total number of layers is ≥20. The height difference between the back surface of the wide bandgap power chip and the bottom surface of the multilayer co-fired ceramic body does not exceed ±20 μm.

3. The packaging module as described in claim 1, characterized in that, The metallized pads are composed of co-fired thick film conductors, and the materials of the co-fired thick film conductors include at least one of silver-based, copper-based, tungsten-based, and molybdenum-based pastes; The wide bandgap power chip includes at least one of silicon carbide MOSFET, silicon carbide Schottky diode, and gallium nitride HEMT.

4. The packaging module as described in claim 1, characterized in that, The multilayer co-fired ceramic co-fired body has at least one decoupling capacitor or at least one gate drive inductor embedded in it, and is connected to the gate circuit or source circuit of the wide bandgap power chip through the internal wiring of the multilayer co-fired ceramic co-fired body.

5. The packaging module as described in claim 1, characterized in that, The back electrode lead-out structure includes the thick copper layer, the copper seed layer is electrically connected to the thick copper layer, and the thick copper layer serves as both the lead-out terminal of the back electrode of the wide bandgap power chip and the welding interface connected to the external heat dissipation structure; the copper seed layer is a copper layer formed by sputter deposition, and the thick copper layer is an electroplated copper layer formed by electroplating with the copper seed layer as the seed. The thickness of the copper seed layer is 0.3 μm to 2 μm; The thickness of the thick copper layer is 100 μm to 500 μm.

6. The packaging module as described in claim 1, characterized in that, The groove and the space between the wide bandgap power chip and the sidewall of the groove are filled with filler adhesive. The filler adhesive is used to fix the wide bandgap power chip, provide electrical insulation between the side of the wide bandgap power chip and the sidewall of the groove, and buffer thermal cycling stress. The filler adhesive includes at least one of epoxy resin filler adhesive, silicone filler adhesive, and high thermal conductivity filler adhesive; the filler adhesive is doped with thermally conductive filler, which includes at least one of alumina, boron nitride, aluminum nitride, and magnesium oxide.

7. The packaging module as described in claim 1, characterized in that, An insulating layer and a second copper seed layer are provided between the copper seed layer and the thick copper layer. The thick copper layer is disposed on the side of the second copper seed layer away from the insulating layer. The insulating layer is used to electrically isolate the back electrode of the wide bandgap power chip from the thick copper layer. The back electrode lead-out structure includes a drain lead-out via penetrating the multilayer co-fired ceramic body. The lower end of the drain lead-out via is connected to the copper seed layer, and the upper end is connected to the drain lead-out pad on the top surface of the multilayer co-fired ceramic body, so that the back electrode of the wide bandgap power chip is led out to the top surface of the multilayer co-fired ceramic body through the copper seed layer and the drain lead-out via. The insulating layer includes at least one of aluminum nitride ceramic dielectric layer, silicon nitride ceramic dielectric layer, alumina ceramic dielectric layer, polyimide high thermal conductivity insulating polymer layer containing ceramic filler, and epoxy resin high thermal conductivity insulating polymer layer containing ceramic filler, with a thickness of 5 μm to 100 μm.

8. The packaging module as described in claim 5 or 7, characterized in that, There are multiple grooves, and a wide bandgap power chip is placed in each groove. The multiple wide bandgap power chips are connected in parallel or in a bridge topology through the back electrode lead-out structure. When the back electrode lead-out structure is the copper seed layer and thick copper layer as described in claim 5, the back electrodes of at least two wide bandgap power chips are electrically connected through the copper seed layer and the thick copper layer to form a multi-chip parallel structure. When the back electrode lead-out structure is the drain lead-out via as described in claim 7, the back electrodes of each wide bandgap power chip are respectively led out through the corresponding drain lead-out via to the drain lead-out pad on the top surface of the multilayer co-fired ceramic co-fired body, and form a half-bridge, full-bridge, multi-level inverter bridge or modular multi-level converter sub-module topology through the internal wiring of the multilayer co-fired ceramic co-fired body.

9. A method for preparing a packaging module as described in any one of claims 1 to 8, characterized in that, include: S1. Provide a green ceramic film strip, wires are laid on the green ceramic film strip, through holes are filled and grooves are punched, and the strip is laminated to form a laminate. S2. Perform debinding and co-firing treatment on the laminated body to form a multi-layer co-fired ceramic co-fired body with grooves; S3. Place the wide bandgap power chip face down into the groove, and connect the front pads of the wide bandgap power chip to the metallized pads at the bottom of the groove. S4. Fill the groove with filler adhesive between the wide bandgap power chip and the sidewall of the groove and cure it. S5. A copper seed layer is sputtered and deposited on the bottom surface of the multilayer co-fired ceramic body and the back surface of the wide bandgap power chip. S6. When the back electrode lead-out structure includes the thick copper layer, the thick copper layer is grown by electroplating using the copper seed layer as a seed, so that the copper seed layer is electrically connected to the thick copper layer; when the back electrode lead-out structure includes a drain lead-out via, an insulating layer is formed and patterned on the copper seed layer, a second copper seed layer is sputtered and deposited on the insulating layer, the thick copper layer is grown by electroplating using the second copper seed layer as a seed, and the lower end of the drain lead-out via is connected to the copper seed layer.

10. The preparation method according to claim 9, characterized in that, In step S2, the debinding and co-firing process includes sequentially subjecting the laminate to a first heat treatment, a second heat treatment, and a third heat treatment; the first heat treatment is performed at a temperature of 80℃~120℃ for 2 h~4 h; the second heat treatment is performed at a temperature of 250℃~500℃ for 2 h~4 h; and the third heat treatment is performed at a temperature of 800℃~1700℃ for 4 h~10 h. In step S3, the front pad of the wide bandgap power chip is connected to the metallized pad at the bottom of the groove by sintering with a metal-based paste or by transient liquid phase bonding. The sintering temperature of the metal-based paste is 200℃~300℃ and the pressure is 5MPa~40MPa. In step S4, the filler adhesive is applied by dispensing or vacuum injection, and the curing temperature is 80℃~180℃, and the time is 10 min~120 min.

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