A board-level system-in-package structure and a preparation method thereof

Abstract

The application provides a board-level system-level package structure and a preparation method, which breaks through the heat dissipation bottleneck of the full plastic package structure, realizes physical isolation of power and signal loops, greatly reduces line parasitic parameters, significantly reduces the process cost of multi-layer integration while ensuring high integration, and adapts to large-size panel-level mass production requirements. It comprises: a high-thermal-conductivity copper plate layer; a high-power chip set comprising at least one high-power chip; a first plastic package layer; a first rewiring layer; and N groups of upper package units, N being a natural number greater than or equal to 1, N groups of adjacent upper package units being arranged in a stacked manner in the height direction, and each upper package unit comprising a plastic package layer, at least one small-power chip, and a rewiring layer, the rewiring layer of the upper package unit located on the top layer being a top-layer rewiring layer, and a plurality of tin balls being arranged on the top-layer rewiring layer.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor device packaging, specifically to a board-level system-in-package structure, and also provides a method for preparing the board-level system-in-package structure. Background Technology

[0002] With the increasing penetration of third-generation power semiconductors in new energy vehicles, photovoltaic inverters, and industrial power supplies, power system-in-package (PSP) is rapidly evolving towards 3D stacking and high power density. Panel-level fan-out (PLFO) packaging, with its inherent advantages of large substrate size and high area utilization, is gradually becoming a core technology for high-power heterogeneous integration. However, existing board-level multilayer stacked packaging still faces three major bottlenecks in engineering implementation, hindering its large-scale mass production application: 1. Heat dissipation is a significant bottleneck. Board-level fan-out packages generally employ a fully encapsulated embedded architecture, with the power chip completely encapsulated within the epoxy molding compound. Heat from the chip must be conducted outwards through a molding layer hundreds of micrometers thick. The steady-state thermal resistance of the package junction is generally higher than 2.5℃ / W, making it difficult to withstand the high heat flux density generated by high-power devices. Conventional external heat dissipation solutions require additional package volume, contradicting the design goal of high integration, and heat dissipation uniformity is even more difficult to control under large-size panels.

[0003] 2. Significant degradation in signal integrity and EMC performance. Traditional board-level power packages mostly adopt a side-by-side layout of chips on the same plane, with no physical isolation structure between power circuits and signal circuits. High-frequency switching noise from power chips can easily couple to small-signal control chips through the common ground plane and spatial radiation, causing control signal distortion. At the same time, in large-size board-level scenarios, the interconnection trace length between chips can reach the millimeter level, significantly increasing parasitic inductance and high-frequency switching losses, failing to fully unleash the high-frequency operating potential of third-generation semiconductors.

[0004] 3. Multilayer integration processes are costly and large-format board warpage control is challenging. Existing board-level 3D stacking solutions often directly adopt wafer-level TSV (Through Silicon Via) processes. On large-size panels, the process window for deep silicon etching and uniform electroplating is narrow, resulting in low yields and significantly increased equipment and process costs. Furthermore, the stress accumulation effect is more pronounced on large-format boards due to traditional one-time thick-layer injection molding processes, with warpage typically exceeding 1.5mm. This easily induces lithography misalignment, interconnect structure cracking, and other failure defects, further increasing mass production costs. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a board-level system-level packaging structure that overcomes the heat dissipation bottleneck of the all-molded architecture, achieves physical isolation between power and signal circuits, and significantly reduces parasitic parameters of the circuits. Furthermore, while ensuring high integration, it significantly reduces the process cost of multi-layer integration, making it suitable for the mass production needs of large-size panels.

[0006] A board-level system-in-package structure, characterized in that it includes: High thermal conductivity copper plate layer; A high-power chipset, which includes at least one high-power chip; First sealing layer; First wiring layer; And N groups of upper packaging units, where N is a natural number greater than or equal to 1. The N groups of adjacent upper packaging units are stacked in the height direction, and each upper packaging unit includes a molding layer, at least one low-power chip, and a redistribution layer. The redistribution layer of the upper packaging unit located at the top is the top redistribution layer, and a number of solder balls are disposed on the top redistribution layer. The high thermal conductivity copper plate layer, the first molding layer, the first redistribution layer, and N sets of upper packaging units are stacked sequentially from bottom to top. A high-power chip group is encapsulated in the first molding layer. The non-active side of each high-power chip is bonded to the high thermal conductivity copper plate layer, and the active side of each high-power chip faces upward.

[0007] Its further features are: When the thickness of the high-power chips is inconsistent, the height of the first molding layer is higher than the thickness of the highest high-power chip. The first molding layer has molded through holes with inconsistent heights. The molded through holes are filled to form corresponding conductive interconnect pillars. The lower end of each conductive interconnect pillar is electrically connected to the active surface pad of the corresponding high-power chip, and the upper end of each conductive interconnect pillar is electrically connected to the first redistribution layer. The high-power chip is a power or radio frequency semiconductor chip that performs the functions of power transmission and power conversion. It is suitable for high voltage, high current and high frequency operating conditions. The high-power chip includes power semiconductor chips such as SiC and GaN transistors and radio frequency semiconductor chips. The first wiring layer includes at least one layer of alternating metal circuit layer and insulating passivation layer, used to realize the lateral transmission of signals and electrical energy or the vertical conduction between layers; The non-active surface of the small signal chip in each upper packaging unit is bonded to the lower redistribution layer, and the active surface of the small signal chip is arranged facing upwards. The small signal chip is a digital or analog semiconductor chip that performs signal acquisition, logic operation, and data storage functions; Each upper-layer encapsulation unit also has electrical signal conductive interconnects on its plastic encapsulation layer, which transmit the electrical signals on the high-power chip layer by layer to the upper redistribution layer.

[0008] A method for fabricating a board-level system-level package structure is characterized by: after fabricating a high thermal conductivity copper plate layer that completely covers the fan-out structure, mounting the non-active surface of the corresponding high-power chip onto the high thermal conductivity copper plate layer, then completely covering the high-power chip with a first molding layer, obtaining molded through-holes for the corresponding high-power chip through external laser drilling, obtaining corresponding conductive interconnects within the molded through-holes, then fabricating a first redistribution layer on the top surface of the first molding layer to complete the signal fan-out of the high-power chip, sequentially completing the mounting of low-power chips in each of the N groups of upper-level packaging units, molding the molding layer, processing the corresponding electrical signal conductive interconnects in the molding layer, and processing the redistribution layer, then performing a back-end packaging process on the top redistribution layer, obtaining solder balls, and then performing board-level dicing to obtain a single independent finished packaged device.

[0009] Its further features are: Includes the following steps: S1 substrate preparation: A square temporary glass panel is selected as a temporary process carrier. A high thermal conductivity copper plate layer is laid on the entire surface of the square temporary glass panel through a temporary bonding adhesive layer. The copper plate is patterned using photolithography and wet etching processes to form a patterned high thermal conductivity copper plate layer that completely covers the dimensions of the fan-out structure. S2 high-power chip mounting uses a high thermal conductivity bonding adhesive layer to mount the non-active side of several high-power chips to a preset position on a high thermal conductivity copper plate layer. The S3 first molding layer is prepared by vacuum hot pressing to press a solid epoxy molding film, which is then cured at high temperature to form the first molding layer, achieving full encapsulation of the high-power chip. Then, the top surface of the first molding layer is ground and flattened using a chemical mechanical polishing process to achieve the preset thickness. The S4 lower conductive interconnect pillars were fabricated using an ultraviolet laser drilling process. Molded vias were fabricated at the locations of different high-power chips in the first molding layer. After preparing a Ti / Cu seed layer by physical vapor deposition, copper electroplating was used to fill the molded vias to form the corresponding conductive interconnect pillars. S5 First wiring layer fabrication: The first wiring layer is fabricated on the flattened top surface of the first molding layer to complete the signal fan-out of the power chip; the first wiring layer includes at least one layer of alternately stacked metal circuit layer and insulating passivation layer to realize the same-layer lateral transmission of signals and electrical energy or the inter-layer vertical conduction. S6 small signal chip mounting involves mounting the non-active side of the small signal chip in the first upper layer packaging unit at a preset position on the top surface of the first rewiring layer, with the active side of the chip facing upwards. The S7 second molding layer is prepared by vacuum hot pressing to press the second solid epoxy molding film, which, after curing, forms a second molding layer that completely encapsulates the small signal chip, thus achieving embedded encapsulation of the small signal chip; the top surface of the second molding layer is ground and planarized using a chemical mechanical polishing process to achieve the preset thickness. The S8 electrical signal conductive interconnect pillars are fabricated using an ultraviolet laser drilling process. Molded vias corresponding to the small signal chip are processed at preset positions in the second molding layer. After preparing a Ti / Cu seed layer by physical vapor deposition, copper electroplating is used to fill the molded vias to form the corresponding electrical signal conductive interconnect pillars, thereby leading out the electrical signals of the first redistribution layer. S9 second wiring layer fabrication: The second wiring layer is fabricated on the flattened top surface of the second molding layer to realize signal interconnection between high-power chips and small-signal chips and to bring out external signals from the package. S10 Prepare the corresponding upper-layer packaging unit layer by layer as needed, and repeat steps S6~S9 until the preparation of upper-layer packaging units of all layers is completed. The redistribution layer of the topmost upper-layer packaging unit is the top redistribution layer. The S11 back-end packaging process completes the fabrication of the insulating passivation layer of the top redistribution layer and the metal layer under the bumps; then the entire substrate is flipped over, and the square temporary glass panel is peeled off using a debonding process to remove the temporary bonding adhesive layer remaining on the surface; conductive solder balls are fabricated in the metal layer area under the bumps using a ball-planting process; finally, board-level cutting and slicing are performed to obtain individual finished packaged devices.

[0010] Its further characteristic is: In step S1, the temporary bonding adhesive layer is a high-temperature resistant UV bonding adhesive or a laser-dissociated bonding adhesive, which can withstand all subsequent high-temperature processes; the high thermal conductivity copper plate layer is an oxygen-free copper plate with a thickness of 100~250μm, which takes into account both process operability and heat dissipation performance. In step S2, the high thermal conductivity bonding adhesive layer is a high thermal conductivity permanent bonding adhesive with a thickness of 1~5μm; the thickness of all high power chips is 150~350μm, and the thickness difference of high power chips is ≤80μm. Excessive thickness difference can easily lead to poor molding or poor consistency of through-hole plating. In step S3, the vertical distance between the top surface of the first molding layer and the top active pad of the thickest high-power chip is 10~20μm, and in step S7, the vertical distance between the top surface of the second molding layer and the top active pad of the relatively thick small signal chip is 10~20μm, so as to avoid grinding damage to the active area of ​​the chip. In step S6, the thickness difference of all small signal chips is controlled within 10μm to ensure the consistency of the subsequent molding and through-hole fabrication processes. In step S10, during multi-layer stacking and packaging, the overall total thickness is controlled within 2.0 mm, and the cumulative total thickness of all molding layers is controlled within 1.5 mm; this thickness is combined with the rigid support of the bottom high thermal conductivity copper plate.

[0011] This invention effectively solves a series of technical problems in traditional wafer-level high-power chip fan-out packaging, such as weak heat dissipation, significant electromagnetic crosstalk between power and small-signal chips, long interlayer interconnect traces, high cost due to TSV process for multilayer stacking, large package warpage, high CMP processing volume, and low area utilization. This invention relies on a board-level vertical layered architecture with a high thermal conductivity copper plate layer to significantly optimize the heat dissipation conduction path, which can reduce the steady-state thermal resistance of the package junction to 0.8~1.2℃ / W, significantly reduce the chip operating temperature rise, and meet the application requirements of 200V / 10A level third-generation semiconductor devices. Furthermore, the vertical layered layout achieves physical isolation between power circuits and signal circuits. Combined with the TMV (molded via) vertical interconnect structure, the interconnect distance between chips can be shortened to 100~200μm, significantly reducing parasitic inductance and high-frequency switching losses. Signal integrity and EMC performance are effectively improved. Moreover, this invention does not require the use of TSV technology and can achieve multi-layer integration by relying on molded vias, which greatly reduces process costs. The layered molding combined with the rigid support of the copper plate can reduce the warpage of the large board by more than 30% compared with the traditional solution. The micro-CMP process also simplifies the production process. Furthermore, the overall architecture can be expanded to a multi-layer chip stack structure, which reduces the packaging footprint while improving system integration. It is also compatible with existing board-level mass production lines throughout the entire process, and has good industrial application value. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a specific embodiment of the present invention, and also a schematic diagram of step S11 of the preparation method; Figure 2 This is a schematic diagram of step S1 of the preparation method of the present invention; Figure 3 This is a schematic diagram of step S2 in the preparation method of the present invention: Figure 4 This is a schematic diagram of step S3 in the preparation method of the present invention; Figure 5 This is a schematic diagram of step S4 in the preparation method of the present invention; Figure 6 This is a schematic diagram of step S5 in the preparation method of the present invention; Figure 7 This is a schematic diagram of step S6 in the preparation method of the present invention; Figure 8 This is a schematic diagram of step S7 in the preparation method of the present invention; Figure 9This is a schematic diagram of step S8 in the preparation method of the present invention; Figure 10 This is a schematic diagram of step S9 in the preparation method of the present invention. Detailed Implementation

[0013] A board-level system-in-package structure, see Figure 1 It includes a high thermal conductivity copper plate layer 210, a first molding layer 400, a first redistribution layer 600, and N sets of upper-layer packaging units (N is a natural number greater than or equal to 1). A high-power chipset includes at least one high-power chip; N groups of adjacent upper packaging units are stacked in the height direction, and each upper packaging unit includes a molding layer, at least one low-power chip, and a redistribution layer. The redistribution layer of the upper packaging unit located at the top is called the top redistribution layer, and several solder balls are provided on the top redistribution layer. A high thermal conductivity copper plate layer 210, a first molding layer 400, a first redistribution layer 600, and N sets of upper packaging units are stacked sequentially from bottom to top. A high-power chipset is packaged inside the first molding layer 400. The non-active side of each high-power chip is bonded to the high thermal conductivity copper plate layer 210, and the active side of each high-power chip faces upward.

[0014] In practice, when the thickness of the high-power chips is inconsistent, the height of the first molding layer 400 is higher than the thickness of the highest high-power chip. Molded through holes with inconsistent heights are opened in the first molding layer 400. Corresponding conductive interconnect pillars are filled in the molded through holes. The lower end of each conductive interconnect pillar is electrically connected to the active surface pad of the corresponding high-power chip, and the upper end of each conductive interconnect pillar is electrically connected to the first redistribution layer 600.

[0015] In practice, high-power chips are power or radio frequency semiconductor chips that perform the functions of power transmission and power conversion. They are suitable for high voltage, high current and high frequency operating conditions. High-power chips include power semiconductor chips such as SiC and GaN transistors and radio frequency semiconductor chips. The first wiring layer 600 includes at least one layer of alternating metal circuit layers and insulating passivation layers for enabling lateral transmission of signals and electrical energy or longitudinal conduction between layers. The non-active surface of the small signal chip in each upper packaging unit is bonded to the lower redistribution layer, and the active surface of the small signal chip is set upwards. Small signal chips are digital or analog semiconductor chips that perform signal acquisition, logic operations, and data storage functions. Each upper-layer packaging unit also has electrical signal conductive interconnects on its plastic encapsulation layer, which transmit the electrical signals on the high-power chip layer by layer to the upper redistribution layer.

[0016] In a specific embodiment, N is set to 1, meaning that the board-level system-level packaging structure includes only one upper packaging unit. This upper packaging unit includes two small signal chips, a second molding layer 800, and a second redistribution layer 1000. The two small signal chips are specifically small signal chip a710 and small signal chip b720. The high-power chip group includes two high-power chips, namely high-power chip a310 and high-power chip b320.

[0017] The specific implementation method for fabricating the board-level system-level packaging structure is as follows, see below. Figures 1-10 : S1 substrate preparation, such as Figure 2 As shown, a square temporary glass panel 100 is selected as a temporary process carrier. A high thermal conductivity copper plate layer is laid on the entire surface of the square temporary glass panel 100 through a temporary bonding adhesive layer 110. The copper plate is patterned using a photolithography + wet etching process to form a patterned high thermal conductivity copper plate 210 that completely covers the dimensions of the fan-out structure. The square temporary glass panel 100 is a Gen1.5 glass substrate with a size of 510mm×515mm; the temporary bonding adhesive layer 110 is a high-temperature resistant UV bonding adhesive or laser-disintegrated bonding adhesive, which can withstand all subsequent high-temperature processes; the high thermal conductivity copper plate layer is an oxygen-free copper plate with a thickness of 100~250μm, which takes into account both process operability and heat dissipation performance. S2 high-power chip mounting, such as Figure 3 As shown, through the high thermal conductivity bonding adhesive layer 301, the non-active surfaces of two high-power chips a 310 (thicker) and b 320 (thinner) with different thicknesses and functions are fully mounted on the preset positions of the patterned high thermal conductivity copper plate 210. The high thermal conductivity bonding adhesive layer 301 is a high thermal conductivity permanent bonding adhesive with a thickness of 1~5μm; the thickness of the high power chip is preferably 150~350μm, and the thickness difference between two high power chips is preferably ≤80μm. If the thickness difference is too large, it will easily lead to poor molding or poor consistency of through-hole plating. S3 First Molding Layer Preparation, such as Figure 4 As shown, a solid epoxy molding film is pressed using a vacuum hot pressing process, and after high-temperature curing, a first molding layer 400 is formed, realizing the embedded full encapsulation of high-power chip a 310 and high-power chip b 320; the top surface of the first molding layer 400 is ground and planarized using a chemical mechanical polishing (CMP) process to achieve a preset thickness. The preset thickness is: the vertical spacing between the top surface of the first molding layer and the top active pad of the high-power chip a310 is 10~20μm to avoid grinding damage to the active area of ​​the chip; S4 conductive interconnect pillar fabrication, such as Figure 5As shown, using ultraviolet laser drilling technology, first molded through-hole TMV1 and second molded through-hole TMV2 are respectively processed at the positions of high-power chips with different thicknesses in the first molding layer 400. After preparing a Ti / Cu seed layer by physical vapor deposition (PVD), copper electroplating is used to fill the through-holes to form the first set of conductive interconnect pillars, including a first conductive interconnect pillar 510 with a larger depth and a second conductive interconnect pillar 520 with a smaller depth, which respectively lead out the electrical signals of high-power chip a310 and high-power chip b320. If the surface of the encapsulation layer is uneven after electroplating and filling, it can be flattened by fine grinding. S5 first redistribution layer fabrication, such as Figure 6 As shown, a first redistribution layer (RDL1) 600 is prepared on the flattened top surface of the first molding layer 400 to complete the signal fan-out of the power chip; the first redistribution layer 600 includes at least one layer of alternating metal circuit layer and insulating passivation layer to realize the same-layer lateral transmission of signals and electrical energy or the inter-layer vertical conduction. S6 small signal chip mounting, such as Figure 7 As shown, several small signal chips a 710 and small signal chips b 720 with similar thicknesses are mounted on the non-active surfaces of the chips at a preset position on the top surface of the first wiring layer 600, with the active surfaces of the chips facing upwards. The thickness difference between small signal chip a 710 and small signal chip b 720 is preferably controlled within 10μm to ensure the consistency of subsequent molding and via fabrication processes. S7 second molding layer preparation, such as Figure 8 As shown, a second solid epoxy molding film is pressed using a vacuum hot pressing process. After curing, it forms a second molding layer 800 that completely encapsulates the small signal chip, achieving embedded encapsulation of small signal chip a 710 and small signal chip b720. The top surface of the second molding layer 800 is planarized using a chemical mechanical polishing (CMP) process to achieve the preset thickness. The preset thickness is: the vertical spacing of the active pads on the top of the small signal chip a710 with a relatively thick plastic encapsulation layer is 10~20μm to avoid grinding damage to the active area of ​​the small signal chip; S8 third conductive interconnect pillar fabrication, such as Figure 9 As shown, a third molded via TMV3 is fabricated at a preset position in the second molding layer 800 using ultraviolet laser drilling technology; after preparing a Ti / Cu seed layer by physical vapor deposition (PVD), the via is filled by copper electroplating to form a third conductive interconnect pillar 900, which leads out the electrical signal of the first redistribution layer 600. If the surface of the encapsulation layer is uneven after electroplating and filling, it can be flattened by fine grinding. S9 second redistribution layer fabrication, such as Figure 10As shown, a second redistribution layer (RDL2) 1000 is prepared on the flattened top surface of the second molding layer 800 to realize signal interconnection between high-power chips and small-signal chips and to bring out external signals of the package. In this embodiment, the second redistribution layer 1000 is the top redistribution layer. S11 back-end packaging process, such as Figure 1 As shown, the top insulating passivation layer and under-bump metal layer (UBM) are prepared; the entire substrate is flipped over, and the square temporary glass panel 100 is peeled off by debonding process, and the temporary bonding adhesive layer 110 remaining on the surface is removed; conductive solder balls 1100 are prepared in the under-bump metal layer area by ball planting process; finally, board-level cutting and slicing are performed to obtain individual finished packaged devices.

[0018] This invention is not limited to the above-described two-layer chip packaging structure, and can be extended to a multi-layer stacked structure of three or more layers according to system integration requirements, as detailed below: Structural extension: Based on the above two-layer structure, at least one upper-layer packaging unit is stacked sequentially on the top surface of the second redistribution layer 1000; each upper-layer packaging unit includes a molding layer, a small signal chip, a molded via, and a redistribution layer stacked sequentially; adjacent upper-layer packaging units are electrically connected through the redistribution layer, and the topmost redistribution layer is used to complete the external signal output of all chips; Process extension: For fabrication methods of three or more layers, after completing the fabrication of the second wiring layer in step S9 above, repeat steps S6 to S9 to sequentially fabricate the 2nd, 3rd, ... Nth upper-layer packaging units; each repetition of steps S6 to S9 completes the embedded encapsulation and interconnection of a small-signal chip; after all upper-layer packaging units have been fabricated, the back-end packaging process of step S11 is then executed.

[0019] When multiple layers are stacked, the overall thickness of the encapsulation is controlled within 2.0mm, and the cumulative total thickness of all molding layers is controlled within 1.5mm. This thickness, combined with the rigid support of the bottom high thermal conductivity copper plate, can control the overall warpage of the 510×515mm large board after peeling off the square temporary glass panel 100 within 1000μm, meeting the processing requirements of subsequent precision processes and avoiding alignment deviations and yield losses caused by warpage.

[0020] The innovative aspects of this invention are as follows: A vertically layered isolation architecture places high-power chips at the bottom layer of the package, with small-signal chips stacked vertically on top, and physical isolation between the two types of chips is achieved through a molding compound. This architecture provides a structural basis for direct mounting of high-thermal-conductivity copper plates on the back of high-power chips, significantly shortening the heat dissipation path. Furthermore, it achieves spatial separation between power and signal circuits, effectively suppressing electromagnetic crosstalk. Simultaneously, vertical vias enable interconnection between chips, significantly shortening interconnection distances and reducing parasitic parameters in the circuitry.

[0021] The 2-chip direct-mount high-efficiency heat dissipation structure features a high thermal conductivity copper plate layer bonded to the entire non-active surface of the high-power chip, without any molding compound or insulating substrate obstructing the process. This creates an extremely short heat dissipation path within the embedded fan-out architecture, effectively improving the overall heat dissipation capacity of the package. Simultaneously, the high thermal conductivity copper plate layer possesses high structural rigidity, suppressing warpage and deformation during the packaging process.

[0022] The 3-differentiated TMV vertical interconnect solution uses differentiated molded vias (TMVs) of different heights to achieve vertical interconnection of multi-layer chips. It can achieve high-density vertical wiring without the need for TSV (Through Silicon Via) technology, and is fully compatible with conventional fan-out packaging technology, effectively reducing the process cost and complexity of multi-layer integration.

[0023] The 4-layer vacuum hot-press molding process uses a solid epoxy molding film for layered vacuum hot-press molding. Relying on the uniform flow characteristics of the solid molding film, a high-flatness surface can be formed after hot pressing. Only a small amount of chemical mechanical polishing (CMP) is required to meet the preparation requirements of the redistribution layer, reducing the processing time and cost of the CMP process, while avoiding stress concentration and warping problems caused by one-time thick-layer molding.

[0024] The five large-area board-level process substrates use large-area square glass panels as temporary process substrates, breaking through the size and area limitations of traditional round wafers, increasing the chip capacity per batch, and improving the substrate area utilization rate to over 95%, effectively reducing the packaging cost of a single chip.

[0025] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0026] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A board-level system-in-package structure, characterized in that, include: High thermal conductivity copper plate layer; A high-power chipset, including at least one high-power chip; First sealing layer; First wiring layer; And N groups of upper packaging units, where N is a natural number greater than or equal to 1. The N groups of adjacent upper packaging units are stacked in the height direction, and each upper packaging unit includes a molding layer, at least one low-power chip, and a redistribution layer. The redistribution layer of the upper packaging unit located at the top is the top redistribution layer, and a number of solder balls are disposed on the top redistribution layer. The high thermal conductivity copper plate layer, the first molding layer, the first redistribution layer, and N sets of upper packaging units are stacked sequentially from bottom to top. A high-power chip group is encapsulated in the first molding layer. The non-active side of each high-power chip is bonded to the high thermal conductivity copper plate layer, and the active side of each high-power chip faces upward.

2. The board-level system-level packaging structure according to claim 1, characterized in that: When the thickness of the high-power chips is inconsistent, the height of the first molding layer is higher than the thickness of the highest high-power chip. The first molding layer has molded through holes of inconsistent heights. The molded through holes are filled to form corresponding conductive interconnect pillars. The lower end of each conductive interconnect pillar is electrically connected to the active surface pad of the corresponding high-power chip, and the upper end of each conductive interconnect pillar is electrically connected to the first redistribution layer.

3. The board-level system-in-package structure according to claim 1, characterized in that: The high-power chip is a power or radio frequency semiconductor chip that performs power transmission and power conversion functions and is suitable for high voltage, high current and high frequency operating conditions. The high-power chip includes power semiconductor chips such as SiC and GaN transistors and radio frequency semiconductor chips.

4. The board-level system-level packaging structure according to claim 1, characterized in that: The first wiring layer includes at least one alternating layer of metal circuitry and insulating passivation layer, used to enable lateral transmission of signals and electrical energy or longitudinal conduction between layers.

5. A board-level system-level packaging structure according to claim 1, characterized in that: The non-active surface of the small signal chip in each upper packaging unit is bonded to the lower redistribution layer, and the active surface of the small signal chip is arranged facing upwards. The small signal chip is a digital or analog semiconductor chip that performs signal acquisition, logic operation, and data storage functions.

6. The board-level system-in-package structure according to claim 1, characterized in that: Each upper-layer encapsulation unit also has electrical signal conductive interconnects on its plastic encapsulation layer, which transmit the electrical signals on the high-power chip layer by layer to the upper redistribution layer.

7. A method for fabricating a board-level system-in-package (SiP) structure, used to fabricate a SiP structure as described in any one of claims 1 to 6, characterized in that: After fabricating a high thermal conductivity copper plate layer that completely covers the fan-out structure, the non-active surface of the corresponding high-power chip is mounted onto the high thermal conductivity copper plate layer. Then, the high-power chip is completely covered by the first molding layer. The corresponding molded through-hole of the high-power chip is obtained by external laser drilling. Then, the corresponding conductive interconnect pillar is obtained in the molded through-hole. Then, the first redistribution layer is fabricated on the top surface of the first molding layer to complete the signal fan-out of the high-power chip. The process is repeated in sequence: mounting the low-power chip in each of the N upper packaging units, molding the molding layer, processing the corresponding electrical signal conductive interconnect pillars of the molding layer, and processing the redistribution layer. Then, the top redistribution layer is processed by the back-end packaging process, and after obtaining solder balls, it is cut and diced at the board level to obtain a single independent finished packaged device.

8. The method for fabricating a board-level system-level packaging structure according to claim 7, characterized in that, Includes the following steps: S1 substrate preparation: A square temporary glass panel is selected as a temporary process carrier. A high thermal conductivity copper plate layer is laid on the entire surface of the square temporary glass panel through a temporary bonding adhesive layer. The copper plate is patterned using photolithography and wet etching processes to form a patterned high thermal conductivity copper plate layer that completely covers the dimensions of the fan-out structure. S2 high-power chip mounting uses a high thermal conductivity bonding adhesive layer to mount the non-active side of several high-power chips to a preset position on a high thermal conductivity copper plate layer. The S3 first molding layer is prepared by vacuum hot pressing to press a solid epoxy molding film, which is then cured at high temperature to form the first molding layer, achieving full encapsulation of the high-power chip. Then, the top surface of the first molding layer is ground and flattened using a chemical mechanical polishing process to achieve the preset thickness. The S4 lower conductive interconnect pillars were fabricated using an ultraviolet laser drilling process. Molded vias were fabricated at the locations of different high-power chips in the first molding layer. After preparing a Ti / Cu seed layer by physical vapor deposition, copper electroplating was used to fill the molded vias to form the corresponding conductive interconnect pillars. S5 First wiring layer fabrication: The first wiring layer is fabricated on the flattened top surface of the first molding layer to complete the signal fan-out of the power chip; the first wiring layer includes at least one layer of alternately stacked metal circuit layer and insulating passivation layer to realize the same-layer lateral transmission of signals and electrical energy or the inter-layer vertical conduction. S6 small signal chip mounting involves mounting the non-active side of the small signal chip in the first upper layer packaging unit at a preset position on the top surface of the first rewiring layer, with the active side of the chip facing upwards. The S7 second molding layer is prepared by vacuum hot pressing to press the second solid epoxy molding film, which, after curing, forms a second molding layer that completely encapsulates the small signal chip, thus achieving embedded encapsulation of the small signal chip; the top surface of the second molding layer is ground and planarized using a chemical mechanical polishing process to achieve the preset thickness. The S8 electrical signal conductive interconnect pillars are fabricated using an ultraviolet laser drilling process. Molded vias corresponding to the small signal chip are processed at preset positions in the second molding layer. After preparing a Ti / Cu seed layer by physical vapor deposition, copper electroplating is used to fill the molded vias to form the corresponding electrical signal conductive interconnect pillars, thereby leading out the electrical signals of the first redistribution layer. S9 second wiring layer fabrication: The second wiring layer is fabricated on the flattened top surface of the second molding layer to realize signal interconnection between high-power chips and small-signal chips and to bring out external signals from the package. S10 Prepare the corresponding upper-layer packaging unit layer by layer as needed, and repeat steps S6~S9 until the preparation of upper-layer packaging units of all layers is completed. The redistribution layer of the topmost upper-layer packaging unit is the top redistribution layer. The S11 back-end packaging process completes the fabrication of the insulating passivation layer of the top redistribution layer and the metal layer under the bumps; then the entire substrate is flipped over, and the square temporary glass panel is peeled off using a debonding process to remove the temporary bonding adhesive layer remaining on the surface; conductive solder balls are fabricated in the metal layer area under the bumps using a ball-planting process; finally, board-level cutting and slicing are performed to obtain individual finished packaged devices.

9. The method for fabricating a board-level system-level packaging structure according to claim 8, characterized in that: In step S1, the temporary bonding adhesive layer is a high-temperature resistant UV bonding adhesive or a laser-dissociated bonding adhesive, which can withstand all subsequent high-temperature processes; the high thermal conductivity copper plate layer is an oxygen-free copper plate with a thickness of 100~250μm, which takes into account both process operability and heat dissipation performance.

10. The method for fabricating a board-level system-level packaging structure according to claim 8, characterized in that: In step S10, during multi-layer stacking and packaging, the overall total thickness is controlled within 2.0 mm, and the cumulative total thickness of all molding layers is controlled within 1.5 mm; this thickness is combined with the rigid support of the bottom high thermal conductivity copper plate.

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