Processor with one or more progressive conservation execution modes

Abstract

Systems and methods related to a processor having one or more progressively conservative execution modes and an aggressive mode are disclosed herein. The aggressive execution mode makes a set of assumptions about a workload of the processor, while each conservative execution mode is based on a smaller set of assumptions than the aggressive mode. The conservative execution modes can be progressive, i.e., each progressive conservative execution mode is associated with a different number of assumptions. While operating in the aggressive mode, the processor can realize certain benefits in terms of execution speed or in terms of a reduction in resources required to execute the workload. While executing instructions in the aggressive execution mode, the processor can detect that a certain assumption is incorrect for at least one instruction, and can transition to a conservative execution mode (which can not make the assumption) to execute the instruction accordingly.

Description

Cross-references to related applications

[0001] This application claims the benefit of U.S. Patent Application No. 18 / 773,632, filed July 16, 2024, and U.S. Provisional Patent Application No. 63 / 569,035, filed March 22, 2024, the entire contents of which are incorporated herein by reference for all purposes. Background Technology

[0002] Designing a computer processor capable of efficiently handling a wide range of workloads inevitably requires incorporating diverse and often redundant resources—a practice that can be considered wasteful to some extent. The purpose of including these extra resources is to ensure adaptability and responsiveness to the evolving landscape of computing demands, thereby providing users with a general-purpose platform capable of effectively handling diverse tasks. Given the vast number of applications and tasks that modern computing systems must accommodate, processor architects strive to create general-purpose designs capable of efficiently executing a wide variety of instructions. Therefore, these processors may possess additional resources that are not frequently utilized, leading to performance degradation, increased power consumption, and higher manufacturing costs. The challenge lies in striking a balance between specialization for specific workloads and the need for a general-purpose architecture.

[0003] Processors conforming to the RISC-V standard, like any other general-purpose architecture, face the challenges of adapting to a wide range of workloads and the trade-offs outlined in the previous paragraph. RISC-V processors are designed based on the Reduced Instruction Set Computing (RISC) philosophy, pursuing simplicity and efficiency by employing a smaller set of instructions that executes within a single clock cycle. However, to handle a broad range of computational tasks, these processors may still incorporate additional resources despite their RISC-based foundation. The need to support diverse workloads and maintain compatibility with various software applications may lead to the inclusion of supplementary features that are not fully utilized in some cases, increasing the risk of waste in terms of power consumption and hardware complexity. Faced with an ever-expanding range of computational workloads, RISC-V designers continue to face the challenge of striking a delicate balance between the needs for simplicity and flexibility.

[0004] The above challenges are particularly pronounced for processors that need to meet standards set by external organizations (such as the RISC-V standard), as these standards are often written to support a wide range of computing tasks that go beyond those that are of interest to the designers of a particular processor. Summary of the Invention

[0005] This disclosure relates to systems and methods relating to a computer processor having one or more progressively conservative execution modes and an aggressive mode. The aggressive mode may make certain assumptions about the processor's workload. A first conservative mode may make fewer assumptions about the workload than the aggressive mode. A second conservative mode may make fewer assumptions about the workload than the first conservative mode (e.g., make no assumptions). By operating within the range of assumptions, the processor may be able to execute the workload faster or with fewer resources than if it were operating without any assumptions. The processor may switch to a conservative execution mode when it detects that the current execution mode cannot successfully execute an instruction. For example, when executing instructions of the processor's workload in the aggressive execution mode, the processor may detect that an assumption is incorrect for at least one instruction. In response to detecting that an incorrect assumption, the processor may switch to a conservative execution mode that does not make that incorrect assumption (e.g., the first conservative mode or the second conservative mode). The processor may then execute the instruction with appropriate assumptions in the conservative execution mode.

[0006] In a particular embodiment of the invention, the conservative execution mode can be progressive, meaning that whenever the processor detects that a hypothesis is incorrect, the processor can switch to a progressively conservative mode that makes fewer assumptions than the mode in which the processor was when it detected the incorrect hypothesis. As the number of assumptions decreases, the processor's efficiency is increasingly affected, so it is beneficial to continue executing instructions with as many assumptions as possible. Simultaneously, detecting an incorrect hypothesis, switching to a new mode, and executing instructions in that new mode all incur efficiency overhead. Therefore, the use of a progressively conservative mode provides the processor with greater flexibility to balance efficiency with the risk that instruction execution might invalidate a hypothesis and require a switch to a new mode to execute the instruction. In a particular embodiment where the processor is a standards-compliant processor, the conservative execution mode can be fully compliant with the standard and configured to execute any instructions or workload required by the specification.

[0007] In a particular embodiment of the invention, a method for executing instructions using a processor is provided. The method includes: extracting the instructions for execution in an aggressive mode, wherein the aggressive mode operates using one or more assumptions about the instructions; detecting that one of the one or more assumptions is incorrect by: (i) evaluating the instructions using decoding logic; and (ii) evaluating the state of the processor after executing the instructions in the aggressive mode; and in response to detecting that one of the one or more assumptions is incorrect: (i) canceling the execution of the instructions if the one or more assumptions are detected to be incorrect by evaluating the instructions using decoding logic; (ii) switching the processor to a conservative mode; and (iii) executing the instructions in the conservative mode; wherein the conservative mode operates without at least one of the one or more assumptions.

[0008] In a particular embodiment of the present invention, an apparatus is provided. The apparatus includes: one or more processors; and a non-transitory computer-readable medium storing instructions. When executed by the one or more processors, the non-transitory computer-readable medium causes the one or more processors to implement a method for executing instructions. The method includes: retrieving the instructions for execution in an aggressive mode, wherein the aggressive mode operates using one or more assumptions about the instructions; detecting that one of the one or more assumptions is incorrect by: (i) evaluating the instructions using decoding logic; and (ii) evaluating the state of the one or more processors after executing the instructions in the aggressive mode; and in response to detecting that one of the one or more assumptions is incorrect: (i) canceling the execution of the instructions if the one or more assumptions are detected to be incorrect by evaluating the instructions using decoding logic; (ii) causing the one or more processors to switch to a conservative mode; and (iii) executing the instructions in the conservative mode; wherein the conservative mode operates without at least one of the one or more assumptions.

[0009] In a particular embodiment of the invention, a method for executing instructions using one or more processors is provided. The method includes: extracting the instructions for execution in an aggressive mode, wherein the aggressive mode operates using a set of assumptions about the instructions; detecting that at least one first assumption in the set of assumptions is incorrect by at least one of: (i) evaluating the instructions before execution; (ii) evaluating the state of the one or more processors after partial execution of the instructions in the aggressive mode; and (iii) evaluating the state of the one or more processors after full execution of the instructions in the aggressive mode; causing the one or more processors to transition to a conservative mode, at least in part based on the detection that at least one first assumption in the set of assumptions is incorrect, wherein the conservative mode operates without at least one second assumption in the set of assumptions; and executing the instructions in the conservative mode, at least in part based on the transition of the one or more processors to the conservative mode. Attached Figure Description

[0010] The accompanying drawings illustrate various embodiments of the system, method, and various other aspects of this disclosure. Those skilled in the art will understand that the element boundaries (e.g., frames, groups of frames, or other shapes) shown in the drawings represent one example of a boundary. In some examples, one element may be designed as multiple elements, or multiple elements may be designed as one element. In some examples, an element shown as an internal component of one element may be implemented as an external component in another element, and vice versa. Furthermore, elements may not be drawn to scale. The following drawings are intended to describe a non-limiting and non-exhaustive illustration. The components in the drawings are not necessarily drawn to scale, but rather the focus is on illustrating principles.

[0011] Figure 1 Examples of systems having a processor that operates hypothetically, according to specific embodiments of the invention disclosed herein, are provided.

[0012] Figure 2 Examples of systems of hypotheses organized into radical and progressively conservative modes according to specific embodiments of the invention disclosed herein are provided.

[0013] Figure 3 Examples of flowcharts of processors using one or more progressive execution modes according to specific embodiments of the invention disclosed herein are provided.

[0014] Figure 4 An example of a processor that uses registers to execute instructions is provided.

[0015] Figure 5An example flowchart is provided for a processor in radical mode, according to a specific embodiment of the invention disclosed herein, assuming that registers will not be merged when updating registers.

[0016] Figure 6 An example flowchart is provided for a processor in aggressive mode, according to a specific implementation of the invention disclosed herein, assuming that the registers will not be updated based on the current architectural state.

[0017] Figure 7 An example flowchart is provided for a processor in aggressive mode, according to a specific embodiment of the invention disclosed herein, assuming that data from a given location will not change between multiple reads during out-of-order execution of instructions.

[0018] Figure 8 An example flowchart is provided for a processor in aggressive mode, according to a specific embodiment of the invention disclosed herein, assuming that vector load instructions or conditional load instructions will not access I / O memory. Detailed Implementation

[0019] Reference will now be made in detail to the various aspects and variations of the systems and methods described herein, as well as their implementations and methods. Although several exemplary variations of the systems and methods are described herein, other variations of the systems and methods may include aspects of the systems and methods described herein in any suitable combination, having combinations of all or some of the described aspects.

[0020] This disclosure describes in detail various systems and methods for processors having one or more progressively conservative execution modes, according to the foregoing invention. The methods and systems disclosed in this section are non-limiting embodiments of the invention, provided for illustrative purposes only, and should not be construed as limiting the full scope of the invention. It should be understood that the disclosed embodiments may or may not overlap. Thus, one embodiment, or a portion thereof, may fall within the scope of another embodiment, or not, or vice versa. Different embodiments from different aspects may be implemented in combination or individually. Many different combinations and sub-combinations of representative embodiments shown within the broad framework of the invention, while likely obvious to those skilled in the art, are not explicitly shown or described and should not be construed as excluded.

[0021] This document discloses systems and methods related to computer processors. In a particular embodiment, the processor includes one or more conservative execution modes. The one or more conservative execution modes may be conservative relative to an aggressive execution mode, which makes certain assumptions about the processor's workload. Based on these assumptions, the processor may achieve certain benefits in terms of execution speed or in terms of reducing the resources required to execute the workload. When executing instructions of the processor's workload in an aggressive execution mode, the processor may detect that an assumption is incorrect for at least one instruction. In response to detecting that an assumption is incorrect, the processor may switch to a conservative execution mode. The processor may then execute the instruction in the conservative execution mode that would have made the assumption incorrect in the aggressive execution mode.

[0022] Compared to an aggressive execution mode, a conservative execution mode can be based on a smaller set of assumptions about the processor's workload. In certain embodiments, the conservative execution mode may not make any assumptions about the processor's workload. In a particular embodiment where the processor is a standards-compliant processor, the conservative execution mode may be fully compliant with the standard and configured to execute any instructions or workload required by the specification. In certain embodiments, the conservative execution mode may make assumptions about the processor's workload, but fewer assumptions about the processor's workload than would be made in a mode where such assumptions are found to be incorrect.

[0023] In a particular embodiment of the invention, the conservative execution mode can be progressive, meaning that whenever the processor detects that a hypothesis is incorrect, the processor can switch to a progressively conservative mode that makes fewer assumptions than the mode in which the processor was when it detected the incorrect hypothesis. As the number of assumptions decreases, the processor's efficiency is increasingly affected, so it is beneficial to continue executing instructions with as many assumptions as possible. Simultaneously, detecting an incorrect hypothesis, switching to a new mode, and executing instructions in that new mode all incur efficiency overhead. Therefore, the use of a progressively conservative mode provides the processor with greater flexibility to balance efficiency with the risk that instruction execution might invalidate a hypothesis and necessitate a switch to a new mode to execute the instruction.

[0024] In certain implementations, the processor may switch to a conservative execution mode when it detects that the current execution mode has been executed incorrectly or will be executed incorrectly. For example, the processor may detect that a hypothesis will become incorrect due to the execution of an instruction (i.e., before the instruction is executed), or that a hypothesis has already become incorrect due to the execution of the instruction (i.e., after the instruction has been fully or partially executed). Detection of incorrect hypotheses may involve explicit detection of whether a hypothesis will be violated or has already been violated (e.g., by using logic circuitry specifically designed to throw a flag to indicate that a hypothesis has been violated). Detection of incorrect hypotheses may also involve implicit detection of whether a hypothesis has been violated (e.g., by using logic circuitry or debugging circuitry designed to detect errors in instruction execution or processor state, detecting that an error has occurred during the execution of the instruction).

[0025] In a particular implementation, the processor may switch to a conservative execution mode when it detects that an assumption of a previous execution mode has been violated. For example, the processor may determine that an assumption will become incorrect by analyzing the instructions (such as by using a decoder or dedicated logic circuitry assigned as an evaluation instruction or in conjunction with the processor's state evaluation instructions). As another example, the processor may determine that an assumption will become incorrect by detecting an error in instruction execution that indicates that an instruction is incorrect. In a particular implementation, the processor may switch to a conservative execution mode when an error is detected (i.e., the error does not indicate that a particular assumption is incorrect).

[0026] In a particular embodiment, the processor can detect both that an assumption has become or will become incorrect, and which assumption has become or will become incorrect. Alternatively, in a particular embodiment, the processor will only detect that an assumption has become or will become incorrect, but will not detect which assumption has become incorrect. The detected information can influence the actions taken by the processor in response to detecting that the assumption has become incorrect.

[0027] In a particular implementation, the processor may perform various operations in response to detecting that a hypothesis has become incorrect. If the instruction has been executed, the processor may modify its state such that the execution of the instruction is reversed (e.g., the execution of the instruction may be canceled, and the processor's state may be reset to its state just before the execution). In any case, the processor may switch to a conservative execution mode (i.e., from an aggressive mode to a conservative mode, or from a more aggressive conservative mode to a progressively conservative mode). If the processor detects that a hypothesis has been violated, the processor may switch to a conservative mode that does not make that particular hypothesis. However, the processor may also switch to a more conservative mode that does not make other hypotheses, in order to more definitively ensure that the execution of the instruction will not make any hypothesis incorrect and can continue without further interruption. If the processor does not detect that a hypothesis has been violated, the processor may switch to a conservative mode that does not make the hypothesis most likely to have become incorrect due to the execution, or a conservative mode that does not make the set of hypotheses most likely to have become incorrect due to the execution. However, the processor may also switch to a more conservative mode that does not make any hypotheses, in order to more definitively ensure that the execution of the instruction can continue without interruption. The processor can redo the instructions associated with the incorrect assumption.

[0028] Figure 1 An example of a system 100 having a processor 101 that operates on assumptions, as described herein, is shown. Processor 101 may fetch instructions 102. Processor 101 may execute instructions 102 using assumptions 110, 111, 112, 113, 114, and 115 to produce output 103. Processor 101 may detect that assumption 114 is incorrect (e.g., by detecting some occurrence or error). Processor 101 may be part of an apparatus or other system.

[0029] In a particular embodiment of the invention, processor 101 may first execute or attempt to execute instruction 102 in either an aggressive mode or a progressively conservative mode. Processor 101 may then detect that an assumption (e.g., assumption 114) is incorrect and may accordingly cancel the execution of instruction 102. Processor 101 may then initiate (e.g., switch to) a more conservative mode and restart or fetch the same instruction 102 again for execution in that more conservative mode.

[0030] In a particular embodiment of the invention, processor 101 may be configured to detect that a hypothesis (e.g., hypothesis 114) has been violated by detecting certain occurrences. While some of these occurrences are specifically related to RISC-V processor architectures (which may be RISC-V compatible), they are generally applicable to the processor unless otherwise stated. These occurrences include: processor 101 attempting to induce a fault or error on a load or store operation; speculatively resynchronizing the last micro-operation; attempting to perform speculative resynchronization up to the last micro-operation; attempting to perform a load / store operation on I / O (input / output) memory; executing a fault-only-first vector load instruction that updates the vector length (VL) register only when an anomaly is detected; performing an operation when the value in the VL register is equal to zero; performing an operation when the value in the Vstart register is not equal to zero; updating a specified configuration register; and many other potential occurrences in the processor architecture. As used herein, terms such as VL register and Vstart refer to their meaning within the RISC-V standard. Furthermore, an equation or literal expression declaring a register equal to a certain value means that the register holds data indicating that value. Based on one or more of these occurrences, processor 101 can determine that at least one hypothesis is incorrect.

[0031] In a particular embodiment, processor 101 may determine that one or more hypotheses are incorrect and may perform operations accordingly. For example, processor 101 may determine that one of hypotheses 110, 111, 112, 113, 114, or 115 is incorrect, without specifically determining which hypothesis is incorrect. In a particular embodiment, processor 101 may determine which hypothesis is incorrect. For example, processor 101 may determine that hypothesis 114 is specifically incorrect. Although hypothesis 114 is shown as incorrect in system 100, any hypothesis or combination of hypotheses (including more than one hypothesis) may be incorrect, depending on instruction 102, hypotheses 110 to 115, and system 100. In a particular embodiment, processor 101 may detect incorrect combinations of hypotheses 110 to 115.

[0032] In a particular embodiment, processor 101 may perform various operations in response to detecting that a hypothesis (e.g., hypothesis 114) has become incorrect. If instruction 102 has been executed to produce output 103, processor 101 may modify its state such that the execution of instruction 102 is reversed (e.g., the execution of instruction 102 can be cancelled, and the state of processor 101 can be reset to its state just before the execution), and output 103 can be discarded. In a particular embodiment, processor 101 may detect that a hypothesis is incorrect before instruction 102 is executed or after instruction 102 has been partially executed.

[0033] Whenever processor 101 detects that a hypothesis is incorrect, processor 101 may switch to a conservative execution mode (i.e., from an aggressive mode to a conservative mode, or from a more aggressive conservative mode to a progressively conservative mode). Processor 101 may re-fetch the instruction to attempt to execute it in the progressively conservative mode. If processor 101 detects that a hypothesis has been violated, processor 101 may switch to a conservative mode that does not make that particular incorrect hypothesis. In other specific examples, processor 101 may switch to a more conservative mode that does not make other hypotheses that may be incorrect based on that particular incorrect hypothesis. Processor 101 may switch to this more conservative mode to more definitively ensure that the execution of instruction 102 will not make any hypothesis (e.g., hypotheses 110 to 115) incorrect, and that execution will be able to continue without further interruption due to incorrect hypotheses. In other specific examples, processor 101 may switch to a conservative mode that does not make any hypothesis to more definitively ensure that the execution of instruction 102 will not make any hypothesis incorrect, and that execution will be able to continue without further interruption due to incorrect hypotheses.

[0034] If processor 101 does not detect any violation of assumptions 110 to 115, processor 101 may determine which assumption(s) are most likely to have become incorrect. Processor 101 may then switch to a conservative mode that does not make assumptions most likely to have become incorrect due to the execution. In a particular implementation, processor 101 may switch to a conservative mode that does not make any assumptions in order to more definitively guarantee that the execution of instruction 102 will proceed without being interrupted by incorrect assumptions.

[0035] In a particular implementation, processor 101 may have an architecture (e.g., having all the necessary hardware) capable of executing instruction 102 without any assumptions. Executing or attempting to execute instruction 102 in a first mode (e.g., aggressive mode) may use a set of hardware components of processor 101. Executing or attempting to execute instruction 102 in a second mode (e.g., conservative mode) may use a different set of hardware components, such as hardware components not used in the first mode. For example, processor 101 may have an architecture for efficiently executing instruction 102 in both a first mode (e.g., with assumptions) and a second mode (e.g., without assumptions).

[0036] In certain implementations, processor 101 may not have an architecture capable of readily executing instruction 102 without any assumptions. Executing or attempting to execute instruction 102 in a first mode (e.g., aggressive mode) may use the same set of hardware components that processor 101 uses to execute or attempt to execute instruction 102 in a second mode (e.g., conservative mode). The way processor 101 executes instruction 102 without the assumption (e.g., an incorrect assumption 114) may be more complex than the way processor 101 would execute instruction 102 if the assumption were correct. For example, system 100 may not include dedicated hardware for edge cases and may assume that the edge case will not occur. When generating one or more sequences of operations to execute instruction 102 in the first mode, an assumption (e.g., the edge case will not occur) may become incorrect. To execute instruction 102 without this assumption (e.g., to execute the edge case), processor 101 may switch to the second mode and insert additional operations to circumvent the lack of dedicated hardware, enforce instruction dependencies, or both. In systems that include dedicated hardware for handling edge cases, these additional operations may not be used. Processor 101 may not directly execute instruction 102, but instead generate, insert, and execute one or more sequences of operations (with or without enforced dependencies) that result in the same outcome as executing the original instruction 102, but require additional operations than directly executing instruction 102. In the second mode, compared to an architecture with a set of hardware components for the second mode, processor 101 may perform additional operations, use more power, and / or spend more time executing instruction 102. For example, processor 101 may have an architecture that efficiently executes instruction 102 in a first mode (e.g., with assumptions) but inefficiently executes instruction 102 in a second mode (e.g., without assumptions). The assumption that the conservative mode will not be used (and that some assumptions will be true) allows for a smaller hardware architecture that does not include special circuitry dedicated to handling edge cases. Without such special circuitry, the processor may be inefficient in handling edge cases. However, if edge cases are not expected to occur frequently (e.g., only during boot), the trade-off of speed for a few rare operations in exchange for smaller circuitry may be beneficial. Overall, by implementing a progressively conservative mode, the processor can strike a balance between the efficiency gained by making correct assumptions and the efficiency gained by avoiding incorrect assumptions.

[0037] Figure 2An example of a system 200 is shown where hypotheses 210 to 229 are organized into multiple modes including an aggressive mode 201 and progressively conservative modes 202, 203, 204, 205, 206, and 207. Different modes may correspond to different combinations of hypotheses 210 to 229. For example, aggressive mode 201 (e.g., aggressive execution mode) may make all hypotheses 210 to 229. Conservative modes 202 to 206 (e.g., conservative execution mode) may each make only some of the hypotheses 210 to 229. Conservative mode 207 may make no hypotheses at all. System 200 is merely one example of how different hypotheses are grouped into different modes. System 200 can be implemented with any number of hypotheses, any number of progressively conservative modes, and aggressive modes, which may group the hypotheses in ways not shown, and may not group the hypotheses in every way shown.

[0038] Aggressive mode 201 and conservative modes 202 to 207 may be implemented by one or more processors. Conservative modes 202 to 207 may be conservative relative to aggressive mode 201, which makes certain assumptions (e.g., assumptions 210 to 229) regarding the workload of the one or more processors. In a particular embodiment, conservative modes 202 to 206 may make assumptions regarding the workload of the one or more processors, but the number of assumptions made regarding the workload of the one or more processors may be fewer than in the mode in which the assumption is found to be incorrect. Based on these assumptions, the one or more processors may achieve certain benefits in terms of execution speed or in terms of reduced resources required to execute the workload. When executing instructions for the processor's workload in aggressive mode 201, the one or more processors may detect that an assumption is incorrect for at least one instruction. In response to detecting that an assumption is incorrect, the processor may switch to a conservative mode (e.g., one of conservative modes 202 to 207). The one or more processors may then execute in this conservative mode the instruction that would have made the assumption incorrect in aggressive mode 201.

[0039] Conservative modes 202 through 206 may overlap in their shared assumptions. Conservative mode 202 may make some of the assumptions made by radical mode 201, such as assumptions 215, 216, 217, 220, 221, and 222. Conservative mode 203 may make some of the assumptions made by radical mode 201, corresponding to those different from those made by conservative mode 202. For example, conservative mode 203 may make assumptions 223, 224, 228, and 229. Conservative mode 204 may overlap with conservative mode 204 in making assumption 217, while also making assumption 212, which is not made by conservative mode 202.

[0040] Conservative modes can be nested within each other. Conservative mode 205 may make some of the assumptions made by conservative mode 202, such as assumptions 221 and 222. Conservative mode 206 may make some of the assumptions made by conservative mode 205, such as assumption 222. In this way, conservative modes can progressively make fewer assumptions. Conservative mode 207 may make no assumptions. In a particular embodiment where the processor is a standards-compliant processor, conservative mode 207 may be fully compliant with the standard and configured to execute any instructions or workload required by the specification.

[0041] In certain embodiments of the invention, assumptions 210 to 229 made by radical mode 201 may relate to a specific instruction set architecture (ISA), wherein assumptions 210 to 229 refer to certain aspects of the ISA that will not be used. In these embodiments, one or more conservative modes 202 to 206 from the group of progressively conservative modes 202 to 207, or the most conservative mode 207, may fully conform to the ISA, while radical mode 201 may not. In certain embodiments, the ISA will be a RISC-V ISA or a RISC-V vector extension ISA. The one or more processors may be RISC-V ISA compatible.

[0042] Assumptions 210, 211, 213, 214, 218, 219, 225, 226, and 227 may be unique to radical mode 201. In certain embodiments, there may be more assumptions (not shown) in which radical mode 201 does not make those assumptions. Some conservative modes may make only one assumption. For example, conservative mode 206 may make only assumption 222.

[0043] Hypotheses within a conservative pattern can be organized according to the likelihood that they are true. For example, hypothesis 210 is likely to be incorrect more often than hypothesis 221, so there are fewer patterns that make hypothesis 210 (e.g., only radical pattern 201) than patterns that make hypothesis 221 (e.g., radical pattern 201, conservative pattern 202, and conservative pattern 205). Some hypotheses can be grouped together more often because of the likelihood that one hypothesis affects another. For example, if the incorrectness of hypothesis 223 means that hypothesis 224 is more likely to be incorrect, then both hypothesis 223 and hypothesis 224 can be grouped into the same pattern (e.g., conservative pattern 203). If the incorrectness of hypothesis 215 means that hypothesis 228 is more likely to be correct (and vice versa), then hypothesis 215 can belong to a different pattern than hypothesis 228 (e.g., conservative pattern 202 makes hypothesis 215 but not hypothesis 228, while conservative pattern 203 makes hypothesis 228 but not hypothesis 215).

[0044] In a particular implementation, when executing instructions of a workload for one or more processors in aggressive mode 201, the one or more processors may detect that assumption 210 is incorrect for at least one instruction. In response to detecting that assumption 210 is incorrect, the processor may transition to a conservative mode 202 that does not make assumption 210. The one or more processors may then execute the instruction in conservative mode 202. In a particular implementation, when executing the instruction (or a subsequent instruction in the processor's workload) in conservative mode 202, the one or more processors may detect that assumption 220 is incorrect for at least one instruction. In response to detecting that assumption 220 is incorrect, the processor may transition to a conservative mode 205 that does not make assumption 220. The one or more processors may then execute the instruction in conservative mode 205. The process of transitioning through progressively conservative modes continues as the processor executes or attempts to execute each instruction in the workload.

[0045] In a particular implementation, when executing instructions of a workload for one or more processors in aggressive mode 201, one or more processors may detect that assumption 221 is incorrect for at least one instruction. In response to detecting that assumption 221 is incorrect, the processor may switch to conservative mode 206 or conservative mode 203, which does not make assumption 221. The processor may avoid switching to conservative mode 202 or conservative mode 205, because both of these modes make assumption 221. The one or more processors may then execute the instruction in conservative mode 206 or conservative mode 203.

[0046] In a particular implementation, when executing instructions of a workload for one or more processors in aggressive mode 201, one or more processors may detect that a hypothesis is incorrect for at least one instruction, but may not detect which hypothesis is incorrect. In response to detecting that a hypothesis is incorrect, the processor evaluates which hypothesis is most likely to be incorrect (e.g., hypothesis 210) and may switch to a conservative mode (e.g., conservative mode 202) that does not make that hypothesis. The one or more processors may then execute the instruction in conservative mode.

[0047] In a particular implementation, when executing instructions of a workload for one or more processors in aggressive mode 201, one or more processors may detect that an assumption is incorrect for at least one instruction. In response to detecting that an assumption is incorrect, the processor may determine which assumption is incorrect, or may continue without knowing which specific assumption is incorrect. The processor may switch to conservative mode 207, making no assumptions. The processor may avoid switching to intermediate progressively conservative modes (e.g., conservative modes 202 to 206) to ensure that the processor can execute the instruction regardless of which assumption is incorrect, or which assumption in subsequent instructions of the workload might be incorrect (if any). The one or more processors may then execute the instruction in conservative mode 207.

[0048] In certain embodiments of the invention, the one or more processors may take various actions in a conservative mode (e.g., conservative modes 202 to 207) that might not be taken in an aggressive mode 201. These actions may reduce or eliminate the chance of errors occurring in response to specific types of instructions, or provide services or features that are not frequently used. These actions may be taken in response to determining that an assumption is incorrect, wherein the incorrect assumption is that the aforementioned specific type of instruction will not be executed, or that the aforementioned service or feature will not be used. Specific examples of these types of actions include: the one or more processors being placed in a state where they break all memory instructions into small fragments (e.g., the smallest possible fragments); the one or more processors being placed in a state where they force all memory instructions to be executed sequentially and do not allow out-of-order execution; the one or more processors being placed in a state where they can write to a processor state (e.g., a vector length register); and the one or more processors being placed in a state where they can merge old data with new data in a register file or configuration register. The one or more processors may also redo the instruction associated with the incorrect instruction, or reset the state of the one or more processors (e.g., reset to the state before the failed instruction).

[0049] Conservative modes (such as one of conservative modes 202 to 207) may also involve decoding logic that generates a sequence of operations to execute instructions that invalidate the hypothesis using the hardware available to the one or more processors. This may involve inserting additional operations or enforcing instruction dependencies so that the instruction is executed correctly regardless of the architecture state. In certain implementations, the efficiency of conservative modes 202 to 207 in executing instructions may be lower than that of an architecture specifically designed to handle instructions that invalidate the hypothesis. However, as long as the use of conservative modes is relatively limited, the reduction in efficiency of conservative modes will be offset by the lower resource consumption and higher efficiency of aggressive mode 201.

[0050] Conservative modes 202 through 207 may differ from aggressive mode 201 in various ways, and are distinct from each other. Each conservative mode may employ various methods to avoid errors. For example, a first conservative mode may break memory instructions into the smallest possible segments, force all memory instructions to be executed sequentially rather than allowing out-of-order execution, and allow certain instructions to update a processor state (e.g., the vector length register) only in conservative mode. A second conservative mode may use different combinations of these methods. A third conservative mode may use methods not employed by the first conservative mode. A fourth conservative mode may use a combination of methods employed by the first conservative mode and methods not employed by the first conservative mode.

[0051] In a particular implementation, aggressive mode 201 (and one or more conservative modes 202 to 206) may make one or more of the following assumptions: instruction execution will not involve detecting any anomalies, instruction execution will not access I / O memory, instructions will not be executed if the value in the VL register is zero, instructions will not be executed if the value in the Vstart register is non-zero, and instructions will not cause read-after-read ordering violations. Using this approach, aggressive mode 201 can operate more efficiently, for example by bypassing hold settings for waiting for merge operations described with reference to the above figures, out-of-order execution of vector aggregation operations, and assuming certain registers have predetermined values ​​(e.g., Vstart register is 0) to avoid the need to check these values, etc.

[0052] Figure 3 A flowchart 300 illustrates the operation of a processor (or more than one processor) using one or more progressively conservative execution modes according to a specific embodiment of the invention disclosed herein.

[0053] At 301, the processor can operate in a certain mode. This mode can be an aggressive mode (e.g., aggressive mode 201) or a conservative mode (e.g., conservative modes 202 to 207). The processor may have successfully executed an instruction or a set of instructions in this mode, or it may have switched to this mode due to failure to execute an instruction (e.g., conservative modes 202 to 207), or it may have switched to this mode due to successful execution of an instruction (e.g., aggressive mode 201 or conservative modes 202 to 206).

[0054] At 302, the processor can fetch instructions. These instructions may be part of the processor's workload and may be part of a set of instructions. The instructions may be normal or common instructions, or may include edge case scenarios. The workload may be a typical workload or a workload that the processor does not frequently utilize (or is not expected to utilize frequently).

[0055] At 303, the processor can detect whether all the assumptions of the mode are correct. The processor can determine that only one assumption is incorrect, or it can determine which of a set of assumptions made by the mode is incorrect. There may be more than one incorrect assumption. The processor can determine that an assumption is incorrect before, after partial, or after full execution of the instruction. If one or more assumptions are incorrect, the processor can switch to a more conservative mode at 304. If all the assumptions of the mode are correct, the processor can successfully execute the instruction at 305.

[0056] In certain implementations, assumptions may include: instruction execution will not involve detecting any anomalies, instruction execution will not access I / O memory, instructions will not be executed if the value in the VL register is zero, instructions will not be executed if the value in the Vstart register is non-zero, and instructions will not cause read-after-read ordering violations. In certain implementations, assumptions may include that specific types of instructions will not be executed (e.g., certain portions of the ISA will not be used), such as instructions involving partial updates to the vector register file, instructions that restore using the value in Vstart, and instructions that load only the first fault vector. If these assumptions are correct, the aggressive mode (and one or more progressively conservative modes that make the relevant assumptions) will be able to operate more efficiently, for example by bypassing hold settings for waiting for merge operations described with reference to the above figures, out-of-order execution of vector aggregation operations, and assuming certain registers have predetermined values ​​(e.g., Vstart register is 0) to avoid needing to check these values, etc.

[0057] In a particular implementation, at point 303, the processor may detect that the current execution mode has incorrectly executed or will incorrectly execute the instruction. For example, the processor may detect that a hypothesis will become incorrect due to the execution of the instruction (i.e., before the instruction is executed), or that a hypothesis has already become incorrect due to the execution of the instruction (i.e., after the instruction has been fully or partially executed). Detection of incorrect hypotheses may involve explicit detection of whether a hypothesis will be violated or has already been violated (e.g., by using logic circuitry specifically designed to throw a flag to indicate that a hypothesis has been violated). Detection of incorrect hypotheses may also involve implicit detection of whether a hypothesis has been violated (e.g., by using logic circuitry or debugging circuitry designed to detect errors in instruction execution or processor state, detecting that an error has occurred during the execution of the instruction).

[0058] In a particular implementation, at point 303, the processor may detect that an assumption of a previous execution mode has been violated. For example, the processor may determine that an assumption will become incorrect by analyzing the instructions (such as by using a decoder or dedicated logic circuitry assigned as an evaluation instruction or in conjunction with the processor's state evaluation instructions). As another example, the processor may determine that an assumption will become incorrect by detecting an error in instruction execution that indicates that an instruction has become incorrect. In a particular implementation, the processor may detect an error that does not indicate which specific assumption made by the processor is incorrect.

[0059] In a particular embodiment, at 303, the processor can detect both that an assumption has become or will become incorrect, and which assumption has become or will become incorrect. Alternatively, in a particular embodiment, the processor may only detect that an assumption has become or will become incorrect, but not which assumption has become incorrect. The detected information can influence the actions taken by the processor in response to detecting that the assumption has become incorrect (e.g., which conservative mode the processor transitions to at 304).

[0060] In certain embodiments of the invention, the processor may be configured to detect a violation of a hypothesis by detecting certain occurrences. While some of these occurrences are specific to the RISC-V processor architecture, they are generally applicable to the processor unless otherwise stated. These occurrences include: the processor attempting to induce a fault or error on a load or store operation; speculatively resynchronizing the last micro-operation; attempting speculative resynchronization up to the last micro-operation; attempting to perform a load / store operation on I / O memory; executing a first-fault vector-only load instruction that only requires updating the vector length (VL) register if an anomaly is detected; performing an operation with the value in the VL register equal to zero; performing an operation with the value in the Vstart register not equal to zero; updating a specified configuration register; and many other potential occurrences in the processor architecture.

[0061] At point 304, the processor may switch to a more conservative mode. The processor may re-fetch the instruction for execution in this conservative mode. Once in the more conservative mode, the processor may check at point 303 whether all assumptions of this more conservative mode are correct. If at point 303, at least one of the assumptions of the more conservative mode is still incorrect, the processor may switch to an even more conservative mode at point 304. This process can continue until all assumptions of the current mode are correct, in which case the processor can successfully execute the instruction at point 305.

[0062] In certain embodiments of the invention, there are more than one conservative mode. Each conservative mode can be progressive, meaning that whenever the processor detects that a hypothesis is incorrect, the processor can switch to a progressively conservative mode (e.g., at 304), which makes fewer assumptions than the mode in which the processor detected the incorrect hypothesis (e.g., at 303). As the number of hypotheses decreases, the processor's efficiency is increasingly affected, so it is beneficial to continue executing instructions with as many hypotheses as possible. Meanwhile, detecting an incorrect hypothesis (e.g., at 303), switching to a new mode (e.g., at 304), and executing or attempting to execute instructions in that new mode all incur efficiency overhead. Therefore, the use of progressively conservative modes provides the processor with greater flexibility to balance efficiency with the risk that instruction execution will render a hypothesis incorrect and require switching to a new mode to execute the instruction.

[0063] In a particular implementation, the processor may take various actions in response to detecting that a hypothesis has become incorrect. If the instruction has been executed, the processor may modify its state such that the execution of the instruction is reversed (e.g., the execution of the instruction may be canceled, and the processor's state may be reset to its state just before the execution). In any case, the processor may transition to a conservative execution mode at 304 (i.e., from an aggressive mode to a conservative mode, or from a more aggressive conservative mode to a progressively conservative mode). If the processor detects that a hypothesis has been violated, the processor may transition to a conservative mode that does not make that particular hypothesis. However, the processor may also transition to a more conservative mode that does not make other hypotheses, in order to more definitively ensure that the execution of the instruction will not make any hypothesis incorrect and that execution can continue without further interruption. If the processor does not detect that a hypothesis has been violated, the processor may transition to a conservative mode that does not make the hypothesis most likely to have become incorrect due to the execution, or a conservative mode that does not make a set of hypotheses most likely to have become incorrect due to the execution. However, the processor may also switch to a more conservative mode that makes no assumptions in order to more definitively guarantee that the execution of instructions can proceed successfully without interruption (e.g., looping around 303 and 304 again) (e.g., at 305).

[0064] After successfully executing the instruction at point 305, the processor can perform various operations. After executing the instruction in conservative mode, the processor can return to a more aggressive (e.g., less conservative) mode. For a processor with a progressively conservative mode, the processor can gradually return to an aggressive execution mode through a progressively (gradually weakening) conservative mode, and wait for one or more instructions to be correctly (e.g., successfully) executed before taking the next step toward a more aggressive mode (e.g., transitioning to a less conservative / more aggressive mode). In implementations where the same instruction causes the processor to gradually pass through multiple progressively conservative modes, the steps back to the aggressive execution mode can follow the same pattern in reverse order because the same instruction is found to invalidate numerous assumptions. Alternatively, for a processor with a progressively conservative mode, the processor can return to the most aggressive execution mode immediately after executing the instruction, or it can wait for one or more additional instructions to be correctly executed before returning to the most aggressive execution mode.

[0065] Figure 4 An example is shown where a processor executes an instruction using register 403, and an exception 404 occurs midway through the execution of that instruction. The processor may have made the assumption that exception 404 will not occur midway through the execution of the instruction, and that the processor will not resume the interrupted instruction execution. This assumption may be made as part of an aggressive mode or a conservative mode that makes the assumption. In a particular embodiment of the invention, the assumption made by the aggressive mode relates to a specific ISA, meaning that certain aspects of that ISA will not be used. In these embodiments, a conservative mode or the most conservative mode (e.g., a mode that makes no assumptions) from a set of progressively conservative modes may fully conform to the ISA, while the aggressive mode may not. In a particular embodiment, the ISA will be a RISC-V ISA or a RISC-V Vector Extension ISA.

[0066] In a particular implementation, the processor assumes that no exceptions or interrupts will occur during instruction execution. In another implementation, if an exception or interrupt is observed midway through instruction execution, the ISA may require a partial update to the architectural state (e.g., an update to the vector register file). For example, when performing a vector load operation on a 256-bit vector instruction, typical execution requires a complete update of the entire 256-bit entry (i.e., bits [255:0] are updated). However, if an exception is detected midway through the instruction, the processor is expected to update only a subset of the entry (e.g., only bits [95:0] are updated, while bits [255:96] retain their old values). This functionality, according to this example, is required by the RISC-V Vector Extension ISA. In a particular implementation (e.g., in the aggressive mode described above), the processor will assume that this functionality is not required.

[0067] In a particular implementation, the processor assumes it will not resume the instruction midway through execution. In a particular implementation, the ISA may require the resumption of the instruction midway through execution. This functionality may require the use of a special-purpose register, which may be referred to as the Vstart register. Consistent with the aforementioned example where instruction execution stops after updating only a subset of the entry, the special-purpose register used for this functionality (e.g., the Vstart register in a RISC-V Vector Extension ISA) may record the state of a previous instruction (e.g., bits [95:0] were previously updated), and the resumption of the previously canceled instruction may utilize the information in this register to update only the remainder of the entry (i.e., only bits [255:96]). The functionality according to this example is required by the RISC-V Vector Extension ISA. In a particular implementation (e.g., in the aggressive mode described above), the processor will assume that this functionality is not required.

[0068] In a particular implementation, the processor may assume that it will not receive a first-fault-only vector load instruction. In a particular implementation, the ISA may require the execution of a special instruction, which may be referred to as a first-fault-only vector load instruction. This functionality can be used to load registers in a specific manner, in which, when a fault is detected midway through register loading, the processor will partially update the register up to the fault location (e.g., [63:0] of the register is updated, but not [256:0]), and the special register will be updated at that fault location (e.g., the register will store the bit that identifies 64 as the fault location). This special register may be referred to as the VL register. The functionality according to this example is required by the RISC-V Vector Extension ISA. In a particular implementation (e.g., in the radical mode described above), the processor will assume that this functionality is not required.

[0069] The ISA's functions of pausing instruction execution, resuming instruction execution, and executing a first-fault vector-only load instruction upon detecting an anomaly can be implemented using three registers and logic for performing the merge operation. Detecting an anomaly and executing the first-fault vector-only load instruction can be considered as occurrences. An anomaly 404 may occur while loading a vector into register 402. This anomaly (e.g., occurrence) can trigger partial updates to certain registers. For example, to perform partial updates to certain registers, the processor may retrieve a value from one register (e.g., register 402) (e.g., updated value 406) and combine that value with an old value from another register (e.g., register 401) (e.g., old value 405) to form the final merged value in a new register (e.g., register 403).

[0070] An anomaly detection and execution of the first-failure-only vector load instruction can be considered an occurrence. As long as the functionality associated with this occurrence (e.g., pausing instruction execution upon an anomaly detection, resuming instruction execution, and executing the first-failure-only vector load instruction) is not required, the vector load operation will only need to generate the updated value 406 (e.g., from register 402). Therefore, the processor operating in this aggressive mode is more efficient because subsequent operations do not need to wait for the generation of the merged value (as the processor would do if it operated without these assumptions). Thus, the aggressive mode, assuming the aforementioned functionality is not required (and the occurrence does not occur), improves the processor's efficiency.

[0071] In a particular implementation, the processor may operate in an aggressive mode that assumes the vector instruction will always be executed with Vstart equal to zero, and the processor will detect that the execution of the instruction necessarily requires Vstart to be non-zero. For example, the processor may be performing a vector load operation using the following code: VLD, v10, [X] (ignoring Vstart or assuming Vstart = 0). VLD is the instruction identifier, v10 is the destination register, [X] is the data to be loaded from memory, and because it is in aggressive mode, the instruction ignores Vstart or assumes Vstart is zero. If this assumption is detected to be false, the processor may enter a conservative mode. The decoder may then insert additional operations to execute the instruction differently. The code for these instructions may be VLD, Vtemp, [X] (masked by Vstart) and VMERGE v10, Vtemp, v10. Vtemp is a temporary register loaded with the value of X, which is masked up to Vstart. VMERGE is the instruction identifier for merging the values ​​of v10 and Vtemp into register v10. Once the instruction has been executed accordingly in the conservative mode, the processor can return to the aggressive mode.

[0072] In a particular implementation, the processor can operate in an aggressive mode that assumes the instruction will not be executed if a fault occurs during instruction execution, and that the processor will detect that the instruction's execution must be completed without detecting a fault at location Y. For example, the processor can execute the instruction VLD.FF, v10, [X] in aggressive mode, where VLD.FF is a first-fault vector load instruction only. Therefore, the processor will enter a conservative mode and generate additional operations to execute the instruction. These additional operations could be VSETVLI, VL, Y (Y: fault location) and VLD, v10, [X]. VSETVLI is an instruction identified by setting the vector length register to the value Y, where Y is the fault location, and after this value is set, a vector load operation to register v10 will load the value X into register v10. This sequence allows the processor to safely execute vector operations up to the fault location without detecting a fault. Once the instruction has been executed accordingly in the conservative mode, the processor can return to the aggressive mode.

[0073] Figure 5 An example flowchart 500 is shown, illustrating a processor in aggressive mode assuming that registers will not be merged when updating them. Flowchart 500 can also be executed by multiple processors working in cooperation. At 501, the processor may update the registers (e.g., as part of an instruction).

[0074] At 502, the processor may wait for multiple register merging in case of an anomaly or condition occurring while the register is being updated at 501. The ISA's functions of pausing instruction execution, resuming instruction execution, and executing a first-fault vector-only load instruction upon detecting an anomaly can be implemented using multiple registers and logic for performing the merging operation. Detecting an anomaly and executing a first-fault vector-only load instruction can each be considered as an occurrence. If an occurrence occurs, the processor may wait for register merging before marking a process (e.g., a vector-loading task) as complete. In conservative mode, the processor may wait for a period of time associated with merging registers, regardless of whether an occurrence triggers a separate vector merging.

[0075] At 503, the processor may mark the process of updating the register as complete. In the aggressive mode, the processor may skip 502 and proceed from 501 to 503. For example, the processor may assume that multiple registers do not need to be merged (e.g., because the processor assumes that no exception or situation will occur) and may not wait for the period of time associated with merging multiple registers before marking the process as complete.

[0076] An anomaly detection and execution of the first-fault-only vector load instruction can be considered an occurrence. As long as the functionality associated with this occurrence (e.g., pausing instruction execution upon an anomaly detection, resuming instruction execution, and executing the first-fault-only vector load instruction) is not required, the vector load operation will not need to wait for multiple register merging. Therefore, the processor operating in this aggressive mode is more efficient because subsequent operations do not need to wait for the generation of merged values ​​(as the processor would do in conservative mode without these assumptions). Thus, the aggressive mode, assuming the aforementioned functionality is not required (and the occurrence does not occur), improves the processor's efficiency.

[0077] In a particular implementation, the processor may determine that an instruction will require an exception or a value of zero in the VL register. In response, the processor may implement a conservative mode that preserves the aforementioned merge operation. Once the instruction has been executed accordingly in the conservative mode, the processor may return to the aggressive mode.

[0078] Figure 6 An example of flowchart 600 is shown where a processor in aggressive mode assumes that a register will not be updated based on the current architecture state. In other words, a processor in aggressive mode may update the register regardless of the current architecture state (not based on the current architecture state). In a particular implementation, the ISA may require conditionally not updating a register (e.g., a vector register) based on the current architecture state (e.g., stored in an architecture register or VL register). The architecture state can be set by having a specific value in a particular register. For example, the register may be an architecture register that can be called a VL register, and the value used to set the condition may be zero. The functionality according to this example is required by the RISC-V Vector Extension ISA. In a particular implementation, aggressive mode will assume that this functionality is not needed. For example, the processor may avoid checking the value in the architecture register corresponding to the current architecture state because the processor has already assumed that the register will be updated based on the instruction. In other words, the processor may avoid checking the value in the architecture register because the processor assumes that the current state of the architecture updates the register based on the instruction, rather than, for example, maintaining the register's previous value.

[0079] At point 601, the processor may receive an instruction to update a first (e.g., vector, v1) register. For example, this update may be part of a VADD instruction (v1 <= v2 + v3) that assigns a new physical register and gives the new first register (e.g., register v1) the value generated from that instruction (e.g., v2 + v3). In a particular implementation, the current value of the first register (e.g., a first value of the first register) does not affect the generated value (e.g., a second value of the first register, i.e., the value generated by the instruction).

[0080] In conservative mode, at position 602, the processor may check the value of a second (e.g., architecture, VL) register to obtain update conditions. The value of the second register may indicate whether to update the first (e.g., vector) register according to the received instruction. For example, if the value of the second register is zero, the first register may retain its first value instead of retaining the second value generated from that instruction (e.g., the result of v2 + v3).

[0081] At 603, the processor may update the first register. In the aggressive mode, the processor may assume that the value of the second register indicates an update to the first register based on the instruction received at 601, without actually checking the second register (e.g., the aggressive mode skips 602). The aggressive mode may not reference (e.g., avoid checking) the value of the first register before it is updated. If, in the conservative mode, the processor checks the second register to obtain an update condition (at 602), and that value indicates an update to the first register based on the received instruction (e.g., the value of the second register is not zero), then the first register may be updated according to the received instruction. If, in the conservative mode, the processor checks the second register to obtain an update condition (at 602), and that value indicates avoiding an update to the first register based on the received instruction (e.g., the value of the second register is zero), then the processor may avoid updating the first register according to the received instruction, instead retaining the value previously stored in the first register, even if the received instruction is executed. For example, the value of the first register before receiving the instruction to update the register (before 601) may be the same as its value after being updated (at 603).

[0082] In a particular implementation, the processor may determine that an instruction will require an exception or a value of zero in the VL register. In response, the processor may implement a conservative mode that checks the VL register to obtain the update condition. Once the instruction has been executed accordingly in the conservative mode, the processor may return to the aggressive mode.

[0083] In a particular implementation, the aggressive mode may allow instruction reordering or parallel processing. For example, the processor may receive four instructions: a first instruction VADD v1 <= v2 + v3, a second instruction VST v1 => [x10 + 0], a third instruction VSUB v1 <= v4 - v5, and a fourth instruction VST v1 => [x10 + 32]. In this example, the first instruction VADD and the third instruction VSUB are independent. However, in the conservative mode, the processor may wait until the first instruction VADD completes before executing the third instruction VSUB, in case the VL register is zero. The processor waits for the first instruction VADD to complete because if the VL register is zero, the third instruction VSUB can retain the current value of v1 (which depends on the first instruction VADD) instead of rewriting v1 as the result of v4 minus v5. However, if the processor assumes that VSUB (or any other instruction) will not retain the current value of v1, the processor may execute the first instruction VADD and the second instruction VSUB out of order or in parallel. Therefore, the processor can operate more efficiently in the radical mode.

[0084] Figure 7 An example flowchart 700 is shown where a processor in aggressive mode assumes that data from a given location will not change between multiple reads when executing instructions out of order. In a particular implementation, the ISA can make the processor susceptible to livelock due to intra-instruction dependencies if instructions are executed out of order. For example, for vector aggregation operations (or vector index load instructions in RISC-V Vector Extensions), the processor may be prone to read-after-read errors in which data from a given location is read for the first time and then modified (e.g., modified by a snooping operation) before it is read a second time. For out-of-order execution of instructions using RISC-V Vector Extensions ISAs, protection against this scenario may be required (e.g., by disabling out-of-order execution of specific instructions). In a particular implementation, aggressive mode will not provide this protection. In other words, aggressive mode will assume that this protection is not needed.

[0085] At 701, the processor may receive a set of instructions to be executed out of order. These instructions may reference data in a given location multiple times.

[0086] At 702, the processor can read data from a location to execute the first instruction in the set of instructions. The processor can use the data to execute the instruction.

[0087] At point 703, the processor may begin executing the second instruction in the set of instructions. The second instruction may also use data from that location.

[0088] In conservative mode, at position 704, the processor can reread the data from that location. The processor can reread the data because the execution of the first instruction, the snooping operation, etc., may have altered the data at that location.

[0089] At 705, the processor can use the (most recently read) data to execute the second instruction. In conservative mode, this data might have been most recently read at 704. In aggressive mode, the data might have been most recently read at 702 (as part of executing the first instruction). For example, the processor (in aggressive mode) could choose not to reread the data at that location when executing the second instruction, instead assuming that the data has not changed between its last read (e.g., at 702) and its next use (e.g., at 705). Therefore, the processor can save time and operate more efficiently.

[0090] In a particular implementation, the processor can determine the likelihood that a certain instruction will result in a read-after-read error. In response, the processor can implement a conservative mode that prevents out-of-order execution of vector load operations. In this conservative mode, the instruction scheduling logic waits until the reorder buffer (ROB) is empty before dispatching the instruction to the out-of-order execution engine. After the instruction is dispatched, subsequent operations are not dispatched until the instruction is retired. Once the instruction has been executed accordingly in the conservative mode, the processor can return to the aggressive mode.

[0091] In a particular implementation, the processor may determine that an instruction might lead to a read-after-read error or some other error associated with out-of-order execution. In response, the processor may implement a conservative mode where the unit handling load / store operations is only allowed to execute a load or store operation if the operation is the oldest unresolved operation (e.g., a vector load / store instruction might generate many scalar load operations to populate vector elements, and the unit handling load / store operations will only execute the load operation if it is the oldest unresolved operation in the processor). If the unit handling load / store operations detects an exception at element N, this information can be broadcast throughout the processor. If the unit handling load / store operations detects an exception at element N, subsequent memory accesses can be masked (i.e., a dummy value is returned without accessing memory). The processor may also operate in a conservative mode where the vector unit manages the Vstart register and the location (N) of the exception reported from the unit handling load / store operations to merge the old and new values. Once the instruction has been executed accordingly in the conservative mode, the processor can return to the aggressive mode.

[0092] Figure 8 An example flowchart 800 is shown illustrating a processor in aggressive mode assuming that vector load instructions or conditional load instructions will not access I / O memory. In certain implementations, the ISA may disallow speculative memory accesses for a specific memory type (e.g., bulk accesses to memory to obtain a subset of the accessed data, or accesses to memory under conditions that are subsequently satisfied and render the memory access unnecessary). For example, the ISA may disallow speculative memory accesses to I / O memory regions to avoid unintended modifications to the I / O device state. The ISA may disallow vector load operations from I / O memory to select a subset of data because bulk access operations might perform I / O accesses to locations the instructions were not intended to access. Such access could lead to unintended modifications to the I / O device state.

[0093] In certain implementations, the aggressive mode assumes that vector load instructions or conditional load instructions will never need to access the I / O memory. Upon detecting a violation of this assumption, the aggressive mode can prevent vector load operations from accessing the I / O memory to avoid speculative memory accesses and fetching bulk data. In these implementations, the aggressive mode benefits from the processor not needing to detect conditional reads of the I / O memory.

[0094] At 801, the processor may receive a set of instructions, one or more of which include a conditional read of the I / O memory.

[0095] In conservative mode, at 802, the processor can organize the set of instructions such that instructions with conditional reads of the I / O memory are executed last in the set. For example, in some RISC-V compliant processors, load operations involving I / O memory are not allowed to be executed until they become the oldest instruction waiting to be executed. This approach ensures that the load operation is not conditionally canceled. However, this requirement reduces the processor's speed because it reduces the chance of parallelism and out-of-order execution.

[0096] At 803, the processor can execute the set of instructions. In the conservative mode, the set of instructions can be organized such that the instruction with a conditional read of the I / O memory is executed last in the set of instructions (e.g., at 802). In the aggressive mode, the processor can assume that the I / O memory will not be read. In other words, the processor can consider the condition for the instruction to read the I / O memory as unmet. Therefore, the aggressive mode, which makes the assumption that the condition for reading the I / O memory will not be met during the execution of the set of instructions, avoids the need for standard protections against this type of error and thus operates more efficiently. In a particular implementation, the aggressive mode will assume that instructions (e.g., vector load operations) never access the I / O memory.

[0097] The assumptions provided in this article are those that are generally true except during initialization time, and / or those that are generally true for most of the process during most workloads that will utilize the processor. Therefore, the aggressive mode is likely to provide sufficient functionality during the execution of a typical workload, and it is unlikely that a particular instruction will need to be repeated with a more conservative operating mode activated.

[0098] In certain implementations, the processor may conform to the RISC-V standard and be configured to operate in an aggressive mode with one or more of the following assumptions: instruction execution will not involve detecting any anomalies, instruction execution will not access I / O memory, instructions will not be executed if the value in the VL register is zero, instructions will not be executed if the value in the Vstart register is non-zero, and instructions will not cause read-after-read ordering violations. In this approach, the aggressive mode can operate more efficiently, for example by bypassing hold settings for waiting for merge operations described with reference to the above figures, out-of-order execution of vector aggregation operations, and assuming certain registers have predetermined values ​​(e.g., the Vstart register is 0) to avoid the need to check these values, etc.

[0099] In certain implementations, a RISC-V compliant processor can be configured to determine if any instruction violates the aforementioned assumptions and change the processor's operation to a more conservative mode that does not make one or more of these assumptions. Execution of the instruction can be canceled before continuing to update the processor's state. Depending on which assumption is being monitored, the detection can occur at various locations. For example, the instruction decoder can determine that Vstart is not equal to zero, and the integer execution unit can detect that the VL register has a zero value, or the load memory unit can detect I / O memory access, exceptions, and potential access ordering violations. The processor can enter a conservative mode when the re-fetched (or restarted) instruction is processed by the instruction decoding stage.

[0100] In a particular implementation, the processor may then be configured to determine whether the instruction violates a new set of assumptions and to change the processor's operation to a more conservative mode that does not make one or more additional assumptions from the original set of assumptions. In another implementation, the processor may be configured to determine which assumptions the instruction violates and select a conservative mode that does not make those assumptions. This method of gradually reducing the assumptions made by the asymptotically conservative mode can mitigate the efficiency degradation experienced by the processor.

[0101] In a particular implementation, the processor may implement a specific conservative mode in which instructions can be committed even if an error is detected in the midcore (the instruction sequence unit responsible for canceling instructions in case of an error). In this conservative mode, incorrect instruction execution is not prevented because the instruction sequences from other units (e.g., load / store units and vector units) will guarantee the correct architectural state.

[0102] At least one processor according to this disclosure may include at least one non-transitory computer-readable medium. The at least one processor may include at least one computing node in a network of computing nodes. The medium may include cache memory on the processor. The medium may also include shared memory not associated with a single computing node. The medium may be shared memory, may be shared random access memory, and may be, for example, DDR DRAM. The shared memory may be accessed through multiple channels. The non-transitory computer-readable medium may store data required for the execution of any method disclosed herein, instruction data disclosed herein, and / or operand data disclosed herein. The computer-readable medium may also store instructions that, when executed by the system, cause the system to perform the methods disclosed herein. The concept of executing instructions is used herein to describe the operation of a device to perform any logical or data movement operation, even if the “instruction” is entirely hardware-specified (e.g., an AND gate performing an AND instruction). This term is not intended to imply programmability of the device.

[0103] Although this specification has been described in detail with respect to specific embodiments of the invention, it should be understood that modifications, variations, and equivalent substitutions of these embodiments will readily occur to those skilled in the art upon understanding the foregoing. Any method steps discussed above may be executed by one or more processors operating in conjunction with a computer-readable non-transitory medium storing instructions for those method steps. The computer-readable medium may be memory within a personal user device or memory accessible via a network. While the examples in this disclosure are generally directed to RISC-VISA, the same approach can be used to meet other standards while improving efficiency. These and other modifications and variations may be made to the invention by those skilled in the art without departing from the scope of the invention, the scope of which is more specifically set forth in the appended claims.

Claims

1. A method for executing instructions using a processor, comprising: The instructions are extracted for execution in an aggressive mode, wherein the aggressive mode operates using one or more assumptions about the instructions; Detect that one of the one or more hypotheses is incorrect by one of the following: (i) evaluating the instruction using decoding logic; and (ii) evaluating the state of the processor after executing the instruction in the aggressive mode; as well as In response to the detection that one of the one or more hypotheses is incorrect: (i) if the instruction is detected to be incorrect by evaluating the instruction using decoding logic, then the execution of the instruction is cancelled; (ii) the processor is switched to a conservative mode; and (iii) the instruction is executed in the conservative mode; The conservative mode operates without at least one of the one or more assumptions.

2. The method according to claim 1, further comprising: The instructions are retrieved again so that they can be executed in the conservative mode; The hypothesis is still incorrect if one of the one or more hypotheses is detected by one of the following: (i) evaluating the instruction using the decoding logic after re-extracting the instruction; and (ii) evaluating the state of the processor after executing the instruction in the conservative mode; as well as In response to the detection that one of the one or more hypotheses is still incorrect: (i) cancel the execution of the instruction in the conservative mode; (ii) switch the processor to a more conservative mode; and (iii) execute the instruction in the more conservative mode.

3. The method according to claim 1, wherein: The processor is compatible with RISC-V Vector Extensions and allows a set of functions including: (i) partial updates of architecture registers; and (ii) conditional updates of second architecture registers; and The one or more assumptions include the assumption that the set of features will not be utilized.

4. The method according to claim 1, wherein: The processor is compatible with RISC-V vector extensions and allows in-instruction memory access ordering violations; and The one or more assumptions include the assumption that the in-instruction memory access ordering violation will not occur.

5. The method according to claim 1, wherein: Executing the instructions in the radical mode includes using the first set of hardware components while avoiding the use of the second set of hardware components; and Executing the instructions in the conservative mode includes using the second set of hardware components and avoiding the use of the first set of hardware components.

6. The method of claim 1, wherein executing the instructions in the conservative mode comprises: Generate a sequence of operations to perform actions that would invalidate the one or more hypotheses; The insertion was not used for one or more additional operations to execute the instruction in the aggressive mode; as well as Force the imposition of instruction dependencies.

7. The method of claim 1, wherein detecting that one of the one or more hypotheses is incorrect includes: Set a flag to indicate that one or more of the hypotheses detected are incorrect.

8. The method of claim 1, wherein detecting that one of the one or more hypotheses is incorrect further comprises: Identify the incorrect hypothesis from a set of hypotheses.

9. The method according to claim 8, further comprising: Based on the identified incorrect assumptions, the conservative mode is selected from a set of conservative modes, wherein the conservative mode does not make the incorrect assumptions.

10. The method according to claim 1, further comprising: Identify one or more hypotheses from a set of hypotheses that may be incorrect; as well as Based on the identified potentially incorrect one or more assumptions, a conservative mode is selected from a set of conservative modes, wherein each of the conservative modes makes a different combination of assumptions, and the conservative mode does not make the potentially incorrect one or more assumptions.

11. The method according to claim 1, further comprising: At least in part, the transition to the third mode is based on executing the aforementioned instructions; Extract the second instruction; as well as The second instruction is executed in the third mode, at least in part, based on the extraction of the second instruction.

12. The method of claim 11, further comprising: Extract the third instruction; as well as At least in part, the third instruction is extracted and executed in the conservative mode before transitioning to the third mode.

13. The method according to claim 11, wherein: The third mode is the radical mode.

14. The method according to claim 1, further comprising: The conservative mode is selected from a set of conservative modes, each of which is associated with a different combination of features, wherein the features include combinations of: (i) breaking memory instructions into small segments; (ii) forcing memory instructions to be executed sequentially; (iii) allowing updates to the processor state; and (iv) merging old data with new data in the register file or configuration register.

15. The method according to claim 1, wherein: The one or more assumptions correspond to the assumption that the execution of the instruction will not involve: (i) detecting any anomaly; (ii) accessing input / output memory; (iii) the value in the first register is zero; (iv) the value in the second register is non-zero; (v) read-after-read ordering violation; or (vi) a combination thereof.

16. An apparatus comprising: One or more processors; as well as A non-transitory computer-readable medium storing instructions, which, when executed by the one or more processors, cause the one or more processors to perform a method for executing the instructions, the method comprising: The instructions are extracted for execution in an aggressive mode, wherein the aggressive mode operates using one or more assumptions about the instructions; The hypothesis is detected as incorrect by one of the following: (i) evaluating the instruction using decoding logic; and (ii) evaluating the state of the one or more processors after executing the instruction in the aggressive mode; and In response to the detection that one of the one or more hypotheses is incorrect: (i) if the instruction is detected to be incorrect by evaluating the instruction using decoding logic, then the execution of the instruction is cancelled; (ii) the one or more processors are switched to a conservative mode; and (iii) the instruction is executed in the conservative mode; The conservative mode operates without at least one of the one or more assumptions.

17. The apparatus of claim 16, wherein the method further comprises: The instructions are retrieved again so that they can be executed in the conservative mode; The hypothesis is still incorrect by one of the one or more assumptions: (i) evaluating the instruction using the decoding logic after re-extracting the instruction; and (ii) evaluating the state of the one or more processors after executing the instruction in the conservative mode; as well as In response to detecting that one of the one or more hypotheses is still incorrect: (i) cancel the execution of the instruction in the conservative mode; (ii) switch the one or more processors to a more conservative mode; and (iii) execute the instruction in the more conservative mode.

18. The apparatus according to claim 16, wherein: The one or more processors are compatible with RISC-V Vector Extensions and allow a set of functions including: (i) partial updates of architecture registers; and (ii) conditional updates of second architecture registers; and The one or more assumptions include the assumption that the set of features will not be utilized.

19. The apparatus according to claim 16, wherein: The one or more processors are compatible with RISC-V vector extensions and allow in-instruction memory access ordering violations; and The one or more assumptions include the assumption that the in-instruction memory access ordering violation will not occur.

20. The apparatus of claim 16, further comprising: The first set of hardware components; as well as The second set of hardware components is different from the first set of hardware components; Executing the instructions in the aggressive mode includes using the first set of hardware components and avoiding the use of the second set of hardware components; and Executing the instructions in the conservative mode includes using the second set of hardware components and avoiding the use of the first set of hardware components.

21. The apparatus of claim 16, wherein the method further comprises: Generate a sequence of operations to perform actions that would invalidate the one or more hypotheses; The insertion was not used for one or more additional operations to execute the instruction in the aggressive mode; as well as Force the imposition of instruction dependencies.

22. The apparatus of claim 16, wherein detecting that one of the one or more hypotheses is incorrect includes: Set a flag to indicate that one or more of the hypotheses detected are incorrect.

23. The apparatus of claim 16, wherein detecting that one of the one or more hypotheses is incorrect further comprises: Identify the incorrect hypothesis from a set of hypotheses.

24. The apparatus of claim 23, wherein the method further comprises: Based on the identified incorrect assumptions, the conservative mode is selected from a set of conservative modes, wherein the conservative mode does not make the incorrect assumptions.

25. The apparatus of claim 16, wherein the method further comprises: Identify one or more hypotheses from a set of hypotheses that may be incorrect; as well as Based on the identified potentially incorrect one or more assumptions, a conservative mode is selected from a set of conservative modes, wherein each of the conservative modes makes a different combination of assumptions, and the conservative mode does not make the potentially incorrect one or more assumptions.

26. The apparatus of claim 16, wherein the method further comprises: At least in part, the transition to the third mode is based on executing the aforementioned instructions; Extract the second instruction; as well as The second instruction is executed in the third mode, at least in part, based on the extraction of the second instruction.

27. The apparatus of claim 26, wherein the method further comprises: Extract the third instruction; as well as At least in part, the third instruction is extracted and executed in the conservative mode before transitioning to the third mode.

28. The apparatus according to claim 26, wherein: The third mode is the radical mode.

29. The apparatus according to claim 16, wherein: The one or more assumptions correspond to the assumption that the execution of the instruction will not involve: (i) detecting any anomaly; (ii) accessing input / output memory; (iii) the value in the first register is zero; (iv) the value in the second register is non-zero; (v) read-after-read ordering violation; or (vi) a combination thereof.

30. A method of executing instructions using one or more processors, comprising: The instructions are extracted for execution in an aggressive mode, wherein the aggressive mode operates using a set of assumptions about the instructions; The following tests to determine if at least one of the first hypotheses in the set of hypotheses is incorrect: (i) evaluating the instruction before execution; (ii) evaluating the state of the one or more processors after partial execution of the instruction in the aggressive mode; and (iii) assessing the state of the one or more processors after the instructions have been fully executed in the aggressive mode; The one or more processors are switched to a conservative mode, at least in part based on the detection that at least one first hypothesis in the set of hypotheses is incorrect, wherein the conservative mode operates without at least one second hypothesis in the set of hypotheses; and The instructions are executed in at least part of the process of switching one or more processors to the conservative mode.

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