Adaptive diode emulation mode offset circuit

Abstract

An apparatus and method for adaptive diode emulation mode offset circuit is disclosed. The apparatus includes a polarity detection circuit to identify a polarity of a phase node of a DC-DC converter; and an adaptive diode emulation mode (DEM) offset circuit to: detect a first early termination or a first late termination of an on-time of a low-side gate drive of the DC-DC converter based on the identified polarity of the phase node; and output an offset voltage to selectively terminate the on-time of the low-side gate drive to mitigate a second early termination or a second late termination of the low-side gate drive, a value of the offset voltage based on the polarity of the phase node of the DC-DC converter; wherein the second early termination occurs after the first early termination, and the second late termination occurs after the first late termination.

Description

priority

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 558,252, filed on February 27, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a diode emulation mode circuit, and more particularly to a diode emulation mode circuit with improved light-load efficiency. Background Technology

[0003] Switch-mode power supplies, or switching regulators (also known as DC-DC converters), are typically used to convert an input supply voltage to a desired output voltage. For example, a 5-volt supply voltage provided to an integrated circuit may need to be reduced to 2.8 volts to operate additional circuitry. Switching regulators provide power through low-loss components such as capacitors, inductors, and transformers, as well as power switches that are turned on and off to transfer energy from the input to the output in discrete packets. Feedback control circuitry is used to regulate energy transfer to maintain a constant output voltage within the circuit's required load limits.

[0004] Switching regulators can be configured to increase or decrease the input voltage, or both. Specifically, buck switching regulators (also known as "buck converters") decrease the input voltage, while boost switching regulators (also known as "boost converters") increase the input voltage. Buck-boost switching regulators or buck-boost converters provide both boost and buck functionality.

[0005] A traditional buck switching regulator includes a pair of power switches that are turned on and off to regulate the output voltage to be proportional to a reference voltage. More specifically, the power switches are alternately turned on and off to generate a switching output voltage at the switching output node (also known as the phase node). The phase node is coupled to an LC filter circuit that includes an output inductor and an output capacitor to generate an output voltage with a substantially constant amplitude. The output voltage can then be used to drive a load.

[0006] Specifically, this pair of power switches is typically referred to as comprising a "high-side power switch" and a "low-side power switch." The high-side power switch is turned on or off to apply energy to the output inductor of the output filter circuit, thereby allowing current to build up through the inductor. When the high-side power switch is turned off or off, the voltage across the inductor reverses, and the current flowing through the inductor decreases during this period.

[0007] While a diode can be used as the low-side power switch, as the amplitude of the output voltage from a DC-DC converter decreases, a transistor can be used instead to improve efficiency. However, unlike a diode, a transistor, such as a field-effect transistor (FET), is a bidirectional switch, allowing current to flow in either direction. When a DC-DC converter operates under a light current load, the current in the inductor may drop to zero or even reverse. Reverse current reduces the efficiency of the DC-DC converter. To prevent reverse current, a diode emulation mode (DEM) circuit can be added to detect when the inductor current reaches zero. At this point, the DEM circuit turns off the transistor, preventing reverse current from flowing.

[0008] Timing DEM circuits is challenging and can be affected by numerous system parameters, including, for example, the inductor current slope, comparator offset and propagation delay in the DEM circuit, gate drive path propagation delay, operating temperature, and inter-component variations. Early or delayed turn-off of the low-side power switch in the DEM circuit can lead to increased power dissipation, reduced efficiency, and performance differences between components. Therefore, there is a need for DEM circuits capable of achieving more accurate low-side power switch termination timing. Summary of the Invention

[0009] A system and method for an adaptive diode emulation mode offset circuit are disclosed. The apparatus includes: a polarity detection circuit for identifying the polarity of a phase node of a DC-DC converter; and an adaptive diode emulation mode (DEM) offset circuit for: detecting, based on the identified polarity of the phase node, a first early termination or a first delayed termination of the on-time of a low-side gate drive of the DC-DC converter; and outputting an offset voltage to selectively terminate the on-time of the low-side gate drive, thereby mitigating a second early termination or a second delayed termination of the low-side gate drive, the value of the offset voltage being based on the polarity of the phase node of the DC-DC converter; wherein the second early termination occurs after the first early termination, and the second delayed termination occurs after the first delayed termination.

[0010] An apparatus includes: a DC-DC converter including a low-side gate drive and a phase node; a polarity detection circuit for identifying the polarity of the phase node; an adaptive diode emulation mode (DEM) offset circuit; and a DEM circuit. The adaptive DEM offset circuit is configured to: receive the identified polarity of the phase node from the polarity detection circuit; detect a first early termination or a first delayed termination of the on-time of the low-side gate drive based on the identified polarity of the phase node; and output an offset voltage, the value of which is based on the polarity of the phase node. The DEM circuit is configured to: receive the offset voltage; and selectively terminate the on-time of the low-side gate drive to mitigate a second early termination or a second delayed termination of the low-side gate drive.

[0011] A method includes: receiving the polarity of a phase node of a DC-DC converter; detecting a first early termination or a first delayed termination of the on-time of a low-side gate drive of the DC-DC converter based on the received polarity of the phase node; and outputting an offset voltage to selectively terminate the on-time of the low-side gate drive, thereby mitigating a second early termination or a second delayed termination of the on-time of the low-side gate drive, the value of the offset voltage being based on the polarity of the phase node. Attached Figure Description

[0012] The accompanying figures illustrate examples of the systems and methods.

[0013] Figure 1 A system including an adaptive DEM circuit in a DC-DC converter, according to an example of this disclosure, is illustrated;

[0014] Figure 2 A DC-DC converter according to an example of this disclosure is illustrated;

[0015] Figure 3 A polarity detection circuit according to an example of this disclosure is illustrated;

[0016] Figure 4 An adaptive DEM offset circuit according to an example of this disclosure is illustrated;

[0017] Figure 5 A DEM circuit according to an example of this disclosure is illustrated;

[0018] Figure 6 Simulation results of a DC-DC converter incorporating an adaptive DEM offset circuit according to an example of this disclosure are illustrated;

[0019] Figure 7 An example of a method for performing an adaptive DEM circuit in a DC-DC converter according to an example of this disclosure is illustrated; and

[0020] Figure 8 Examples according to this disclosure are illustrated. Figure 7 A more detailed version of the method described in [the document].

[0021] Reference numerals for any illustrated element appearing in multiple different figures have the same meaning in all figures, and any reference or discussion of any illustrated element in the context of any particular figure also applies to every other figure (if any) in which the same illustrated element is shown. Detailed Implementation

[0022] According to one aspect of the invention, an adaptive diode emulation mode (DEM) offset circuit is provided. The DEM offset circuit enables more accurate timing for terminating switches in a DC-DC converter, thereby improving the efficiency of the DC-DC converter.

[0023] Figure 1 An example of a system including adaptive DEM circuitry in a DC-DC converter according to the present disclosure is illustrated. System 100 may include DC-DC converter 110, polarity detection circuitry 120, adaptive DEM offset circuitry 130, and DEM circuitry 140.

[0024] The DC-DC converter 110 can be a circuit for converting direct current from one voltage to another, such as a buck converter, a boost converter, or a buck-boost converter. The DC-DC converter 110 can be connected to an input voltage (V... IN The DC-DC converter 110 may include two gate drives (e.g., a high-side gate drive and a low-side gate drive) and at least one energy storage element, such as a capacitor, an inductor, or any combination thereof. In some examples, one of the gate drives may be a transistor, such as a field-effect transistor (FET). The state of the low-side gate drive in the DC-DC converter 110 may be controlled by the DEM circuit 140 to time the termination of the on-time of the low-side gate drive, thereby improving the efficiency of the DC-DC converter 110. Figure 2 A more detailed example of the DC-DC converter 110 is shown.

[0025] The polarity detection circuit 120 may be a circuit for determining the polarity of a phase node in the DC-DC converter 110. The polarity detection circuit 120 may receive the phase node polarity or a representative thereof, and may compare the phase node voltage with a reference voltage to determine whether the termination of the on-time of the low-side gate drive in the DC-DC converter 110 is prematurely terminated (e.g., the phase node voltage is below ground potential) or delayed (e.g., the phase node voltage is above V). INThe polarity detection circuit 120 can output the polarity (e.g., positive or negative) of the phase node to the adaptive DEM offset circuit 130. Figure 3 A more detailed example of the polarity detection circuit 120 is shown.

[0026] The adaptive DEM offset circuit 130 can be a circuit used to detect whether the low-side gate drive in the DC-DC converter 110 may have been terminated prematurely or delayed. For example, if the polarity of the phase node is positive, the low-side gate drive may have been terminated delayed, and if the polarity of the phase node is negative, the low-side gate drive may have been terminated prematurely. The adaptive DEM offset circuit 130 can also output an offset voltage based on the polarity of the phase node. The offset voltage can be output to the DEM circuit 140. Figure 4 A more detailed example of the adaptive DEM offset circuit 130 is shown.

[0027] DEM circuit 140 may be a circuit that receives an offset voltage from adaptive DEM offset circuit 130 and outputs a control signal to control the state of the low-side gate drive of DC-DC converter 110. The control signal can be used to selectively terminate the on-time of the low-side gate drive to more accurately time the termination of the low-side gate drive's on-time, thereby mitigating subsequent early or delayed termination. In some examples, the control signal output by DEM circuit 140 may be a logic value input to the low-side gate drive (e.g., logic value 1 turns the low-side gate drive on, and logic value 0 turns it off). Figure 5 A more detailed example of the DEM circuit 140 is shown.

[0028] Figure 2 A DC-DC converter according to an example of this disclosure is illustrated. Figure 2 In the example shown, the DC-DC converter is a buck converter or a step-down converter. The DC-DC converter 210 is... Figure 2 The circuit is illustrated as comprising four main components: a high-side power switch 211, a low-side switch 212, an inductor 214, and a capacitor 215.

[0029] The low-side switch 212 (which can be a transistor such as a FET or a metal-oxide-semiconductor field-effect transistor (MOSFET)) can be supplied by a DEM circuit (such as... Figure 1 The input logic value of the DEM circuit 140 shown (in) Figure 2 The inductor 214 is controlled by a circuit labeled "LG". If the on-time of the low-side switch 212 is delayed, the current flowing through the inductor 214 may reverse, causing the voltage at phase node 216 to rise rapidly to V after the low-side switch 212 is deactivated. INThis leads to increased power dissipation. If the on-time of the low-side switch 212 is prematurely terminated, the voltage at phase node 216 is pulled below ground potential by the current circulating through the DC-DC converter 210. Specifically, since current flows from ground to phase node 216 through the low-side switch 212, and the ground potential is a zero-volt reference potential, the voltage at phase node 216 will be pulled below ground potential to allow current flow. Premature termination also results in increased power dissipation compared to accurate timing termination of the low-side switch 212. An offset voltage from a DEM offset circuit (such as adaptive DEM offset circuit 130) can provide an offset voltage to a DEM circuit (such as DEM circuit 140) to achieve more accurate timing termination of the low-side switch 212 and mitigate the occurrence of premature or delayed termination of the on-time of the low-side switch 212.

[0030] The DC-DC converter 210 may also include a high-side power switch 211, which may be a second switch (such as a diode or transistor) and may be used to selectively supply input voltage to the DC-DC converter 210. The location of the high-side power switch 211 may be determined by... Figure 2 The input logic value marked "HG" controls the input. Capacitor 215 can be a capacitor that works in conjunction with inductor 214 to store energy. Capacitor 215 can have any suitable value, such as 1mF.

[0031] The DC-DC converter 210 is also illustrated to include an error amplifier 213, a current sensor 221, a pulse width modulation (PWM) comparator 217, a set-reset (SR) latch 218, an inverter 220, and a clock 219, which can be used to close the power supply loop and provide a fixed output voltage V. OUT Error amplifier 213 compares the output voltage with a reference voltage. Current sensor 221 senses the current in inductor 214. PWM comparator 217 compares the signal from current sensor 221 with the output of error amplifier 213. The output of PWM comparator 217 can be provided to SR latch 218 and used to reset SR latch 218. SR latch 218 latches the high-side gate drive signal (labeled "HG") to the high bit in each clock cycle and latches it to the low bit on each reset from PWM comparator 217. Inverter 220 ensures that the low-side gate drive signal (labeled "LG") remains in the opposite state of the high-side gate drive signal by outputting a signal opposite to the high-side gate drive signal (labeled "nHG"). Clock 219 can signal SR latch 218 to signal the start of each switching cycle. Clock 219 can also signal to fix the PWM frequency.

[0032] To implement DEM in a DC-DC converter (such as DC-DC converter 210), a DEM comparator circuit 140 can be added to DC-DC converter 210. An AND gate 222 can receive the output of inverter 220 and the output of DEM circuit 140 as inputs, and output a low-side gate drive signal LG. The output of DEM circuit 140 can occur earlier than in the absence of DEM comparator circuit 140 (e.g., if the output of PWM comparator 217 is used to provide the low-side gate drive signal).

[0033] Figure 3 An example of a polarity detection circuit according to this disclosure is illustrated. The polarity detection circuit 320 can receive the phase node of a DC-DC converter (such as...) Figure 2 The voltage of phase node 216 (shown). Polarity detection circuit 320 can determine the polarity of the phase node based on the received voltage. Specifically, comparator 322 can compare the voltage of the phase node with a DC reference voltage (in... Figure 3 The middle is marked as V PREF The DC reference voltage can be greater than ground potential and less than or equal to V in a system where the DC-DC converter is part of it. IN Any reference voltage. For example, V can be selected. IN As the reference voltage for the DEM polarity detection circuit 320, even if the voltage at the phase node oscillates after the synchronous switch is terminated, in the case of delayed termination, the voltage at the phase node will rise to V through the forward voltage drop of the high-side switch (e.g., the forward voltage drop of the body diode of the high-side switch). IN Furthermore, in the case of delayed termination, the phase node voltage will be less than the ground potential, and the phase node voltage will not exceed V. IN The polarity of the phase node immediately following the termination of the conduction time of the low-side gate drive can be used to determine whether the termination of the conduction time occurs early (e.g., the phase node voltage is below ground potential) or delayed (e.g., the phase node voltage is above V). IN ).

[0034] The polarity detection circuit 320 may include a trigger switch 324. When a rising edge of the clock input, provided by a delayed DEM OUT signal, occurs, the trigger switch 324 may sample the output of comparator 322 (e.g., the polarity of the phase node). The DEM OUT signal may originate from a DEM circuit (such as...). Figure 2 The DEM circuit 140 shown is shown, and relative to Figure 5 A more detailed description is needed. Delay 323 can be applied to circuits from DEM circuits (such as...). Figure 1 The DEM circuit 140 shown is in Figure 3The DEM signal, marked "DEM OUT", provides a short delay. The delay provided by delay 323 ensures that sampling performed by trigger switch 324 occurs on the low-side gate drive (such as...). Figure 2 This occurs slightly after the termination of the low-side gate drive 212 shown.

[0035] The output of the trigger switch 324 is controlled by a clock (such as...) Figure 2 The polarity of the phase node within the current cycle of the clock 219 shown is determined. Specifically, when the polarity of the phase node is positive (e.g., the voltage of the phase node is greater than the reference voltage), the output of Q of the trigger switch 324 can be -1, and when the polarity of the phase node is negative (e.g., the voltage of the phase node is less than the reference voltage), The output of trigger switch 324 can be one (1). In Figure 3 In the code, the output of Q is labeled "POL", and The output is labeled "nPOL". The outputs of the trigger switch 324 (e.g., POL and nPOL) can be provided as inputs to an adaptive DEM offset circuit (such as...). Figure 2 The adaptive DEM offset circuit 130 shown is illustrated, and as relative to... Figure 4 A more detailed description.

[0036] Figure 4 An adaptive DEM offset circuit according to an example of this disclosure is illustrated. The adaptive DEM offset circuit 430 can be derived from a polarity detection circuit (such as...) Figure 3 The polarity detection circuit 320 shown receives a polarity signal and a current DEM OUT signal from the DEM circuit 140. The DEM OUT signal can indicate the polarity of the inductor (such as...). Figure 2 The current in the inductor 214 (shown) is checked for zero crossing. The polarity signal can be added to the DEM OUT signal at AND gates 431a and 431b. The outputs of AND gates 431a and 431b can be input to single-shot timers 432a and 432b. Single-shot timers 432a and 432b control the charging and discharging durations of capacitor 434. Specifically, when the polarity of the phase node is negative, single-shot timer 432a outputs a logic value of 1 (in the...). Figure 4 The timer 432b is marked as "CHG" and outputs a logic value of 1 when the polarity of the phase node is positive. Figure 4 (It is marked as "DIS" in the middle).

[0037] The adaptive DEM offset circuit 430 can receive current from current sources 433a and 433b. The sizes of current sources 433a and 433b can be any suitable amount. In some examples, current source 433a may have a different size than current source 433b. At switch 435a, when the single-shot timer 432a outputs CHG, switch 435a closes to provide current from current source 433a to capacitor 434, thereby charging capacitor 434. At switch 435b, when the single-shot timer 432b outputs DIS, switch 435b closes to provide current from current source 433b to capacitor 434, thereby discharging capacitor 434. Therefore, the voltage level of capacitor 434 rises and falls by the opening and closing of switches 435a and 435b. The voltage level of capacitor 434 is buffered at buffer 436 and output as an offset voltage. Figure 4 It is marked as "DEM REF". The offset voltage DEM REF can be a DEM circuit (such as...) Figure 2 The reference voltage of the DEM circuit 140 shown, and as relative to Figure 5 A more detailed description. When the inductor (such as...) flows through the DC-DC converter... Figure 2 When the current of the inductor 214 shown is not zero, the offset voltage can be forced to zero millivolts.

[0038] The periods of single-time timers 432a and 432b, the strengths of current sources 433a and 433b, and the value of capacitor 434 determine the step size for adjusting the DEM REF. These values ​​can be adjusted based on the specific implementation of the adaptive DEM offset circuit and the DC-DC converter in which the adaptive DEM offset circuit is incorporated, thereby providing the optimal step size and die area for the application.

[0039] Figure 5 An example of a DEM circuit according to this disclosure is illustrated. The DEM circuit 540 can receive a voltage at the phase node (“PHASE”) and an offset voltage (“DEM REF”) from an adaptive DEM offset circuit. Comparator 542 compares the voltage at the phase node with the offset voltage and outputs “1” if the voltage at the phase node is greater than the offset voltage, or outputs “0” if the offset voltage is greater than the voltage at the phase node. The output of comparator 542 is added with an inverted high-side gate drive signal nHG at an AND gate 544, as described above relative to… Figure 2 As described. The output of AND gate 544 is then provided to SR latch 546. SR latch 546 can be set when the high-side gate drive is low. SR latch 546 can be reset by the high-side gate drive signal HG in each switching cycle to ensure that the diode emulation mode is checked independently in each cycle. SR latch 546 can output... Figure 5The logic value marked "DEM OUT" indicates whether the low-side gate drive in the DC-DC converter should be turned off or on. DEM OUT can be provided to components of the DC-DC converter, such as... Figure 2 The AND gate 222 shown is used to control the position of the low-side gate drive.

[0040] DEM circuit 540 can be similar to a standard DEM circuit, with the addition of the output DEMREF of an adaptive DEM offset circuit. DEM REF can replace the reference value used in the standard DEM circuit, which can be a fixed value.

[0041] Figure 6 Simulation results of a DC-DC converter incorporating an adaptive DEM offset circuit according to an example of this disclosure are illustrated. Graph 600 illustrates the inductor (such as...) flowing through the DC-DC converter in region 630 of graph 600. Figure 2 The current flowing through the inductor 214 (as shown). When the current flowing through the inductor is not zero or does not cross zero, the offset voltage to the DEM comparator (in Figure 6 The current (denoted as DEM_REF) is forced to 0mV. In the example shown in graph 600, the current flowing through the inductor reaches zero at approximately 1.42 milliseconds. At this point, the offset voltage (DEM_REF) is gradually adjusted until the polarity at the phase node changes. Although in the example shown in region 620 of graph 600, the offset voltage is adjusted in 100µV increments until the polarity at the phase node changes, in other examples, the increment can be of any size.

[0042] Graph 600 illustrates the polarity detection circuit (such as...) in region 610 of graph 600. Figure 3 The output of the polarity detection circuit 320 shown. At approximately 1.495 milliseconds, the polarity of the phase node reverses. Once the polarity of the phase node reverses, the offset voltage increases until the polarity of the phase node reverses again. During steady-state operation, the offset voltage can continue to increase and decrease between the positive and negative polarities of the phase node to achieve low-side gate drive (such as in DC-DC circuits) in DC-DC circuits. Figure 2 The precise timing of the termination of the low-side switch 212 shown.

[0043] Figure 7 An example of a method for performing an adaptive DEM circuit in a DC-DC converter, according to an example of this disclosure, is illustrated. Method 700 may use an adaptive DEM offset circuit (such as...) Figure 4The adaptive DEM offset circuit 430 shown, or any other circuit capable of operating to implement method 700, is used to implement this method. Although examples have been described above, other variations and examples may be made according to this disclosure without departing from the spirit and scope of these disclosed examples.

[0044] Method 700 may begin at block 710, where the adaptive DEM offset circuitry receives the polarity of the phase node of the DC-DC converter. The polarity of the phase node may be determined by a polarity detection circuit (such as...) Figure 3 The polarity detection circuit 320 shown outputs to the adaptive DEM offset circuit.

[0045] At block 720, the adaptive DEM offset circuitry detects a first early termination or a first delayed termination of the low-side gate drive's on-time in the DC-DC converter. The adaptive DEM offset circuitry detects the termination of the low-side gate drive's on-time and determines whether the termination is early or delayed based on the polarity of the phase node immediately following the termination of the low-side gate drive's on-time. Termination may occur early when the phase node voltage is below ground potential, or when the phase node voltage is above V... IN At that time, the termination may have already been delayed.

[0046] At block 740, the adaptive DEM offset circuit can output an offset voltage to selectively terminate the on-time of the low-side gate drive, thereby mitigating a second early termination or a second delayed termination of the low-side gate drive's on-time. The adaptive DEM offset circuit can mitigate this by adjusting the capacitors (such as...) in the adaptive DEM offset circuit. Figure 4 The capacitor 434 shown is selectively charged to output an offset voltage. The offset voltage can be based on the polarity of the phase node received at block 710.

[0047] although Figure 7 A specific number of operations related to method 700 are disclosed, but method 700 is available in more... Figure 7 The number of operations described can be increased or decreased to perform the task. Furthermore, although... Figure 7 The specific order of operations to be performed in method 700 is disclosed, but the operations including method 700 can be performed in any suitable order.

[0048] Figure 8 Examples according to this disclosure are illustrated. Figure 7 A more detailed version of the method described herein. Method 800 may use an adaptive DEM offset circuit (such as...) Figure 4The adaptive DEM offset circuit 430 shown, or any other circuit capable of operating to implement method 800, is used to implement this method. Although examples have been described above, other variations and examples may be made according to this disclosure without departing from the spirit and scope of these disclosed examples.

[0049] Method 800 may begin at block 810, where the adaptive DEM offset circuitry receives the polarity of the phase node of the DC-DC converter. The polarity of the phase node may be determined by a polarity detection circuit (such as...) Figure 3 The polarity detection circuit 320 shown outputs to the adaptive DEM offset circuit.

[0050] At block 820, the adaptive DEM offset circuitry detects a first early termination or a first delayed termination of the conduction time of the low-side gate drive in the DC-DC converter. The adaptive DEM offset circuitry detects the termination of the low-side gate drive's conduction time and determines whether the termination is early or delayed based on the polarity of the phase node immediately following the termination of the low-side gate drive. The termination of the conduction time may occur early when the phase node voltage is below ground potential, or when the phase node voltage is above V... IN At that time, the termination of the conduction time may have already been delayed.

[0051] At block 830, the adaptive DEM offset circuit can dynamically adjust the offset voltage based on the polarity of the phase node after the previous termination of the low-side gate drive's on-time. This can be achieved by adjusting the capacitors (such as...) in the adaptive DEM offset circuit. Figure 4 The capacitor 434 shown is selectively charged to dynamically adjust the offset voltage. For example, the polarity of the phase node can be based on the previous termination of the low-side gate drive's on-time. When the phase node polarity is negative (e.g., the low-side gate drive's on-time was previously terminated earlier), the capacitor can be charged, and when the phase node polarity is positive (e.g., the low-side gate drive's on-time was previously terminated later), the capacitor can be discharged.

[0052] At box 835, the adaptive DEM offset circuit can incrementally and repeatedly adjust the offset voltage until the polarity of the phase node is reversed. For example, the capacitor in the adaptive DEM offset circuit can be charged incrementally to generate an offset voltage increment. The offset voltage can be adjusted through these increments until the polarity of the phase node is reversed, as relative to... Figure 6 Further detailed description. The offset voltage increment can have any suitable size. In some examples, the increments can have equal magnitudes, and in other examples, the increments can have different magnitudes.

[0053] At block 840, the adaptive DEM offset circuit can output an offset voltage to selectively terminate the on-time of the low-side gate drive, thereby mitigating a second early termination or a second delayed termination of the low-side gate drive's on-time. The adaptive DEM offset circuit can mitigate this by adjusting the capacitors (such as...) in the adaptive DEM offset circuit. Figure 4 The capacitor 434 shown is selectively charged to output an offset voltage. The offset voltage can be based on the polarity of the phase node received at block 810.

[0054] although Figure 8 A specific number of operations related to method 800 are disclosed, but method 800 is available in more... Figure 8 The number of operations described can be increased or decreased to perform the task. Furthermore, although... Figure 8 The specific order of operations to be performed in method 800 is disclosed, but the operations including method 800 can be performed in any suitable order.

[0055] While the reference buck converter exemplifies adaptive DEM zero-crossing detection, the adaptive DEM zero-crossing detection circuit can also be used in any DC-DC converter topology, including buck-boost and synchronous boost topologies.

[0056] Examples of this disclosure may include an apparatus. The apparatus may include a polarity detection circuit and an adaptive diode emulation mode (DEM) offset circuit. The polarity detection circuit may be used to identify the polarity of a phase node of a DC-DC converter. The adaptive DEM offset circuit may be used to: detect a first early termination or a first delayed termination of the on-time of the low-side gate drive of the DC-DC converter based on the identified polarity of the phase node; and output an offset voltage to selectively terminate the on-time of the low-side gate drive, thereby mitigating a second early termination or a second delayed termination of the low-side gate drive. The value of the offset voltage may be based on the polarity of the phase node of the DC-DC converter. The second early termination may occur after the first early termination, and the second delayed termination may occur after the first delayed termination.

[0057] Combining any of the examples above, the adaptive DEM offset circuit can be used to dynamically adjust the offset voltage based on the polarity of the phase node.

[0058] Combining any of the examples above, the adaptive DEM offset circuit can be used to repeatedly adjust the offset voltage in an incremental manner until the polarity of the phase node is reversed.

[0059] Combining any of the examples above, an adaptive DEM offset circuit can be used to receive the polarity of the phase node of a DC-DC converter.

[0060] Combining any of the examples above, the adaptive DEM offset circuit can be used to detect the first premature termination by detecting that the voltage of the phase node is pulled below ground potential.

[0061] Combining any of the examples above, the adaptive DEM offset circuit can be used to detect the first delay termination by detecting that the voltage of the phase node is pulled above the input voltage.

[0062] Combining any of the examples above, the offset voltage can be approximately zero when the current flowing through the DC-DC converter is in the positive direction.

[0063] Examples of this disclosure may include another apparatus. This apparatus may include any of the apparatuses described in the examples above. The apparatus may include a DC-DC converter that may include a low-side gate drive and a phase node. The apparatus may include diode emulation mode (DEM) circuitry configured to: receive an offset voltage; and selectively terminate the on-time of the low-side gate drive to mitigate a second early termination or a second delayed termination of the low-side gate drive. An adaptive DEM offset circuit may be used to receive the identified polarity of the phase node from a polarity detection circuit.

[0064] Combining any of the examples above, an adaptive DEM offset circuit can be used to repeatedly adjust the offset voltage in an incremental manner until the polarity of the phase node is reversed, where the increments have equal magnitudes.

[0065] Examples of this disclosure may include a method. This method may include operations performed by any of the means described above. The method may include: receiving the polarity of a phase node of a DC-DC converter; detecting a first early termination or a first delayed termination of the on-time of a low-side gate drive of the DC-DC converter based on the received polarity of the phase node; and outputting an offset voltage to selectively terminate the on-time of the low-side gate drive, thereby mitigating a second early termination or a second delayed termination of the on-time of the low-side gate drive. The value of the offset voltage may be based on the polarity of the phase node.

[0066] In conjunction with any of the examples above, the method may include: dynamically adjusting the offset voltage based on the polarity of the phase node after a previous termination of the low-side gate drive.

[0067] Combining any of the examples above, the method may include: repeatedly adjusting the offset voltage in an incremental manner until the polarity of the phase node is reversed.

[0068] Combining any of the examples above, the increments can have equal magnitudes.

[0069] In conjunction with any of the examples above, detecting a first premature termination may include: detecting that the voltage of a phase node is pulled below ground potential.

[0070] In conjunction with any of the examples above, detecting the first delay termination may include: detecting that the voltage of the phase node is pulled above the input voltage.

[0071] Although examples have been described above, other variations and examples may be made in accordance with this disclosure without departing from the substance and scope of these disclosed examples.

Claims

1. An apparatus, the apparatus comprising: A polarity detection circuit, which is used to identify the polarity of the phase nodes of a DC-DC converter; and An adaptive diode emulation mode (DEM) offset circuit is used for: Based on the polarity identified by the phase node, a first early termination or a first delayed termination of the on-time of the low-side gate drive of the DC-DC converter is detected. as well as An output offset voltage is provided to selectively terminate the on-time of the low-side gate drive, thereby mitigating a second early termination or a second delayed termination of the low-side gate drive. The value of the offset voltage is based on the polarity of the phase node of the DC-DC converter. The second early termination occurs after the first early termination, and the second delayed termination occurs after the first delayed termination.

2. The apparatus of claim 1, wherein the adaptive DEM offset circuit is used to dynamically adjust the offset voltage based on the polarity of the phase node.

3. The apparatus of claim 2, wherein the adaptive DEM offset circuit is used to repeatedly adjust the offset voltage incrementally until the polarity of the phase node is reversed.

4. The apparatus according to any one of claims 1 to 3, wherein the adaptive DEM offset circuit is used to receive the polarity of the phase node of the DC-DC converter.

5. The apparatus according to any one of claims 1 to 4, wherein the adaptive DEM offset circuit is used to detect the first early termination by detecting that the voltage of the phase node is pulled below ground potential.

6. The apparatus according to any one of claims 1 to 5, wherein the adaptive DEM offset circuit is used to detect the first delay termination by detecting that the voltage of the phase node is pulled above the input voltage.

7. The apparatus according to any one of claims 1 to 6, wherein the offset voltage is approximately zero when the current flowing through the DC-DC converter flows in the positive direction.

8. An apparatus comprising: Any of the devices according to claims 1 to 7; A DC-DC converter, the DC-DC converter including a low-side gate drive and a phase node; and A diode emulation mode (DEM) circuit, wherein the diode emulation mode circuit is used for: Receive offset voltage; and Selectively terminate the on-time of the low-side gate drive to mitigate the second early termination or second delayed termination of the low-side gate drive; The adaptive DEM offset circuit is used to receive the identified polarity of the phase node from the polarity detection circuit.

9. The apparatus of claim 8, wherein the adaptive DEM offset circuit is used to repeatedly adjust the offset voltage incrementally until the polarity of the phase node is reversed, wherein the increment has an equal magnitude.

10. A method, the method comprising: Receive the polarity of the phase node of the DC-DC converter; Based on the received polarity of the phase node, a first early termination or a first delayed termination of the conduction time of the low-side gate drive of the DC-DC converter is detected. as well as An offset voltage is output to selectively terminate the on-time of the low-side gate drive, thereby mitigating a second early termination or a second delayed termination of the on-time of the low-side gate drive, the value of which is based on the polarity of the phase node.

11. The method according to claim 10, wherein the method comprises: After the previous termination of the low-side gate drive, the offset voltage is dynamically adjusted based on the polarity of the phase node.

12. The method according to claim 11, wherein the method comprises: The offset voltage is repeatedly adjusted incrementally until the polarity of the phase node is reversed.

13. The method of claim 12, wherein the increments have equal magnitudes.

14. The method according to any one of claims 10 to 13, wherein detecting the first early termination comprises: The voltage of the phase node is detected to be pulled below ground potential.

15. The method according to any one of claims 10 to 14, wherein detecting the first delayed termination comprises: The voltage of the phase node is pulled above the input voltage.

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