Display device

Abstract

One embodiment of the present application provides a display device including a display region and a non-display region outside the display region, the display device including: a plurality of pixels provided in the display region, each pixel including a transistor and a light-emitting diode electrically connected to the transistor; a connection wiring provided in the display region and electrically connecting adjacent pixels among the plurality of pixels to each other; and a peripheral wiring provided in the non-display region, wherein a modulus of a conductive layer included in the transistor is greater than a modulus of the connection wiring, and the modulus of the connection wiring is greater than a modulus of the peripheral wiring.

Description

Technical Field

[0001] One or more embodiments of this disclosure relate to display devices, such as flexible display devices. Background Technology

[0002] With the development of display devices that visually display electrical signals, various display devices with excellent characteristics such as reduced thickness, light weight, and low power consumption have been introduced. For example, flexible display devices that can be folded or rolled into roll shapes have been introduced. Recently, research and development on stretchable display devices that can be changed into various shapes has been actively carried out. Summary of the Invention Technical issues

[0003] One or more embodiments of this disclosure include display devices capable of simultaneously (e.g., concurrently) ensuring excellent tensile strength while possessing high mechanical stability. However, these aspects are shown by way of example, and the scope of this disclosure is not limited thereto. Solution to the problem

[0004] According to one or more embodiments, a display device includes a display area and a non-display area located outside the display area, wherein the display device includes: a plurality of pixels disposed in the display area, each of the plurality of pixels including a transistor and a light-emitting diode electrically connected to the transistor; connecting lines disposed in the display area, the connecting lines electrically connecting adjacent pixels among the plurality of pixels to each other; and peripheral lines disposed in the non-display area, wherein the modulus of the conductive layer of the transistor is greater than the modulus of the connecting lines, and the modulus of the connecting lines is greater than the modulus of the peripheral lines.

[0005] In this embodiment, the conductive layer, interconnects, and peripheral wires of the transistor may include different materials.

[0006] In an embodiment, the modulus of the conductive layer of the transistor can be greater than 100 GPa and less than 1000 GPa.

[0007] In this embodiment, the conductive layer of the transistor may include a thin metal film.

[0008] In this embodiment, the modulus of the connecting wire can be greater than 1 MPa and less than 100 MPa.

[0009] In this embodiment, the connecting wire may include a metal nanostructure and an elastic polymer.

[0010] In the embodiments, the metal nanostructure may include at least one of silver (Ag) nanoparticles, Ag nanosheets, and Ag nanowires.

[0011] In the embodiments, the elastic polymer may include at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex.

[0012] In an embodiment, the connecting wire may further comprise a carbon-based material, and the carbon-based material includes carbon nanotubes (CNTs), carbon fibers, graphene, graphene oxide, or any combination thereof.

[0013] In an embodiment, the modulus of the outer perimeter can be greater than 1 kPa and less than 100 kPa.

[0014] In one embodiment, the perimeter wire may include liquid metal.

[0015] In the embodiments, the liquid metal may include gallium indium eutectic alloy (EGaIn) or gallium indium tin alloy (Galinstan).

[0016] In an embodiment, each of the transistor's conductive layer, interconnects, and peripheral lines may comprise a metal nanostructure and an elastic polymer.

[0017] In an embodiment, the concentration of metal nanostructures in the conductive layer of the transistor can be greater than the concentration of metal nanostructures in the interconnects, and the concentration of metal nanostructures in the interconnects can be greater than the concentration of metal nanostructures in the peripheral lines.

[0018] In the embodiments, the metal nanostructure may include at least one of Ag nanoparticles, Ag nanosheets and Ag nanowires, and the elastic polymer may include at least one of polydimethylsiloxane (PDMS), polyurethane (PU) and Ecoflex.

[0019] In an embodiment, the connection line may include multiple signal lines and multiple voltage lines, and the multiple signal lines may include at least one of data lines, transmit control lines, scan signal lines, initialization control lines, and bypass control lines.

[0020] In an embodiment, the peripheral lines may include at least one of the following: a drive voltage supply line, a common voltage supply line, a fan-out line, a drive circuit input line, and a drive circuit output line.

[0021] In an embodiment, the display device may further include a gate driving circuit located in a non-display area, wherein the modulus of the conductive layer of the gate driving circuit may be less than the modulus of the connecting line.

[0022] In one embodiment, the conductive layer of the gate drive circuit may include liquid metal.

[0023] According to one or more embodiments, a display device includes a display area and a non-display area located outside the display area, wherein the display device includes: a plurality of pixels disposed in the display area, each of the plurality of pixels including a transistor and a light-emitting diode electrically connected to the transistor; connecting lines disposed in the display area, the connecting lines electrically connecting adjacent pixels among the plurality of pixels to each other; and peripheral lines disposed in the non-display area, wherein the conductive layer of the transistor includes a metal thin film, the connecting lines include a metal nanostructure and an elastic polymer, and the peripheral lines include liquid metal.

[0024] In an embodiment, the modulus of the conductive layer of the transistor can be greater than the modulus of the connecting wire, and the modulus of the connecting wire can be greater than the modulus of the peripheral wire.

[0025] In an embodiment, the modulus of the conductive layer of the transistor is in the range of about 100 GPa to about 1000 GPa, the modulus of the connecting wire is in the range of about 1 megapascal (MPa) to about 100 MPa, and the modulus of the peripheral wire is in the range of about 1 kilopascal (kPa) to about 100 kPa.

[0026] In the embodiments, the metal nanostructure may include at least one of Ag nanoparticles, Ag nanosheets and Ag nanowires, and the elastic polymer may include at least one of polydimethylsiloxane (PDMS), polyurethane (PU) and Ecoflex.

[0027] In the embodiments, the liquid metal may include gallium indium eutectic alloy (EGaIn) or gallium indium tin alloy (Galinstan). Beneficial effects of the invention

[0028] According to embodiments, a display device is provided that can prevent damage caused by stress concentration and can be stretched in various directions. However, these effects are exemplary, and the scope of this disclosure is not limited thereto. Attached Figure Description

[0029] Figure 1 This is a schematic perspective view of a display device according to an embodiment.

[0030] Figure 2a and Figure 2b Each is illustrated in its own diagram. Figure 1 A perspective view of the display device stretched in a first direction.

[0031] Figure 2c It is shown in the diagram. Figure 1 A perspective view of the display device stretched in the second direction.

[0032] Figure 2d It is shown in the diagram. Figure 1 A perspective view of the display device in a stretched state in the first and second directions.

[0033] Figure 2e It is shown in the diagram. Figure 1 A perspective view of the display device stretched upwards from a third-party perspective.

[0034] Figure 3 This is a schematic plan view of a display device according to an embodiment.

[0035] Figure 4a yes Figure 3 This is an enlarged plan view of region A, a portion of the display device according to an embodiment.

[0036] Figure 4b yes Figure 3 This is an enlarged plan view of region A, a portion of the display device according to an embodiment.

[0037] Figure 4c yes Figure 3 This is an enlarged plan view of region A, a portion of the display device according to an embodiment.

[0038] Figure 5 It is a schematic cross-sectional view of the main island-shaped portion and the main bridging portion arranged in the display area of ​​the display device according to the embodiment.

[0039] Figures 6a to 6c Each of the illustrations is an equivalent circuit diagram of a sub-pixel of a display device according to an embodiment.

[0040] Figure 7a and Figure 7b These are schematic cross-sectional views illustrating the light-emitting elements of a display device according to an embodiment.

[0041] Figure 8a This is a schematic structural diagram of a display device according to an embodiment.

[0042] Figure 8b This is a schematic diagram illustrating the gate driving circuit of a display device according to an embodiment.

[0043] Figure 9a This is an enlarged plan view of the main island-shaped portion of the display device according to an embodiment.

[0044] Figure 9b This is a plan view illustrating the arrangement of lines on the main bridging portion of the display device according to an embodiment.

[0045] Figure 9c This is an enlarged plan view of the peripheral island portion and the peripheral bridging portion of the display device according to an embodiment.

[0046] Figure 10 Showing along respectively Figure 9a The line I-I' Figure 9b Line II-II' and Figure 9c The cross-sectional view taken from line III-III'.

[0047] Figure 11 This is a schematic cross-sectional view of a display device according to another embodiment.

[0048] Figure 12 This is a schematic plan view of a display device according to another embodiment.

[0049] Figures 13a to 13g These are schematic perspective views illustrating embodiments of electronic devices including a display device according to an embodiment. Detailed Implementation

[0050] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be illustrated in the accompanying drawings and described in detail in the written description. The effects, aspects, and features of this disclosure, as well as methods of implementation thereof, will be apparent from the embodiments and drawings described in detail below. However, this disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0051] The present disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated. The same reference numerals in the drawings denote the same elements, and therefore their description will not be repeated.

[0052] In the following embodiments, although various elements may be described using terms such as “first”, “second”, etc., these elements are not necessarily limited to the terms above.

[0053] In the following embodiments, the singular form is used in a manner that encompasses the plural form, unless it has a distinctly different meaning in the context.

[0054] In the following embodiments, it will be understood that terms such as “comprising” and “having” are intended to indicate the presence of features or elements disclosed in this disclosure and are not intended to exclude the possibility that one or more other features or elements may be present or added.

[0055] It will be understood that when a layer, region, or element is said to be formed on another layer, region, or element, it can be formed directly or indirectly on that other layer, region, or element. That is, for example, an intermediary layer, region, or element may exist.

[0056] For ease of illustration, the dimensions of the elements in the accompanying drawings may be exaggerated. In other words, because the dimensions and thicknesses of the parts in the drawings are arbitrarily illustrated for ease of illustration, the following embodiments are not limited thereto.

[0057] When an embodiment can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0058] In this disclosure, "A and / or B" may include "A", "B", or "A and B". Additionally, "at least one of A and B" may include "A", "B", or "A and B".

[0059] It will be understood that when a layer, region, or component is referred to as being connected to another layer, region, or component, it can be directly or indirectly connected to that other layer, region, or component. That is, for example, intermediary layers, regions, or components may exist. For example, it will be understood that when a layer, region, or component is referred to as being electrically connected to another layer, region, or component, it can be directly or indirectly electrically connected to that other layer, region, or component. That is, for example, intermediary layers, regions, or components may exist.

[0060] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a general sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0061] In view of the overall content of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0062] Figure 1 This is a schematic perspective view of the display device 1 according to an embodiment. Figure 2a and Figure 2b Each is illustrated in its own diagram. Figure 1 A perspective view of the display device 1 in a stretched state in a first direction. Figure 2c It is shown in the diagram. Figure 1 A perspective view of the display device 1 in a stretched state in the second direction. Figure 2d It is shown in the diagram. Figure 1 A perspective view of the display device 1 in a stretched state in the first and second directions. Figure 2e It is shown in the diagram. Figure 1 The perspective view of the display device 1 in a state where it is stretched upwards from a third party.

[0063] refer to Figure 1The display device 1 may include a display area DA and a non-display area NDA. The display area DA may include multiple pixels. The display device 1 can provide an image by using light emitted by the multiple pixels. The non-display area NDA may be arranged outside the display area DA. The non-display area NDA may completely surround the display area DA.

[0064] The display device 1 can be stretched or contracted in various directions. The display device 1 can be stretched in a first direction (e.g., the x-direction and / or the -x-direction) by external forces applied by an external object or the user. In embodiments, such as... Figure 2a and Figure 2b As shown, the display area DA and / or non-display area NDA of the display device 1 can be stretched in a first direction (e.g., the x-direction and / or the -x-direction). For example, as Figure 2a As shown, the display device 1 can be stretched in the x-direction and the -x-direction, or as... Figure 2b As shown, the display device 1 can be stretched in the x-direction while one side of the display device 1 is fixed.

[0065] The display device 1 can be stretched in a second direction (e.g., the y-direction and / or the -y-direction) by an external force applied by an external object or a user. In an embodiment, such as Figure 2c As shown, the display area DA and / or non-display area NDA of the display device 1 can be stretched in the y-direction and the -y-direction. In another embodiment, the display device 1 can be stretched in the y-direction or the -y-direction while one side of the display device 1 is fixed.

[0066] The display device 1 can be stretched in multiple directions, such as a first direction (e.g., x-direction and / or -x-direction) and a second direction (e.g., y-direction and / or -y-direction), by external forces applied by an external object or a part of a person's body. Figure 2d As shown, the display area DA and / or the non-display area NDA of the display device 1 can be stretched in the ±x and ±y directions.

[0067] The display device 1 can be stretched in a third direction (e.g., the z-direction or the -z-direction (e.g., the thickness direction of the display device 1)) by an external force applied by an external object or a part of a person's body. In an embodiment, Figure 2e A portion of the display device 1 (e.g., a portion of the display area DA) protrudes in the z-direction. In another embodiment, a portion of the display device 1 (e.g., a portion of the display area DA) may protrude in the z-direction (or may be recessed in the -z-direction).

[0068] Figures 2a to 2eThe illustration shows the display device 1 being stretched in a first direction (e.g., the x-direction and / or the -x-direction), a second direction (e.g., the y-direction and / or the -y-direction), and / or a third direction (e.g., the z-direction and / or the -z-direction), but this disclosure is not limited thereto. In another embodiment, the display device 1 may be modified in various ways to, for example, to have two or more axes and to be bent or twisted into an irregular shape.

[0069] Figure 3 This is a schematic plan view of the display device 1 according to an embodiment.

[0070] refer to Figure 3 Various types of components forming the display device 1 are disposed on the substrate 100. The substrate 100 may include a display area DA and a non-display area NDA surrounding the display area DA (e.g., around the display area DA) along the edge or periphery of the display area DA. The display area DA may be covered by an encapsulation member to be protected from external air or moisture.

[0071] Subpixels P are arranged in the display area DA of the substrate 100. Each subpixel P can display an image by using light emitted by a light-emitting element such as a light-emitting diode. Each light-emitting diode can emit, for example, red light, green light, and blue light.

[0072] Each light-emitting diode (LED) can be electrically connected to a sub-pixel circuit, and each sub-pixel circuit can include a transistor and a storage capacitor. Each sub-pixel circuit can be electrically connected to peripheral circuitry arranged in the non-display area (NDA). The peripheral circuitry arranged in the NDA can include a gate drive circuit (GDC), a terminal portion (PAD), and peripheral lines (PW). The peripheral lines (PW) can include a drive voltage supply line (W11), a common voltage supply line (W13), and a fan-out line (FW).

[0073] The gate driving circuit GDC may include a driver configured to provide electrical signals to the gate electrode of each transistor electrically connected to the light-emitting element. Specifically, the gate driving circuit GDC can apply scan signals to each sub-pixel circuit corresponding to each sub-pixel P via gate line GL. Additionally, the gate driving circuit GDC can apply emission control signals to each sub-pixel circuit via emission control line EML. In this case, gate line GL may include the following (refer to the following) Figure 6b and Figure 6c The scan signal line GWL, the initialization control line GIL, and the bypass control line GBL are described.

[0074] The gate driving circuit GDC may include a first gate driving circuit GDC1 and a second gate driving circuit GDC2 disposed on both sides of the display device 1, with the display area DA between them. The second gate driving circuit GDC2 may be located on the opposite side of the first gate driving circuit GDC1, with the display area DA between them, and the second gate driving circuit GDC2 may be substantially parallel to the first gate driving circuit GDC1. Some sub-pixel circuits in the sub-pixel circuit may be electrically connected to the first gate driving circuit GDC1, and other sub-pixel circuits in the sub-pixel circuit may be electrically connected to the second gate driving circuit GDC2. In some embodiments, the second gate driving circuit GDC2 may be omitted.

[0075] The terminal portion PAD can be disposed on one side of the substrate 100. The terminal portion PAD can be exposed by the insulating layer rather than covered by the insulating layer, so as to be connected to the display circuit board 30. The display driving unit 32 can be disposed in the display circuit board 30.

[0076] The display driving unit 32 can generate control signals to be transmitted to the first gate driving circuit GDC1 and the second gate driving circuit GDC2. The display driving unit 32 can generate data signals, and the generated data signals can be transmitted to the sub-pixel circuit of the sub-pixel P via the fan-out line FW and the data line DL connected to the fan-out line FW.

[0077] The display driver unit 32 can output the first power supply voltage VDD (reference) Figures 6a to 6c The second power supply voltage VSS (reference) is supplied to the drive voltage supply line W11 and can be supplied to the drive voltage supply line W11. Figures 6a to 6c The first power supply voltage VDD can be applied to the sub-pixel circuit of sub-pixel P through the drive voltage line PL connected to the drive voltage supply line W11, and the second power supply voltage VSS can be applied to the counter electrode of the light-emitting element connected to the common voltage supply line W13.

[0078] The drive voltage supply line W11 can extend in the x direction from the underside of the display area DA. The common voltage supply line W13 can have a ring shape with one side open to partially surround the display area DA.

[0079] Figure 4a yes Figure 3 This is an enlarged plan view of a portion of region A of the display device 1 according to an embodiment.

[0080] In the display area DA, the display device 1 may include main island-shaped portions 11 spaced apart from each other in a first direction (e.g., x direction or -x direction) and a main bridging portion 12 connecting adjacent main island-shaped portions 11 to each other.

[0081] Each main island portion 11 can be connected to multiple main bridging portions 12. For example, each main island portion 11 can be connected to four main bridging portions 12. Two main bridging portions 12 can be respectively arranged on both sides of the main island portion 11 in a first direction (e.g., the x-direction or the -x-direction), and the remaining two main bridging portions 12 can be respectively arranged on both sides of the main island portion 11 in a second direction (e.g., the y-direction or the -y-direction). In an embodiment, the four main bridging portions 12 can be respectively connected to the four sides of the main island portion 11. Each of the four main bridging portions 12 can be adjacent to a corresponding corner of the main island portion 11.

[0082] Each main bridging portion 12 can be spaced apart from each other by a first opening CS1 located between each main bridging portion 12. In an embodiment, the first opening CS1 having an approximately H-shape and the first opening CS1 having an approximately I-shape obtained by rotating the aforementioned H-shape by 90 degrees can be arranged alternately and repeatedly along a first direction (e.g., the x-direction or the -x-direction) and a second direction (e.g., the y-direction or the -y-direction). The two ends of each main bridging portion 12 are respectively connected to the adjacent main island portion 11, but one side of each main bridging portion 12 can be spaced apart from one side of the adjacent main island portion 11 and / or one side of another main bridging portion 12 by the first opening CS1.

[0083] The display device 1 may include peripheral island-shaped portions 21 spaced apart from each other and peripheral bridging portions 22 connecting adjacent peripheral island-shaped portions 21 to each other in the non-display area NDA.

[0084] Each peripheral island portion 21 may extend in a first direction (e.g., the x-direction or the -x-direction). The peripheral island portions 21 may be spaced apart from each other in a second direction (e.g., the y-direction or the -y-direction) intersecting the first direction (e.g., the x-direction or the -x-direction). Each peripheral island portion 21 may include the above-referenced... Figure 3 The described gate drive circuit is the driver for the GDC.

[0085] The peripheral bridging portion 22 may have a serpentine shape. The length of the peripheral bridging portion 22 may be greater than the shortest distance between adjacent peripheral island portions 21 in a second direction (e.g., the y-direction or the -y-direction). In an embodiment, the peripheral bridging portion 22 may have an approximately omega (Ω) shape protruding toward a first direction (e.g., the x-direction or the -x-direction). The peripheral bridging portions 22 may be arranged between adjacent peripheral island portions 21 and may be spaced apart from each other.

[0086] The peripheral bridging portions 22 between adjacent peripheral island portions 21 can be spaced apart from each other by a second opening CS2. The second opening CS2 and the peripheral bridging portions 22 can be alternately arranged between adjacent peripheral island portions 21 in a first direction. The second opening CS2 can have the same shape. The two ends of each peripheral bridging portion 22 are respectively connected to the adjacent peripheral island portion 21, but one side of each peripheral bridging portion 22 can be spaced apart from one side of the adjacent peripheral island portion 21 and / or one side of another peripheral bridging portion 22 by the second opening CS2.

[0087] Any peripheral island portion 21 arranged in the non-display area NDA can correspond to multiple rows of main island portions 11 arranged in the display area DA. For example, any peripheral island portion 21 arranged in the non-display area NDA can correspond to the main island portion 11 arranged in the i-th row and the main island portion 11 arranged in the (i+1)-th row in the display area DA (where i is a positive number greater than 0). Figure 4a A peripheral island portion 21 is shown corresponding to two rows of main island portions 11, but this disclosure is not limited thereto. In another embodiment, any one of the peripheral island portions 21 arranged in the non-display area NDA may correspond to n rows of main island portions 11 arranged in the display area DA (where n is a positive number greater than 3).

[0088] The non-display area NDA may include a first sub-non-display area SNDA1 in which the aforementioned peripheral island portion 21 and peripheral bridging portion 22 are disposed, and a second sub-non-display area SNDA2 located between the first sub-non-display area SNDA1 and the display area DA. A sub-bridging portion 23 connecting the display area DA to the first sub-non-display area SNDA1 may be disposed in the second sub-non-display area SNDA2. One end of the sub-bridging portion 23 may be connected to the peripheral island portion 21 and / or the peripheral bridging portion 22, and the other end of the sub-bridging portion 23 may be connected to the main island portion 11 and / or the main bridging portion 12.

[0089] The sub-bridging portion 23 may have a serpentine shape. In an embodiment, the shape of the sub-bridging portion 23 may differ from the shape of each of the main bridging portion 12 and the peripheral bridging portion 22. In an embodiment, such as Figure 4aAs shown, the sub-bridging portion 23 may have an approximately omega (Ω) shape protruding toward a second direction (e.g., the y-direction or the -y-direction). Adjacent sub-bridging portions 23 arranged in the second direction (e.g., the y-direction or the -y-direction) may have a symmetrical structure; for example, one of adjacent sub-bridging portions 23 arranged along the second direction (e.g., the y-direction or the -y-direction) may protrude in the y-direction, and the other may protrude in the -y-direction. A repeating structure of a third opening portion CS3 and a fourth opening portion CS4 with different shapes may be provided between the sub-bridging portions 23. The width of the sub-bridging portion 23 may differ from the width of the main bridging portion 12 and the width of the peripheral bridging portion 22. In an embodiment, the width of the sub-bridging portion 23 may be greater than the width of the main bridging portion 12 and less than the width of the peripheral bridging portion 22.

[0090] Figure 4a The diagram shows that the peripheral island portion 21 and peripheral bridging portion 22 of the non-display area NDA have different shapes from the main island portion 11 and main bridging portion 12 of the display area DA, respectively. In another embodiment, the peripheral island portion 21 and peripheral bridging portion 22 of the non-display area NDA may have the same shape as the main island portion 11 and main bridging portion 12 of the display area DA, respectively.

[0091] Figure 4b yes Figure 3 This is an enlarged plan view of a portion of region A of the display device 1 according to an embodiment.

[0092] refer to Figure 4b The display device 1 may include main island-shaped portions 11 spaced apart from each other in the display area DA and main bridging portions 12 spaced apart from each other through a first opening portion CS1 and connecting adjacent main island-shaped portions 11 to each other. Figure 4b The structure of the display area DA can be referenced above. Figure 4a The structure of the described display area DA is the same.

[0093] The display device 1 may include a peripheral island portion 21 and a peripheral bridging portion 22 disposed in the non-display area NDA. In an embodiment, the peripheral island portion 21 and the peripheral bridging portion 22 may have substantially the same shape as the main island portion 11 and the main bridging portion 12, respectively.

[0094] The peripheral island portions 21 may be spaced apart from each other in a first direction (e.g., x-direction or -x-direction) and a second direction (e.g., y-direction or -y-direction) within a non-display area (e.g., non-display area NDA). Peripheral bridging portions 22 may be connected to adjacent peripheral island portions 21 respectively. Each peripheral bridging portion 22 may be spaced apart from each other by a second opening CS2 located between each peripheral bridging portion 22.

[0095] The second opening portion CS2 may have a shape substantially the same as that of the first opening portion CS1. For example, second opening portions CS2 with an approximate H shape and second opening portions CS2 with an approximate I shape may be arranged alternately and repeatedly in the non-display area (e.g., non-display area NDA). The two ends of each peripheral bridging portion 22 are respectively connected to the adjacent peripheral island portion 21, but one side of each peripheral bridging portion 22 may be spaced apart from one side of the adjacent peripheral island portion 21 and / or one side of another peripheral bridging portion 22 by the second opening portion CS2.

[0096] Each peripheral island portion 21 can be connected to four peripheral bridging portions 22. Each peripheral island portion 21 may include the above reference. Figure 3 The described gate drive circuit is the driver for the GDC.

[0097] Any outer island portion 21 arranged in a row in the non-display area NDA can correspond to any main island portion 11 arranged in a row in the display area DA. For example, an outer island portion 21 arranged in the i-th row along a first direction (e.g., the x-direction or the -x-direction) in the non-display area NDA can correspond to a main island portion 11 arranged in the same row (e.g., the i-th row) in the display area DA (where i is a positive number greater than 0).

[0098] Display device 1 may include a sub-bridging portion 23 disposed in a second sub-non-display area SNDA2 connecting a display area DA to a first sub-non-display area SNDA1. The non-display area NDA may include a first sub-non-display area SNDA1 in which a peripheral island portion 21 and a peripheral bridging portion 22 are disposed, and a second sub-non-display area SNDA2 including the sub-bridging portion 23 and located between the first sub-non-display area SNDA1 and the display area DA. The sub-bridging portion 23 may be substantially the same as the main bridging portion 12 and the peripheral bridging portion 22. For example, the width of the sub-bridging portion 23 may be equal to the width of the main bridging portion 12 and the width of the peripheral bridging portion 22.

[0099] Figure 4c yes Figure 3 This is an enlarged plan view of a portion of region A of the display device 1 according to an embodiment.

[0100] refer to Figure 4c The display device 1 may include, in the display area DA, main island-shaped portions 11 spaced apart from each other in a first direction (e.g., x direction or -x direction) and a main bridging portion 12 connecting adjacent main island-shaped portions 11 to each other.

[0101] Each main bridging portion 12 can be arranged to be spaced apart from each other by a first opening CS1 located between each main bridging portion 12. The main bridging portions 12 can have a serpentine shape. For example, as... Figure 4c As shown, the main bridging portion 12 may have an approximate “letter S” shape.

[0102] Each main island section 11 can be connected to multiple main bridging sections 12. For example, each main island section 11 can be connected to four main bridging sections 12. Two main bridging sections 12 can be arranged on either side of the main island section 11 in a first direction (e.g., the x-direction or the -x-direction), and the remaining two main bridging sections 12 can be arranged on either side of the main island section 11 in a second direction (e.g., the y-direction or the -y-direction). The four main bridging sections 12 can be connected to the four sides of the main island section 11. Each of the four main bridging sections 12 can be adjacent to a corresponding corner of the main island section 11.

[0103] The display device 1 can be used in a non-display area (e.g., Figure 4c The non-display area (NDA) shown includes peripheral island-shaped portions 21 spaced apart from each other in a first direction (e.g., x direction or -x direction) and a peripheral bridging portion 22 connecting adjacent peripheral island-shaped portions 21 to each other.

[0104] Each peripheral bridging portion 22 can be arranged to be spaced apart from each other by a second opening CS2 located between each peripheral bridging portion 22. The peripheral bridging portions 22 can have a serpentine shape. For example, as Figure 4c As shown, the outer bridging portion 22 may have an approximate "letter S" shape. The size and / or width of the outer bridging portion 22 may differ from the size and / or width of the main bridging portion 12. For example, the size and / or width of the outer bridging portion 22 may be larger than the size and / or width of the main bridging portion 12. The radius of curvature of the rounded portion of the outer bridging portion 22 may differ from the radius of curvature of the rounded portion of the main bridging portion 12. For example, the radius of curvature of the rounded portion of the outer bridging portion 22 may be larger than the radius of curvature of the rounded portion of the main bridging portion 12.

[0105] Each peripheral island portion 21 can be connected to multiple peripheral bridging portions 22. Each peripheral island portion 21 can be connected to four peripheral bridging portions 22. Two peripheral bridging portions 22 can be respectively arranged on both sides of the peripheral island portion 21 in a first direction (e.g., the x-direction or the -x-direction), and the remaining two peripheral bridging portions 22 can be respectively arranged on both sides of the peripheral island portion 21 in a second direction (e.g., the y-direction or the -y-direction). In an embodiment, the four peripheral bridging portions 22 can be respectively connected to the four sides of the peripheral island portion 21. Each peripheral bridging portion 22 can be connected to the central portion of the corresponding side of the peripheral island portion 21.

[0106] Any row of peripheral island portions 21 arranged in the non-display area NDA can correspond to multiple rows of main island portions 11 arranged in the display area DA. For example, any row of peripheral island portions 21 arranged in the non-display area NDA can correspond to the main island portions 11 arranged in the i-th row of the display area DA and the main island portions 11 arranged in the (i+1)-th row of the display area DA. In another embodiment, any row of peripheral island portions 21 can correspond to n rows of main island portions 11 (where n is a positive number greater than 3).

[0107] The non-display area NDA may include a first sub-non-display area SNDA1 in which the aforementioned peripheral island portion 21 and peripheral bridging portion 22 are disposed, and a second sub-non-display area SNDA2 located between the first sub-non-display area SNDA1 and the display area DA. A sub-bridging portion 23 connecting the display area DA to the first sub-non-display area SNDA1 may be disposed in the second sub-non-display area SNDA2. One end of the sub-bridging portion 23 may be connected to the peripheral island portion 21, and the other end of the sub-bridging portion 23 may be connected to the main island portion 11. For example, one end of the sub-bridging portion 23 may be connected to the central portion of one side of the peripheral island portion 21, and the other end of the sub-bridging portion 23 may be connected to the central portion of one end of the main island portion 11.

[0108] The sub-bridging portion 23 may have a serpentine shape. In an embodiment, the shape of the sub-bridging portion 23 may differ from the shape of each of the main bridging portion 12 and the peripheral bridging portion 22. The width of the sub-bridging portion 23 may differ from the width of the main bridging portion 12 and the width of the peripheral bridging portion 22. The width of the sub-bridging portion 23 may be greater than the width of the main bridging portion 12 and less than the width of the peripheral bridging portion 22. A third opening portion CS3 and a fourth opening portion CS4 with different shapes may be alternately arranged between the sub-bridging portions 23 along a second direction (e.g., the y-direction or the -y-direction).

[0109] Figure 5It is a schematic cross-sectional view of the main island-shaped portion and the main bridging portion arranged in the display area of ​​the display device according to the embodiment.

[0110] refer to Figure 5 The main island portion 11 and the main bridging portion 12, arranged in the display area DA, may be spaced apart from each other, with a first opening portion CS1 between them. The main island portion 11 may include light-emitting elements (LEDs) and corresponding circuitry (e.g., pixel driving circuit units PC) electrically connected to and configured to drive the LEDs, and the main bridging portion 12 may include connection lines WL electrically connected to the pixel driving circuit units PCs respectively arranged in adjacent main island portions 11.

[0111] When observing the main island-shaped portion 11, a buffer layer 111 comprising an inorganic insulating material can be disposed on the substrate 100, and a pixel driving circuit unit PC can be disposed on the buffer layer 111. An insulating layer ISL comprising an inorganic insulating material and / or an organic insulating material can be disposed between the pixel driving circuit unit PC and the light-emitting element LED. The light-emitting element LED can be disposed on the insulating layer ISL and can be electrically connected to the corresponding pixel driving circuit unit PC. The light-emitting element LED can emit light of different colors or the same color. In an embodiment, the light-emitting element LED can emit red light, green light, and blue light, respectively. In some embodiments, the light-emitting element LED can emit white light. In another embodiment, the light-emitting element LED can emit red light, green light, blue light, and white light, respectively.

[0112] Substrate 100 may comprise polymeric resins such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. In one embodiment, substrate 100 may be a single layer comprising the aforementioned polymeric resin. In another embodiment, substrate 100 may have a multilayer structure comprising a base layer containing the aforementioned polymeric resin and a barrier layer comprising an inorganic insulating material. Substrate 100 comprising polymeric resin may be flexible, rollable, or bendable.

[0113] In an embodiment, Figure 5 The illustration shows three pixel driving circuit units (PCs) arranged in each main island portion 11 and three light-emitting elements (LEDs) respectively connected to these pixel driving circuit units (PCs), but the present disclosure is not limited thereto. In another embodiment, the number of each of the pixel driving circuit units (PCs) and light-emitting elements (LEDs) arranged in the main island portion 11 may be one, two, or more than four.

[0114] The encapsulation layer 300 can be disposed on the light-emitting element (LED) and can protect the LED from external forces and / or moisture penetration. The encapsulation layer 300 may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer 300 may include a structure in which inorganic encapsulation layers comprising inorganic insulating materials, organic encapsulation layers comprising organic insulating materials, and inorganic encapsulation layers comprising inorganic insulating materials are stacked. In another embodiment, the encapsulation layer 300 may include an organic material such as a resin. In some embodiments, the encapsulation layer 300 may include urethane epoxy acrylate. The encapsulation layer 300 may include a photosensitive material (e.g., a material such as a photoresist).

[0115] When observing the main bridging portion 12, an insulating layer ISL comprising organic insulating material may be disposed on the substrate 100. When the display device 1 is stretched, the relatively deformed main bridging portion 12 differs from the main island portion 11 and may not include a layer containing easily broken inorganic insulating material.

[0116] In one embodiment, the substrate 100 corresponding to the main bridging portion 12 may have the same stacking structure as the substrate 100 corresponding to the main island portion 11. In another embodiment, the substrate 100 corresponding to the main bridging portion 12 and the substrate 100 corresponding to the main island portion 11 may be polymer resin layers formed together in the same process. In yet another embodiment, the substrate 100 corresponding to the main bridging portion 12 may have a different stacking structure than the substrate 100 corresponding to the main island portion 11. In some embodiments, the substrate 100 corresponding to the main island portion 11 may have a multilayer structure including a base layer comprising a polymer resin and a barrier layer comprising an inorganic insulating material, and the substrate 100 corresponding to the main bridging portion 12 may have a structure without a polymer resin layer comprising an inorganic insulating material.

[0117] As described above, the connection line WL of the main bridging portion 12 can be a signal line (e.g., a gate line or data line, etc.) for providing electrical signals to transistors included in the pixel driving circuit unit PC of the main island portion 11, or it can be a voltage line (e.g., a driving voltage line or an initialization voltage line, etc.) for providing voltage. The encapsulation layer 300 may also be disposed in the main bridging portion 12. In another embodiment, the encapsulation layer 300 may not be present in the main bridging portion 12.

[0118] refer to Figures 4a to 4c as well as Figure 5 The substrate 100 corresponding to the main island portion 11 and the substrate 100 corresponding to the main bridging portion 12 can be connected to each other. In other words, previously in Figures 4a to 4c The floor plan shown can be compared with Figure 5The plan view of the substrate 100 is substantially the same. In other words, the substrate 100 may include a region corresponding to the main island portion 11, a region corresponding to the main bridging portion 12, and an opening 100OP1 having the same shape as the first opening portion CS1.

[0119] Similarly, the encapsulation layer 300 corresponding to the main island portion 11 and the encapsulation layer 300 corresponding to the main bridging portion 12 can be connected to each other. For example, previously in Figures 4a to 4c The plan view shown may be substantially the same as the plan view of the encapsulation layer 300. In other words, the encapsulation layer 300 may include a region corresponding to the main island portion 11, a region corresponding to the main bridging portion 12, and an opening 300OP1 having the same shape as the first opening portion CS1.

[0120] The circuit light-emitting element layer 200 between the substrate 100 and the encapsulation layer 300 may include a buffer layer 111, a pixel driving circuit unit PC, connecting lines WL, an insulating layer ISL, and a light-emitting element LED. Similar to the substrate 100, previously in Figures 4a to 4c The plan view shown may be substantially the same as the plan view of the circuit light-emitting element layer 200. In other words, the circuit light-emitting element layer 200 may include an opening 200OP1 having the same shape as the first opening portion CS1.

[0121] Figures 6a to 6c Each of the illustrations is an equivalent circuit diagram of a sub-pixel of the display device 1 according to an embodiment.

[0122] refer to Figure 6a The light-emitting element (LED) corresponding to the sub-pixel can be electrically connected to the pixel driving circuit unit PC, and the pixel driving circuit unit PC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The pixel driving circuit unit PC can be electrically connected to signal lines and voltage lines. The signal lines can include data lines DL and gate lines GL such as scan signal lines GWL (see reference). Figure 3 ), and the voltage line may include a first voltage line VDDL. In this case, the first voltage line VDDL can be connected to the drive voltage supply line W11 (see reference). Figure 3 ), and the second voltage line VSSL can be connected to the common voltage supply line W13 (reference). Figure 3 ).

[0123] The second transistor T2 can be electrically connected to the scan signal line GWL and the data line DL. The scan signal line GWL can provide the scan signal GW to the gate electrode of the second transistor T2. The second transistor T2 can be configured to transmit the data signal Dm input from the data line DL to the first transistor T1 according to the scan signal GW input from the scan signal line GWL.

[0124] The storage capacitor Cst can be electrically connected to the second transistor T2 and the first voltage line VDDL, and can store a voltage corresponding to the difference between the voltage received from the second transistor T2 and the first power supply voltage VDD supplied by the first voltage line VDDL.

[0125] The first transistor T1 is a driving transistor capable of controlling the driving current flowing through the light-emitting element LED. One electrode of the first transistor T1 can be connected to the first voltage line VDDL and the storage capacitor Cst, and the other electrode of the first transistor T1 can be connected to the light-emitting element LED. The first transistor T1 can control the driving current flowing from the first voltage line VDDL through the light-emitting element LED according to the voltage value stored in the storage capacitor Cst. The light-emitting element LED can emit light with a specific brightness according to the driving current. The first electrode of the light-emitting element LED can be electrically connected to the first transistor T1, and the second electrode of the light-emitting element LED can be electrically connected to the second voltage line VSSL that provides the second power supply voltage VSS.

[0126] although Figure 6a The illustration shows a pixel driving circuit unit PC comprising two transistors and a storage capacitor, but in another embodiment, the pixel driving circuit unit PC may include three or more transistors.

[0127] refer to Figure 6b The pixel driving circuit unit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0128] The pixel driving circuit unit PC is electrically connected to signal lines and voltage lines. Signal lines may include data lines DL, scan signal lines GWL, bypass control lines GBL, initialization control lines GIL, and gate lines GL such as the transmit control line EML (see reference). Figure 3 The voltage lines may include a first initialization voltage line VIL1 and a second initialization voltage line VIL2, a first voltage line VDDL, and a second voltage line VSSL. At this time, the first voltage line VDDL can be connected to the drive voltage supply line W11 (see reference). Figure 3 ), and the second voltage line VSSL can be connected to the common voltage supply line W13 (reference). Figure 3 ).

[0129] The first voltage line VDDL transmits the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 transmits the first initialization voltage Vint, which initializes the first transistor T1, to the pixel driving circuit unit PC. The second initialization voltage line VIL2 transmits the second initialization voltage Vaint, which initializes the first electrode of the light-emitting element LED, to the pixel driving circuit unit PC.

[0130] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5, and can be electrically connected to the light-emitting element LED via the sixth transistor T6. The first transistor T1 acts as a driving transistor and receives the data signal Dm according to the switching operation of the second transistor T2 to supply driving current to the light-emitting element LED.

[0131] The second transistor T2 is a data write transistor electrically connected to the scan signal line GWL and the data line DL. The second transistor T2 can be connected between the data line DL and the first node N1, which is connected to one electrode of the first transistor T1. The second transistor T2 is electrically connected to the first voltage line VDDL via a fifth transistor T5. The second transistor T2 is turned on according to the scan signal GW received through the scan signal line GWL and performs a switching operation to provide the data signal Dm transmitted through the data line DL to the first node N1.

[0132] The third transistor T3 is electrically connected to the scan signal line GWL and is electrically connected to the light-emitting element LED via the sixth transistor T6. The third transistor T3 can be connected between the gate electrode of the first transistor T1 and another electrode. The third transistor T3 can be turned on according to the scan signal GW received through the scan signal line GWL to connect the first transistor T1 diode.

[0133] The fourth transistor T4 is the first initialization transistor electrically connected to the initialization control line GIL and the first initialization voltage line VIL1. The fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the first initialization voltage line VIL1. The fourth transistor T4 is turned on according to the initialization control signal GI received through the initialization control line GIL to transmit the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1, thereby initializing the voltage of the gate electrode of the first transistor T1. The initialization control signal GI can correspond to a scan signal from another pixel driving circuit unit arranged in the row preceding the corresponding pixel driving circuit unit PC.

[0134] The fifth transistor T5 can be an operation control transistor, and the sixth transistor T6 can be an emitter control transistor. The fifth transistor T5 and the sixth transistor T6 are electrically connected to the emitter control line EML at their respective gate electrodes, and are concurrently (e.g., simultaneously) turned on according to the emitter control signal EM received through the emitter control line EML to form a current path, such that the drive current can flow in the direction from the first voltage line VDDL to the light-emitting element LED.

[0135] The seventh transistor T7 is a second initialization transistor that can be electrically connected to the bypass control line GBL, the second initialization voltage line VIL2, and the first electrode of the sixth transistor T6 or the light-emitting element LED. The seventh transistor T7 can be turned on according to the bypass control signal GB received through the bypass control line GBL, and can transmit the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting element LED to initialize the first electrode of the light-emitting element LED.

[0136] The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. The first electrode CE1 is electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 is electrically connected to the first voltage line VDDL. The storage capacitor Cst can maintain the voltage applied to the gate electrode of the first transistor T1 by storing and holding a voltage corresponding to the voltage difference between the first voltage line VDDL and the gate electrode of the first transistor T1.

[0137] refer to Figure 6c The pixel driving circuit unit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a storage capacitor Cst, and an auxiliary capacitor Ca.

[0138] The pixel driving circuit unit PC is electrically connected to signal lines and voltage lines. Signal lines may include data lines DL, scan signal lines GWL, bypass control lines GBL, initialization control lines GIL, and gate lines such as transmit control lines EML. Voltage lines may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, a hold voltage line VSL, a first voltage line VDDL, and a second voltage line VSSL. The first voltage line VDDL can be connected to the drive voltage supply line W11 (see reference). Figure 3 ), and the second voltage line VSSL can be connected to the common voltage supply line W13 (reference). Figure 3 ).

[0139] The first voltage line VDDL transmits the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 transmits the first initialization voltage Vint, which initializes the first transistor T1, to the pixel driving circuit unit PC. The second initialization voltage line VIL2 transmits the second initialization voltage Vaint, which initializes the first electrode of the light-emitting element LED, to the pixel driving circuit unit PC. During the initialization and data write intervals, the holding voltage line VSL provides the holding voltage VSUS to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst) and the auxiliary capacitor Ca.

[0140] The first transistor T1 can be connected between the first node N1 and the sixth transistor T6. The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8, and can be electrically connected to the light-emitting element LED via the sixth transistor T6. The first transistor T1 can be used as a driving transistor, and can receive the data signal Dm via the first node N1 according to the switching operation of the second transistor T2, so as to supply driving current to the light-emitting element LED.

[0141] The second transistor T2 can be connected between the data line DL and the first node N1. The second transistor T2 is electrically connected to the scan signal line GWL and the data line DL, and is electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8. The second transistor T2 is turned on in response to the scan signal GW received through the scan signal line GWL, and performs a switching operation to transmit the data signal Dm transmitted through the data line DL to the first node N1.

[0142] The third transistor T3 can be connected between the gate electrode of the first transistor T1 and another electrode connected to the sixth transistor T6. The third transistor T3 is electrically connected to the scan signal line GWL and is electrically connected to the light-emitting element LED via the sixth transistor T6. The third transistor T3 can be turned on in response to the scan signal GW received through the scan signal line GWL to connect the diode of the first transistor T1, thereby compensating for the threshold voltage of the first transistor T1.

[0143] A fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the first initialization voltage line VIL1. The fourth transistor T4 is electrically connected to the initialization control line GIL and the first initialization voltage line VIL1, and is turned on in response to an initialization control signal GI received via the initialization control line GIL to transmit a first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1, thereby initializing the voltage at the gate electrode of the first transistor T1. The initialization control signal GI can correspond to a scan signal from another pixel driving circuit unit arranged in the row preceding the corresponding pixel driving circuit unit PC.

[0144] The fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are electrically connected to the emitter control line EML and are concurrently (e.g., simultaneously) turned on in response to the emitter control signal EM received through the emitter control line EML to form a current path, such that the drive current can flow in the direction from the first voltage line VDDL to the light-emitting element LED.

[0145] The seventh transistor T7 is a second initialization transistor that can be electrically connected to the bypass control line GBL, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 is turned on in response to the bypass control signal GB received through the bypass control line GBL to transmit the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting element LED, thereby initializing the first electrode of the light-emitting element LED.

[0146] The ninth transistor T9 can be electrically connected to the bypass control line GBL, can be electrically connected to the second electrode CE2 of the storage capacitor Cst via the second node N2, and can be electrically connected to the holding voltage line VSL. During the initialization and data write intervals, the ninth transistor T9 can be turned on in response to the bypass control signal GB received via the bypass control line GBL, and can transmit the holding voltage VSUS to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst).

[0147] The eighth transistor T8 and the ninth transistor T9 can each be electrically connected to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst). In some embodiments, during the initialization and data write intervals, the eighth transistor T8 can be turned off and the ninth transistor T9 can be turned on, and during the emitt interval, the eighth transistor T8 can be turned on and the ninth transistor T9 can be turned off. Because the voltage VSUS is maintained and transmitted to the second node N2 during the initialization and data write intervals, the brightness uniformity of the display device according to the voltage drop across the first voltage line VDDL (e.g., long-range uniformity (LRU)) can be improved.

[0148] The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. The first electrode CE1 is electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 is electrically connected to the eighth transistor T8 and the ninth transistor T9 via the second node N2.

[0149] An auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the holding voltage line VSL, and the first electrode of the light-emitting element LED. When the seventh transistor T7 and the ninth transistor T9 are turned on, the auxiliary capacitor Ca can store and maintain a voltage corresponding to the voltage difference between the first electrode of the light-emitting element LED and the holding voltage line VSL, thereby reducing or preventing the problem of increased black brightness when the sixth transistor T6 is turned off.

[0150] Figure 7a This is a schematic cross-sectional view illustrating the light-emitting element of a display device according to an embodiment.

[0151] refer to Figure 7a According to an embodiment, the light-emitting element may include an organic light-emitting diode 220 comprising organic materials. The organic light-emitting diode 220 may include a first electrode 221 disposed on an insulating layer, a second electrode 225 facing the first electrode 221, and an emitting layer 223 disposed between the first electrode 221 and the second electrode 225. A first functional layer 222 may be disposed between the first electrode 221 and the emitting layer 223, and a second functional layer 224 may be disposed between the emitting layer 223 and the second electrode 225.

[0152] The edge of the first electrode 221 may be covered by a dam layer BKL comprising an insulating material. The dam layer BKL may include an opening B-OP that overlaps with the central portion of the first electrode 221.

[0153] The first electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). In another embodiment, the first electrode 221 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or mixtures thereof. In another embodiment, the first electrode 221 may further include a layer comprising ITO, IZO, ZnO, or In2O3 above / below the aforementioned reflective layer.

[0154] The emitting layer 223 may include a polymeric organic material or a low molecular weight organic material that emits light of a specific color. The first functional layer 222 may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer 224 may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0155] The second electrode 225 may include a conductive material with a low work function. For example, the second electrode 225 may include a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the second electrode 225 may further include a layer such as ITO, IZO, ZnO, or In2O3 above the (semi-)transparent layer comprising the above-described material.

[0156] Figure 7b This is a schematic cross-sectional view illustrating the light-emitting element of a display device according to an embodiment.

[0157] refer to Figure 7b According to the embodiments, the light-emitting element may include an inorganic light-emitting diode 230 comprising inorganic materials. The inorganic light-emitting diode 230 may include a first semiconductor layer 231, a second semiconductor layer 232, an intermediate layer 233 located between the first semiconductor layer 231 and the second semiconductor layer 232, a first electrode 235 electrically connected to the first semiconductor layer 231, and a second electrode 238 electrically connected to the second semiconductor layer 232. The first electrode 235 and the second electrode 238 of the inorganic light-emitting diode 230 may be electrically connected to a first electrode pad 241 and a second electrode pad 242 disposed on the same layer, respectively.

[0158] In some embodiments, the first semiconductor layer 231 may include a p-type semiconductor layer. The p-type semiconductor layer may be a semiconductor material selected from GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN, having the compositional formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and may be doped with p-type dopants such as Mg, Zn, Ca, Sr, or Ba.

[0159] The second semiconductor layer 232 may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be a semiconductor material selected from GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN, having the compositional formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and may be doped with n-type dopants such as Si, Ge, or Sn.

[0160] The intermediate layer 233 is the region where electrons and holes recombine. As electrons and holes recombine, the intermediate layer 233 can transition to a lower energy level and generate light with the corresponding wavelength. For example, the intermediate layer 233 can be formed using a semiconductor material comprising the compositional formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multiple quantum well (MQW) structure. Alternatively, the intermediate layer 233 can also comprise a quantum wire structure or a quantum dot structure.

[0161] Figure 7b The illustration shows a first semiconductor layer 231 comprising a p-type semiconductor layer and a second semiconductor layer 232 comprising an n-type semiconductor layer, but the present disclosure is not limited thereto. In another embodiment, the first semiconductor layer 231 may comprise an n-type semiconductor layer, and the second semiconductor layer 232 may comprise a p-type semiconductor layer.

[0162] Figure 8a This is a schematic structural diagram of a display device according to an embodiment.

[0163] refer to Figure 8a Multiple sub-pixels P and signal lines that can apply electrical signals to the multiple sub-pixels P can be located in the display area DA. The signal lines that can apply electrical signals to the sub-pixels P can include multiple data lines DL, multiple transmit control lines EML, multiple scan signal lines GWL, multiple initialization control lines GIL, and multiple bypass control lines GBL.

[0164] The driving circuit DC, which supplies the signal for driving the sub-pixel P, can be located outside the display area DA. The driving circuit DC may include a data driving circuit DDC and a gate driving circuit GDC (see reference). Figure 3 ), and the gate drive circuit GDC (reference) Figure 3 This may include a transmit control drive circuit EMDC, a bypass drive circuit GBDC, an initialization drive circuit GIDC, and a data write drive circuit GWDC. The data drive circuit DDC may be arranged adjacent to the lower side of the display area DA to connect to the data line DL and output the data signal Dm to the data line DL.

[0165] The transmit control driver circuit EMDC, bypass driver circuit GBDC, initialization driver circuit GIDC, and data write driver circuit GWDC can be arranged adjacent to the left or right side of the display area DA. The transmit control driver circuit EMDC can be connected to the transmit control line EML and can output the transmit control signal EM via the transmit control line EML. The bypass driver circuit GBDC can be connected to the bypass control line GBL and can output the bypass control signal GB via the bypass control line GBL. The initialization driver circuit GIDC can be connected to the initialization control line GIL and can output the initialization control signal GI via the initialization control line GIL. The data write driver circuit GWDC can be connected to the scan signal line GWL to output the scan signal GW.

[0166] Figure 8b This is a schematic diagram of a gate drive circuit according to an embodiment. Figure 8b This is a schematic diagram illustrating the structure of the transmit control drive circuit EMDC, bypass drive circuit GBDC, initialization drive circuit GIDC, and data write drive circuit GWDC.

[0167] refer to Figure 8b The transmit control drive circuit EMDC can be implemented as a shift register comprising multiple transmit control stages (e.g., a first transmit control stage EMST1, a second transmit control stage EMST2, a third transmit control stage EMST3, ...). Each of the transmit control stages (e.g., the first transmit control stage EMST1, the second transmit control stage EMST2, the third transmit control stage EMST3, ...) can be a sub-drive circuit. Each of the transmit control stages (e.g., the first transmit control stage EMST1, the second transmit control stage EMST2, the third transmit control stage EMST3, ...) can be connected to a corresponding transmit control line EML and can output a transmit control signal EM via the corresponding transmit control line EML. The first transmit control stage EMST1 can output the transmit control signal EM in response to an external start signal STV, and each of the remaining transmit control stages (e.g., the second transmit control stage EMST2, the third transmit control stage EMST3, ...) can receive a carry signal CR output from the previous stage as a start signal. Each of the transmit control stages (e.g., the first transmit control stage EMST1, the second transmit control stage EMST2, the third transmit control stage EMST3, ...) can be connected to multiple input lines IL arranged outside the transmit control stages (e.g., the first transmit control stage EMST1, the second transmit control stage EMST2, the third transmit control stage EMST3, ...).

[0168] The bypass drive circuit GBDC can be implemented as a shift register comprising multiple bypass stages (e.g., first bypass stage GBST1, second bypass stage GBST2, third bypass stage GBST3, ...). Each of the bypass stages (e.g., first bypass stage GBST1, second bypass stage GBST2, third bypass stage GBST3, ...) can be a sub-drive circuit. Each of the bypass stages (e.g., first bypass stage GBST1, second bypass stage GBST2, third bypass stage GBST3, ...) can be connected to a corresponding bypass control line GBL and can output a bypass control signal GB via the corresponding bypass control line GBL. The first bypass stage GBST1 can output the bypass control signal GB in response to an external start signal STV, and each of the remaining bypass stages (e.g., second bypass stage GBST2, third bypass stage GBST3, ...) can receive a carry signal CR output from the previous stage as a start signal. Each of the bypass stages (e.g., the first bypass stage GBST1, the second bypass stage GBST2, the third bypass stage GBST3, ...) can be connected to multiple input lines IL arranged outside the bypass stages (e.g., the first bypass stage GBST1, the second bypass stage GBST2, the third bypass stage GBST3, ...).

[0169] The initialization driver circuit GIDC can be implemented as a shift register comprising multiple initialization stages (e.g., first initialization stage GIST1, second initialization stage GIST2, third initialization stage GIST3, ...). Each of the initialization stages (e.g., first initialization stage GIST1, second initialization stage GIST2, third initialization stage GIST3, ...) can be a sub-driver circuit. Each of the initialization stages (e.g., first initialization stage GIST1, second initialization stage GIST2, third initialization stage GIST3, ...) can be connected to a corresponding initialization control line GIL and can output an initialization control signal GI via the corresponding initialization control line GIL. The first initialization stage GIST1 can output the initialization control signal GI in response to an external start signal STV, and each of the remaining initialization stages (e.g., second initialization stage GIST2, third initialization stage GIST3, ...) can receive the carry signal CR output from the previous stage as a start signal. Each of the initialization stages (e.g., first initialization stage GIST1, second initialization stage GIST2, third initialization stage GIST3, ...) can be connected to multiple input lines IL arranged outside the initialization stages (e.g., first initialization stage GIST1, second initialization stage GIST2, third initialization stage GIST3, ...).

[0170] The data write driver circuit GWDC can be implemented as a shift register comprising multiple data write stages (e.g., a first data write stage GWST1, a second data write stage GWST2, a third data write stage GWST3, ...). Each of the data write stages (e.g., a first data write stage GWST1, a second data write stage GWST2, a third data write stage GWST3, ...) can be a sub-driver circuit. Each of the data write stages (e.g., a first data write stage GWST1, a second data write stage GWST2, a third data write stage GWST3, ...) can be connected to a corresponding scan signal line GWL and can output a scan signal GW via the corresponding scan signal line GWL. The first data write stage GWST1 can output the scan signal GW in response to an external start signal STV, and each of the remaining data write stages (e.g., a second data write stage GWST2, a third data write stage GWST3, ...) can receive a carry signal CR output from the previous stage as a start signal. Each of the data write stages (e.g., the first data write stage GWST1, the second data write stage GWST2, the third data write stage GWST3, ...) can be connected to multiple input lines IL arranged outside the data write stages (e.g., the first data write stage GWST1, the second data write stage GWST2, the third data write stage GWST3, ...).

[0171] Multiple input lines (IL) can be signal lines comprising multiple voltage lines and multiple clock lines. For ease of illustration, Figure 8b Only one input line is shown. Multiple input lines IL may include a gate high voltage line, a gate low voltage line, a start signal line, a first clock line, a second clock line, a carry line, and a reset signal line.

[0172] Figure 9a This is an enlarged plan view of the main island-shaped portion of the display device according to an embodiment, and Figure 9b This is an enlarged plan view of the wiring arrangement on the main bridging portion of the display device according to an embodiment. Figure 9c This is an enlarged plan view of the peripheral island portion and the peripheral bridging portion of the display device according to an embodiment.

[0173] refer to Figure 9a The main island-shaped portion 11 arranged in the display area DA may include a light-emitting element and a pixel driving circuit unit PC electrically connected to the light-emitting element. As described above, the pixel driving circuit unit PC may include a transistor and at least one capacitor. Figure 9aThree pixel driving circuit units (PCs) arranged in the main island portion 11 are shown, but this disclosure is not limited thereto. In another embodiment, the number of pixel driving circuit units (PCs) and the number of light-emitting elements arranged in the main island portion 11 may be one, two, or more than four.

[0174] refer to Figure 9b The main bridging portion 12 may include multiple connection lines WL electrically connected to pixel driving circuit units PC respectively arranged in adjacent main island portions 11. As described above, the connection lines WL may be signal lines for providing electrical signals to transistors in the pixel driving circuit units PC of the main island portion 11 or voltage lines for providing voltage. For example, the connection lines WL may include data lines DL (see reference). Figure 8b ), Scan signal line GWL (reference) Figure 8b Bypass control line GBL (reference) Figure 8b ), Initialize control line GIL (reference) Figure 8b ) and transmit control line EML (reference) Figure 8b At least one of the following. Alternatively, the connection line WL may include a first voltage line VDDL (reference). Figure 6b ), second voltage line VSSL (reference) Figure 6b ), First initialization voltage line VIL1 (reference) Figure 6b ) and the second initialization voltage line VIL2 (reference) Figure 6b At least one of the following. Figure 9b Multiple connecting lines WL (e.g., first to third connecting lines WL1, WL2, and WL3) are shown disposed on the main bridging portion 12, but this disclosure is not limited thereto. In another embodiment, one connecting line WL may be disposed on the main bridging portion 12, or four or more connecting lines WL may be disposed.

[0175] refer to Figure 9c The peripheral island portions 21 and peripheral bridging portions 22 can be arranged in the non-display area NDA. Multiple peripheral island portions 21 can be arranged spaced apart from each other, and the peripheral bridging portions 22 can connect adjacent peripheral island portions 21 to each other. Gate drive circuit GDC (reference) Figure 3 Multiple peripheral lines PW can be set on the peripheral island portion 21 and the peripheral bridging portion 22.

[0176] As described above, the gate drive circuit GDC (reference) Figure 3 This may include the transmit control drive circuit EMDC (reference). Figure 8a ), bypass drive circuit GBDC (reference) Figure 8a ), Initialize the drive circuit GIDC (reference) Figure 8a ) and data write drive circuit GWDC (reference) Figure 8aIn this case, each drive circuit may include multiple driver stages. For example, the data write drive circuit GWDC may include multiple data write stages (e.g., the nth data write stage GWSTn, the (n+1)th data write stage GWSTn+1, the (n+2)th data write stage GWSTn+2, and the (n+3)th data write stage GWSTn+3). Figure 9c As shown, the nth data write stage GWSTn, the (n+1)th data write stage GWSTn+1, the (n+2)th data write stage GWSTn+2, and the (n+3)th data write stage GWSTn+3 can be arranged in some of the peripheral island portion 21. Each of the driver stages can then include a capacitor and multiple transistors for generating the output signal.

[0177] Additionally, multiple peripheral lines PW can be disposed on the peripheral island portion 21 and the peripheral bridging portion 22. The peripheral lines PW can be lines arranged in the non-display area NDA where sub-pixels are not located. Specifically, as referenced above... Figure 3 As described, the peripheral line PW may include a drive voltage supply line W11, a common voltage supply line W13, and a fan-out line FW. Furthermore, the peripheral line PW may include components for inputting signals to the gate drive circuit GDC (see reference). Figure 3 The multiple input lines IL and the gate drive circuit GDC (reference) are used for transmission. Figure 3 The generated output signal has multiple output lines OL.

[0178] Figure 10 Showing along respectively Figure 9a The line I-I' Figure 9b Line II-II' and Figure 9c The cross-sectional view taken from line III-III'.

[0179] refer to Figure 10 The substrate 100 corresponding to the main island portion 11 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104. Each of the first base layer 101 and the second base layer 103 may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. Each of the first barrier layer 102 and the second barrier layer 104 may include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0180] The buffer layer 111 may be disposed on the substrate 100, and the pixel driving circuit unit PC (including at least a thin film transistor TFT and a first storage capacitor Cst) may be disposed on the buffer layer 111. The buffer layer 111 may include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0181] A thin-film transistor (TFT) may include a first semiconductor layer Act, a first gate electrode GE, a first source electrode SE, and a first drain electrode DE. Figure 10 The illustration shows a top-gate type where the first gate electrode GE is disposed on the first semiconductor layer Act and the gate insulating layer 113 is located between the first gate electrode GE and the first semiconductor layer Act. However, according to another embodiment, the thin-film transistor TFT can be a bottom-gate type.

[0182] The first semiconductor layer Act may include polycrystalline silicon. Alternatively, the first semiconductor layer Act may include amorphous silicon, oxide semiconductor, or organic semiconductor, etc. The first gate electrode GE may include a metal thin film comprising a low-resistance metallic material. The first gate electrode GE may include a conductive material comprising molybdenum (Mo), Al, copper (Cu), or titanium (Ti), and may be formed as a single layer or multiple layers comprising the aforementioned materials. For example, the first gate electrode GE may include a three-layer metal thin film comprising a Ti / Al / Ti structure.

[0183] The gate insulating layer 113 between the first semiconductor layer Act and the first gate electrode GE may comprise an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and titanium oxide. The gate insulating layer 113 may be a single layer or multiple layers each comprising the aforementioned materials. The gate insulating layer 113 may be disposed on the buffer layer 111 and the first semiconductor layer Act. The first gate electrode GE of the thin-film transistor (TFT) may be disposed on the gate insulating layer 113 overlapping the first semiconductor layer Act. The first gate electrode GE may be the first electrode CE1 of the first storage capacitor Cst. A first interlayer insulating layer 115 may be disposed on the gate insulating layer 113 and the first gate electrode GE. The second electrode CE2 of the first storage capacitor Cst may be disposed on the first interlayer insulating layer 115. A second interlayer insulating layer 117 may be disposed on the first interlayer insulating layer 115 and the second electrode CE2 of the first storage capacitor Cst.

[0184] The first source electrode SE and the first drain electrode DE may be located on the same layer (e.g., at the same location) (e.g., on the second interlayer insulating layer 117) and may comprise the same material. The first source electrode SE and the first drain electrode DE may be connected to the first semiconductor layer Act via corresponding contact holes penetrating the gate insulating layer 113, the first interlayer insulating layer 115, and the second interlayer insulating layer 117. The first source electrode SE and the first drain electrode DE may each comprise a thin metal film containing a low-resistance metallic material. The first source electrode SE and the first drain electrode DE may comprise conductive materials comprising Mo, Al, Cu, or Ti, and may be formed as a multilayer or a single layer each comprising the aforementioned materials. For example, similar to the first gate electrode GE, each of the first source electrode SE and the first drain electrode DE may comprise a three-layered thin metal film comprising a Ti / Al / Ti structure. The second interlayer insulating layer 117 may comprise inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and titanium oxide, and may be a single layer or multiple layers each comprising the aforementioned materials.

[0185] The first storage capacitor Cst may include a first electrode CE1 and a second electrode CE2 that overlap each other and are sandwiched between a first interlayer insulating layer 115. The first storage capacitor Cst may overlap with a thin-film transistor (TFT). In this respect, Figure 10 The first gate electrode GE of the thin-film transistor TFT is shown to be the first electrode CE1 of the first storage capacitor Cst. In another embodiment, the first storage capacitor Cst may not overlap with the thin-film transistor TFT. The first storage capacitor Cst may be covered by a second interlayer insulating layer 117.

[0186] The first interlayer insulation layer 115 may be disposed between the gate insulation layer 113 and the second interlayer insulation layer 117. The first interlayer insulation layer 115 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and titanium oxide, and may be a single layer or multiple layers each comprising the aforementioned materials.

[0187] The second electrode CE2 of the first storage capacitor Cst may include a conductive material and may be formed as a multilayer or a single layer. The second electrode CE2 may include a metal thin film comprising a low-resistance metallic material. The second electrode CE2 may include a conductive material comprising Mo, Al, Cu, or Ti, and may be formed as a multilayer or a single layer comprising each of the aforementioned materials. For example, the second electrode CE2 may include a three-layer metal thin film comprising a Ti / Al / Ti structure.

[0188] The inorganic insulating material layer IOL on the substrate 100 may include, for example, a buffer layer 111, a gate insulating layer 113, a first interlayer insulating layer 115, and a second interlayer insulating layer 117.

[0189] A first organic insulating layer 119 may be disposed on a second interlayer insulating layer 117, a first source electrode SE, and a first drain electrode DE. A second organic insulating layer 121 may be disposed on a first organic insulating layer 119. Each of the first organic insulating layer 119 and the second organic insulating layer 121 may include an organic insulating material such as polyimide.

[0190] The first connecting electrode CM1 can be disposed on the first organic insulating layer 119, and the second connecting electrode CM2 can be disposed on the second organic insulating layer 121. The first connecting electrode CM1 and the second connecting electrode CM2 can electrically connect the thin-film transistor (TFT) to the inorganic light-emitting diode (LED) 230. The first connecting electrode CM1 can be connected to the first source electrode SE or the first drain electrode DE via a contact hole penetrating the first organic insulating layer 119. The second connecting electrode CM2 can be connected to the first connecting electrode CM1 via a contact hole penetrating the second organic insulating layer 121. Each of the first connecting electrode CM1 and the second connecting electrode CM2 may include a metal thin film containing a low-resistance metallic material. Each of the first connecting electrode CM1 and the second connecting electrode CM2 may include a conductive material containing Mo, Al, Cu, or Ti, and can be formed as a multilayer or a single layer each comprising the aforementioned material. For example, each of the first connecting electrode CM1 and the second connecting electrode CM2 may include a three-layer metal thin film containing a Ti / Al / Ti structure.

[0191] A second voltage line VSSL can be disposed on the second organic insulating layer 121, and a third organic insulating layer 123 can be disposed on the second organic insulating layer 121 and the second voltage line VSSL. The third organic insulating layer 123 may include an organic insulating material such as polyimide. The second voltage line VSSL can be connected to the common voltage supply line W13 (see reference). Figure 3 ), to convert the second power supply voltage VSS (reference) Figure 6a The voltage is transmitted to the second electrode 238 of the inorganic light-emitting diode 230. The second voltage line VSSL may include a conductive material and may be formed as a multilayer or a single layer. However, in this case, the second voltage line VSSL may include a material different from the material of the second connecting electrode CM2, which is disposed on the same layer as the second voltage line VSSL. The material of the second voltage line VSSL is described in more detail below.

[0192] First electrode pad 241 and second electrode pad 242 can be disposed on the third organic insulating layer 123. The first electrode pad 241 can be electrically connected to the thin-film transistor (TFT) via a first connecting electrode CM1 located between the first organic insulating layer 119 and the second organic insulating layer 121, and a second connecting electrode CM2 located between the second organic insulating layer 121 and the third organic insulating layer 123. Inorganic light-emitting diodes 230 on the first electrode pad 241 and the second electrode pad 242 are referenced above. Figure 7b As described. For example, the light-emitting diode of inorganic light-emitting diode 230 can be protected by encapsulation layer 300, and encapsulation layer 300 may include inorganic encapsulation layer and / or organic encapsulation layer or organic material such as resin. Figure 10 The above reference shows a light-emitting diode. Figure 7b The inorganic light-emitting diode 230 described herein may, in another embodiment, be the light-emitting diode referenced above. Figure 7a The organic light-emitting diode 220 is described.

[0193] In summary, the thin-film transistor (TFT) included in the pixel driving circuit unit PC can include multiple conductive layers. Specifically, the multiple conductive layers included in the thin-film transistor TFT can include a first gate electrode GE, a first source electrode SE, a first drain electrode DE, and a first electrode CE1 and a second electrode CE2 of a first storage capacitor Cst. The first connection electrode CM1, the second connection electrode CM2, and the multiple conductive layers included in the thin-film transistor TFT can each comprise a metal thin film material. For example, the first connection electrode CM1, the second connection electrode CM2, and the multiple conductive layers included in the thin-film transistor TFT can each comprise a three-layer metal thin film comprising a Ti / Al / Ti structure. Accordingly, the modulus of each of the first connection electrode CM1, the second connection electrode CM2, and the multiple conductive layers included in the thin-film transistor TFT can be greater than 100 gigapascals (GPa) and less than 1000 GPa. In other words, the modulus of the conductive layers of the thin-film transistor TFT can be greater than the modulus of each of the connection line WL and the peripheral line PW, which will be described below.

[0194] Next, refer to Figure 10The main bridging portion 12, and the substrate 100 corresponding to the main bridging portion 12, may have the same stacking structure as the substrate 100 corresponding to the main island portion 11. In one embodiment, the substrate 100 corresponding to the main bridging portion 12 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104. In another embodiment, the substrate 100 corresponding to the main bridging portion 12 may have a different stacking structure than the substrate 100 corresponding to the main island portion 11. The substrate 100 corresponding to the main bridging portion 12 may have a structure with a first base layer 101 and a second base layer 103.

[0195] The inorganic insulating material layer IOL may not be disposed on the substrate 100, and the insulating layer OSL, the first organic insulating layer 119, and the second organic insulating layer 121 may be disposed on the substrate 100. The insulating layer OSL may include an organic insulating material such as polyimide. In embodiments, the insulating layer OSL may have a thickness corresponding to that of the inorganic insulating material layer IOL. In some embodiments, the insulating layer OSL may be omitted.

[0196] Multiple connection lines WL can be disposed on the main bridging portion 12. For example, the multiple connection lines WL1, WL2, and WL3 of the first to third connection lines can be disposed on different layers, but can be electrically connected to the same pixel driving circuit unit PC. For example, the first connection line WL1 can be disposed between the second organic insulating layer 121 and the third organic insulating layer 123, the second connection line WL2 can be disposed between the first organic insulating layer 119 and the second organic insulating layer 121, and the third connection line WL3 can be disposed between the insulating layer OSL and the first organic insulating layer 119. However, this disclosure is not limited thereto, and in another embodiment, at least some of the first to third connection lines WL1, WL2, and WL3 can be disposed on the same layer.

[0197] At this time, the multiple connection lines WL can be signal lines for providing electrical signals to the thin-film transistor TFTs included in the pixel driving circuit unit PC, or voltage lines for providing voltage. For example, the connection lines WL may include data lines DL (reference). Figure 8b ), Scan signal line GWL (reference) Figure 8b Bypass control line GBL (reference) Figure 8b ) and transmit control line EML (reference) Figure 8b At least one of the following. Alternatively, the connection line WL may include a first voltage line VDDL (reference). Figure 6b ), second voltage line VSSL, first initialization voltage line VIL1 (reference) Figure 6b ) and the second initialization voltage line VIL2 (reference) Figure 6b At least one of the following.

[0198] However, even when the multiple connection lines WL are disposed on the same layer as the conductive layer of the thin-film transistor TFT, the first connection electrode CM1, and the second connection electrode CM2, the multiple connection lines WL may comprise a material different from the material of the conductive layer of the thin-film transistor TFT, the first connection electrode CM1, and the second connection electrode CM2. In an embodiment, each of the multiple connection lines WL may comprise a material having a modulus lower than that of each of the conductive layer of the thin-film transistor TFT, the first connection electrode CM1, and the second connection electrode CM2. For example, the modulus of each of the multiple connection lines WL may be greater than 1 MPa and less than 100 MPa.

[0199] Specifically, each of the multiple connecting lines WL can comprise a metallic nanostructure and an elastic polymer. The metallic nanostructure is, for example, a nanoscale structure comprising inorganic, organic, or a combination of organic and inorganic materials, and can be a nanostructure with one-dimensional, two-dimensional, and / or three-dimensional shapes. The metallic nanostructure can include, for example, nanoparticles, nanorods, nanoplates, nanowires, nanosheets, nanotubes, nanocapsules, or combinations thereof, but is not limited thereto. For example, the metallic nanostructure can be inorganic nanoparticles, inorganic nanorods, inorganic nanoplates, inorganic nanosheets, inorganic nanotubes, inorganic nanocapsules, or combinations thereof, but is not limited thereto.

[0200] Metal nanostructures can be, for example, oxides, nitrides, or oxynitrides, and can be, for example, metal oxides, metal-like oxides, metal nitrides, metal-like nitrides, metal oxynitrides, or metal-like oxynitrides. In embodiments, the metal nanostructures may include at least one of Ag nanoparticles, Ag nanosheets, and Ag nanowires.

[0201] Metallic nanostructures can have, for example, long axes of less than about 200 nm, such as long axes of about 5 nm to about 100 nm, long axes of about 5 nm to about 80 nm, and long axes of about 5 nm to about 50 nm. Here, in the case of a spherical shape, the long axis can be the diameter, and in the case of a non-spherical shape, the long axis can be the longest of the height, width, and thickness.

[0202] The elastic polymer may include at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex. However, this disclosure is not limited thereto, and the elastic polymer may be a material that is readily composited with metal nanostructures.

[0203] In addition to the metal nanostructures and elastic polymers, each of the multiple interconnects WL may further include other conductive additives. In embodiments, each of the multiple interconnects WL may further include a carbon-based material comprising carbon nanotubes (CNTs), carbon fibers, graphene, graphene oxide, or any combination thereof. In embodiments, the concentration of the metal nanostructure in each of the multiple interconnects WL may be from approximately 60 wt% to approximately 80 wt%, and the concentration of the carbon-based material in each of the multiple interconnects WL may be from approximately 1 wt% to approximately 10 wt%. Accordingly, the minimum conductivity of the multiple interconnects WL can meet the following requirements. The level.

[0204] Next, refer to Figure 10 The outer island portion 21, the gate drive circuit GDC, and multiple peripheral lines PW can be disposed on the outer island portion 21. The substrate 100 corresponding to the outer island portion 21 can have the same stacking structure as the substrate 100 corresponding to the main island portion 11. A buffer layer 111 can be disposed on the substrate 100, and the gate drive circuit GDC can be disposed on the buffer layer 111.

[0205] A gate drive circuit (GDC) may include multiple driver stages, and each of the driver stages may include a capacitor and multiple transistors. For example, as Figure 10 As shown, the gate drive circuit GDC may include a peripheral thin-film transistor (TFT). The peripheral thin-film transistor (TFT) may include a second semiconductor layer Act', a second gate electrode GE', a second source electrode SE', a second drain electrode DE', and a second storage capacitor Cst'. Similar to the first semiconductor layer Act, the second semiconductor layer Act' may include polycrystalline silicon, amorphous silicon, oxide semiconductor, or organic semiconductor, etc.

[0206] Conversely, although the second gate electrode GE' can be disposed on the gate insulating layer 113 like the first gate electrode GE, the second gate electrode GE' can have a different material than the first gate electrode GE. In an embodiment, the second gate electrode GE' may comprise a material having a modulus smaller than that of the first gate electrode GE and the connecting line WL. For example, the modulus of the second gate electrode GE' may be greater than 1 kilopascal (kPa) and less than 100 kPa.

[0207] Specifically, the second gate electrode GE' may comprise liquid metal. In embodiments, the second gate electrode GE' may comprise liquid metal comprising a gallium-indium eutectic alloy (EGaIn) or a gallium-indium-tin alloy (Galinstan). That is, the second gate electrode GE' may comprise at least one of gallium (Ga), indium (In), and tin (Sn). Specifically, in the case of a Ga-In eutectic alloy, which is a eutectic alloy of Ga and In, its melting point is below room temperature, and therefore, the Ga-In eutectic alloy can remain liquid at room temperature and has a low resistivity.

[0208] Similarly, the second electrode CE2' of the second source electrode SE', the second drain electrode DE', and the second storage capacitor Cst' may comprise the same material as the second gate electrode GE'. Specifically, the second electrode CE2' of the second source electrode SE', the second drain electrode DE', and the second storage capacitor Cst' may each comprise liquid metal. In an embodiment, each of the second source electrode SE', the second drain electrode DE', and the second electrode CE2' of the second storage capacitor Cst' may comprise liquid metal comprising EGaIn or Galinstan. In other words, the second electrode CE2' of the second storage capacitor Cst' is disposed on the first interlayer insulating layer 115, but may comprise a material having a modulus smaller than that of the second electrode CE2' of the first storage capacitor Cst and the connecting line WL. Each of the second source electrode SE' and the second drain electrode DE' is disposed on the second interlayer insulating layer 117, but may comprise a material having a modulus smaller than that of the first source electrode SE, the first drain electrode DE, and the connecting line WL.

[0209] The first organic insulating layer 119 can be disposed on the peripheral thin-film transistor TFT', and multiple peripheral lines PW can be disposed on the first organic insulating layer 119. For example, as Figure 10 As shown, the input line IL for transmitting electrical signals to the gate drive circuit GDC and the output line OL for transmitting output signals of the gate drive circuit GDC can be disposed on the first organic insulating layer 119. Additionally, although not in... Figure 10 As shown, however, the drive voltage supply line W11 and the common voltage supply line W13, which may be included in the peripheral line PW, may also be disposed on the first organic insulating layer 119 and the second organic insulating layer 121.

[0210] At this point, similar to the conductive layer of the peripheral thin-film transistor TFT', each of the plurality of peripheral lines PW can comprise a material having a modulus smaller than that of each of the conductive layer of the thin-film transistor TFT and the interconnecting lines WL. Specifically, each of the plurality of peripheral lines PW can comprise liquid metal. In an embodiment, each of the plurality of peripheral lines PW can comprise liquid metal comprising EGaIn or Galinstan.

[0211] In summary, the conductive layers in the thin-film transistors (TFTs) of the pixel driving circuit unit PC may each comprise a metal thin film, the connecting lines WL may comprise a composite material of a metal nanostructure and an elastic polymer, and the conductive layers of the peripheral lines PW and the peripheral thin-film transistors (TFTs) may each comprise liquid metal. Accordingly, the modulus of each of the conductive layers in the thin-film transistors (TFTs) of the pixel driving circuit unit PC may be greater than the modulus of the connecting lines WL, and the modulus of each of the connecting lines WL may be greater than the modulus of the peripheral lines PW and the conductive layers of the peripheral thin-film transistors (TFTs). For example, the modulus of each of the conductive layers in the thin-film transistors (TFTs) may differ from the modulus of the connecting lines WL by approximately 100 to approximately 1000 times, and the modulus of the connecting lines WL may differ from the modulus of the peripheral lines PW and the conductive layers of the peripheral thin-film transistors (TFTs) by approximately 100 to approximately 1000 times.

[0212] Generally, the higher the modulus of a material layer, the better its recovery rate; conversely, the lower the modulus, the better its elongation. In this case, because the connecting line WL has a lower modulus than the conductive layer included in the thin-film transistor TFT, the connecting line WL can exhibit relatively superior tensile strength compared to the conductive layer included in the thin-film transistor TFT. Similarly, because the modulus of each of the peripheral line PW and the conductive layer included in the peripheral thin-film transistor TFT' is lower than the modulus of the connecting line WL, the peripheral line PW and the conductive layer included in the peripheral thin-film transistor TFT' exhibit relatively superior tensile strength compared to the connecting line WL.

[0213] In the case of the stretchable display device 1, when the display device 1 is stretched, high stress may form at the outer portion of the display device 1, and low stress may form at the central portion of the display device 1. At this time, as with the display device 1 according to the embodiment, when lines comprising a low-modulus material are formed in the non-display area NDA corresponding to the outer portion of the display device 1, and lines comprising a high-modulus material are formed in the pixel driving circuit unit PC of the display area DA, the deformation of the display area DA can be reduced when stress is applied, thereby ensuring the stability of the device in the display device. Specifically, when a material with low modulus and excellent tensile strength (e.g., liquid metal) is arranged in the non-display area NDA where high stress is formed, the high stress can be released, and a material with high modulus and excellent recovery rate and electrical properties (e.g., metal thin film) can be arranged in the pixel driving circuit unit PC of the display area DA, where electrical properties and device stability are important. Furthermore, since the connecting lines WL that connect multiple sub-pixels P to each other in the display area DA also include materials with excellent tensile and electrical properties (such as composite materials of metal nanostructures and elastic polymers), the tensile and mechanical stability of the display device 1 can be achieved simultaneously.

[0214] In another embodiment, even when all of the connecting line WL, peripheral line PW, conductive layer of the thin-film transistor TFT, and conductive layer of the peripheral thin-film transistor TFT' are made of the same material, the tensile strength and mechanical stability of the display device 1 can be achieved simultaneously. Specifically, in another embodiment, all of the connecting line WL, peripheral line PW, conductive layer of the thin-film transistor TFT, and conductive layer of the peripheral thin-film transistor TFT' may include metal nanostructures and elastic polymers. In this case, the metal nanostructure may include at least one of silver nanoparticles, silver nanosheets, and silver nanowires, and the elastic polymer may include at least one of PDMS, PU, ​​and Ecoflex.

[0215] However, even when the connecting line WL, the peripheral line PW, the conductive layer of the thin-film transistor TFT, and the conductive layer of the peripheral thin-film transistor TFT' all comprise the same material, they can still have different moduli. That is, although all of the connecting line WL, the peripheral line PW, the conductive layer of the thin-film transistor TFT, and the conductive layer of the peripheral thin-film transistor TFT' may consist of a composite material of metal nanostructures and elastic polymers, the concentration of the metal nanostructures can differ. For example, the conductive layer of the thin-film transistor TFT may have a higher concentration of metal nanostructures than the connecting line WL, and the connecting line WL may have a higher concentration of metal nanostructures than the conductive layers of the peripheral line PW and the peripheral thin-film transistor TFT'. Alternatively, the conductive layer of the thin-film transistor TFT may have a higher concentration of carbon-based materials than the connecting line WL, and the connecting line WL may have a higher concentration of carbon-based materials than the conductive layers of the peripheral line PW and the peripheral thin-film transistor TFT'. The concentration of the metal nanostructures can be adjusted from about 60 wt% to about 80 wt%, and the concentration of the carbon materials can be adjusted from about 1 wt% to about 10 wt%.

[0216] Accordingly, the modulus of each of the conductive layers in the thin-film transistor TFT can be greater than the modulus of the interconnect WL, and the modulus of the interconnect WL can be greater than the modulus of each of the conductive layers in the peripheral line PW and the peripheral thin-film transistor TFT'. For example, the modulus of each of the conductive layers included in the thin-film transistor TFT can differ from the modulus of the interconnect WL by approximately 100 to approximately 1000 times, and the modulus of the interconnect WL can differ from the modulus of each of the conductive layers in the peripheral line PW and the peripheral thin-film transistor TFT' by approximately 100 to approximately 1000 times.

[0217] In another embodiment, although all of the connecting line WL, peripheral line PW, conductive layer of the thin-film transistor TFT, and conductive layer of the peripheral thin-film transistor TFT' comprise composite materials of metal nanostructures and elastic polymers, their moduli can be formed differently by setting differences in the thermosetting or ultraviolet (UV) curing processes. For example, in the case of the conductive layer of the thin-film transistor TFT, the modulus characteristics of the material of the conductive layer of the thin-film transistor TFT can be improved by increasing the thermosetting process time or the UV curing process time. Similarly, in the case of the conductive layer of the peripheral line PW and the conductive layer of the peripheral thin-film transistor TFT', the modulus characteristics of the material of the peripheral line PW and the conductive layer of the peripheral thin-film transistor TFT' can be reduced by shortening the thermosetting process time or the UV curing process time. Even with the above process modifications, the modulus of the conductive layer of the thin-film transistor TFT can be formed to be greater than the modulus of the connecting line WL, and the modulus of the connecting line WL can be formed to be greater than the modulus of each of the conductive layers of the peripheral line PW and the peripheral thin-film transistor TFT'.

[0218] In summary, in the display device according to another embodiment and in the display device according to other embodiments, by arranging materials with different moduli for each region, excellent tensile strength and mechanical stability can be ensured simultaneously.

[0219] Figure 11 This is a schematic cross-sectional view of a display device according to another embodiment. Figure 12 This is a schematic plan view of a display device according to another embodiment.

[0220] First, refer to Figure 11 The substrate 100' of the display device 1 can be formed as a single unit without being divided into spaced-apart sections. However, the substrate 100' can be a stretchable substrate, allowing the display device 1 to be stretched. For example, the substrate 100' may include at least some stretchable regions. The stretchable regions can be stretched in at least one direction by an external force and may have the property of returning to their initial state when the external force is removed. Accordingly, the stretchable regions included in the substrate 100' may be made of a polymer material with specific stretchability. Specifically, the substrate 100' may include polymer resins such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate.

[0221] A buffer layer 111 may be disposed on the substrate 100'. As described above, the buffer layer 111 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. However, in order to display the tensile strength of the device 1, the buffer layer 111 may be omitted or may include an organic insulating material.

[0222] Multiple pixel driving circuit units PC can be disposed on the buffer layer 111. An insulating layer ISL, including inorganic and / or organic insulating materials, can be disposed between the pixel driving circuit units PC and the light-emitting elements LED. The light-emitting elements LED can be disposed on the insulating layer ISL and can be electrically connected to the corresponding pixel driving circuit units PC. An encapsulation layer 300 can be disposed on the light-emitting elements LED and can protect the light-emitting elements LED from external forces and / or moisture penetration.

[0223] Multiple pixel driving circuit units (PCs) can be arranged spaced apart from each other. In this case, connecting lines (WLs) can be arranged between the spaced-apart pixel driving circuit units (PCs). The connecting lines (WLs) can be signal lines (e.g., gate lines or data lines) for providing electrical signals to transistors included in the pixel driving circuit units (PCs) or voltage lines (e.g., driving voltage lines or initialization voltage lines). In this case, the connecting lines (WLs) can comprise a material having a modulus lower than that of the conductive layer arranged in the pixel driving circuit units (PCs). That is, because the connecting lines (WLs) comprise a material with excellent tensile strength, thus... Figure 11 The display device 1 shown can be stretched by using the stretchability of the components therein without being divided into island-shaped portions and bridging portions.

[0224] Next, refer to Figure 12 Multiple display units (PUs) can be arranged in the display area DA. Each display unit (PU) may include a first sub-pixel SP1 emitting red light, a second sub-pixel SP2 emitting green light, and a third sub-pixel SP3 emitting blue light. Adjacent display units (PUs) can be electrically connected to each other via a connecting line WL. Additionally, adjacent sub-pixels P (e.g., SP1, SP2, SP3) within a single display unit (PU) can also be electrically connected to each other via a connecting line WL. However, as... Figure 12 As shown, the distance between adjacent display units PU can be greater than the distance between adjacent sub-pixels P (e.g., SP1, SP2, SP3) in a display unit PU.

[0225] The gate drive circuit (GDC) can be located in the non-display area (NDA). As mentioned above, the gate drive circuit (GDC) may include the emitter control drive circuit (EMDC) (see reference). Figure 8a ), bypass drive circuit GBDC (reference) Figure 8aThe system comprises an initialization driver circuit GIDC and a data write driver circuit GWDC. Each driver circuit may include multiple driver stages. For example, the initialization driver circuit GIDC may include an nth initialization stage GISTn and an (n+1)th initialization stage GISTn+1, and the data write driver circuit GWDC may include an nth data write stage GWSTn and an (n+1)th data write stage GWSTn+1. Each driver stage may include a capacitor and multiple transistors.

[0226] Additionally, the peripheral line PW can be placed in the non-display area NDA. For example... Figure 12 As shown, the peripheral line PW may include an input line IL that can input electrical signals to the gate drive circuit GDC and an output line OL that transmits the output signals of the gate drive circuit GDC. Although not shown in... Figure 12 The diagram shows that, however, the peripheral line PW may further include a drive voltage supply line W11, a common voltage supply line W13, and a fan-out line FW (see, for example, see...). Figure 3 ).

[0227] Even in such Figure 11 and Figure 12 In the structure shown, materials with different moduli can be arranged in the display area DA and the non-display area NDA, respectively. Specifically, the conductive layer arranged in the pixel driving circuit unit PC can be provided with a material having a higher modulus than the connecting line WL, and the connecting line WL can be provided with a material having a higher modulus than the peripheral line PW and each of the conductive layers included in the gate driving circuit GDC.

[0228] In an embodiment, the conductive layers disposed in the pixel driving circuit unit PC may each comprise a metal thin film. For example, each of the conductive layers disposed in the pixel driving circuit unit PC may comprise a three-layer metal thin film comprising a Ti / Al / Ti structure. The interconnect line WL may comprise a composite material of a metal nanostructure and an elastic polymer. For example, the metal nanostructure included in the interconnect line WL may comprise at least one of silver nanoparticles, silver nanosheets, and silver nanowires, and the elastic polymer may comprise at least one of PDMS, PU, ​​and Ecoflex. The peripheral line PW and the conductive layer included in the gate driving circuit GDC may each comprise liquid metal. For example, the peripheral line PW and the conductive layer included in the gate driving circuit GDC may each comprise liquid metal comprising EGaIn or Galinstan.

[0229] In another embodiment, although the connecting line WL, the peripheral line PW, the conductive layer disposed in the pixel driving circuit unit PC, and the conductive layer disposed in the gate driving circuit GDC all comprise the same material, their moduli may differ from each other. For example, although the connecting line WL, the peripheral line PW, the conductive layer disposed in the pixel driving circuit unit PC, and the conductive layer disposed in the gate driving circuit GDC may all comprise composite materials of metal nanostructures and elastic polymers, the concentration of their metal nanostructures may differ from each other.

[0230] because Figure 11 and Figure 12 The display device 1 shown may be stretched as a whole, so the mechanical stability of the transistors included in the pixel driving circuit unit PC and the stretchability of other connection lines WL and peripheral lines PW may be required simultaneously. Accordingly, in the display device according to another embodiment, the conductive layer included in the pixel driving circuit unit PC comprises a material with a higher modulus and excellent recovery rate compared to the connection lines WL, and thus, the stability and electrical characteristics of the transistors can be ensured. In addition, since the connection lines WL connecting the multiple sub-pixels P to each other comprise a composite material of metal nanostructures and elastic polymers that ensures both stretchability and electrical characteristics, electrical signals can be stably transmitted to the multiple sub-pixels P, and the stress applied to the display device 1 during stretching can also be reduced. Since the conductive layer of the peripheral lines PW and the gate driving circuit GDC arranged in the non-display area NDA comprises liquid metal with a modulus lower than that of the connection lines WL, the stress at the outermost region of the display device 1 that receives the highest stress during stretching can be greatly reduced, thereby improving the stretchability of the display device. In summary, the display device according to another embodiment can simultaneously ensure excellent tensile strength and mechanical stability of the device by arranging materials with different moduli for each region.

[0231] Figures 13a to 13g These are schematic perspective views illustrating embodiments of electronic devices including a display device according to an embodiment.

[0232] refer to Figure 13a The display device according to the embodiment can be used as a wearable electronic device 3100 that can be worn on a part of a user's body. The wearable electronic device 3100 may include a main body portion 3110 and a display portion 3120 provided in the main body portion 3110. The display device according to the embodiment can be used as the display portion 3120 of the wearable electronic device 3100. Figure 13a As shown, the wearable electronic device 3100 can be deformable. In an embodiment, depending on the user's choice, the wearable electronic device 3100 can be used as a smartwatch or a smartphone.

[0233] Figure 13b A medical electronic device 3200 is shown. In an embodiment, the medical electronic device 3200 may include a main body portion 3210 and a light-emitting portion 3220. A display device according to an embodiment may be used as the light-emitting portion 3220 of the medical electronic device 3200. The light-emitting portion 3220 may emit light of a specific wavelength (e.g., infrared light or visible light) toward the patient's body. In an embodiment, the main body portion 3210 may include a stretchable fibrous material and may have a structure in which the light-emitting portion 3220 can be worn on the user's body.

[0234] Figure 13c An educational electronic device 3300 is shown. In an embodiment, the educational electronic device 3300 may include a display portion 3320 provided in a frame 3310. The display portion 3320 may use a display device according to an embodiment. The display portion 3320 may provide images such as a turbulent sea, a snow-covered mountain, or a lava-flowing volcano, and in this case, the display portion 3320 may extend in the height direction (e.g., the z-direction) by reflecting the height of the waves, mountains, or volcano. In some embodiments, a portion of the display portion 3320 may display the movement of lava in a three-dimensional manner by sequentially changing its height along the direction of lava flow. The educational electronic device 3300 may include a plurality of pins (or stroke portions) 3330 arranged on the rear surface of the display portion 3320 such that the display portion 3320 may be stretched in the height direction. When the pins 3330 move along a third direction (e.g., the z-direction or the -z-direction), the image displayed on the display portion 3320 may be realized to have a three-dimensional height. Figure 13c An educational electronic device 3300 is shown, but its use is not limited as long as the device provides specific image information.

[0235] like Figures 13a to 13c As shown, an electronic device whose shape can be changed is described as an electronic device, but this disclosure is not limited thereto. As will be described below, a display device according to an embodiment can be used in an electronic device in which the portion capable of displaying images (e.g., a screen) is fixed.

[0236] Figure 13d The robot 3400 is illustrated as an electronic device according to an embodiment. The robot 3400 can identify movement or objects using a camera unit 3440, and can display specific images via display portions 3420 and 3430. In some embodiments, as described above, because the display device according to the embodiment can be stretched in various directions, the display device can be assembled into a main frame having a hemispherical shape, and accordingly, the robot 3400 may include display portions 3420 and 3430 having hemispherical shapes.

[0237] Figure 13e A vehicle display device 3500 is shown as an electronic device according to an embodiment. The vehicle display device 3500 may include an instrument cluster 3510, a center information display (CID) 3520, and / or a passenger display 3530. Because the display device according to the embodiment can be stretched in various directions, the display device can be used in the instrument cluster 3510, CID 3520, and / or passenger display 3530 regardless of the shape of the vehicle's internal frame.

[0238] Figure 13e The instrument panel 3510, CID 3520, and passenger display 3530 are shown to be independent of each other, but this disclosure is not limited thereto. In another embodiment, two or more of the instrument panel 3510, CID 3520, and passenger display 3530 may be connected to each other as a single unit.

[0239] In some embodiments, the vehicle display device 3500 may include a button 3540 capable of displaying a specific image. (See reference) Figure 13e An enlarged view shows that the button 3540, which has a hemispherical shape, may include an object 3542 and a display device disposed on the object 3542, the object 3542 providing a tactile feedback while moving along the z-direction or the -z-direction. In some embodiments, when the object 3542 has a three-dimensional arcuate surface, the display device may also have a three-dimensional arcuate surface.

[0240] Figure 13f The electronic device shown according to an embodiment is an advertising or display electronic device 3600. In some embodiments, the advertising or display electronic device 3600 may be mounted on a fixed structure 3610 such as a wall or pillar. When the structure 3610 includes, for example, Figure 13f When the surface is uneven as shown, the advertising or display electronic device 3600 can be arranged along the uneven surface of the structure 3610. In some embodiments, the advertising or display electronic device 3600 can be mounted on the structure 3610 using a heat-shrink film or the like.

[0241] Figure 13g The electronic device shown according to an embodiment is a controller 3700. The controller 3700 may include image-based buttons. For example, the controller 3700 may include first to third button areas 3720, 3730, and 3740 in which a portion of the display portion 3710 protrudes in the z-direction or in the -z-direction (or is recessed in the z-direction). In some embodiments, the first button area 3720 and the third button area 3740 may protrude in the z-direction, and the second button area 3730 may protrude in the -z-direction (or be recessed in the z-direction).

[0242] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device comprising a display area and a non-display area located outside the display area, the display device comprising: Multiple pixels are arranged in the display area, each of the multiple pixels including a transistor and a light-emitting diode electrically connected to the transistor; Connecting lines are arranged in the display area, the connecting lines electrically connecting adjacent pixels among the plurality of pixels; as well as Peripheral lines are arranged in the non-display area. Wherein, the modulus of the conductive layer of the transistor is greater than the modulus of the connecting wire, and The modulus of the connecting line is greater than the modulus of the outer line.

2. The display device according to claim 1, wherein, The conductive layer, the interconnect, and the peripheral wire of the transistor are made of different materials.

3. The display device according to claim 1, wherein, The modulus of the conductive layer of the transistor is greater than 100 GPa and less than 1000 GPa.

4. The display device according to claim 1, wherein, The conductive layer of the transistor comprises a thin metal film.

5. The display device according to claim 1, wherein, The modulus of the connecting wire is greater than 1 MPa and less than 100 MPa.

6. The display device according to claim 1, wherein, The connecting wire comprises a metal nanostructure and an elastic polymer.

7. The display device according to claim 6, wherein, The metal nanostructure includes at least one of silver nanoparticles, silver nanosheets, or silver nanowires.

8. The display device according to claim 6, wherein, The elastic polymer includes at least one of polydimethylsiloxane (PDMS), polyurethane (PU), or Ecoflex.

9. The display device according to claim 6, wherein, The connecting wire further comprises a carbon-based material, and The carbon-based materials include carbon nanotubes (CNTs), carbon fibers, graphene, graphene oxide, or any combination thereof.

10. The display device according to claim 1, wherein, The modulus of the outer perimeter is greater than 1 kPa and less than 100 kPa.

11. The display device according to claim 1, wherein, The outer perimeter includes liquid metal.

12. The display device according to claim 11, wherein, The liquid metal includes gallium indium eutectic alloy (EGaIn) or gallium indium tin alloy (Galinstan).

13. The display device according to claim 1, wherein, Each of the conductive layer, the interconnect, and the peripheral line of the transistor comprises a metal nanostructure and an elastic polymer.

14. The display device according to claim 13, wherein, The concentration of the metal nanostructure in the conductive layer of the transistor is greater than the concentration of the metal nanostructure in the interconnect, and The concentration of the metal nanostructure in the connecting line is greater than the concentration of the metal nanostructure in the peripheral line.

15. The display device according to claim 13, wherein, The metal nanostructure includes at least one of silver nanoparticles, silver nanosheets, and silver nanowires, and The elastic polymer includes at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex.

16. The display device according to claim 1, wherein, The connecting line includes multiple signal lines and multiple voltage lines, and The multiple signal lines include at least one of the following: data line, transmit control line, scan signal line, initialization control line, and bypass control line.

17. The display device according to claim 1, wherein, The peripheral lines include at least one of the following: drive voltage supply line, common voltage supply line, fan-out line, drive circuit input line, and drive circuit output line.

18. The display device according to claim 1, further comprising a gate driving circuit located in the non-display area. in, The modulus of the conductive layer of the gate drive circuit is less than the modulus of the connecting line.

19. The display device according to claim 18, wherein, The conductive layer of the gate drive circuit comprises liquid metal.

20. A display device comprising a display area and a non-display area located outside the display area, the display device comprising: Multiple pixels are arranged in the display area, each of the multiple pixels including a transistor and a light-emitting diode electrically connected to the transistor; Connecting lines are arranged in the display area, the connecting lines electrically connecting adjacent pixels among the plurality of pixels; as well as Peripheral lines are arranged in the non-display area. The conductive layer of the transistor includes a thin metal film. The connecting wires comprise metal nanostructures and elastic polymers, and The outer perimeter line includes liquid metal.

21. The display device according to claim 20, wherein, The modulus of the conductive layer of the transistor is greater than the modulus of the interconnect. The modulus of the connecting line is greater than the modulus of the outer line.

22. The display device according to claim 21, wherein, The modulus of the conductive layer of the transistor is in the range of 100 GPa to 1000 GPa. Wherein, the modulus of the connecting wire is in the range of 1 MPa to 100 MPa, and The modulus of the outer perimeter is in the range of 1 kPa to 100 kPa.

23. The display device according to claim 20, wherein, The metal nanostructure includes at least one of silver nanoparticles, silver nanosheets, and silver nanowires, and The elastic polymer includes at least one of polydimethylsiloxane (PDMS), polyurethane (PU), and Ecoflex.

24. The display device according to claim 20, wherein, The liquid metal includes gallium indium eutectic alloy (EGaIn) or gallium indium tin alloy (Galinstan).

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