Component for semiconductor manufacturing apparatus and method for regenerating the same

Abstract

A member (10) for a semiconductor manufacturing apparatus includes a first ceramic plate (21) having a wafer placement surface (26) on an upper surface thereof, a second ceramic plate (22) disposed on a lower surface of the first ceramic plate (21), a suction electrode (26) built into the second ceramic plate (22), and a first amorphous layer (24) present between the first ceramic plate (21) and the second ceramic plate (22). The first ceramic plate (21) has a higher dielectric breakdown voltage than the second ceramic plate (22), and the dielectric breakdown voltage is 70 kV / mm or more.

Description

Technical Field

[0001] This invention relates to components for semiconductor manufacturing apparatus and methods for regenerating them. Background Technology

[0002] Conventionally, components used in semiconductor manufacturing apparatuses include those that utilize plasma to perform CVD, etching, and other processes on wafers. As shown in Patent Document 1, a component with a ceramic insulating layer formed on the upper surface of a ceramic dielectric layer where electrostatic electrodes are embedded is known as a component for such semiconductor manufacturing apparatuses. The ceramic insulating layer is formed, for example, from a CVD film, PVD film, AD film, or a sputtered film. The upper surface of the ceramic insulating layer has a wafer mounting surface. Aluminum oxide is an example of a material used for the ceramic insulating layer.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent No. 7214867 Summary of the Invention

[0004] The technical problem that the invention aims to solve However, the dielectric withstand voltage of conventional alumina is only around 10kV / mm to 15kV / mm, which is not high. Therefore, there is a concern that insulation failure may occur when a large potential difference is generated between the wafer and the electrostatic electrode. In addition, it is sometimes impossible to obtain sufficient bonding strength between the ceramic insulating layer and the ceramic dielectric layer.

[0005] This invention was made to solve the above-mentioned technical problems, and its main purpose is to reduce concerns about insulation failure and improve the bonding strength between ceramic plates.

[0006] Technical solutions for solving technical problems [1] The component for the semiconductor manufacturing apparatus of the present invention comprises: The first ceramic plate has a wafer mounting surface on its upper surface; The second ceramic plate is disposed on the lower surface of the first ceramic plate; Adsorption electrode, which is embedded in the first ceramic plate or the second ceramic plate; and A first amorphous layer exists between the first ceramic plate and the second ceramic plate. The insulation withstand voltage of the first ceramic plate is higher than that of the second ceramic plate, and is above 70kV / mm.

[0007] In this component for a semiconductor manufacturing apparatus, the first ceramic plate, which has a wafer mounting surface on its upper surface, has a higher dielectric withstand voltage than the second ceramic plate, exceeding 70 kV / mm. Therefore, even if a large potential difference arises between the wafer and the adsorption electrode, the risk of insulation failure is relatively low. Furthermore, the presence of a first amorphous layer between the first and second ceramic plates results in a higher bonding strength between the two plates.

[0008] In this specification, "up" and "down" do not indicate an absolute positional relationship, but rather a relative positional relationship. Therefore, depending on the orientation of the components in the semiconductor manufacturing apparatus, "up" and "down" may become "down" and "up," or "left" and "right," or "front" and "back."

[0009] [2] In the semiconductor manufacturing apparatus component of the present invention (the semiconductor manufacturing apparatus component described in [1]), the insulation withstand voltage of the first ceramic plate can be 120kV / mm or more.

[0010] [3] In the semiconductor manufacturing apparatus component of the present invention (the semiconductor manufacturing apparatus component described in [1] or [2]), the first ceramic plate and the second ceramic plate may be alumina plates with different insulation and voltage resistance.

[0011] [4] The semiconductor manufacturing apparatus component of the present invention (the semiconductor manufacturing apparatus component described in any one of [1] to [3]) may include: a first modified layer, which exists in the first ceramic plate on the side in contact with the first amorphous layer; and a second modified layer, which exists in the second ceramic plate on the side in contact with the first amorphous layer.

[0012] [5] The semiconductor manufacturing apparatus component of the present invention (the semiconductor manufacturing apparatus component described in any one of [1] to [4]) may include: a third ceramic plate disposed on the lower surface of the second ceramic plate; and a second amorphous layer existing between the second ceramic plate and the third ceramic plate. In this case, the third ceramic plate may be formed of a material with a higher thermal conductivity than the second ceramic plate, or it may be formed of a material with a lower purity than the second ceramic plate.

[0013] [6] In the semiconductor manufacturing apparatus component of the present invention (the semiconductor manufacturing apparatus component described in [5]), a refrigerant flow path for refrigerant to flow or a gas flow path for supplying gas to the wafer mounting surface may be provided at the position of the second ceramic plate facing the second amorphous layer or at the position of the third ceramic plate facing the second amorphous layer.

[0014] [7] The semiconductor manufacturing apparatus component of the present invention (the semiconductor manufacturing apparatus component described in [5] or [6]) may include: a third modified layer, which exists in the second ceramic plate on the side in contact with the second amorphous layer; and a fourth modified layer, which exists in the third ceramic plate on the side in contact with the second amorphous layer.

[0015] [8] The method for regenerating components for a semiconductor manufacturing apparatus according to the present invention may include the following steps: (a) A process of processing the upper surface of the first ceramic plate of a component for a semiconductor manufacturing apparatus as described in any one of [1] to [7], thereby forming a processing surface on the first ceramic plate from which the wafer mounting surface has been removed; and (b) A process of further processing the processing surface to form a new wafer mounting surface.

[0016] [9] The method for regenerating components for a semiconductor manufacturing apparatus according to the present invention may include the following steps: (a) A process of processing the upper surface of the first ceramic plate of a component for a semiconductor manufacturing apparatus as described in any one of [1] to [7], thereby forming a processing surface on the first ceramic plate from which the wafer mounting surface has been removed; and (b) A process of directly bonding a regenerable ceramic plate with an insulation withstand voltage higher than that of the second ceramic plate and greater than 70 kV / mm to the processed surface.

[0017] In this case, the recycled ceramic plate used in process (b) may not have a wafer mounting surface on its upper surface before direct bonding, and may have a wafer mounting surface formed on its upper surface after direct bonding, or the recycled ceramic plate with a wafer mounting surface formed on its upper surface before direct bonding may be directly bonded.

[0018]

[10] The method for regenerating components for a semiconductor manufacturing apparatus according to the present invention may include the following steps: (a) A process of processing and removing the first ceramic plate of a component for a semiconductor manufacturing apparatus as described in any one of [1] to [7] to expose the second ceramic plate and forming a processed surface on the second ceramic plate; and (b) A process of directly bonding a regenerable ceramic plate with an insulation withstand voltage higher than that of the second ceramic plate and greater than 70 kV / mm to the processed surface.

[0019] In this case, the recycled ceramic plate used in process (b) may not have a wafer mounting surface on its upper surface before direct bonding, and may have a wafer mounting surface formed on its upper surface after direct bonding, or the recycled ceramic plate with a wafer mounting surface formed on its upper surface before direct bonding may be directly bonded. Attached Figure Description

[0020] Figure 1 This is a top view of component 10 for a semiconductor manufacturing apparatus.

[0021] Figure 2 yes Figure 1 AA sectional view.

[0022] Figure 3 yes Figure 2 A magnified view of a portion of the image.

[0023] Figure 4 This is an explanatory diagram of the grinding device 50.

[0024] Figure 5 This is a cross-sectional view of a component 10 for a semiconductor manufacturing apparatus having a refrigerant flow path 70.

[0025] Figure 6 This is a cross-sectional view of a component 10 for a semiconductor manufacturing apparatus having a refrigerant flow path 70.

[0026] Figure 7 This is a cross-sectional view of a component 10 for a semiconductor manufacturing apparatus having a gas flow path 80.

[0027] Figure 8 This is a cross-sectional view of a component 10 for a semiconductor manufacturing apparatus having a gas flow path 80.

[0028] Figure 9 This is a diagram of the regeneration process of component 10 for semiconductor manufacturing equipment.

[0029] Figure 10 This is a diagram of the regeneration process of component 10 for semiconductor manufacturing equipment.

[0030] Figure 11 This is a diagram of the regeneration process of component 10 for semiconductor manufacturing equipment. Detailed Implementation

[0031] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a top view of component 10 for a semiconductor manufacturing apparatus. Figure 2 yes Figure 1 AA section view, Figure 3 yes Figure 2 A magnified view of a portion of the image.

[0032] like Figure 2 As shown, the component 10 for a semiconductor manufacturing apparatus includes a ceramic plate laminate 20, a cooling plate 30, and an adhesive sheet 40.

[0033] The ceramic plate stack 20 is a three-layer ceramic disc. The ceramic plate stack 20 includes: a first ceramic plate 21 with a wafer mounting surface 26 on its upper surface; a second ceramic plate 22 disposed on the lower surface of the first ceramic plate 21; and a third ceramic plate 23 disposed on the lower surface of the second ceramic plate 22. A first amorphous layer 24 exists between the first ceramic plate 21 and the second ceramic plate 22, and a second amorphous layer 25 exists between the second ceramic plate 22 and the third ceramic plate 23. The first amorphous layer 24 exhibits a peak wider than that of the first ceramic plate 21 and the second ceramic plate 22 during XRD measurement, and the second amorphous layer 25 exhibits a peak wider than that of the second ceramic plate 22 and the third ceramic plate 23 during XRD measurement. In a cross-sectional magnified image of the ceramic plate stack 20 observed at 4 millionx using a transmission electron microscope (TEM), the first amorphous layer 24 and the second amorphous layer 25 are observed as thin bands. The first amorphous layer 24 is sometimes formed as a single layer, but sometimes as multiple layers (e.g., three layers). The same applies to the second amorphous layer 25. To improve the bonding strength between the first ceramic plate 21 and the second ceramic plate 22, and between the second ceramic plate 22 and the third ceramic plate 23, the average thicknesses t1 and t2 of the first amorphous layer 24 and the second amorphous layer 25 are preferably 0.1 nm or more, more preferably 1 nm or more. Furthermore, to prevent the mixing of dissimilar materials, the average thicknesses t1 and t2 of the first amorphous layer 24 and the second amorphous layer 25 are preferably 30 nm or less, more preferably 20 nm or less. Therefore, the average thicknesses t1 and t2 of the first amorphous layer 24 and the second amorphous layer 25 are preferably, for example, 0.1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less. The thickness of the first amorphous layer 24 refers to the total thickness of the multiple layers when the first amorphous layer 24 is composed of multiple layers. The same applies to the second amorphous layer 25.

[0034] The average thicknesses t1 and t2 of the first amorphous layer 24 and the second amorphous layer 25 were measured based on TEM observations, following these steps. On a TEM image (magnification: 4 millionx) of one field of view, the thicknesses of the first amorphous layer 24 and the second amorphous layer 25 were measured at five locations every 10 nm along the bonding interface, and the average thicknesses of the first amorphous layer 24 and the second amorphous layer 25 in each field of view were calculated. Five fields of view were selected unbiasedly, including the vicinity of the center, the vicinity of the outer perimeter, and the vicinity of the radius center when viewing the semiconductor manufacturing apparatus component 10 from above, and the thickness measurements were performed based on the same TEM observations. Furthermore, the average thickness t1 of the first amorphous layer 24 was obtained by dividing the sum of the average thicknesses of the first amorphous layer 24 in the five fields of view by the number of fields of view, which is 5. Similarly, the average thickness t2 of the second amorphous layer 25 was obtained by dividing the sum of the average thicknesses of the second amorphous layer 25 in the five fields of view by the number of fields of view, which is 5.

[0035] The amorphous layer observed by TEM can be confirmed by the following method: when obtaining X-ray diffraction patterns based on X-ray diffraction (XRD) for both the inner and outer sides of the thin stripe, a halo pattern wider than that on the outer sides of the thin stripe is observed. Typically, when measuring the XRD diffraction patterns on the outer sides of the thin stripe (ceramic plates) separately, diffraction patterns corresponding to the crystal structure of the material constituting each ceramic plate are observed.

[0036] The upper surface of the first ceramic plate 21 becomes the wafer mounting surface 26 for mounting the wafer W. An annular sealing strip 26a is formed along the outer edge of the wafer mounting surface 26, and a plurality of small circular protrusions 26b are formed on the entire inner surface of the sealing strip 26a. The sealing strip 26a and the small circular protrusions 26b have the same height, for example, several... μ m ~ tens μ m (e.g., 50) μ The diameter of the small circular protrusion 26b is, for example, several hundred. μ m (e.g. 800) μ (m). It should be noted that the portion of the wafer mounting surface 26 without the sealing strip 26a and the small circular protrusion 26b is referred to as the reference surface 26c. The insulation withstand voltage of the first ceramic plate 21 is higher than that of the second ceramic plate 22, and is 70 kV / mm or more. In such a first ceramic plate 21, the insulation withstand voltage is preferably 120 kV / mm or more. It should be noted that the insulation withstand voltage of the first ceramic plate 21 can be higher than that of the second ceramic plate 22 in general, or the second ceramic plate 22 can be partially fitted with ceramics with an insulation withstand voltage equal to or lower than that of the first ceramic plate 21. Examples of ceramic plates with an insulation withstand voltage of 70 kV / mm or more include the alumina plates shown in Example 5, Comparative Example 1 and Comparative Example 3 of Japanese Patent No. 5972630, and the alumina plates shown in Experimental Examples 1 to 10 of Japanese Patent No. 6373212. Examples of ceramic plates with an insulation withstand voltage of 120 kV / mm or higher include the alumina plate shown in Example 5 of Japanese Patent No. 5972630 and the alumina plates shown in Experimental Examples 1-3 and 5-8 of Japanese Patent No. 6373212. The open porosity is preferably 0.001% to 0.15%, and the average particle size is preferably 0.9 mm. μ m~18 μ m, with a purity preferably above 99.5% by mass, and a volume resistivity preferably 3×10 at 400℃. 12 ~1×10 18 Ω·cm Insulation withstand voltage can be determined by the following steps. First, prepare a test piece with a thickness of 0.2 mm and a square diameter of 50 mm. Clamp the test piece in insulating oil using a pair of SUS probes. Then, increase the voltage applied between the pair of SUS probes until insulation failure (short circuit) occurs in the test piece. Calculate the electric field strength (insulation withstand voltage) (kV / mm) based on the voltage at which insulation failure occurs and the thickness of the insulation failure portion of the test piece.

[0037] The second ceramic plate 22 is a circular ceramic plate with the same diameter as the first ceramic plate 21 at its mating surface, and sequentially houses an adsorption electrode 27 and a heater electrode 28 from top to bottom. The adsorption electrode 27 is a planar electrode connected to an external DC power supply via a power supply component (not shown). Examples of adsorption electrodes 27 include mesh electrodes or printed electrodes. The power supply component is electrically insulated from the cooling plate 30. When a DC voltage is applied to the adsorption electrode 27, the wafer W is adsorbed and fixed to the wafer mounting surface 26 (specifically, the upper surface of the sealing strip 26a and the upper surface of the small circular protrusion 26b) by electrostatic adsorption force. When the DC voltage is released, the adsorption and fixation of the wafer W to the wafer mounting surface 26 is released. The adsorption electrode 27 can be embedded in either the first ceramic plate 21 or the second ceramic plate 22, but is preferably embedded in a position where it is retained during the regeneration of the semiconductor manufacturing apparatus component 10 without being removed. The heater electrode 28 is a resistive heating element formed by a general wiring extending from one of a pair of terminals across the wafer mounting surface 26 and reaching the other of the pair of terminals in plan view. The pair of terminals are connected to an external heater power supply via a power supply component (not shown). The power supply component is electrically insulated from the cooling plate 30. When power is supplied to the heater electrode 28 from the heater power supply, the heater electrode 28 heats up and heats the wafer W on the wafer mounting surface 26. Examples of the second ceramic plate 22 include an alumina plate with an insulation withstand voltage of 10kV / mm to 60kV / mm (e.g., commercially available aluminum, plates, or alumina plates obtained by hot-pressing and sintering alumina powder separately).

[0038] The third ceramic plate 23 is a circular ceramic plate with steps on its outer perimeter. The diameter of the upper part is the same as that of the second ceramic plate 22, and the diameter of the lower part is larger than that of the second ceramic plate 22. The third ceramic plate 23 is made of, for example, a material with a higher thermal conductivity than the second ceramic plate 22 (e.g., AlN sintered body).

[0039] The first ceramic plate 21 has a first modified layer 21a on the side in contact with the first amorphous layer 24, and the second ceramic plate 22 has a second modified layer 22a on the side in contact with the first amorphous layer 24. For example, when XRD is measured, the first modified layer 21a is wider than the portion of the first ceramic plate 21 other than the first modified layer 21a, but exhibits a sharp peak compared to the first amorphous layer 24. Similarly, when XRD is measured, the second modified layer 22a is wider than the portion of the second ceramic plate 22 other than the second modified layer 22a, but exhibits a sharp peak compared to the first amorphous layer 24. In a magnified cross-sectional image of the ceramic plate stack 20 based on TEM, the first modified layer 21a is observed to have a different morphology than the portion of the first ceramic plate 21 other than the first modified layer 21a, and the second modified layer 22a is observed to have a different morphology than the portion of the second ceramic plate 22 other than the second modified layer 22a. The thickness of the first metamorphic layer 21a and the second metamorphic layer 22a is preferably 10 nm or more, more preferably 100 nm or more and 1 μ Below m.

[0040] The second ceramic plate 22 has a third modified layer 22b on the side in contact with the second amorphous layer 25, and the third ceramic plate 23 has a fourth modified layer 23b on the side in contact with the second amorphous layer 25. For example, when XRD is measured, the third modified layer 22b is wider than the portion of the second ceramic plate 22 other than the third modified layer 22b, but exhibits a sharp peak compared to the second amorphous layer 25. Similarly, when XRD is measured, the fourth modified layer 23b is wider than the portion of the third ceramic plate 23 other than the fourth modified layer 23b, but exhibits a sharp peak compared to the second amorphous layer 25. In a magnified cross-sectional image of the ceramic plate stack 20 based on TEM, the third modified layer 22b is observed to have a different morphology from the portion of the second ceramic plate 22 excluding the third modified layer 22b, and the fourth modified layer 23b is observed to have a different morphology from the portion of the third ceramic plate 23 excluding the fourth modified layer 23b. The thickness of the third metamorphic layer 22b and the fourth metamorphic layer 23b is preferably 10 nm or more, more preferably 100 nm or more and 1 μ Below m.

[0041] The cooling plate 30 is a circular plate with good thermal conductivity (its diameter is the same as or larger than the diameter of the lower part of the third ceramic plate 23 of the ceramic plate laminate 20). A refrigerant flow path 32 for refrigerant circulation is formed inside the cooling plate 30. The refrigerant flowing in the refrigerant flow path 32 is preferably a liquid, and preferably electrically insulating. Examples of electrically insulating liquids include fluorine-based inert liquids. The refrigerant flow path 32, viewed from top view, is formed integrally with the cooling plate 30 in a single stroke from one end (inlet) to the other end (outlet). A supply port and a return port (not shown) of an external refrigerant device are connected to one end of the refrigerant flow path 32, respectively. Refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 returns to the return port of the external refrigerant device after passing through the refrigerant flow path 32, and is then supplied back to one end of the refrigerant flow path 32 from the supply port after temperature adjustment. The cooling plate 30 can also be used as an RF electrode.

[0042] The material of the cooling plate 30 can be, for example, a metallic material or a metal-ceramic composite material. Examples of metallic materials include Al, Ti, Mo, or alloys thereof. Examples of metal-ceramic composite materials include metal matrix composites (MMC) and ceramic matrix composites (CMC). Specific examples of such composite materials include materials containing Si, SiC, and Ti (also known as SiSiCTi), materials impregnated with Al and / or Si in a porous SiC matrix, and composite materials of Al2O3 and TiC. Preferably, the material of the cooling plate 30 has a coefficient of thermal expansion close to that of the material of the third ceramic plate 23.

[0043] The adhesive sheet 40 is a circular, double-sided adhesive tape that bonds the lower surface of the ceramic plate laminate 20 to the upper surface of the cooling plate 30. Examples of materials for the adhesive sheet 40 include epoxy resin, acrylic resin, and silicone resin. It should be noted that a metal bonding layer may also be used instead of the adhesive sheet 40.

[0044] Next, an example of using the semiconductor manufacturing apparatus component 10 configured in this way will be described. First, with the semiconductor manufacturing apparatus component 10 disposed in a chamber (not shown), a wafer W is placed on the wafer mounting surface 26. Then, the vacuum level in the chamber is adjusted to a given vacuum degree by depressurizing the chamber using a vacuum pump, and a DC voltage is applied to the adsorption electrode 27 of the ceramic plate laminate 20 to generate an electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface 26 (specifically, the upper surface of the sealing strip 26a and the upper surface of the small circular protrusion 26b). Next, the chamber is set to a reactive gas atmosphere at a given pressure (e.g., tens to hundreds of Pa). In this state, a high-frequency voltage is applied between the upper electrode (not shown) of the ceiling portion disposed in the chamber and the cooling plate 30 of the semiconductor manufacturing apparatus component 10 to generate plasma. The surface of the wafer W is treated by the generated plasma. Refrigerant circulates in the refrigerant flow path 32 of the cooling plate 30. In addition, as needed, electricity is supplied to the heater electrode 28 to heat the wafer W.

[0045] Next, an example of manufacturing the ceramic plate laminate 20 will be described. First, a first ceramic plate 21 and a second ceramic plate 22 are manufactured. For example, the first ceramic plate 21 is manufactured by hot pressing a molded body containing ceramic powder (e.g., alumina powder) (for example, refer to Example 5 of Japanese Patent No. 5972630 and Experimental Example 1 of Japanese Patent No. 6373212). In this way, the first ceramic plate 21 can be made into a dense body. The second ceramic plate 22 is manufactured by hot pressing a molded body containing ceramic powder (e.g., alumina powder) with embedded adsorption electrode 27 and heater electrode 28. In this way, the second ceramic plate 22 can be made into a dense body. The third ceramic plate 23 is manufactured by hot pressing a molded body containing ceramic powder (e.g., aluminum nitride powder). In this way, the third ceramic plate 23 can be made into a dense body. At this stage, the first ceramic plate to the third ceramic plate 21 to 23 do not have a modified layer.

[0046] Next, use Figure 4The polishing apparatus 50 shown performs polishing on a first ceramic plate 21. The polishing apparatus 50 includes: a disc-shaped polishing platform 52 with a large diameter and a polishing pad 54; a disc-shaped carrier 56 with a small diameter; and a pipe 58 for supplying a slurry containing abrasive particles to the polishing pad 54. The polishing platform 52 has a shaft at the center of its lower surface, which rotates by a drive motor (not shown). The carrier 56 has a shaft at the center of its upper surface, which rotates by a drive motor (not shown). The carrier 56 is positioned off-center from the center of the polishing platform 52. To polish the first ceramic plate 21 using this polishing apparatus 50, the first ceramic plate 21 is mounted on the lower surface of the carrier 56, and the first ceramic plate 21 is sandwiched between the polishing pad 54 of the polishing platform 52 and the carrier 56. Then, a slurry containing abrasive particles is supplied to the polishing pad 54 from the pipe 58. Thus, slurry is supplied between the first ceramic plate 21 and the polishing pad 54 of the polishing platform 52. In this state, the first ceramic plate 21 is pressed against the polishing pad 54 by the carrier 56, while the polishing platform 52 and the carrier 56 rotate to perform polishing. Regarding polishing, for example, polishing conditions are set such that the surface roughness (arithmetic mean roughness) Ra of the lower surface of the first ceramic plate 21 is less than 1 nm. The surface roughness (arithmetic mean roughness) Ra of the polished surface is measured using a non-contact surface roughness meter according to ISO 25178 standard. Furthermore, a first modified layer 21a is formed on the polished surface side of the first ceramic plate 21.

[0047] The second ceramic plate 22 is polished and ground on both its top and bottom surfaces using the grinding device 50 in the same manner as the first ceramic plate 21. As a result, the surface roughness Ra of both surfaces of the second ceramic plate 22 becomes less than 1 nm. In addition, a second metamorphic layer 22a and a third metamorphic layer 22b are formed on both surfaces of the second ceramic plate 22.

[0048] The third ceramic plate 23 is polished and ground using a grinding device 50 on its smaller diameter surface in the same manner as the first ceramic plate 21. As a result, the surface roughness Ra of the ground surface of the third ceramic plate 23 becomes less than 1 nm. In addition, a fourth modified layer 23b is formed on the ground surface of the third ceramic plate 23.

[0049] Next, surface activation treatment (high-speed electron beam (FAB) or plasma activation treatment) is performed on the surface of the first ceramic plate 21 with the first modified layer 21a (polished surface) and the surface of the second ceramic plate 22 with the second modified layer 22a (polished surface) under high vacuum. The FAB conditions are appropriately adjusted, for example, within the range of voltage 0.5kV to 2kV, current 50mA to 200mA, and irradiation time 30 seconds to 300 seconds. As a result, oxides and adsorbed molecules on the surface of the first ceramic plate 21 with the first modified layer 21a and the surface of the second ceramic plate 22 with the second modified layer 22a are removed, thereby forming and activating an amorphous layer. Then, while maintaining high vacuum conditions, the two surfaces are overlapped with the surface of the first ceramic plate 21 with the first modified layer 21a facing the surface of the second ceramic plate 22 with the second modified layer 22a, and bonded under pressure (direct bonding). The load during pressurization is set to, for example, 0.1 kN to 50 kN. This results in a joint formed by joining the first ceramic plate 21 and the second ceramic plate 22. It should be noted that, to improve the joint strength, the joint can also be subjected to heat treatment. For example, it can be heat-treated at approximately 100°C after joining at room temperature.

[0050] Under high vacuum, the surfaces of the second ceramic plate 22 with the third modified layer 22b (polished surface) and the third ceramic plate 23 with the fourth modified layer 23b (polished surface) in the obtained composite are subjected to surface activation treatment (high-speed electron beam (FAB) or plasma activation treatment). This removes oxides and adsorbed molecules from the surfaces of the second ceramic plate 22 with the third modified layer 22b and the third ceramic plate 23 with the fourth modified layer 23b, thereby forming and activating an amorphous layer. Then, while maintaining high vacuum conditions, the surfaces of the second ceramic plate 22 with the third modified layer 22b and the third ceramic plate 23 with the fourth modified layer 23b are aligned, and bonding is performed under pressure (direct bonding). It should be noted that the FAB conditions and the load during pressure application are as described above. This yields a ceramic plate laminate 20. It should be noted that, to improve the bonding strength of the ceramic plate laminate 20, heat treatment can also be applied to the ceramic plate laminate 20. For example, after joining at room temperature, a heat treatment of about 100°C can be performed.

[0051] For the amorphous layer, its strength was compared with that of the AD film and the spray-coated film. An AD film was formed on the surface of a separately prepared MMC substrate (test piece). Cylindrical anti-slip studs were fixed to the surface of the AD film using adhesive. An upward load (direction away from the AD film) was applied to the anti-slip studs. The result was that, at approximately 60 MPa, the AD film itself did not fracture at the interface between it and the test piece. Furthermore, a spray-coated film was formed instead of the AD film, and the same experiment was conducted. The result was that the spray-coated film also fractured at approximately 60 MPa. On the other hand, anti-slip studs were fixed to the surface of the first ceramic plate 21 of the ceramic plate laminate 20 using adhesive. An upward load was applied to the anti-slip studs, and the interface between the anti-slip studs and the ceramic plate fractured at 70 MPa. Therefore, it can be concluded that the amorphous layer has stronger strength than the AD film and the spray-coated film.

[0052] In the semiconductor manufacturing apparatus component 10 described above, the insulation withstand voltage of the first ceramic plate 21, which has a wafer mounting surface 26 on its upper surface, is higher than that of the alumina and the second ceramic plate 22, exceeding 70 kV / mm. Therefore, even if a large potential difference is generated between the wafer W and the adsorption electrode 27, there is little concern about insulation failure of the first ceramic plate 21. Furthermore, since a first amorphous layer 24 exists between the first ceramic plate 21 and the second ceramic plate 22, the bonding strength between the two plates 21 and 22 becomes higher. A second amorphous layer 25 also exists between the second ceramic plate 22 and the third ceramic plate 23, thus the bonding strength between the two plates 22 and 23 also becomes higher.

[0053] Furthermore, the insulation withstand voltage of the first ceramic plate 21 is preferably 120kV / mm or higher. Alternatively, the first ceramic plate 21 and the second ceramic plate 22 can also be alumina plates with different insulation withstand voltages.

[0054] Furthermore, the third ceramic plate 23 is made of a material with a higher thermal conductivity than the second ceramic plate 22 (e.g., AlN sintered body), thus improving the heat uniformity and heat dissipation of the wafer W.

[0055] Furthermore, the semiconductor manufacturing apparatus component 10 uses a laminate of a first ceramic plate 21 and a second ceramic plate 22. Therefore, ceramic plates with different properties can be used as the first ceramic plate 21 and the second ceramic plate 22. This makes it easy to adapt to the characteristics required by the semiconductor manufacturing apparatus component 10.

[0056] Furthermore, the purity of the second ceramic plate 22 can also be lower than that of the first ceramic plate 21. In this way, it is possible to manufacture the component 10 for a semiconductor manufacturing device at a lower cost.

[0057] It should be noted that the present invention is not limited to any of the above embodiments. As long as it falls within the technical scope of the present invention, it can be implemented in various ways.

[0058] For example, in the aforementioned component 10 for a semiconductor manufacturing apparatus, such as Figure 5 As shown, the ceramic plate laminate 20 can also have a refrigerant flow path 70 positioned in the second ceramic plate 22 facing the amorphous layer 25. Alternatively, as... Figure 6 As shown, the ceramic plate laminate 20 can also have a refrigerant flow path 70 positioned in the third ceramic plate 23 facing the amorphous layer 25. Figure 5 and Figure 6 In this drawing, the same reference numerals are used to denote the same components as in the embodiments described above. The refrigerant flow path 70, viewed from top view, is formed integrally on the wafer mounting surface 26 in a single stroke from one end (inlet) to the other end. A supply port and a return port (not shown) of an external refrigerant device are connected to one end and the other end of the refrigerant flow path 70, respectively. Refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 70 returns to the return port of the external refrigerant device from the other end of the refrigerant flow path 70 after passing through the refrigerant flow path 70, and is then supplied back to one end of the refrigerant flow path 70 from the supply port after temperature adjustment.

[0059] In the aforementioned component 10 for a semiconductor manufacturing apparatus, such as Figure 7 As shown, the ceramic plate laminate 20 can also have a gas flow path 80 positioned in the second ceramic plate 22 facing the amorphous layer 25. Alternatively, as... Figure 8 As shown, the ceramic plate laminate 20 can also have a gas flow path 80 positioned in the third ceramic plate 23 facing the amorphous layer 25. Figure 7 and Figure 8 In this drawing, the same reference numerals are used to denote the same components as in the embodiments described above. The gas flow path 80 is an annular flow path concentric with the ceramic plate laminate 20. The ceramic plate laminate 20 includes: a gas supply path 81 disposed from the lower surface of the cooling plate 30 in communication with the gas flow path 80; and a gas ejection path 82 opening from multiple locations of the gas flow path 80 to the reference surface 26c of the wafer mounting surface 26. Gas (e.g., a heat-conducting gas such as He gas) supplied from the gas supply path 81 to the gas flow path 80 fills the space on the lower surface side of the wafer W (the space surrounded by the lower surface of the wafer W, the sealing strip 26a, the small circular protrusion 26b, and the reference surface 26c) from the gas ejection path 82. The filling gas ensures good thermal conductivity between the wafer W and the wafer mounting surface 26.

[0060] In the above embodiments, when the first ceramic plate 21 can no longer exhibit its initial characteristics due to years of deterioration, etc., by... Figures 9-11 The method for regenerating the component 10 of the semiconductor manufacturing apparatus shown enables the regeneration and reuse of the component 10. Figures 9-11In this drawing, the same reference numerals are used to denote the same components as in the embodiments described above. It should be noted that in... Figures 9-11 For convenience, the joining plate 40 and the cooling plate 30 are omitted.

[0061] For example, in Figure 9 In the middle, for components 10 of semiconductor manufacturing equipment ( Figure 9 The upper surface (including the wafer mounting surface 26) of the first ceramic plate 21 in (A) is processed and removed, leaving the lower part of the first ceramic plate 21. Figure 9 (B). Thus, the processing surface of the wafer mounting surface 26 formed on the first ceramic plate 21 is removed. Next, the processing surface of the first ceramic plate 21 is further processed to form a new wafer mounting surface 126 (sealing strip 126a, small circular protrusion 126b, and reference surface 126c). Figure 9 (C). This allows for the production of a reusable semiconductor manufacturing apparatus component 110. The processing method is not particularly limited; for example, grinding or polishing can be used. Other processing methods include sandblasting and laser processing. Sandblasting can also selectively remove the sealing strip 26a and the small circular protrusions 26b constituting the wafer mounting surface 26 by masking the wafer mounting surface 26. Furthermore, a new wafer mounting surface 126 (sealing strip 126a, small circular protrusions 126b, and reference surface 126c) can be formed using sandblasting, laser processing, or the like.

[0062] exist Figure 10 In the middle, for components 10 of semiconductor manufacturing equipment ( Figure 10 The upper surface (including the wafer mounting surface 26) of the first ceramic plate 21 in (A) is processed and removed, leaving the lower part of the first ceramic plate 21. Figure 10 (B). Thus, the processing surface formed on the first ceramic plate 21, the wafer mounting surface 26, is removed. Next, a regeneration ceramic plate 221 with an insulation withstand voltage higher than the second ceramic plate 22 and exceeding 70 kV / mm is prepared. Figure 10 (C). The regenerated ceramic plate 221 has a wafer mounting surface 226 (sealing strip 226a, small circular protrusions 226b, and reference surface 226c) pre-formed on its upper surface. Next, the processed surfaces of the first ceramic plate 21 and the lower surface of the regenerated ceramic plate 221 are polished and ground. After surface activation treatment of each ground surface, the two are joined (direct joining). Figure 10(D). After bonding, an amorphous layer 224 is formed between the first ceramic plate 21 and the recycled ceramic plate 221. This provides a reusable component 210 for a semiconductor manufacturing apparatus. It should be noted that the recycled ceramic plate 221 can also be a ceramic plate without the wafer mounting surface 226 formed thereon. In this case, after bonding the recycled ceramic plate 221 to the processed surface of the first ceramic plate 21, the wafer mounting surface 226 can be formed on the upper surface of the recycled ceramic plate 221. There are no particular limitations on the processing method; for example, grinding or polishing can be used. Other processing methods include sandblasting and laser processing. It is acceptable if the insulation withstand voltage of the recycled ceramic plate 221 is higher than that of the second ceramic plate 22 and is 70 kV / mm or more, but in order to reproduce the performance of the component 10 for a semiconductor manufacturing apparatus, the recycled ceramic plate 221 is preferably composed of the same material as the first ceramic plate 21. Furthermore, the wafer mounting surface 226 can be formed by sandblasting, laser processing, or the like.

[0063] exist Figure 11 In the middle, for components 10 of semiconductor manufacturing equipment ( Figure 11 The first ceramic plate 21 in (A) is ground and removed, exposing the second ceramic plate 22. Figure 11 (B). Here, together with the first ceramic plate 21, the first amorphous layer 24 is also processed and removed (it can also be further removed to the second modified layer 22a (see B)). Figure 3 Thus, the processed surface (exposed surface) is formed on the second ceramic plate 22. Next, a recyclable ceramic plate 321 with an insulation withstand voltage higher than that of the second ceramic plate 22 and above 70kV / mm is prepared. Figure 11 (C). The regenerated ceramic plate 321 has a wafer mounting surface 326 (sealing strip 326a, small circular protrusions 326b, and reference surface 326c) pre-formed on its upper surface. Next, the exposed processed surface of the second ceramic plate 22 and the lower surface of the regenerated ceramic plate 321 are polished and ground. After surface activation treatment of the ground surfaces, the two are joined (direct joining). Figure 11(D). After bonding, an amorphous layer 324 is formed between the recycled ceramic plate 321 and the second ceramic plate 22. This provides a reusable component 310 for a semiconductor manufacturing apparatus. It should be noted that the recycled ceramic plate 321 can also be a ceramic plate without the wafer mounting surface 326 formed thereon. In this case, after bonding the recycled ceramic plate 321 to the exposed processing surface of the second ceramic plate 22, the wafer mounting surface 326 can be formed on the upper surface of the recycled ceramic plate 321. There are no particular limitations on the processing method; for example, grinding or polishing can be used. Other processing methods include sandblasting and laser processing. It is acceptable if the insulation withstand voltage of the recycled ceramic plate 321 is higher than that of the second ceramic plate 22, exceeding 70 kV / mm, but to reproduce the performance of the component 10 for a semiconductor manufacturing apparatus, the recycled ceramic plate 321 is preferably composed of the same material as the first ceramic plate 21. Furthermore, the wafer mounting surface 326 can be formed by sandblasting, laser processing, or the like.

[0064] In the ceramic plate laminate 20 of the semiconductor manufacturing apparatus component 10 described above, although the third ceramic plate 23 is formed using a material with a higher thermal conductivity than the second ceramic plate 22, it is not particularly limited to this. For example, the third ceramic plate 23 can also be formed using a material with a lower purity than the second ceramic plate 22 (e.g., an alumina sintered body with a purity of 90% to 95%). In this way, the cost of the third ceramic plate 23 can be kept relatively low.

[0065] The ceramic plate laminate 20 of the semiconductor manufacturing apparatus component 10 described above includes a third ceramic plate 23, but may not include a third ceramic plate 23.

[0066] In the aforementioned component 10 for a semiconductor manufacturing apparatus, an adsorption electrode 27 and a heater electrode 28 are embedded in the second ceramic plate 22. However, it is also possible to embed only either the adsorption electrode 27 or the heater electrode 28 in the second ceramic plate 22. Alternatively, an RF electrode may be further embedded in the second ceramic plate 22. Furthermore, instead of embedding the adsorption electrode 27 in the second ceramic plate 22, the adsorption electrode 27 may be embedded in the first ceramic plate 21.

[0067] In the aforementioned semiconductor manufacturing apparatus component 10, the heater electrode 28 employs a structure in which resistive heating elements are distributed throughout the wafer mounting surface 26 via an overall wiring. However, the wafer mounting surface 26 may be divided into multiple regions, and heater electrodes may be embedded in each region to enable independent power control.

[0068] In the aforementioned semiconductor manufacturing apparatus component 10, at least one portion of the ceramic plate laminate 20, the outer periphery of the bonding layer 40, and the side surface of the base plate 30 can be covered with an insulating film. Examples of insulating films include sprayed films of alumina, yttrium oxide, etc.

[0069] This application is based on Japanese Patent Application No. 2024-055225, filed on March 29, 2024, the entire contents of which are incorporated herein by reference.

[0070] Industrial availability This invention can be used in semiconductor manufacturing apparatus.

[0071] Explanation of reference numerals in the attached figures 10: Components for semiconductor manufacturing equipment 20: Ceramic plate laminate 21: First ceramic plate 21a: First metamorphic layer 22: Second ceramic plate 22a: Second metamorphic layer 22b: Third metamorphic layer 23: Third ceramic plate 23b: Fourth metamorphic layer 24: First amorphous layer 25: Second amorphous layer 26: Wafer mounting surface 26a: Sealing tape 26b: Small round protrusion 26c: Reference plane 27: Adsorption electrode 28: Heater electrode 30: Cooling plate 32: Refrigerant Flow Path 40: Adhesive sheet 50: Grinding device 52: Grinding Platform 54: Grinding pad 56: Carrier 58: pipe 70: Refrigerant Flow Path 80: Gas Flow Path 81: Gas supply path 82: Gas ejection path.

Claims

1. A component for a semiconductor manufacturing apparatus, characterized in that, have: The first ceramic plate has a wafer mounting surface on its upper surface; The second ceramic plate is disposed on the lower surface of the first ceramic plate; An adsorption electrode is embedded in the first ceramic plate or the second ceramic plate; as well as A first amorphous layer exists between the first ceramic plate and the second ceramic plate. The insulation withstand voltage of the first ceramic plate is higher than that of the second ceramic plate, and is above 70kV / mm.

2. The component for a semiconductor manufacturing apparatus according to claim 1, wherein, The insulation withstand voltage of the first ceramic plate is above 120kV / mm.

3. The component for a semiconductor manufacturing apparatus according to claim 1 or 2, wherein, The first ceramic plate and the second ceramic plate are alumina plates with different insulation and voltage resistance.

4. The component for a semiconductor manufacturing apparatus according to claim 1 or 2, wherein, The component for the semiconductor manufacturing apparatus includes: A first modified layer, which exists on the side of the first ceramic plate in contact with the first amorphous layer; and The second modified layer exists on the side of the second ceramic plate that is in contact with the first amorphous layer.

5. The component for a semiconductor manufacturing apparatus according to claim 1 or 2, wherein, The component for the semiconductor manufacturing apparatus includes: A third ceramic plate, disposed on the lower surface of the second ceramic plate; and A second amorphous layer exists between the second ceramic plate and the third ceramic plate.

6. The component for a semiconductor manufacturing apparatus according to claim 5, wherein, A refrigerant flow path for refrigerant to flow or a gas flow path for supplying gas to the wafer mounting surface is provided at a position in the second ceramic plate facing the second amorphous layer or at a position in the third ceramic plate facing the second amorphous layer.

7. The component for a semiconductor manufacturing apparatus according to claim 5, wherein, The component for the semiconductor manufacturing apparatus includes: A third modified layer exists on the side of the second ceramic plate that contacts the second amorphous layer; and A fourth altered layer exists on the side of the third ceramic plate that is in contact with the second amorphous layer.

8. A method for regenerating components for a semiconductor manufacturing apparatus, characterized in that, The process includes the following steps: (a) A process of processing the upper surface of the first ceramic plate of a component for a semiconductor manufacturing apparatus according to claim 1 or 2, forming a processed surface on the first ceramic plate from which the wafer mounting surface has been removed; and (b) A process of further processing the processing surface to form a new wafer mounting surface.

9. A method for regenerating components for a semiconductor manufacturing apparatus, characterized in that, The process includes the following steps: (a) A process of processing the upper surface of the first ceramic plate of a component for a semiconductor manufacturing apparatus according to claim 1 or 2, forming a processed surface on the first ceramic plate from which the wafer mounting surface has been removed; and (b) A process of directly bonding a regenerable ceramic plate with an insulation withstand voltage higher than that of the second ceramic plate and greater than 70 kV / mm to the processed surface.

10. A method for regenerating components for a semiconductor manufacturing apparatus, characterized in that, The process includes the following steps: (a) A step of processing and removing the first ceramic plate of a component for a semiconductor manufacturing apparatus according to claim 1 or 2 to expose the second ceramic plate, and forming a processed surface on the second ceramic plate; and (b) A process of directly bonding a regenerable ceramic plate with an insulation withstand voltage higher than that of the second ceramic plate and greater than 70 kV / mm to the processed surface.

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