Enhanced power rail connection

Abstract

A semiconductor structure has a power rail between at least two front side semiconductor devices and a connector via connecting the power rail and a back side metal layer of a back side power supply network. The connector via is located within a shallow isolation trench. The connector via has a top surface that is lower than a top surface of the shallow isolation trench. The connector via provides a direct connection between the power rail connected to at least one of the front side semiconductor devices and the back side power supply network.

Description

Background Technology

[0001] The present invention generally relates to forming semiconductor devices, and more specifically, to advanced semiconductor devices having power rails and a rear power supply network.

[0002] The amount of data we process is increasing rapidly at a rate exceeding Moore's Law. The increasing demands on system performance, driven at least in part by the growing use of artificial intelligence, continue to push for tighter spacing and smaller semiconductor chips. The scaling of logic and memory devices at two-nanometer nodes necessitates scaling planar and non-planar semiconductor device structures, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), to even smaller dimensions.

[0003] As the semiconductor industry continues to move towards two-nanometer technology nodes with smaller device elements featuring tighter spacing and improved performance, the use of back-side interconnect (BEOL) layers for back-side power supply networks (BSOLs) is increasing. Creating a BEOL layer beneath the front-end-of-line (FOL) semiconductor device provides improved power performance and more routing options, thus mitigating some BEOL wiring congestion. The BEOL BSOL improves the gate delay of the semiconductor device and reduces BEOL wiring congestion. Summary of the Invention

[0004] The following overview is provided to give a basic understanding of one or more embodiments of this disclosure. This overview is not intended to identify key elements or to limit any scope of a particular embodiment or any scope of the claims.

[0005] The disclosed aspects relate to a semiconductor structure including a power rail and a connector via that connects the power rail to a back metal layer, wherein the connector via is located within a shallow isolation trench.

[0006] The disclosed aspects of the invention relate to a semiconductor structure having a connector via. In an embodiment, the connector via is a copper element having a trapezoidal cross-section. The connector via has a width greater than the width of its top surface than its bottom surface. A portion of a power rail is located directly above and in contact with the top surface of the connector via. The power rail extends between the gates of at least two adjacent semiconductor devices. A back metal layer of a back-side power supply network is in contact with the bottom surface of the connector via.

[0007] The disclosed aspects of the invention relate to a semiconductor structure having a connector via. The connector via is a copper element with a trapezoidal cross-section, located in the bottom portion of a shallow isolation trench. The connector via has a top surface whose width is greater than the width of its bottom surface. A liner is located on the sidewalls of the connector via. Power rails are located directly above and in contact with the top surface of the connector via. The power rails are located between the gates of at least two adjacent semiconductor devices. A back metal layer is in contact with the bottom surface of the connector via.

[0008] The disclosed aspects of the invention relate to a method of forming a semiconductor structure, the method comprising etching a hole between two portions of a nanosheet stack, wherein the hole extends to the bottom surface of a shallow isolation trench (STI). The method comprises depositing an inner liner layer in the hole. The method comprises removing a horizontal portion of the inner liner layer using a directional etching process and epitaxially growing a placeholder layer in the bottom portion of the hole. The top surface of the placeholder layer is below the top surface of the STI. The method comprises removing exposed portions of the inner liner layer. The method comprises depositing and recessing an oxide layer. A portion of the oxide layer remains on the placeholder layer. The method comprises forming source / drain electrodes using epitaxy and forming a replacement metal gate. The method comprises forming a power rail having a power rail liner layer in contact with the placeholder layer. The method comprises forming gate contacts and source / drain contacts, wherein one source / drain contact is connected to the power rail. The method comprises removing a back substrate, an etch stop layer, and a portion of the semiconductor material directly beneath the STI. The method comprises removing a portion of the deposited backside interlayer dielectric to expose the bottom surface of the placeholder layer, and then removing the placeholder layer. The method includes depositing and patterning a back-side interlayer dielectric, and depositing a metal layer in vias formed by removing a placeholder layer and on the back-side interlayer dielectric. A portion of the metal layer deposited in the vias formed by removing the placeholder layer is a connector via, and a portion of the metal layer in the back-side interlayer dielectric is a first back-side metal layer for a back-side power supply network.

[0009] The disclosed aspects of the invention relate to a method for forming a semiconductor structure, the method comprising etching a hole between two portions of a nanosheet stack, wherein the hole extends to the bottom of a shallow isolation trench (STI). A first liner layer is deposited over the semiconductor structure. The method includes removing a horizontal portion of the first liner layer using a directional etching process and depositing a second liner layer. The method includes removing a horizontal portion of the second liner layer. The method includes growing a placeholder layer in a portion of the hole using epitaxy. The top surface of the placeholder layer is lower than the top surface of the STI. The method includes removing exposed portions of the first and second liner layers. The method includes depositing and recessing an oxide. A portion of the oxide remains on the placeholder layer. The method includes forming source / drain electrodes using epitaxy and forming a replacement metal gate. The method includes forming a power rail having a liner layer in contact with the placeholder layer. The method includes forming a gate contact and a source / drain contact, wherein one source / drain contact is connected to the power rail. The method includes removing a back substrate, an etch stop layer, and portions of the semiconductor material. The method includes removing a portion of the deposited back-side interlayer dielectric to expose the bottom surface of the placeholder layer, and then removing the placeholder layer. The method also includes forming connector vias by depositing metal in the vias formed by removing the placeholder layer and forming a back-side metal layer on the connector vias. The connector vias connect the back-side metal layer of the back-side power supply network to power rails on the front side of the semiconductor substrate. Attached Figure Description

[0010] The above and other aspects, features and advantages of various embodiments of the present invention will become more apparent from the following description, taken in conjunction with the accompanying drawings.

[0011] Figure 1 A top view depicting a semiconductor design according to an embodiment of the present invention.

[0012] Figure 2 A cross-sectional view Y1-Y1 depicts a semiconductor structure after a dielectric insulating material has been deposited over a stack of two nanosheets according to an embodiment of the present invention.

[0013] Figure 3 Cross-sectional views Y1-Y1 of a semiconductor structure after deposition of a first inner liner layer, patterning of power rail etching, and etching of power rail openings according to an embodiment of the present invention are depicted.

[0014] Figure 4 Cross-sectional views Y1-Y1 of a semiconductor structure after optionally removing the horizontal portion of the first inner liner layer, according to an embodiment of the invention, are depicted.

[0015] Figure 5Cross-sectional views Y1-Y1 of a semiconductor structure after optionally forming an additional thickness of a first inner liner and removing the horizontal portion of the thicker inner liner, according to an embodiment of the invention, are depicted.

[0016] Figure 6 Cross-sectional views Y1-Y1 depict a semiconductor structure after a placeholder layer has been grown on the bottom surface of the power rail opening according to an embodiment of the present invention.

[0017] Figure 7 A cross-sectional view Y1-Y1 of a semiconductor structure after the exposed surface of the inner liner has been removed, according to an embodiment of the present invention, is depicted.

[0018] Figure 8 Cross-sectional views Y1-Y1 depict a semiconductor structure after oxide deposition, CMP performance, and oxide pitting according to an embodiment of the present invention.

[0019] Figure 9 A top view of a semiconductor structure with a placeholder layer according to an embodiment of the present invention is depicted.

[0020] Figure 10A Cross-sectional views X1-X1 depict a semiconductor structure after the formation of a dummy gate, according to an embodiment of the present invention.

[0021] Figure 10B A cross-sectional view Y1-Y1 of a semiconductor structure after the formation of a dummy gate is depicted according to an embodiment of the present invention.

[0022] Figure 10C A cross-sectional view Y2-Y2 of the semiconductor structure after the formation of the dummy gate is depicted according to an embodiment of the present invention.

[0023] Figure 11A Cross-sectional views X1-X1 of a semiconductor structure following the deposition of an interlayer dielectric (ILD) according to an embodiment of the present invention are depicted.

[0024] Figure 11B Cross-sectional views Y1-Y1 of a semiconductor structure after epitaxial growth of a placeholder layer and deposition of an ILD according to an embodiment of the present invention are depicted.

[0025] Figure 11C A cross-sectional view Y2-Y2 of a semiconductor structure after epitaxial formation of a placeholder layer and deposition of an ILD is depicted according to an embodiment of the present invention.

[0026] Figure 12A Cross-sectional views X1-X1 of a semiconductor structure after the removal of the dummy gate material and the sacrificial layer according to an embodiment of the present invention are depicted.

[0027] Figure 12B Cross-sectional views Y1-Y1 depict the semiconductor structure after the removal of the dummy gate material and the sacrificial layer, according to an embodiment of the present invention.

[0028] Figure 12C A cross-sectional view Y2-Y2 of a semiconductor structure after the removal of the dummy gate material and the sacrificial layer is depicted according to an embodiment of the present invention.

[0029] Figure 13A Cross-sectional views X1-X1 depict a semiconductor structure after the formation of a replacement metal gate, according to an embodiment of the present invention.

[0030] Figure 13B A cross-sectional view Y1-Y1 depicts a semiconductor structure after the formation of a replacement metal gate according to an embodiment of the present invention.

[0031] Figure 13C A cross-sectional view Y2-Y2 of a semiconductor structure after the formation of a replacement metal gate, according to an embodiment of the present invention, is depicted.

[0032] Figure 14A Cross-sectional views X1-X1 of a semiconductor structure after etching openings for power rails, according to an embodiment of the present invention, are depicted.

[0033] Figure 14B A cross-sectional view Y1-Y1 of a semiconductor structure after etching openings for power rails, according to an embodiment of the present invention, is depicted.

[0034] Figure 14C A cross-sectional view Y2-Y2 of a semiconductor structure after etching openings for power rails, according to an embodiment of the present invention, is depicted.

[0035] Figure 15A Cross-sectional views X1-X1 of a semiconductor structure after deposition of an inner liner for a power rail, according to an embodiment of the present invention, are depicted.

[0036] Figure 15B Cross-sectional views Y1-Y1 of a semiconductor structure after deposition of an inner liner for power rails, according to an embodiment of the present invention, are depicted.

[0037] Figure 15C A cross-sectional view Y2-Y2 of a semiconductor structure after deposition of an inner liner for power rails, according to an embodiment of the present invention, is depicted.

[0038] Figure 16 A top view illustrating a semiconductor design with power rails according to an embodiment of the present invention is shown.

[0039] Figure 16A Cross-sectional views X1-X1 depict a semiconductor structure following the deposition of power rail metal according to an embodiment of the present invention.

[0040] Figure 16B A cross-sectional view Y1-Y1 depicts a semiconductor structure following the deposition of power rail metal according to an embodiment of the present invention.

[0041] Figure 16C A cross-sectional view Y2-Y2 of a semiconductor structure following the deposition of power rail metal, according to an embodiment of the present invention, is depicted.

[0042] Figure 17A Cross-sectional views X1-X1 of a semiconductor structure after the deposition of another ILD layer according to an embodiment of the present invention are depicted.

[0043] Figure 17B A cross-sectional view Y1-Y1 of a semiconductor structure after the deposition of another ILD layer is depicted according to an embodiment of the present invention.

[0044] Figure 17C A cross-sectional view Y2-Y2 of a semiconductor structure after the deposition of another ILD layer is depicted according to an embodiment of the present invention.

[0045] Figure 18A Cross-sectional views X1-X1 depict a semiconductor structure after patterning an OPL layer and etching source / drain (S / D) contact holes according to an embodiment of the present invention.

[0046] Figure 18B Cross-sectional views Y1-Y1 depict a semiconductor structure after patterning the OPL and etching the gate contact holes according to an embodiment of the present invention.

[0047] Figure 18C A cross-sectional view Y2-Y2 of a semiconductor structure after patterning the OPL and etching the S / D contact holes is depicted according to an embodiment of the present invention.

[0048] Figure 19A Cross-sectional views X1-X1 of a semiconductor structure after contact formation are depicted according to an embodiment of the present invention.

[0049] Figure 19B A cross-sectional view Y1-Y1 of a semiconductor structure after contact formation is depicted according to an embodiment of the present invention.

[0050] Figure 19C A cross-sectional view Y2-Y2 of the semiconductor structure after the formation of contacts is depicted according to an embodiment of the present invention.

[0051] Figure 20ACross-sectional views X1-X1 depict a semiconductor structure after deposition of an ILD layer, formation of vias, formation of one or more metal layers, and front-side interconnect wiring according to an embodiment of the present invention.

[0052] Figure 20B Cross-sectional views Y1-Y1 depict a semiconductor structure after deposition of an ILD layer, formation of vias, formation of one or more metal layers, and front-side interconnect wiring according to an embodiment of the present invention.

[0053] Figure 20C A cross-sectional view Y2-Y2 depicts a semiconductor structure after deposition of an ILD layer, formation of vias, formation of one or more metal layers, and front-side interconnect wiring according to an embodiment of the present invention.

[0054] Figure 21A Cross-sectional views X1-X1 of a semiconductor structure after the removal of the semiconductor substrate and etch stop layer according to an embodiment of the present invention are depicted.

[0055] Figure 21B Cross-sectional views Y1-Y1 of a semiconductor structure after the removal of the semiconductor substrate and etch stop layer according to an embodiment of the present invention are depicted.

[0056] Figure 21C A cross-sectional view Y2-Y2 of the semiconductor structure after the removal of the semiconductor substrate and the etch stop layer is depicted according to an embodiment of the present invention.

[0057] Figure 22A Cross-sectional views X1-X1 of a semiconductor structure are depicted according to an embodiment of the invention, after a portion of the semiconductor material has been removed and a portion of the semiconductor material between adjacent shallow trench isolation (STI) sections has been recessed.

[0058] Figure 22B Cross-sectional views Y1-Y1 depict a semiconductor structure after a portion of the semiconductor material has been removed and a portion of the semiconductor material between adjacent STIs has been recessed, according to an embodiment of the present invention.

[0059] Figure 22C A cross-sectional view Y2-Y2 of a semiconductor structure is depicted according to an embodiment of the present invention after a portion of the semiconductor material has been removed and the portion of the semiconductor material between the STIs has been further recessed.

[0060] Figure 23A Cross-sectional views X1-X1 of a semiconductor structure following the deposition of a backside ILD according to an embodiment of the present invention are depicted.

[0061] Figure 23BA cross-sectional view Y1-Y1 of a semiconductor structure after deposition of a backside ILD is depicted according to an embodiment of the present invention.

[0062] Figure 23C A cross-sectional view Y2-Y2 of a semiconductor structure after deposition of a backside ILD is depicted according to an embodiment of the present invention.

[0063] Figure 24A Cross-sectional views X1-X1 depict a semiconductor structure after patterning and etching openings in the back-side ILD according to an embodiment of the present invention.

[0064] Figure 24B A cross-sectional view Y1-Y1 of a semiconductor structure after the deposition of another ILD layer is depicted according to an embodiment of the present invention.

[0065] Figure 24C A cross-sectional view Y2-Y2 depicts a semiconductor structure after patterning and etching openings in the back-side ILD according to an embodiment of the present invention.

[0066] Figure 25A Cross-sectional views X1-X1 of a semiconductor structure after the removal of the placeholder layer are depicted according to an embodiment of the present invention.

[0067] Figure 25B A cross-sectional view Y1-Y1 of a semiconductor structure after the removal of the placeholder layer is depicted according to an embodiment of the present invention.

[0068] Figure 25C A cross-sectional view Y2-Y2 of a semiconductor structure after the removal of the placeholder layer is depicted according to an embodiment of the present invention.

[0069] Figure 26A Cross-sectional views X1-X1 of a semiconductor structure after the formation of a first back metal layer are depicted according to an embodiment of the present invention.

[0070] Figure 26B A cross-sectional view Y1-Y1 of a semiconductor structure after the formation of a first back metal layer is depicted according to an embodiment of the present invention.

[0071] Figure 26C A cross-sectional view Y2-Y2 of a semiconductor structure after the formation of a first back metal layer is depicted according to an embodiment of the present invention.

[0072] Figure 27B Cross-sectional views Y1-Y1 depict a semiconductor structure without a thick inner liner after the formation of a first back metal layer, according to an embodiment of the present invention.

[0073] Figure 27CA cross-sectional view Y2-Y2 depicts a semiconductor structure without a thick inner liner after the formation of a first back metal layer, according to an embodiment of the present invention. Detailed Implementation

[0074] Embodiments of the present invention recognize that overlap misalignment of vias and power rails, along with high aspect ratios, results in increased resistance or voltage drops (e.g., a decrease in current multiplied by resistance (IR drop)), which degrades the electrical performance of semiconductor devices and chips, particularly in semiconductor devices using back-side wiring and back-side power supply networks (BSPDNs). Semiconductor device designs using semiconductor manufacturing processes that reduce overlap misalignment and decrease aspect ratios in vias and power rails will improve the electrical performance of semiconductor devices and chips.

[0075] The present invention provides a semiconductor device having a connector via and a method of forming the semiconductor device, the connector via directly connecting power rails extending above and below the semiconductor device to a back metal layer of a back power supply network.

[0076] In an aspect of the invention, the connector via is formed by a placeholder layer in the bottom portion of a shallow trench isolation (STI). The trench for forming the placeholder layer is etched from the front side of the semiconductor structure. The bottom portion of the trench is filled by an epitaxially grown placeholder layer. The top surface of the placeholder layer is lower than the top surface of the STI.

[0077] Power rails extending between adjacent semiconductor devices can be formed directly on a placeholder layer using known semiconductor fabrication processes. After depositing a back-side interlayer dielectric (ILD) and forming openings for back-side metal lines and vias in the back-side ILD, connector vias are formed for both the connector vias and the first back-side metal layer by removing the placeholder layer using a back-side etching process and depositing a metal such as copper in the openings formed in the STI after placeholder removal and in the openings formed in the back-side ILD. These processes, in which a placeholder layer is formed in a portion of the STI and then later replaced with a back-side metal such as copper, provide a semiconductor structure that directly connects power rails to the first back-side metal layer via connector vias located in a portion of the STI.

[0078] Aspect ratio is the ratio of the width to the depth of a hole, with holes generally easier to form at lower aspect ratios. Front-side vias (FSVs) were introduced as a type of connection for BSPDN. Due to the higher aspect ratio of FSVs, which must extend at least to the STI (Surface Mount Technology), additional via connections were introduced to improve or reduce the aspect ratio. However, forming additional connections from front-side vias to the BSPDN presents alignment challenges. Further scaling or miniaturization of semiconductor devices will be limited if the additional via connections are processed from the back side. Processing additional via connections from the back side introduces overlay problems. Overlay refers to the alignment accuracy of two or more layers or masks during manufacturing. Overlay is the process of precisely aligning multiple chip layers together to create a desired pattern. Overlay control largely determines the minimum feature size that can be incorporated into a semiconductor device design.

[0079] This invention utilizes a created placeholder layer to connect front-side devices and wiring to the back-side wiring of the BSPDN. By using a placeholder layer that is removed and replaced to form connections between front-side devices and wiring and the BSPDN via connector vias, the front-side via process is improved by providing a lower aspect ratio for the front-side vias. In various embodiments, the front-side via or front via is referred to as a power rail or front power rail located between adjacent semiconductor devices. Furthermore, by using a placeholder layer created from the front side of the wafer, and then replaced with a back-side contact metal using a self-aligned process, semiconductor process yield and the overlap problem of conventional front-side wiring connections to the BSPDN are improved.

[0080] The semiconductor device can be a logic or memory semiconductor device that uses connector vias to connect at least one source / drain of the semiconductor device to a power rail. The connector vias directly contact the BSPDN and the power rail, which is connected to at least one source / drain of the semiconductor device. The semiconductor device (one or more) can be a logic device such as a full-around-gate field-effect device, a FinFET, a planar FET, a stacked FET (including complementary FETs), other types of logic devices, or a memory device (including one or more stacked memory devices).

[0081] The following description, provided with reference to the accompanying drawings, is intended to aid in a comprehensive understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to aid understanding, but these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of the invention. Some of the processing steps depicted can be combined into integrated processing steps. Furthermore, for clarity and brevity, descriptions of well-known functions and constructions may be omitted.

[0082] The terms and words used in the following description and claims are not limited to their dictionary meanings, but are merely used to enable the invention to be clearly and consistently understood. Therefore, it will be apparent to those skilled in the art that the following description of exemplary embodiments of the invention is provided for illustrative purposes only and is not intended to limit the scope of the invention as defined by the appended claims and their equivalents.

[0083] It should be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context otherwise specifies. Thus, for example, a reference to “component surface” includes a reference to one or more of such surfaces unless the context otherwise specifies.

[0084] For the purposes of the following description, terms such as “up,” “down,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall be used in relation to the disclosed structures and methods, as oriented as in the accompanying drawings. Terms such as “above,” “on,” “cover,” “on top,” “at the apex,” “on,” or “on the top of” mean that a first element (such as a first structure) is present on a second element (such as a second structure), wherein an intervening element, such as an interface structure, may be present between the first and second elements. The terms “direct contact” or “contact” mean that the first element (such as a first structure) and the second element (such as a second structure) are connected without any intermediate conductive, insulating, or semiconductor layer at the interface of the two elements.

[0085] To avoid obscuring the presentation of embodiments of the present invention, some processing steps or operations known in the art may be combined in the following detailed description for illustrative purposes, and in some cases may not be described in detail. In other instances, some processing steps or operations known in the prior art may not be described at all. It should be understood that the following description focuses more on the salient features or elements of various embodiments of the present invention.

[0086] This document discloses detailed embodiments of the claimed structures and methods. The method steps described below do not form a complete process flow for fabricating integrated circuits on semiconductor chips. These embodiments can be practiced in conjunction with integrated circuit fabrication techniques for semiconductor chips and devices currently used in the field, and only include as many steps as are typically practiced for understanding the described embodiments. The accompanying drawings show cross-sectional portions of a semiconductor chip or substrate (such as a semiconductor wafer) during fabrication and are not drawn to scale but are depicted to illustrate features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art to employ the methods and structures of this disclosure in various ways. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0087] References to "one embodiment," "other embodiments," "another embodiment," "embodiment," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, it should be understood that its influence in combination with other embodiments on such feature, structure, or characteristic is within the knowledge of those skilled in the art, whether or not it has been explicitly described.

[0088] Reference will now be made in detail to embodiments of the invention, examples of which are shown in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout the drawings.

[0089] Deposition processes used for materials (such as metallic, dielectric, and sacrificial materials) include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular layer deposition (MLD), high-density plasma (HDP) deposition, or gas cluster ion beam (GCIB) deposition. Variations in CVD processes include, but are not limited to, atmospheric pressure CVD (APCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), and metal-organic CVD (MOCVD), and combinations thereof may also be employed.

[0090] The removal, stripping, or etching used herein includes, but is not limited to, patterning using photolithography, photo-etching, extreme ultraviolet (EUV) lithography, or any other known semiconductor patterning process, followed by one or more etching processes. Some examples of etching processes include, but are not limited to, dry etching processes using reactive ion etching (RIE) or ion beam etching (IBE), wet chemical etching processes, or combinations of these etching processes.

[0091] Referring now to the accompanying drawings, which provide schematic cross-sectional views of a semiconductor device at an intermediate stage of manufacturing according to one or more embodiments of the invention. The drawings are provided as a schematic representation of the device of the invention and should not be considered as precise or limiting information regarding the dimensions of the device components.

[0092] Figure 1 A top view illustrating a semiconductor design according to an embodiment of the present invention is shown. Figure 1 It includes an active region 10, a gate structure 30, and a power rail 26 with an inner liner 27, wherein Figure 1 An example of two field-effect transistors (FETs) is depicted. Although Figure 1 An example of a semiconductor device design is depicted, but in other examples, other types of one or more logic semiconductor designs or one or more memory device designs may be used in conjunction with the processes discussed later in the embodiments of the present invention.

[0093] Figure 1 Also shown are cross-sectional views Y1-Y1 parallel to and passing through one of the gate structures 30, and cross-sectional views Y2-Y2 parallel to and between two adjacent gate structures 30. Additionally, in Figure 1 The image shows the position of cross-sectional view X1-X1 in the top active region 10, which is perpendicular to the gate structure 30, cross-sectional view Y1-Y1, and cross-sectional view Y2-Y2.

[0094] As shown in the figure, the semiconductor design illustrates two semiconductor devices, which can be two logic devices (e.g., such as...). Figure 27B and Figure 27C The two semiconductor devices shown are either two GAA FETs or two memory devices. In some embodiments, the two semiconductor devices are two or more stacked semiconductor devices (e.g., stacked FETs, complementary FETs, or stacked memory devices).

[0095] exist Figure 9 In addition to the accompanying drawings, cross-sectional views X1-X1 are shown in the drawings labeled with the letter "A"; cross-sectional views Y1-Y1 are shown in the drawings labeled with the letter "B"; and cross-sectional views Y2-Y2 are shown in the drawings labeled with the letter "C".

[0096] Figure 2 Cross-sectional views Y1-Y1 depict a semiconductor structure after depositing a dielectric isolation 8 over a stack of two nanosheets according to an embodiment of the present invention. The nanosheet stack consists of alternating channel 6 nanosheet layers and sacrificial material 7 nanosheet layers. As shown in the figure... Figure 2The device includes a substrate 2 below etch stop 3, a semiconductor material 4 on etch stop 3, a shallow trench isolation (STI) 5 in a portion of the semiconductor material 4, and two nanosheet stacks having alternating layers of sacrificial material 7 and channel 6 on the semiconductor material 4, with a dielectric isolation 8 covering the exposed surface of the nanosheet stacks. As shown, the two nanosheet stacks on the semiconductor material 4 are located above and between the STIs 5. The sacrificial material 7 can be SiGe, but is not limited to SiGe. The channel 6 can be silicon, but is not limited to this semiconductor material. The substrate 2 and the semiconductor material 4 can be silicon, but are not limited to this semiconductor material. The dielectric isolation 8 can be any dielectric material used in semiconductor devices, such as, but not limited to, SiO2.

[0097] although Figure 2 Nanosheet structures for forming two gate-all-around FETs (GAA FETs) are described, but different semiconductor structures can also be used to form different types of logic devices, such as, but not limited to, planar FETs, finFETs, complementary FETs, stacked FETs, or one or more memory devices, including stacked memory devices.

[0098] Figure 3 Cross-sectional views Y1-Y1 depict a semiconductor structure according to an embodiment of the present invention, after the deposition of the inner liner layer 31, patterning of the organic planarization layer (OPL) 32 for power rail etching, and etching of the power rail openings. As shown in the figure... Figure 3 include Figure 2 The elements, without the middle STI 5 portion, and with the addition of an inner lining layer 31 and patterned OPL 32. Figure 3 It also includes the width X t and X b , where X t It is the width of the top portion of the etched opening or trench between the two sides of the middle STI 5, and X b This refers to the width of the bottom portion of the etched opening between the two sides of the central STI 5. The width X is determined by the etching process that forms part of the opening. t Slightly larger than width X b For example, a RIE etching process that extends from the top surface of OPL 32 down to stop at semiconductor material 4 can create an opening or trench etched through the intermediate STI 5, which has an opening or hole that narrows slightly as it extends down from OPL 32 to semiconductor material 4.

[0099] In various embodiments, the inner liner 31 is composed of SiN, but is not limited to this liner material. Figure 4In the semiconductor structure shown, before the trench etching process, an inner liner 31 is deposited on the top surface of STI 5 and the sidewalls of the dielectric isolation 8. After the inner liner 31 is deposited, the opening of the trench is etched in the middle of STI 5. As shown, the trench etching process stops at semiconductor material 4.

[0100] Figure 4 A cross-sectional view Y1-Y1 depicts a semiconductor structure after the horizontal portions of OPL 32 and inner liner 31 have been removed, according to an embodiment of the present invention. As shown in the figure, Figure 4 include Figure 3 The elements are missing, but the horizontal portions of OPL 32 and liner 31 are not present.

[0101] After depositing the inner liner 31 and performing RIE to remove the horizontal portion of the inner liner 31 on the dielectric isolation 8 and the semiconductor material 4, the inner liner 31 remains on the almost vertical sidewalls and the middle STI 5.

[0102] When in Figure 5 This semiconductor structure can be used to manufacture semiconductors where the second inner liner material for the inner liner 51 is not deposited on the sidewall of the middle STI 5 during the process. Figure 27B and Figure 27C The semiconductor structure. When by skipping... Figure 5 The process steps shown, without depositing the inner liner 51 on the sidewalls of STI 5, result in the epitaxial growth of a wider site layer 66 on the semiconductor material 4, thereby leading to Figure 27B and Figure 27C The wider connector through-hole 394 is shown. This is to form... Figure 27B and Figure 27C The semiconductor structure does not perform Figure 5 Optional process steps. These can be skipped. Figure 5 After the process steps, use Figure 4 Semiconductor structure formation Figure 27B and Figure 27C Then execute Figure 5 The remaining process steps (e.g., performing...) Figure 6 The process steps and the remaining process steps to form Figure 27B and Figure 27C ).

[0103] Figure 5 Cross-sectional views Y1-Y1 depict a semiconductor structure according to an embodiment of the present invention, after optionally forming a second inner liner 51 on a first inner liner 31 and removing a horizontal portion of the inner liner 51. As shown in the figures, Figure 5 include Figure 4The elements, wherein the inner liner 51 is on the exposed sidewall of the inner liner 31. The inner liner 51 may be the same material as the inner liner 31 (e.g., SiN). In one embodiment, the inner liner 51 is an inner liner material different from that of the inner liner 31. RIE can remove any horizontal portion of the inner liner 51 on the semiconductor material 4 and the dielectric isolation 8.

[0104] Figure 6 A cross-sectional view Y1-Y1 depicts a semiconductor structure after a surcharge layer 66 has been grown on an exposed portion of the semiconductor material 4 in an opening between a channel 6 covered by a dielectric isolation 8 and two nanosheet stacks of sacrificial material 7, according to an embodiment of the present invention. As shown in the figure... Figure 6 include Figure 5 The element added a placeholder layer of 66. Additionally, in Figure 6 The diagram shows widths X1 and X2, where X1 is the width of the top surface of the placeholder layer 66 and width X2 is the width of the bottom portion of the placeholder layer 66.

[0105] Using epitaxy, a placeholder layer 66 is grown on a portion of the semiconductor material 4 between the inner liner layers 51 on the intermediate STI 5. For example... Figure 6 As shown, the top surface of the placeholder layer 66 is lower than the top surfaces of semiconductor material 4 and STI 5. The bottom of the placeholder layer 66 is located on STI 5 and flush with the bottom portion of STI 5. Figure 6 As shown, the width X1 of the occupant layer 66 can be less than 80% of the distance between the two nanosheet stacks. The cross-sectional view of the occupant layer 66 is slightly tapered and has a trapezoidal shape that is slightly wider at the top. Therefore, X1 (which is the width of the top surface of the occupant layer 66) is slightly larger than X2 (which is the width of the bottom surface of the occupant layer 66).

[0106] In some embodiments, Figure 4 In the semiconductor structure, a site layer 66 is epitaxially grown on semiconductor material 4. Figure 4 There is no inner liner 51, and in these embodiments, the placeholder layer 66 contacts the intermediate sidewall of the STI 5. Without the inner liner 51 on the STI 5, the placeholder layer 66 is wider. Using this embodiment in relation to… Figure 6-25C The process discussed led to Figure 27B and Figure 27C The semiconductor structure shown is... Figure 26B and Figure 26C Compared to semiconductor structures, due to... Figure 26B and Figure 26C Compared to the connector through-hole 294 shown, Figure 27B and Figure 27C The connector through-hole 394 shown is wider, so the embodiment with a wider spacer layer 66 is in... Figure 27B and Figure 27C This provides better electrical performance in the semiconductor structure. As described below, in Figure 27B and Figure 27C The connector through-hole 394 in the middle replaces the one in Figure 4 The spacer layer (without the inner liner 51) grown in the opening of the middle STI 5 can be replaced by Figure 6 A placeholder layer 66 is grown in the opening above the semiconductor material 4 in the middle of STI 5 to form the connector via 294.

[0107] Figure 7 A cross-sectional view Y1-Y1 of a semiconductor structure after the exposed surface of the inner liner 51 has been removed, according to an embodiment of the present invention, is depicted. As shown in the figure, Figure 7 include Figure 6 The elements, but excluding the exposed portions of the liner 51, are removed using one or more known dry or wet etching processes for removing liner materials (e.g., SiN). The exposed portions of the liner 51 on the sidewalls of the dielectric isolation 8 and on the remaining portion of the intermediate STI 5 are removed. The portions of the liner 51 between the placeholder layer 66 and the STI 5 are retained.

[0108] Figure 8 Cross-sectional views Y1-Y1 depict a semiconductor structure after deposition of dielectric 85, CMP performance, and recessing of dielectric 85 according to an embodiment of the present invention. As shown in the figures, Figure 8 include Figure 7 The element is a dielectric 85. A dielectric 85 is deposited over the semiconductor structure using a known deposition process such as CVD or PVD. For example, the dielectric 85 can be SiO2. CMP can planarize the surface of the dielectric 85 and an etching process such as RIE removes the portion of the dielectric 85 above the surface of the STI 5. A portion of the dielectric 85 remains above the placeholder layer 66 and the inner liner layer 51, which has a surface flush with the surface of the STI 5.

[0109] Figure 9 A top view illustrating a semiconductor design with a placeholder layer 66 and an inner liner layer 51 according to an embodiment of the present invention is shown. Figure 9 It includes two active regions 10, three gate structures 30, and a placeholder layer 66 with an inner liner layer 51. Additionally, Figure 9 The location of the cross-sectional views X1-X1, Y1-Y1, and Y2-Y2 is also shown. Figure 9 In the top view, the occupant layer 66 with the inner lining layer 51 has a rectangular shape, its horizontal length being parallel to the active region 10 and longer than the vertical width of the occupant layer 66. For example... Figure 9As shown, the occupancy layer 66 extends just beyond and is located between the two gate structures 30. The occupancy layer 66 is located between and parallel to the active regions 10.

[0110] Figure 10A Cross-sectional views X1-X1 depict a semiconductor structure after forming a dummy gate with dummy gate material 23, gate spacer 29, and internal spacer 15, according to an embodiment of the present invention. As shown in the figures, Figure 10A It includes a substrate 2, an etch stop layer 3, a semiconductor material 4, a channel 6, a sacrificial material 7, a dielectric isolation 8, an internal spacer 15, a gate spacer 29, and a dummy gate material 23, wherein the dummy gate material 23 is typically polysilicon.

[0111] As those skilled in the art will know, the dummy gate may include a dummy gate material 23 (e.g., polysilicon), an internal spacer 15 (e.g., SiN), and a gate spacer 29, and may be formed using known semiconductor processes.

[0112] Figure 10B A cross-sectional view Y1-Y1 of the semiconductor structure after the formation of the dummy gate is depicted according to an embodiment of the present invention. As shown in the figure, Figure 10B The system includes a substrate 2, an etch stop layer 3, a semiconductor material 4, a channel 6, a sacrificial material 7, a dielectric isolation layer 8, a dummy gate material 23, and three STIs 5, wherein the intermediate STI 5 includes a placeholder layer 66 with an inner liner layer 51 located in the bottom portion of the intermediate STI 5, and a dielectric 85 located above the placeholder layer 66 with the inner liner layer 51. The dummy gate material 23 can be deposited on the exposed surfaces of the STI 5, the dielectric isolation layer 8, and the dielectric 85.

[0113] Figure 10C The formation according to an embodiment of the present invention is described. Figure 10A and Figure 10B The cross-sectional view of the semiconductor structure after the dummy gate is shown in Y2-Y2. As shown in the figure, Figure 10C include Figure 8 Element.

[0114] Figure 11A Cross-sectional views X1-X1 depict a semiconductor structure after growing S / D 28 and depositing ILD 13 on the exposed portion of semiconductor material 4 according to an embodiment of the present invention. As shown in the figure, Figure 11A include Figure 10A The elements, as well as S / D 28 and ILD 111.

[0115] Using known epitaxial processes, two S / D 28s can be grown between the remaining portions of the nanosheet stack on the exposed surfaces of channel 6 and semiconductor material 4. Figure 11A In this configuration, the top surface of S / D 28 is higher than the top channel of channel 6 and slightly higher than the dielectric isolation 8. ILD 111 can be deposited on S / D 28, gate spacer 29, and dummy gate material 23 using PVD, CVD, or another known dielectric deposition process. CMP can planarize the top surface and remove excess ILD 111 above the dummy gate material 23.

[0116] Figure 11B The invention depicts an embodiment of the use of epitaxial growth of S / D 28 and... Figure 11A and Figure 11C A cross-sectional view Y1-Y1 of the semiconductor structure after ILD deposition. As shown in the figure. Figure 11B and Figure 10B same.

[0117] Figure 11C A cross-sectional view Y2-Y2 of the semiconductor structure according to an embodiment of the present invention is depicted after removing the following portions: channel 6, sacrificial material 7, dielectric isolation 8 above each portion of the semiconductor material 4 raised between the three STIs 5, and epitaxy for S / D 28 and deposition of ILD111. As shown in the figure... Figure 11C include Figure 10C The semiconductor material 4 contains elements, but does not include the portion consisting of two stacked nanosheets, and ILD 111 and S / D 28 are added. After removing the portion of the two stacked nanosheets consisting of channel 6, sacrificial material 7, and dielectric isolation 8 (e.g., using RIE and / or IBE), S / D 28 is epitaxially grown on the exposed portion of the semiconductor material 4. In various embodiments, S / D 28 can be epitaxially grown and doped. After forming two S / D 28s, a layer of ILD 111 can be deposited and CMP performed. ILD 111 can be an oxide (e.g., SiO2) or other materials used for interlayer dielectrics.

[0118] Figure 12A Cross-sectional views X1-X1 depict the semiconductor structure after the removal of the dummy gate material 23 and the sacrificial material 7 according to an embodiment of the present invention. As shown in the figure, Figure 12A include Figure 11A The elements, excluding dummy gate material 23 and sacrificial material 7, are removed using known dummy gate removal and sacrificial material 7 etching processes.

[0119] Figure 12BCross-sectional views Y1-Y1 depict a semiconductor structure after the removal of dummy gate material 23, dielectric isolation 8, and sacrificial material 7 according to an embodiment of the present invention. The sacrificial material 7 and dummy gate material 23 are removed using known dummy gate removal processes and sacrificial material 7 etching processes.

[0120] Figure 12C The following describes the process of removing according to an embodiment of the invention. Figure 12A and Figure 12B A cross-sectional view Y2-Y2 of the semiconductor structure following the virtual gate material 23 and sacrificial material 7. As shown in the figure. Figure 12C and Figure 11C same.

[0121] Figure 13A Cross-sectional views X1-X1 depict a semiconductor structure after the formation of the replacement metal gate (RMG) according to an embodiment of the present invention. As shown in the figures, Figure 13A include Figure 12A The elements, but excluding the dummy gate material 23, include a replacement metal gate comprising a gate 33 situated above a gate dielectric material (not shown) in place of the dummy gate material 23, internal spacer 15, and gate spacer 29. A dielectric 37 may be deposited above the exposed surface of the gate 33, wherein the gate 33 may consist of at least a work function metal situated above a high-k gate dielectric material (not shown). As known to those skilled in the art, the replacement metal gate structure includes a gate 33 with gate spacer 29 and internal spacer 15. In various embodiments, the dielectric 37 is SiN, but is not limited to this material.

[0122] Figure 13B A cross-sectional view Y1-Y1 depicts a semiconductor structure after the formation of a replacement metal gate according to an embodiment of the present invention. As shown in the figure, Figure 13B include Figure 12B The elements, as well as gate 33 and dielectric 37 located above gate 33. In various embodiments, prior to gate 33 deposition (e.g., by CVD, PVD, or ALD), Figure 12B A gate dielectric material layer (not shown) is deposited on the exposed surface (e.g., via ALD).

[0123] Figure 13C A cross-sectional view Y2-Y2 depicts a semiconductor structure after the formation of a replacement metal gate according to an embodiment of the present invention. As shown in the figure, Figure 13C and Figure 12C same.

[0124] Figure 14ACross-sectional views X1-X1 of a semiconductor structure after etching openings for power rails, according to an embodiment of the present invention, are depicted. As shown in the figures, Figure 14A and Figure 13A same.

[0125] Figure 14B A cross-sectional view Y1-Y1 of a semiconductor structure after etching openings for power rails, according to an embodiment of the present invention, is depicted. As shown in the figure, Figure 14B include Figure 13B The elements, but excluding dielectric 37, gate 33 and a portion of dielectric 85. Trenches for power rails can be etched over the placeholder layer 66 using known patterning and etching processes, and the etching process stops at the top surface of the placeholder layer 66.

[0126] Figure 14C A cross-sectional view Y2-Y2 of the semiconductor structure after etching openings for power rails, according to an embodiment of the present invention, is depicted. As shown in the figure, Figure 14C include Figure 13C The elements, but excluding the ILD 111 above the placeholder layer 66 and a portion of the dielectric 85. (Use the above reference.) Figure 14B The discussed process allows for the formation of openings or trenches above the top surface of the occupant layer 66. As shown, openings can be etched between two adjacent S / D 28s in ILD 111.

[0127] Figure 15A The invention describes an embodiment of the invention in Figure 15B and Figure 15C A cross-sectional view X1-X1 of the semiconductor structure after the deposition of the inner liner layer 55 for the power rail. As shown in Figure 15, this includes... Figure 14A Same elements.

[0128] Figure 15B A cross-sectional view Y1-Y1 depicts a semiconductor structure after deposition of an inner liner 55 for power rails according to an embodiment of the present invention. As shown in the figure, Figure 15B A liner layer 55 is included on the sidewalls of the openings in the dielectric 37 and the gate 33. The liner layer 55 may be composed of a dielectric material suitable for a power rail liner (e.g., SiBCN, SiN, AlOx). A thin layer of the liner layer 55 can be deposited using known semiconductor processes (e.g., via ALD), and a dry directional etching process such as RIE removes the horizontal portions of the liner layer 55 on the surfaces of the placeholder layer 66 and the ILD 111.

[0129] Compared to the openings or trenches typically etched for power rails, Figure 15B and Figure 15CThe etching process shown stops at the top surface of the placeholder layer 66, which is lower than the top surface of STI 5. Due to the presence of the placeholder layer 66, holes with a lower aspect ratio can be used in embodiments of the invention. (This is in contrast to power rails, e.g.,...) Figure 26B Compared to the opening width of the power rail 96 in the middle STI 5, the spacer 66 is provided with a slightly increased width. The additional connection vias reduce the front via height, and the additional connection vias reduce the space for the BSPDN (not shown) and the power rail 96 (not shown in the middle STI 5). Figure 15B The need for high aspect ratio holes or grooves for connections in the middle.

[0130] Figure 15C A cross-sectional view Y2-Y2 of a semiconductor structure after deposition of an inner liner for a power rail, according to an embodiment of the present invention, is depicted. As shown in the figure, Figure 15C include Figure 14C The elements and the inner lining 55. The inner lining 55 can be made of the following materials: Figure 15B The process discussed is how it is formed.

[0131] Figure 16 A top view illustrating a semiconductor design having two semiconductor devices, a power rail 96, and a placeholder layer 66 according to an embodiment of the present invention is shown. Figure 16 It includes two active regions 10, a gate structure 30, a power rail 96 with an inner liner 55, and a placeholder layer 66 with an inner liner 51 below the power rail 96. In some embodiments, the power rail 96 is a front via or a front through-hole. Figure 16 As shown, power rail 96 extends across three gate structures 30, and a placeholder layer 66 extends between two adjacent gate structures 30. Figure 16 As shown, the top view of the occupant layer 66 has a relatively long horizontal length, slightly exceeding the width shown between the two adjacent gate structures 30 extending into the active region 10. The occupant layer 66, located below a portion of the power rail 26, extends below and between the two gate structures 30. The occupant layer 66 is wider and shorter than the power rail 26 in the horizontal direction (i.e., parallel to the active region 10). Additionally, in Figure 16 The positions of cross-sectional views X1-X1, Y1-Y1, and Y2-Y2 are depicted.

[0132] Figure 16A The process of depositing power rail metal and performing CMP to form power rail 96 (not shown) according to an embodiment of the invention is depicted. Figure 16A The cross-sectional view of the semiconductor structure after (middle) is shown in the figure, X1-X1. Figure 16A With Figure 15A Same elements.

[0133] Figure 16BA cross-sectional view Y1-Y1 depicts a semiconductor structure after deposition of power rail metal and CMP performance to form power rail 96 according to an embodiment of the present invention. As shown in the figure, Figure 16B include Figure 15B The elements and power rail 96. For example, the deposition of power rail metal of one of W, Mo, Ru or Co can be performed using known deposition processes (e.g., CVD, ALD or PVD). After CMP, as Figure 16B As shown, a power rail 96 with an inner liner 55 is located between two adjacent gates 33, the remainder of the two nanosheet stacks (e.g., channel 6 in the gates 33), and a dielectric 37. In some embodiments, the power rail 96 is a front via connected to a placeholder layer 66 and extends between the plurality of gates. A portion of the power rail 96 with the inner liner 55 extends downward into the top portion of the intermediate STI 5. The bottom surface of the power rail 96 contacts the top surface of the placeholder layer 66. The top surface of the power rail 96 is above the gates 33 and flush with the top surface of the dielectric 37. As shown, the sidewalls of the power rail 96 are electrically isolated from the gates 33 by the inner liner 55.

[0134] Figure 16C A cross-sectional view Y2-Y2 depicts a semiconductor structure after deposition of power rail metal and CMP performance to form power rail 96 according to an embodiment of the present invention. As shown in the figure, Figure 16C include Figure 15C The elements and power rail 96. Use regarding... Figure 16B The known materials and processes discussed form a power rail 96 with an inner liner 55, which contacts the top surface of a berth layer 66 and is located between two adjacent S / D 28s. Figure 16C In this configuration, a portion of ILD 111 separates ILD 111 from each S / D 28. In other examples, the liner 55 can separate and electrically isolate the power rail 96 from one or both S / D 28. As shown, the power rail 96 with the liner 55 is located between two S / D 28.

[0135] Figure 17A Cross-sectional views X1-X1 of a semiconductor structure after deposition of ILD 117 according to an embodiment of the present invention are depicted. As shown in the figure, Figure 17A include Figure 16A The elements and ILD 117 above ILD 111, dielectric 37 and gate spacer 29. CMP can be performed.

[0136] Figure 17BCross-sectional views Y1-Y1 of the semiconductor structure after deposition of ILD 117 according to an embodiment of the present invention are depicted. ILD 117 is deposited on the exposed surfaces of dielectric 37, inner liner 55 and power rail 96 using a known deposition process (e.g., CVD).

[0137] Figure 17C A cross-sectional view Y2-Y2 of the semiconductor structure after deposition of ILD 117 according to an embodiment of the present invention is depicted. Figure 17C As shown, ILD 117 is deposited on top of ILD 111, inner liner 55 and power rail 96.

[0138] Figure 18A Cross-sectional views X1-X1 depict a semiconductor structure after patterning the OPL 180 and etching the source / drain (S / D) contact holes according to an embodiment of the present invention. As shown in the figure, Figure 18A include Figure 17A The elements and patterned OPL 180, but excluding the portions of ILD 117, ILD 111 and dielectric 37 above a portion of each S / D 28. Openings for contacting each S / D 28 can be formed using known photolithography and etching processes (e.g., RIE) for S / D contact holes.

[0139] Figure 18B Cross-sectional views Y1-Y1 depict a semiconductor structure after patterning the OPL 180 and etching the gate contact holes according to an embodiment of the present invention. As depicted, Figure 18B include Figure 17B The elements are without the ILD 117 and dielectric 37 portions above each gate 33. After patterning the OPL 180, two gate contact holes can be formed using one or more known etching processes for oxide removal and then dielectric 37 removal (e.g., nitride etching). Each hole contacts the top surface of one of the gates 33.

[0140] Figure 18C A cross-sectional view Y2-Y2 depicts a semiconductor structure after patterning the OPL 180 and etching the S / D contact holes according to an embodiment of the present invention. As depicted, Figure 18C include Figure 17C The elements without portions of OPL 180, ILD 117 and ILD 111 above the top surface of each of at least S / D 28.

[0141] Using known processes for etching S / D contact holes for these two GAA FET devices, an S / D contact hole can be formed for each of the two S / D 28s. The rightmost contact hole is located above and in contact with the top surface of the rightmost S / D 28, as depicted, and extends upward beyond the top surface of ILD 117.

[0142] A slightly larger and angled S / D contact hole (e.g., using a slightly angled IBE) can be etched above the leftmost S / D 28, where the larger contact hole exposes the top surface of the left S / D 28 and most of the top surface of the power rail 96, as well as a portion of the liner 55. In other words, a portion of the power rail 96 having the liner 55 adjacent to the left S / D 28 is... Figure 18C The middle is exposed. The portion of the inner liner 55 adjacent to the rightmost S / D 28 is covered by the ILD 111 located above and adjacent to the leftmost S / D 28.

[0143] Figure 19A Cross-sectional views X1-X1 of the semiconductor structure after the formation of contact 92A are depicted according to an embodiment of the present invention. As depicted, Figure 19A include Figure 18A The elements, wherein contact metal fills the S / D contact holes to form two contacts 92A as S / D contacts. Each contact 92A contacts the top surface of one of two adjacent S / D 28, as depicted. After depositing contact metal (e.g., W, Cu, Ru, Co) using known processes, CMP planarizes the top surface of the semiconductor surface and removes excess contact metal.

[0144] Figure 19B A cross-sectional view Y1-Y1 of the semiconductor structure after the formation of contact 92B is depicted according to an embodiment of the present invention. As depicted, contact 92B (e.g., gate contact) is formed using the process discussed above. Each of the contacts 92B contacts a portion of the top surface of one of the gates 33.

[0145] Figure 19C A cross-sectional view Y2-Y2 depicts the semiconductor structure after the formation of contact 92A according to an embodiment of the present invention. (Using information about...) Figure 19A The process discussed can form each of the contacts 92A connected to one of the S / D 28. Figure 19CThe leftmost contact 92A is also connected to a portion of the exposed top surface of the power rail 96. Using conventional processes, the leftmost S / D contact, designated contact 92A, has a bottom surface connected to the left-side S / D 28 and another portion of the bottom surface located above the S / D 28 and connected to the exposed portion of the top surface of the power rail 96. The right-side contact 92A is connected to the top surface of the right-side S / D 28.

[0146] Figure 20A Cross-sectional views X1-X1 depict a semiconductor structure after one or more layers of deposited ILD 127, vias 194 and 196, and front-side interconnect wiring 101, according to an embodiment of the present invention. As depicted, Figure 20A include Figure 19A The elements include ILD 127, via 194 connecting contact 92A to metal layer 196, and front-side interconnect wiring 101.

[0147] Using known semiconductor manufacturing processes for via formation, metal layer formation, and backend-of-line (BEOL) semiconductor processes, one or more ILD 127 layers are deposited on ILD 117 and contact 92A. Using known processes, vias 194 and metal layers 196 can be formed to connect to the created front-side interconnect wiring 101. Figure 20A In the S / D 28, each of the S / D 28 is connected to the front interconnect wiring 101 via a contact 92A, a via 194 and a portion of a metal layer 196.

[0148] Figure 20B Cross-sectional views Y1-Y1 depict a semiconductor structure after the deposition of the ILD 127 layer, the formation of vias 194 and 196, and the formation of the front-side interconnect wiring 101, according to an embodiment of the present invention. (Using information about...) Figure 20A In the process discussed above, each of the gates 33 is connected to the via 194 via contact 92B, and the metal layer 196 is connected to the front interconnect wiring 101.

[0149] Figure 20C A cross-sectional view Y2-Y2 depicts a semiconductor structure after the deposition of the ILD 127 layer, the formation of vias 194 and 196, and the formation of the front-side interconnect 101, according to an embodiment of the present invention. Using the known via and BEOL processes discussed previously, the rightmost S / D contact 28 is connected to the via 194, the metal layer 196, and the front-side interconnect 101 via contact 92A. The leftmost S / D 28 is connected to the power rail 96 located directly above the placeholder layer 66 via the leftmost contact 92A.

[0150] Each of the following figures is depicted: Figure 21A Cross-sectional views X1-X1 of a semiconductor structure after the removal of substrate 2 and etch stop layer 3 according to an embodiment of the present invention are depicted. Figure 21B Cross-sectional views Y1-Y1 of the semiconductor structure after removal of substrate 2 and etch stop layer 3 according to an embodiment of the present invention are depicted; and Figure 21C A cross-sectional view Y2-Y2 depicts the semiconductor structure after the removal of substrate 2 and etch stop layer 3 according to an embodiment of the present invention. Substrate 2 and etch stop layer 3 were removed using known semiconductor polishing and / or etching processes. The bottom surface of semiconductor material 4 was exposed.

[0151] As those skilled in the art will know, in some cases, using typical semiconductor processing, a carrier wafer (not shown) is bonded to the front-side interconnect wiring 101, and the semiconductor structure is flipped so that the substrate 2 is the top surface before the wafer is ground and etched to the substrate 2 and the etch stop layer 3. To maintain consistency, Figure 21A , 21B 21C- Figure 27B and 27C The semiconductor structure is not shown as being flipped.

[0152] Figure 22A Cross-sectional views X1-X1 of the semiconductor structure after a portion of the semiconductor material 4 has been removed, according to an embodiment of the present invention. A semiconductor substrate grinding and / or wet etching process removes the bottom portion of the semiconductor material 4. Following semiconductor grinding / etching, wet etching of the semiconductor material 4 further removes another portion of the semiconductor material 4. The remaining portion of the semiconductor material 4 lies beneath the S / D 28 and the gate 33, as depicted.

[0153] Figure 22B Cross-sectional views Y1-Y1 depict the semiconductor structure after a portion of the semiconductor material 4 has been removed, according to an embodiment of the present invention. (Using information about...) Figure 22A The discussed process (e.g., wafer grinding and / or etching) removes semiconductor material 4 from the bottom surface of STI 5, and a second etching process of semiconductor material 4 causes a portion of semiconductor material 4 between the three STI 5s to be recessed. After these two semiconductor etching processes are completed, the bottom portion of the sidewalls of STI 5, the bottom surface of STI 5, the placeholder layer 66 with the inner liner layer 51, and the remaining portion of semiconductor material 4 are exposed. As depicted, the exposed bottom surface of the remaining portion of semiconductor material 4 is located above the bottom surface of STI 5 and below the placeholder layer 66 and the top surface of STI 5.

[0154] Figure 22CA cross-sectional view Y2-Y2 of the semiconductor structure after a portion of the semiconductor material 4 has been removed, according to an embodiment of the present invention, is depicted. (Using information about...) Figure 22B The process discussed involves removing semiconductor material 4 from STI 5, and a second etching process of semiconductor material 4 causes a recess in the semiconductor material 4 between portions of STI 5. As depicted, the exposed surface of the remaining portion of semiconductor material 4 is located above the bottom surface of STI 5 and below the placeholder layer 66 and the top surface of STI 5.

[0155] Each of the following figures is depicted: Figure 23A Cross-sectional views X1-X1 of a semiconductor structure following the deposition of the backside ILD227 according to an embodiment of the present invention are depicted. Figure 23B Cross-sectional views Y1-Y1 of a semiconductor structure following the deposition of the backside ILD 227 according to an embodiment of the present invention are depicted; and Figure 23C A cross-sectional view Y2-Y2 of the semiconductor structure following the deposition of the backside ILD 227 according to an embodiment of the present invention is depicted. As depicted, it is possible to... Figure 23A , 23B ILD 227 was deposited on the exposed bottom surface of 23C.

[0156] Figure 24A The invention describes an embodiment of the invention in Figure 24B and Figure 24C Cross-sectional view X1-X1 of the semiconductor structure after patterning and etching openings in the back-side ILD. As shown in the figure. Figure 24A and Figure 23A same.

[0157] According to embodiments of the present invention, known patterning and etching processes are used to achieve... Figure 24B (Depicting a cross-sectional view of the semiconductor structure Y1-Y1) and Figure 24C In the cross-sectional view Y2-Y2 depicting the semiconductor structure, trenches or openings in the backside ILD 227 can be formed beneath the occupant layer 66 having an inner liner layer 51. Figure 24B and Figure 24C Of the two, the trench or opening is wider than the intermediate STI 5 with the occupancy layer 66.

[0158] Figure 25A The invention describes an embodiment of the invention in Figure 25B and Figure 25C A cross-sectional view X1-X1 of the semiconductor structure after removing the placeholder layer 66. As shown in the figure. Figure 25A and Figure 24A same.

[0159] Using one or more known wet and / or dry etching processes (e.g., for SiGe), from Figure 25B and Figure 25C The inner lining layer 51 has its internal spacer layer 66 removed, wherein Figure 25B A cross-sectional view Y1-Y1 of a semiconductor structure according to an embodiment of the present invention is depicted. Figure 25C A cross-sectional view Y2-Y2 depicts a semiconductor structure according to an embodiment of the present invention. The removal of the placeholder layer 66 creates an opening with a height less than that of STI 5. The top of this opening is... Figure 25B It is located below the bottom surface of gate 33, and in Figure 25C The middle is located below S / D 28. For example... Figure 25B and Figure 25C As shown, the top of the opening is flush with the surface of the remaining semiconductor material 4, although in other examples the top of the opening may be higher or lower. The bottom of the opening is flush with the bottom of the intermediate STI 5. The opening created by the removal of the placeholder layer 66 is flush with the surface of the remaining semiconductor material 4. Figure 25A and Figure 25B The openings in ILD 227 formed in the middle meet.

[0160] Figure 26A The invention describes an embodiment of the invention in Figure 26B and Figure 26C Cross-sectional view X1-X1 of the semiconductor structure after the deposition of metal material for connector via 294 and back metal 296. As shown in the figure. Figure 26A and Figure 25A same.

[0161] Figure 26B Cross-sectional views Y1-Y1 depict a semiconductor structure after deposition of metal material for connector via 294 and back metal 296 according to an embodiment of the present invention. As shown in the figure, Figure 26B include Figure 25B The elements include connector through-hole 294 and back metal 296, where the back metal 296 may be the first metal layer of the BSPDN. Furthermore, Figure 26B The widths X1 and X2 of the top and bottom surfaces of the connector through-hole 294 are also shown.

[0162] In various embodiments, the metal material used for connector via 294 and back metal 296 is the same (e.g., it is deposited for both in a single deposition process). This metal material can be any material suitable for a back metal layer (e.g., Cu), such as in a back-side power supply network (BSPDN). In various embodiments, the metal material used for connector via 294 has a density greater than 3.0 x 10⁻⁶. 7The electrical conductivity σ. In some embodiments, the metal material used for the connector through-hole 294 has a conductivity greater than 4.0 x 10⁻⁶ at 20 degrees Celsius. 7 The electrical conductivity of σ, such as copper or copper alloys. Using the same metal for connector via 294 and back metal 296 reduces the interface between different metal materials and reduces any electrical discontinuities between different metal materials, especially when the metal material is copper, which is deposited in a single deposition process for both connector via 294 and back metal 296.

[0163] Additionally, since the connector via 294 replaces the placeholder layer 66 formed in the front etched trench, the width of the top surface of the connector via 294 is greater than the width of the power rail 96. The connector via 294 can be wider than a typical front via or TSV connected to the back metal 296, which reduces the resistance of the path between the S / D 28 and the back metal 296. The connector via 294 is located at the center of the intermediate STI 5.

[0164] In some embodiments, the connector via 294 is composed of a different metallic material (e.g., W, Co, or Ru). In this case, the metal deposited in a first deposition process (e.g., ALD, CVD, or PVD) fills the opening surrounded by the liner layer 55. A second metal deposition process may deposit the back metal 296 (e.g., a different metal, such as Cu).

[0165] As shown in the figure, X1 is the width of the top surface of connector through-hole 294. (Regarding...) Figure 6As discussed in detail previously, the width X1 of the top surface of the placeholder layer 66 is wider than X2 (the width of the bottom surface of the connector via 294), resulting in a slightly trapezoidal cross-section of the connector via 294. Providing a wider top surface for the connector via 294 reduces the chance of misalignment between the power rails 96. The wider opening in the back metal 296 in the back ILD 227, which forms a line in the back metal 296 contacting the bottom surface of the placeholder layer 66 in the middle of the STI 5, reduces the possible misalignment between the connector via 294 and the back metal 296, and allows a single back metal deposition process to contact the power rails 96 metallized on the front side of the semiconductor structure. In conventional semiconductor structures with BSPDNs, much smaller diameter back vias or TSVs are typically used to connect the buried power rails to the first back metal layer of the BSPDN. Providing a larger diameter and larger contact area for the connector via 294 to connect to the power rails 96 improves electrical performance (e.g., reduces the resistance connected to the power rails 96). Using connector via 294 for a direct connection between a power rail formed on the front side of the wafer and a back metal layer reduces the number of connections between front and back wiring. Reducing the number of connections reduces potential sources of misalignment between the connections from power rail 96 to back metal 296, and by reducing connection misalignment, connector via 294 improves the electrical performance of the semiconductor structure. Furthermore, the direct connection between power rail 96 and back metal 296 provides a shorter electrical path with less electrical discontinuity caused by additional back vias or TSV connections. The distance between power rail 96 and back metal 296 is only the height of connector via 294, which is less than the height of STI5 (e.g., for use with...). Figure 26B and Figure 26C The small distance of the very short electrical path between the front and back wafer metallization is shown.

[0166] Figure 26C A cross-sectional view Y2-Y2 depicts a semiconductor structure after deposition of metal material for connector via 294 and back metal 296 according to an embodiment of the present invention. (Using...) Figure 26B The above-mentioned process can form Figure 26C The leftmost S / D 28 is connected to the power rail 96 via the left contact 92A. Connector via 294 is located at the center of the middle STI 5. As shown, the center of connector via 294 is directly below the power rail 96 and above the back metal 296.

[0167] Figure 26C The semiconductor structure gives rise to the above about Figure 26BThe connector through-hole 294, discussed in detail, directly connects to the power rail 96 and the back metal 296, providing similar or identical advantages. As previously stated, using the connector through-hole 294 to directly connect the power rail 96 to the back metal 296 reduces the resistance of the connection between the power rail 96 and the back metal 296 compared to conventionally formed power rails and BSPDNs. As previously stated, the wider top surface of the connector through-hole 294 reduces misalignment that can occur in conventional power rail-to-BSPDN back through-hole connections.

[0168] As shown in the figure Figure 26C The semiconductor structure features a power rail 96 that directly connects the contact 92A (i.e., the S / D contact) to the back metal 296 using a connector via 294, without using the typical BSPDN connections of front vias, back vias, through-silicon vias (TSVs), or nano-TSVs (nTSVs). Eliminating via connections and / or TSV connections in the electrical path from the S / D 28 to the back metal 296 improves the electrical performance of the semiconductor device.

[0169] The length or height of the connector via 294 above the back metal 296 is equal to or less than the height of the STI 5. Therefore, the electrical path length from the power rail 96 to the back metal 296 is very short (e.g., less than the height of the STI 5), and the copper material passing through the connector via 294 has a width greater than the width of the power rail 96. Compared to conventional semiconductor structures with power rails, TSVs, buried power rails with back vias or nTSVs, or combinations thereof, to connect one or more source / drain terminals to the BSPDN, Figure 26C The semiconductor structure leads to improvements in the electrical performance of the semiconductor structure due to the resistance-capacitance (RC) element or the current-resistance (IR) voltage drop.

[0170] Figure 27B A cross-sectional view Y1-Y1 depicts a semiconductor structure according to an embodiment of the present invention without the inner liner layer 51 on the intermediate STI 5. As depicted, Figure 27B include Figure 26B The element is omitted, and the inner liner 51 is not present; instead, the connector through-hole 294 is replaced with the connector through-hole 394. The inner liner 51 is omitted. Figure 27B The connector through-hole 394 is more than Figure 26B The connector through-hole 294 is slightly wider. Furthermore, in... Figure 27B The width X of the top surface of connector through-hole 394 is depicted in the figure. 11 The width X of the bottom surface of the connector through hole 394 22 Width X 11 Greater than width X 22 Additionally, the width X 11Greater than Figure 26B The connector through-hole 294 has a width of X1. Compared to connector through-hole 294, the increased width of connector through-hole 394 improves electrical performance (e.g., lower resistance) and reduces potential misalignment or overlap errors.

[0171] Figure 27B and Figure 27C The semiconductor structure can be made of Figure 4 The semiconductor structure is formed, wherein an inner liner 31 is present above STI 5, and there is no... Figure 5 A liner layer 51 is deposited on the sidewall of the intermediate STI 5. A cross-sectional view X1-X1 (not shown) of a semiconductor structure without the liner layer 51 on the intermediate STI 5 is shown. Figure 26A The cross-sectional views X1-X1 shown are the same. Figure 27B and Figure 27C The cross-sectional view X1-X1 (not shown) of the semiconductor structure shown is in relation to... Figure 26A The cross-sectional views X1-X1 shown are the same. Figure 4 The implementation of about on the semiconductor structure without inner liner 51 on the intermediate STI 5. Figure 5 and Figure 6 Following the discussion, it led to Figure 7 The surrounding occupant layer 66 has no inner lining layer 55. In implementing [the relevant regulations]... Figures 7 to 26C Following the discussion, a wider connector through-hole 394 was achieved.

[0172] Furthermore, the wider top surface of the connector via 394 further reduces the possibility of misalignment between the power rail 96 and the connector via 394, which would also increase the resistance between the connector via 394 and the metal layer 396 of the BSPDN. In other words, the wider connector via 394 improves the electrical performance of the semiconductor device and the resulting semiconductor chip. The connector via 394 provides information about... Figure 26B The advantages of the semiconductor structure with connector via 294 are discussed in detail.

[0173] Figure 27C A cross-sectional view Y2-Y2 depicts a semiconductor structure without the inner liner 51 according to an embodiment of the present invention. As depicted, Figure 27C include Figure 26C The element is omitted, and the inner liner 51 is not present; instead, the connector through-hole 294 is replaced with the connector through-hole 394. The inner liner 51 is omitted. Figure 27C The connector through-hole 394 is more than Figure 26C The connector through-hole 294 is slightly wider. Furthermore, in... Figure 27C The width X of the top surface of connector through-hole 394 is depicted in the figure. 11The width X of the bottom surface of the connector through hole 394 22 .

[0174] Figure 27C The semiconductor structure provides information about Figure 27B A detailed discussion of the advantages and about Figure 26B and Figure 26C The advantages of connector through-hole 294 are discussed in detail.

[0175] The various embodiments of the present invention are described for illustrative purposes and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The terminology used herein has been chosen to best explain the principles of the embodiments, practical applications of techniques found in the market or improvements thereof, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

[0176] In a preferred embodiment of the invention described herein, a connector via is provided, comprising: a connector via having a trapezoidal cross-section, the top surface of which has a width greater than the width of its bottom surface, wherein the connector via is copper; a portion of a power rail directly above and in contact with the top surface of a copper element, wherein the power rail extends between one or more gates of at least two adjacent semiconductor devices; and a back metal layer in contact with the bottom surface of the copper element, wherein the copper element is the connector via. The connector via may extend between one or more gates of at least two adjacent semiconductor devices. The connector via may be below and parallel to the active regions of at least two adjacent semiconductor devices. The power rail may have a width smaller than the width of the top surface of the connector via, and the connector via may have a bottom surface whose width is smaller than the width of the top surface of the back metal layer. The connector via and the back metal layer may be made of copper. The connector via may be located at the center of a shallow isolation trench.

[0177] In a preferred embodiment of the invention described herein, a connector via is provided, comprising: a connector via having a trapezoidal cross-section and a top surface width greater than the width of its bottom surface, wherein the connector via is made of copper; an inner liner layer on the sidewalls of the connector via; a portion of a power rail located directly above and in contact with the top surface of the connector via, wherein the power rail is located between one or more gates of at least two adjacent semiconductor devices; and a back metal layer in contact with the bottom surface of the connector via. The connector via may extend between two gates of at least two adjacent semiconductor devices. The connector via may be below and parallel to the active regions of at least two adjacent semiconductor devices. The power rail may have a width smaller than the width of the top surface of the connector via, and the connector via may have a bottom surface smaller than the width of the top surface of the back metal layer. The connector via and the back metal layer may be composed of the same metallic material. The connector via may be located at the center of a shallow isolation trench, wherein the top surface of the shallow isolation trench is higher than the top surface of the connector via.

[0178] In a preferred embodiment of the invention described herein, a method for forming a semiconductor structure is provided, the method comprising: etching a hole between two portions of a nanosheet stack to the bottom of a shallow isolation trench (STI); depositing a first liner layer; removing a horizontal portion of the first liner layer using a directional etching process; depositing a second liner layer; removing the horizontal portion of the second liner layer; growing a placeholder layer in a portion of the hole using epitaxy, wherein the top surface of the placeholder layer is lower than the top surface of the STI; depositing and recessing an oxide, wherein a portion of the oxide remains on the placeholder layer; forming a source / drain electrode using epitaxy; forming a replacement metal gate; forming a power rail having a liner layer in contact with the placeholder layer; forming gate contacts and source / drain contacts, wherein one source / drain contact is connected to the power rail; removing a back substrate, an etch stop layer, and a portion of semiconductor material; removing a portion of the deposited back interlayer dielectric to expose the bottom surface of the placeholder layer; removing the placeholder layer; forming a connector via by depositing metal in the hole formed by the removed placeholder layer; and forming a back metal layer on the connector via, wherein the connector via connects the back metal layer to the power rail.

[0179] In a preferred embodiment of the invention described herein, a method for forming a semiconductor structure is provided, the method comprising: etching a hole between two portions of a nanosheet stack to the bottom of a shallow isolation trench (STI); depositing a first liner layer; removing a horizontal portion of the first liner layer using a directional etching process; depositing a second liner layer; removing the horizontal portion of the second liner layer; growing a placeholder layer in a portion of the hole using epitaxy, wherein the top surface of the placeholder layer is lower than the top surface of the STI; depositing and recessing an oxide, wherein a portion of the oxide remains on the placeholder layer; forming a source / drain electrode using epitaxy; forming a replacement metal gate; forming a power rail having a liner layer in contact with the placeholder layer; forming gate contacts and source / drain contacts, wherein one source / drain contact is connected to the power rail; removing a back substrate, an etch stop layer, and a portion of semiconductor material; removing a portion of the deposited back interlayer dielectric to expose the bottom surface of the placeholder layer; removing the placeholder layer; forming a connector via by depositing metal in the hole formed by the removed placeholder layer; and forming a back metal layer on the connector via, wherein the connector via connects the back metal layer to the power rail.

Claims

1. A semiconductor structure, comprising: Power rail; as well as Connector through-holes connect the power rails to the back metal layer, wherein the connector through-holes are located within shallow isolation trenches.

2. The semiconductor structure of claim 1, wherein the connector via has a top surface that is wider than the bottom surface of the connector via.

3. The semiconductor structure of claim 1, wherein the connector via has a top surface that is wider than the bottom of the connector via.

4. The semiconductor structure of claim 3, wherein the back metal layer has a top surface that contacts the bottom surface of the connector via and the bottom surface of the shallow isolation trench.

5. The semiconductor structure according to claim 1, wherein the back metal layer is a first metal layer in the back power supply network.

6. The semiconductor structure of claim 1, wherein the connector via has a diameter greater than 4.0 x 10⁻⁶. 7 The composition of metallic materials with electrical conductivity σ.

7. The semiconductor structure of claim 1, wherein the connector via and the back metal layer are composed of the same metal material.

8. The semiconductor structure of claim 1, wherein the power rail has a first portion adjacent to the source / drain, wherein the top surface of the first portion of the power rail contacts a portion of the source / drain contacts, and wherein the bottom surface of the power rail contacts the connector via.

9. The semiconductor structure according to claim 1, further comprising: Two sources / drains of two adjacent semiconductor devices, wherein a first portion of the power rail is located between the two sources / drains; Two source / drain contacts, one of which is connected to a connector via a first portion of the power rail, and the second source / drain contact is connected to at least one metal layer and to one or more front-side interconnect layers via a first via. Two gates of two adjacent semiconductor devices, wherein a second portion of the power rail is located between the two gates; and Two gate contacts, each of which is connected via a second via to: (i) at least one metal layer and (ii) one or more front-side interconnect layers.

10. The semiconductor structure of claim 9, wherein the two gates are electrically isolated from the power rail by an inner liner surrounding the sidewall of the power rail.

11. A method for forming a semiconductor structure, comprising: A hole is etched between the two portions of the nanosheet stack to the bottom of a shallow isolation trench (STI); Deposited inner lining; The horizontal portion of the inner liner is removed using a directional etching process; An epitaxial layer is grown in a portion of the hole, wherein the top surface of the spacer layer is lower than the top surface of the STI; Deposit and recess oxides, wherein a portion of the oxides is retained on the site layer; Use epitaxy to form the source / drain; Forming a replacement metal gate; A power rail is formed having a power rail liner that contacts the spacer layer; A gate contact and a source / drain contact are formed, wherein one of the source / drain contacts is connected to the power rail; Remove a portion of the back substrate, etch stop layer, and semiconductor material; A portion of the deposited back-side interlayer dielectric is removed to expose the bottom surface of the occupant layer; Remove the placeholder layer; Deposit and pattern the back-side interlayer dielectric; as well as A metal layer is deposited on the back interlayer dielectric and in the holes formed by removing the placeholder layer, wherein the portion of the metal layer in the holes formed by removing the placeholder layer is a connector via, and the portion of the metal layer in the back interlayer dielectric is a back metal layer.

12. The method according to claim 11, wherein: The back metal layer and the connector through-hole are made of copper; The connector through-hole is located in the STI and is below the top surface of the STI; and The connector through-hole connects the power rail to the back metal layer of the back power supply network.

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