Method of manufacturing an interconnect structure

Abstract

Methods of fabricating interconnect structures as part of a microelectronic element fabrication process are described. The methods include forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap having a sidewall and a bottom. The methods further include forming a barrier layer on the bottom by exposing the substrate to a barrier species, the barrier species including a hydrocarbon and at least one additive; selectively depositing a barrier layer on the sidewall; selectively depositing a metal liner on the barrier layer on the sidewall; removing the barrier layer; and performing a gap fill process to fill the gap with a gap fill material.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to methods of fabricating interconnect structures in the manufacture of microelectronic components. More specifically, embodiments of this disclosure relate to barrier materials for selective barrier applications and selective pad applications. Background Technology

[0002] As transistors and interconnects are scaled to 3 nm, 2 nm, 1.4 nm, and smaller nodes, several challenges hinder improvements in power and performance. Interconnects consist of metal lines that carry current within the same element layer and metal vias that carry current between layers. Reducing the pitch narrows both the width of the metal lines and the metal vias, increasing resistance and also increasing the voltage drop across the circuit, thus limiting circuit speed and increasing power dissipation.

[0003] While transistor performance improves with scaling, this is not the case for interconnect metals. With shrinking dimensions, interconnect via resistance can increase tenfold. This increase in via resistance can lead to resistive-capacitive (RC) delay, which degrades performance and increases power consumption. Conventional interconnect structures, such as copper interconnects, include barrier layers and / or metal pads deposited on the sidewalls providing the gaps between vias. These sidewalls are made of a dielectric material, providing good adhesion and preventing copper diffusion into the dielectric layer. Due to the high resistivity of the barrier layer itself, it is often the largest contributor to via resistance. Past approaches have focused on reducing the thickness of the barrier layer or finding barrier layers with lower resistivity to reduce via resistance. The increased via resistance remains a problem when the barrier layer on the sidewalls creates an increased percentage of via volume, especially in smaller features.

[0004] One approach is to block or reduce the thickness of the barrier layer on the metal surface at the bottom of the via, while keeping the thickness on the dielectric surface at the sidewalls unchanged. Due to the barrier properties required between the metal and dielectric surfaces, this method allows the barrier layer to remain intact, but the reduced thickness on the metal surface decreases the via resistance. This process is known as selective deposition.

[0005] Selective deposition of materials can be achieved in various ways. A chemical precursor can react selectively with one surface relative to another (metal or dielectric). Process parameters (such as pressure, substrate temperature, precursor partial pressure, and / or gas flow rate) can be tuned to modulate the chemical kinetics of the reaction on a specific surface. Another possible approach involves surface pretreatment of the incoming deposition precursor, which can be used to activate or deactivate the surface of interest. Typically, selective deposition refers to layer deposition on a metallic surface. Reverse selective deposition processes deposit layers on dielectric surfaces rather than metallic surfaces.

[0006] In current interconnect manufacturing processes, metal pads deposited on a barrier layer adhere to the barrier layer and facilitate subsequent metal filling in the gaps between sidewalls. Current methods focus on selectively growing metal pads on the via sidewalls relative to the via bottom with high selectivity in an attempt to reduce via resistance and metal corrosion, although selective growth remains a challenge.

[0007] For example, one of the key challenges associated with some unsaturated hydrocarbon blocking compounds is surface contamination following the barrier layer removal step. For instance, integration problems may arise after the removal of some unsaturated hydrocarbon blocking compounds, which could become points of failure during electrical testing.

[0008] For example, another key challenge with some unsaturated hydrocarbon blocking compounds is their ability to inhibit or prevent the subsequent deposition of certain materials. For instance, some unsaturated hydrocarbon blocking compounds (such as intermediate alkynes) effectively inhibit or prevent the subsequent deposition of copper (Cu) or cobalt (Co), but not tungsten (W) or molybdenum (Mo) or copper (Cu) or cobalt (Co). It has been found that oxygen-containing blocking compounds and nitrogen-containing compounds effectively inhibit or prevent the subsequent deposition of conductive materials, but also inappropriately inhibit or prevent the subsequent deposition of underlying interconnect materials (such as etch-stop layers).

[0009] Therefore, there is a need to improve interconnect performance, for example, by reducing via resistance and / or improving the deposition selectivity of barrier layers and / or metal pads for depositing material layers. There is also a need for barrier materials that can be easily removed without causing integration problems; provide reduced electrical losses in the final microelectronic device; and effectively suppress or prevent subsequent deposition of conductive metals without suppressing or preventing subsequent deposition of the underlying interconnect material. Summary of the Invention

[0010] One or more embodiments of this disclosure relate to a method of manufacturing a microelectronic component. In one or more embodiments, the method includes forming a dielectric layer on a substrate. The dielectric layer includes at least one feature defining a gap having sidewalls and a bottom. In one or more embodiments, the method includes forming a barrier layer on the bottom by exposing the substrate to a barrier material. In one or more embodiments, the barrier material includes a hydrocarbon and at least one additive. In one or more embodiments, the method includes selectively depositing the barrier layer on the sidewalls; removing the barrier layer; and performing a gap-filling process to fill the gaps using a gap-filling material.

[0011] Additional embodiments of this disclosure relate to methods of manufacturing microelectronic components. In one or more embodiments, the method includes pre-cleaning a substrate and forming a dielectric layer on the substrate. The dielectric layer includes at least one feature defining a gap having sidewalls and a bottom. In one or more embodiments, the method includes forming a barrier layer on the bottom by exposing the substrate to a barrier material. In one or more embodiments, the barrier material comprises a hydrocarbon and at least one additive. In one or more embodiments, the at least one additive comprises one or more of an oxygen-containing compound or a nitrogen-containing compound. In one or more embodiments, the method includes: selectively depositing a barrier layer, such as, for example, a barrier layer comprising tantalum nitride (TaN) formed on a sidewall by atomic layer deposition (ALD); selectively depositing a metal pad on the barrier layer on the sidewall, such as, for example, a metal pad comprising one or more of ruthenium (Ru), cobalt, molybdenum (Mo), and tantalum (Ta); removing the barrier layer; and performing a gap-filling process to fill the gaps with a gap-filling material comprising one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo). Attached Figure Description

[0012] To gain a more detailed understanding of the features described above in this disclosure, a more specific description of the disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate common embodiments of this disclosure and are not intended to limit its scope, as this disclosure allows for other equivalent and effective embodiments.

[0013] Figure 1A A process flow diagram of a method for manufacturing a microelectronic component according to one or more embodiments of the present disclosure is shown;

[0014] Figure 1B A schematic cross-sectional view of a microelectronic component including a gap having sidewalls and a bottom, according to one or more embodiments of the present disclosure, is shown, wherein a barrier layer is formed on the bottom of the gap;

[0015] Figure 1C One or more embodiments of the present disclosure are shown. Figure 1B A barrier layer is selectively deposited on the sidewalls of the gap;

[0016] Figure 1D One or more embodiments of the present disclosure are shown. Figure 1C Selectively deposited metal pads on the barrier layer;

[0017] Figure 1E One or more embodiments according to this disclosure are shown. Figure 1BThe removal of the barrier layer formed in the middle; and

[0018] Figure 1F The filling according to one or more embodiments of this disclosure is shown. Figure 1B The gap filling process. Detailed Implementation

[0019] Before describing several exemplary embodiments of this disclosure, it will be understood that this disclosure is not limited to the details of the construction or process steps set forth in the following description. This disclosure can have other embodiments and can be practiced or carried out in various ways.

[0020] As used herein, the term “about” means approximately or nearly, and in the context of the numerical value or range described, it means a variation of ±15% or less of the value. For example, values ​​differing by ±14%, ±10%, ±5%, ±2%, or ±1% would satisfy the definition of about.

[0021] For ease of description, this document uses spatially relative terms (such as "below," "under," "lower," "above," "upper," and the like) to describe the relationship between one element and another element or feature shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatially relative terms are intended to encompass different orientations of the microelectronic element in use or operation. For example, if the microelectronic element in the figures is flipped, the element described as "below" or "under" other elements will be oriented "above" other elements. Therefore, the illustrative term "below" can encompass both "below" and "above" orientations. Microelectronic elements may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein are interpreted accordingly.

[0022] Unless otherwise indicated herein or explicitly denied by the context, the use of the terms “a”, “an”, “the”, and similar references in the context of describing the materials and methods discussed herein (particularly in the context of the following claims) shall be understood to cover both the singular and the plural. Unless otherwise indicated herein, the description of value ranges herein is intended merely as a simplified method independently referring to each individual value falling within that range, and each individual value is incorporated into the specification as if it were independently described herein. Unless otherwise indicated herein or explicitly denied by the context, all methods described herein may be performed in any suitable order. The use of any and all instances or illustrative language provided herein (e.g., “such as”) is merely intended to better elucidate the materials and methods and does not impose any limitation on the scope unless otherwise claimed. The language in the specification should not be construed as indicating that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0023] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," "some embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, the use of phrases such as "in one or more embodiments," "in some embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" in various places throughout this specification does not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, the particular feature, structure, material, or characteristic is combined in any suitable manner.

[0024] As used in this specification and the appended claims, the terms "substrate" and "wafer" are used interchangeably and both refer to the surface on which the process is performed, or a portion thereof. As will also be understood by those skilled in the art, unless the context clearly indicates otherwise, reference to substrate may also refer to only a portion of the substrate. Additionally, references to "deposited on a substrate" or "formed on a substrate" can mean a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0025] As used herein, “substrate” refers to any substrate on which a film treatment is performed during a manufacturing process, or a material surface formed on a substrate. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. In some embodiments, the substrate comprises one or more of doped or undoped crystalline silicon (Si), doped or undoped crystalline silicon germanium (SiGe), doped or undoped amorphous silicon (Si), or doped or undoped amorphous silicon germanium (SiGe). The substrate may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to film treatments performed directly on the surface of the substrate itself, any film treatment steps disclosed herein, as detailed below, may also be performed on an underlayer formed on the substrate, and the term "substrate surface" is intended to include such an underlayer as indicated by the context. Thus, for example, in the case where a film / layer or a portion thereof has already been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0026] The term "on" indicates that there is direct contact between components. The term "directly on" indicates that there is direct contact between components without any intermediary components.

[0027] As used herein, the term "in situ" refers to a process performed in the same processing chamber or in different processing chambers connected as part of an integrated processing system, such that each of the processes is performed without intermediate vacuum disruption. As used herein, the term "out situ" refers to a process performed in at least two different processing chambers, such that one or more of the processes are performed with intermediate vacuum disruption. In some embodiments, the process is performed without disrupting the vacuum or being exposed to ambient air.

[0028] As used herein, the terms “precursor,” “reactant,” “reactive gas,” “reactive substance,” and the like are used interchangeably to refer to any gaseous substance that can react with the surface of a substrate.

[0029] Sputtering is a physical vapor deposition (PVD) process in which high-energy ions bombard and erode a solid target, depositing the target material onto the surface of a substrate (such as a semiconductor substrate). In semiconductor manufacturing, sputtering processes are typically performed in a semiconductor manufacturing chamber (also known as a PVD processing chamber or sputtering chamber). Sputtering has long been used for the deposition of metals and related materials in the manufacture of semiconductor integrated circuits.

[0030] Typically, a sputtering chamber includes an outer shell wall enclosing the processing area (in which the processing gas is introduced), a gas actuator for exciting the processing gas, and an exhaust port for discharging and controlling the pressure of the processing gas in the chamber. The chamber is used to sputter and deposit material from a sputtering target onto a semiconductor substrate. In the sputtering process, the sputtering target is bombarded with high-energy ions (such as plasma), causing material to detach from the target and deposit as a film on the semiconductor substrate.

[0031] Common semiconductor manufacturing chambers have a target assembly comprising a dish-shaped target of solid metal or other material supported by a backplate holding the target. To promote uniform deposition, PVD chambers may have a concentric annular metal ring circumferentially surrounding the dish-shaped target; this ring is often referred to as a shield.

[0032] Plasma sputtering can be performed using either DC sputtering or RF sputtering. Plasma sputtering typically involves a magnetron positioned on the back side of a sputtering target, which includes two magnets of opposite polarity magnetically coupled at its back side via a yoke to project a magnetic field into the processing space, increasing plasma density and enhancing the sputtering rate from the front of the target. The magnets used in the magnetron are typically closed-loop for DC sputtering and open-loop for RF sputtering.

[0033] As used herein, the term "chemical vapor deposition" refers to exposing at least one reactive substance to deposit a material layer on a substrate surface. In some embodiments, a chemical vapor deposition (CVD) process includes mixing two or more reactive substances in a processing chamber to allow for vapor-phase reaction and deposition of the reactive substances. In some embodiments, a CVD process includes simultaneously exposing a substrate surface to two or more reactive substances. In some embodiments, a CVD process includes continuously exposing a substrate surface to a first reactive substance in conjunction with intermittent exposure to a second reactive substance. In some embodiments, the substrate surface undergoes a CVD reaction to deposit a layer of predetermined thickness. In a CVD process, a layer may be deposited in a single exposure to a mixed reactive substance, or it may be exposed to a mixed reactive substance multiple times, with descaling between exposures. In some embodiments, the substrate surface is substantially simultaneously exposed to a first reactive substance and a second reactive substance.

[0034] As used in this article, “substantially simultaneously” means that the majority of the duration of exposure to the first reactive substance overlaps with the duration of exposure to the second reactive substance.

[0035] As used herein, the term "decontamination" includes any suitable decontamination process that removes unreacted precursors, reaction products, and byproducts from a processing area. Suitable decontamination processes include moving a substrate through a gas shield to a portion or sector of the processing area that contains no or substantially no reactants. In one or more embodiments, the decontamination chamber includes applying a vacuum. In some embodiments, the decontamination area includes a decontamination gas flowing over the substrate. In some embodiments, the decontamination process includes a flowing inert gas. In one or more embodiments, the decontamination gas is selected from one or more of nitrogen (N2), helium (He), and argon (Ar). In some embodiments, before the substrate is exposed to the second reactive substance, the first reactive substance is decontaminated from the reaction chamber for a period of time ranging from 0.1 seconds to 30 seconds, from 0.1 seconds to 10 seconds, from 0.1 seconds to 5 seconds, from 0.5 seconds to 30 seconds, from 0.5 seconds to 10 seconds, from 0.5 seconds to 5 seconds, from 1 second to 30 seconds, from 1 second to 10 seconds, from 1 second to 5 seconds, from 5 seconds to 30 seconds, from 5 seconds to 10 seconds, or from 10 seconds to 30 seconds.

[0036] "Cyclic deposition" or "atomic layer deposition" (ALD) refers to the sequential exposure of two or more reactive substances to deposit a material layer on a substrate surface. The substrate, or portions thereof, are individually exposed to two or more reactive substances introduced into the reaction zone of a processing chamber. In time-domain ALD processes, exposure to each reactive substance is separated by a time delay to allow each compound to adhere to and / or react on the substrate surface and subsequently be decontaminated from the processing chamber. These reactive substances are considered to be sequentially exposed to the substrate. In spatial ALD processes, the substrate surface or different portions of the material on the substrate surface are simultaneously exposed to two or more reactive substances, such that at any given point on the substrate, there is substantially no simultaneous exposure to more than one reactive substance. As used in this specification and the appended claims, and as will be understood by those skilled in the art, the term "substantially" as used in this context means the possibility that a small portion of the substrate may be attributably exposed to multiple reactive gases simultaneously, and that such simultaneous exposure is unintentional.

[0037] In one aspect of the time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive material or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of the reactive material. The reactive material is pulsed alternately until a desired layer or layer thickness is formed on the substrate surface. In either case, the ALD process of pulsed compound A, purge gas, compound B, and purge gas is a cycle. The cycle may begin with compound A or compound B and continue in the corresponding order until a layer with a predetermined thickness is obtained.

[0038] One or more layers deposited on a substrate or substrate surface are continuous. As used herein, the term "continuous" means a layer that covers the entire exposed surface without any gaps or exposed points of material underlying the deposited layer. A continuous layer may have gaps or exposed points with a surface area less than about 15% or less than 10% of the total surface area of ​​the layer.

[0039] Generally, front-end of line (FEOL) refers to the first part of integrated circuit manufacturing, including transistor manufacturing; middle-of-line (MOL) uses a series of contact structures to connect transistors and the interconnect parts of the chip; and back-end of line (BEOL) refers to a series of process steps after transistor manufacturing until the chip is completed.

[0040] The methods according to one or more embodiments of this disclosure can be advantageously used in MOL and / or BEOL processes. Some embodiments of this disclosure provide methods for improving interconnect performance. As used herein, and as those skilled in the art will understand, an interconnect generally refers to wiring in an integrated circuit that connects transistors to each other and to external connections. Interconnects include metal lines that carry current within the same element layer and metal vias that carry current between layers. These metal lines and metal vias are formed in gaps within a microelectronic component using one or more conductive metals such as copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo). In one or more embodiments, the dielectric layer includes at least one feature defining a gap having sidewalls and a bottom. In one or more embodiments, the gap includes at least one metal line and at least one metal via. In one or more embodiments, each of the metal lines has sidewalls and a bottom. In one or more embodiments, each of the metal vias has sidewalls and a bottom. As used in this specification and the appended claims, unless otherwise stated, reference to "bottom of the gap" is intended to mean the bottom of the metal via closest to the substrate surface.

[0041] Embodiments of this disclosure provide methods for fabricating interconnect structures in the manufacture of microelectronic components. In one or more embodiments, the microelectronic component described herein includes at least one top interconnect structure interconnected to at least one bottom interconnect structure. Embodiments of this disclosure provide microelectronic components that improve interconnect performance (e.g., reduce via resistance) and methods for fabricating microelectronic components.

[0042] This article references Figures 1A to 1F The method for manufacturing microelectronic components is described. Figure 1A This is a process flow diagram of an exemplary method 10 for manufacturing microelectronic components 100. Figures 1B to 1F The manufacturing phase of the microelectronic component 100 during method 10 is shown.

[0043] The methods described herein (e.g., method 10) generally refer to methods for manufacturing microelectronic components, and more specifically to methods for manufacturing interconnect structures as part of a microelectronic component manufacturing process. Thus, those skilled in the art will appreciate that one or more additional operations required to complete the manufacturing of a microelectronic component are known to those skilled in the art and are within the scope of this disclosure without the need for excessive experimentation.

[0044] See Figure 1AMethod 10 includes pre-cleaning substrate 110 at operation 11. In one or more embodiments, the pre-cleaning process is maintained under vacuum to ensure that no oxides are introduced / formed on substrate 110 during method 10. At operation 11, pre-cleaning substrate 110 removes native oxides from the surface of substrate 110.

[0045] The pre-cleaning process of operation 11 can be any suitable process. In some embodiments, the pre-cleaning process of operation 11 removes polymer residues and metal oxides from the interconnect and maintains the integrity of the dielectric surface. As used herein, the term "substrate 110" can be used to refer to the substrate and / or the pre-cleaned substrate, unless the context clearly indicates otherwise.

[0046] At operation 12, method 10 includes forming a dielectric layer on substrate 110 (e.g., a pre-cleaned substrate). Dielectric layer 145 includes at least one feature defining a gap 146 having sidewalls 148 and a bottom 149. At operation 13, method 10 includes forming a barrier layer 150 on the bottom 149 by exposing substrate 110 to a barrier material. At operation 14, method 10 includes selectively depositing a barrier layer 160 on the sidewalls 148. At operation 15, method 10 includes, as appropriate, selectively depositing a metal pad 170 on the barrier layer 160 (in... Figure 1A (Optional, indicated by a dashed box). At operation 16, method 10 includes removing the blocking layer 150. At operation 17, method 10 includes performing a gap-filling process to fill gap 146.

[0047] In one or more embodiments, method 10 includes operations 11, 12, 13, 14, 15, 16, and 17. In one or more embodiments, method 10 is substantially composed of operations 11, 12, 13, 14, 15, 16, and 17. In one or more embodiments, method 10 is composed of operations 11, 12, 13, 14, 15, 16, and 17. In one or more embodiments, method 10 is composed of operation 13 (wherein a dielectric layer 145 is provided on substrate 110 (e.g., a pre-cleaned substrate),) operations 14, 15, 16, and 17. In one or more embodiments, method 10 is composed of operation 13 (wherein a dielectric layer 145 is provided on substrate 110 (e.g., a pre-cleaned substrate),) operations 14, 16, and 17. Depending on the specific application, one or more operations of method 10 may be repeated any suitable number of times.

[0048] See Figures 1B to 1F This shows a portion of a microelectronic component 100 during the manufacturing phase. Figure 1BIn this embodiment, the microelectronic component 100 includes a substrate 110, a barrier layer 120 on the substrate 110, a metal layer 130 on the barrier layer 120, a conductive fill gap 140, an etch stop layer 142, and a dielectric layer 145 on the etch stop layer 142. The dielectric layer 145 includes at least one feature defining a gap 146 having sidewalls 148 and a bottom 149. According to one or more embodiments, a barrier layer 150 is formed on the bottom 149 of the gap 146. It will be understood that, in one or more embodiments, the conductive fill gap 140 is formed within the same component layer as a metal line that carries current.

[0049] In one or more embodiments, substrate 110 is a wafer, such as a semiconductor substrate. In one or more embodiments, substrate 110 is an etch stop layer on the wafer. In one or more embodiments, substrate 110 is an alumina etch stop layer on the wafer.

[0050] In one or more embodiments, the barrier layer 120 comprises tantalum nitride (TaN). In one or more embodiments, the barrier layer 120 comprises tantalum nitride (TaN) formed by ALD.

[0051] In one or more embodiments, the metal layer 130 comprises one or more of ruthenium (Ru), copper (Cu), cobalt, molybdenum (Mo), tantalum (Ta), or tungsten (W). In one or more embodiments, the metal layer 130 comprises one or more of copper (Cu), cobalt, molybdenum (Mo), or tungsten (W). In one or more embodiments, a portion of the metal layer 130 is etched. In one or more embodiments, a barrier layer 150 is deposited on the etched portion of the metal layer 130. In one or more embodiments, the conductive fill gap 140 comprises one or more of copper (Cu), cobalt, ruthenium (Ru), tungsten (W), or molybdenum (Mo). In one or more embodiments, the etch stop layer 142 comprises one or more of aluminum oxide (AlOx), silicon nitride (SiN), or aluminum nitride (AlN).

[0052] In one or more embodiments, dielectric layer 145 comprises a low dielectric constant dielectric material. In one or more embodiments, dielectric layer 145 comprises silicon oxide (SiO2). x In one or more embodiments, dielectric layer 145 comprises SiO2. x H y (CH z Another embodiment provides a dielectric layer 145 comprising porous or carbon-doped SiO₂. x In some embodiments, dielectric layer 145 is porous or carbon-doped SiO₂ with a dielectric constant (κ) value of less than about 5. xIn other embodiments, dielectric layer 145 is a multilayer structure. For example, in one or more embodiments, dielectric layer 145 includes a multilayer structure having one or more of a dielectric layer, an etch stop layer, and a hard mold layer.

[0053] In one or more of the illustrated embodiments, dielectric layer 145 includes at least one feature defining a gap 146 having sidewalls 148 and a bottom 149. For illustrative purposes, the figures show a substrate 110 with a single feature; however, those skilled in the art will understand that more than one feature may be present.

[0054] As used herein, the term "feature" means any intentional surface irregularity. Suitable examples of features include, but are not limited to, grooves having a top, two sidewalls, and a bottom, and peaks having a top and two sidewalls. Features may have any suitable aspect ratio (the ratio of the feature's depth to its width). In some embodiments, the aspect ratio is greater than or equal to about 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1.

[0055] In some embodiments, at least one feature defines a cylindrical via that carries current between layers when filled with metal, and a line that carries current within the same element layer. In some embodiments, at least one feature defines a gap 146 in the dielectric layer 145. In some embodiments, the gap 146 defines a via portion 146V and a line portion 146L.

[0056] The bottom 149 of the gap 146 is defined by a metal layer 130. In one or more embodiments, the bottom 149 of the gap 146 and the metal layer 130 comprise the same material. In one or more embodiments, the bottom 149 of the gap 146 comprises one or more of ruthenium (Ru), copper (Cu), cobalt, molybdenum (Mo), tantalum (Ta), or tungsten (W).

[0057] In one or more embodiments, according to operation 13 of method 10 ( Figure 1A and Figure 1B A barrier layer 150 is formed on the bottom 149 of the gap 146. In other words, in one or more embodiments, the barrier layer 150 is formed on the metal layer 130 that defines the bottom 149 of the gap 146. In one or more embodiments, the portion of the metal layer 130 on which the barrier layer 150 is formed defines the bottom 149 of the gap 146. In one or more embodiments, the barrier layer 150 is selectively formed on the bottom 149 of the gap 146 by exposing the substrate 110 to the barrier material.

[0058] Embodiments of this disclosure employ a barrier material comprising a hydrocarbon and at least one additive, which can be used to form a barrier layer on a surface to inhibit or prevent subsequent deposition on that surface. It has been advantageously discovered that the disclosed barrier material, which will be described in further detail herein, can be used to inhibit or prevent subsequent deposition on metal surfaces (e.g., metal wires).

[0059] As used herein, barrier materials can be used in one or more of "selective barrier applications" or "selective pad applications" as part of the disclosed method of fabricating interconnect structures in a microelectronic component. Advantageously, the barrier materials of this disclosure can be used in selective barrier applications and / or selective pad applications.

[0060] It has been advantageously found that the use of a barrier material comprising hydrocarbons and at least one additive leads to improved interconnect performance by reducing via resistance. It has also been advantageously found that the use of a barrier material comprising hydrocarbons and at least one additive leads to improved interconnect performance by improving deposition selectivity in selective barrier applications and / or selective pad applications. Advantageously, the barrier material comprising hydrocarbons and at least one additive can be easily removed without causing integration problems.

[0061] Barrier materials comprising hydrocarbons and at least one additive advantageously provide reduced electrical losses in the final microelectronic components. Advantageously, barrier materials comprising hydrocarbons and at least one additive effectively inhibit or prevent subsequent deposition of one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo).

[0062] It has been found that oxygen-containing blocking compounds and nitrogen-containing compounds effectively inhibit or prevent subsequent deposition of conductive materials, but also inappropriately inhibit or prevent subsequent deposition of underlying interconnect materials (such as etch-stop layers (e.g., etch-stop layer 142)). Advantageously, blocking substances comprising hydrocarbons and at least one additive effectively inhibit or prevent subsequent deposition of one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo), without inhibiting or preventing subsequent deposition of underlying interconnect materials (e.g., etch-stop layer 142).

[0063] Embodiments of this disclosure advantageously provide a barrier substance comprising a hydrocarbon and at least one additive. The hydrocarbon may include, but is not limited to, any compound comprising hydrogen (H) atoms and carbon (C) atoms. The hydrocarbon according to one or more embodiments may comprise a substituted or unsubstituted straight-chain hydrocarbon chain, a substituted or unsubstituted branched-chain hydrocarbon chain, or a substituted or unsubstituted aryl hydrocarbon chain. In one or more embodiments, the hydrocarbon comprises a saturated hydrocarbon. As used herein, a “saturated hydrocarbon” refers to a compound having only single bonds. In one or more embodiments, the hydrocarbon comprises a saturated hydrocarbon having a carbon (C) atom ranging from 1 to 25. In one or more embodiments, the saturated hydrocarbon is a substituted or unsubstituted straight-chain hydrocarbon chain, a substituted or unsubstituted branched-chain hydrocarbon chain, or a substituted or unsubstituted aryl hydrocarbon chain having a carbon (C) atom ranging from 1 to 25. In one or more embodiments, the hydrocarbon comprises an unsaturated hydrocarbon. An unsaturated hydrocarbon may comprise any compound comprising unsaturated bonds (e.g., double and / or triple bonds), hydrogen (H) atoms, and carbon (C) atoms. In one or more embodiments, the unsaturated hydrocarbon has the general formula of formula (I) or formula (II).

[0064]

[0065] It has 1 to 25 carbon (C) atoms, wherein R and R' are each independently hydrogen (H), alkyl group, olefinic group, alkyne group, ether group, or amide group.

[0066] In specific embodiments, the unsaturated hydrocarbon comprises a terminal olefin. As used herein, the term "terminal olefin" refers to an unsaturated hydrocarbon having a double bond at position 1. For example, in one or more embodiments, the terminal olefin is 1-butene, 1-pentene, 1-hexene, 1-heptene, 1-octene, 1-nonene, 1-decene, 1-undecene, or 1-dodecene. In specific embodiments, the unsaturated hydrocarbon comprises an intermediate olefin. As used herein, the term "intermediate olefin" refers to an unsaturated hydrocarbon having a double bond at any position other than position 1. For example, in one or more embodiments, wherein the unsaturated hydrocarbon comprises butene, pentene, hexene, hepten, octene, nonene, decene, undecene, or dodecene, and the intermediate olefin is at position 2, 3, 4, 5, or 6. In one or more embodiments, the intermediate olefin is a symmetrical olefin. In embodiments where the intermediate olefin is a symmetrical olefin, the unsaturated hydrocarbon comprises the same number of carbons on each side of the double bond. In specific embodiments where the intermediate olefin is a symmetrical olefin, the unsaturated hydrocarbon comprises, for example, 3-hexene or 5-decene.

[0067] In specific embodiments, the unsaturated hydrocarbon comprises a terminal alkyne. As used herein, the term "terminal alkyne" refers to an unsaturated hydrocarbon having a triple bond at position 1. For example, in one or more embodiments, the terminal alkyne is 1-butyne, 1-pentyne, 1-hexyne, 1-heptyne, 1-octyne, 1-nonyne, 1-decyne, 1-undecyne, or 1-dodecyne. In specific embodiments, the unsaturated hydrocarbon comprises an intermediate alkyne. As used herein, the term "intermediate alkyne" refers to an unsaturated hydrocarbon having a triple bond at any position other than position 1. For example, in one or more embodiments, wherein the unsaturated hydrocarbon comprises butyne, pentyne, hexyne, heptyne, octyne, nonyne, dedecyne, undecyne, or dodecyne, and the intermediate alkyne is at position 2, 3, 4, 5, or 6. In one or more embodiments, the intermediate alkyne is a symmetrical alkyne. In embodiments where the intermediate alkyne is a symmetrical alkyne, the unsaturated hydrocarbon comprises the same number of carbons on each side of the triple bond. In specific embodiments where the intermediate alkyne is a symmetrical alkyne, the unsaturated hydrocarbon includes, for example, 3-hexyne or 5-decyne.

[0068] For example, one of the key challenges with some unsaturated hydrocarbon blocking compounds is surface contamination following the barrier layer removal step. For instance, integration problems may arise after the removal of some unsaturated hydrocarbon blocking compounds, which could be a point of failure in electrical testing.

[0069] Time-dependent dielectric breakdown (TDDB) is measured in electrical tests and refers to the physical process by which a dielectric material stored in a constant electric field less than the material's breakdown strength will break down over time. For example, TDDB in low-dielectric-constant dielectrics is one of the more significant failure mechanisms in integrated circuit manufacturing.

[0070] For example, another key challenge with some unsaturated hydrocarbon blocking compounds is their ability to inhibit or prevent the subsequent deposition of certain materials. For instance, some unsaturated hydrocarbon blocking compounds (such as intermediate alkynes) effectively inhibit or prevent the subsequent deposition of copper (Cu) or cobalt (Co), although they do not inhibit or prevent the subsequent deposition of tungsten (W) or molybdenum (Mo) and copper (Cu) or cobalt (Co).

[0071] Embodiments of this disclosure advantageously provide a barrier substance comprising a hydrocarbon and at least one additive. The at least one additive comprises one or more of an oxygen-containing compound or a nitrogen-containing compound. As those skilled in the art will appreciate, reference to "at least one additive" may refer to, but is not limited to, any suitable number of individual additives or additives in combination with any disclosed additives, and the additives in the combination may include the same or different additives.

[0072] In one or more embodiments, at least one additive has a general formula of formula (III), formula (IV), formula (V), formula (VI), or formula (VII):

[0073]

[0074] It has 1 to 18 carbon (C) atoms, wherein R1, R2, R3, and R4 are each independently hydrogen (H), alkyl group, olefin group, alkyne group, ether group, or amide group.

[0075] In one or more embodiments, at least one additive has a concentration in the barrier substance ranging from 1 ppm to 200,000 ppm. In embodiments where at least one additive has a concentration in the barrier substance ranging from 1 ppm to 200,000 ppm, the remainder of the barrier substance comprises hydrocarbons as described herein. In one or more embodiments, at least one additive has a concentration in the barrier substance ranging from 1 ppm to 1,500 ppm. In embodiments where at least one additive has a concentration in the barrier substance ranging from 1 ppm to 1,500 ppm, the remainder of the barrier substance comprises hydrocarbons as described herein.

[0076] Advantageously, it has been found that having at least one additive in the barrier material at a concentration ranging from 1 ppm to 200,000 ppm does not affect the barrier material’s ability to inhibit or prevent the subsequent deposition of one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and / or molybdenum (Mo).

[0077] In a specific embodiment, at least one additive comprises an additive having a concentration in the barrier substance ranging from 1 ppm to 200,000 ppm. In a specific embodiment, at least one additive comprises two additives, which may be the same or different, each of which independently has a concentration in the barrier substance ranging from 1 ppm to 200,000 ppm. In a specific embodiment, at least one additive comprises three additives, which may be the same or different, each of which independently has a concentration in the barrier substance ranging from 1 ppm to 200,000 ppm. In a specific embodiment, at least one additive comprises four additives, which may be the same or different, each of which independently has a concentration in the barrier substance ranging from 1 ppm to 200,000 ppm.

[0078] Without being bound by theory, it is believed that after pre-cleaning the substrate 110 at operation 11, the surface on which the barrier layer 150 is formed (e.g., the metal layer 130 defining the bottom 149 of the gap 146) has different surface end caps after pre-cleaning, and at least one additive of the barrier material can be differently bound to different surface end caps other than hydrocarbons.

[0079] It is also believed that, without being bound by theory, the disclosed barrier material defines a large portion of the bottom 149 of the metal layer 130 of the hydrocarbon barrier gap 146, and at least one additive fills any vacancies. Thus, it is believed that at least one additive in the disclosed barrier material can improve the filling density of the barrier layer 150 on the metal layer 130, and therefore improve the barrier properties of the barrier layer 150.

[0080] In some embodiments, the processing conditions for exposing the substrate 110 to the barrier material to form the barrier layer 150 can be controlled and can vary depending on the composition of the barrier material.

[0081] The substrate 110 may be exposed to the barrier material at any suitable pressure to form the barrier layer 150. In some embodiments, the substrate 110 is exposed to the barrier material at pressures less than or equal to about 80 Torr, less than or equal to about 70 Torr, less than or equal to about 60 Torr, less than or equal to about 50 Torr, less than or equal to about 40 Torr, less than or equal to about 30 Torr, less than or equal to about 20 Torr, less than or equal to about 15 Torr, less than or equal to about 10 Torr, or less than or equal to about 5 Torr.

[0082] The substrate 110 may be exposed to the barrier material for any suitable period of time to form the barrier layer 150 to a predetermined thickness. In some embodiments, the substrate 110 is exposed to the barrier material for a period ranging from 1 second to 2,000 seconds. In some embodiments, the substrate 110 is exposed to the barrier material for a period ranging from 1 second to 600 seconds. In some embodiments, the substrate 110 is exposed to the barrier material for up to 400 seconds. In one or more embodiments, the substrate 110 may be exposed to the barrier material in one or more cycles ranging from 1 second to 2,000 seconds.

[0083] The substrate 110 may be exposed to the barrier material at any suitable temperature to form the barrier layer 150. In some embodiments, the substrate 110 is exposed to the barrier material at a temperature ranging from 150°C to 500°C (e.g., from 250°C to 350°C, or from 200°C to 300°C).

[0084] The barrier layer 150 can be formed using any suitable deposition technique. In one or more embodiments, the barrier layer 150 is formed in an atomic layer deposition (ALD) chamber.

[0085] Advantageously, the barrier materials of this disclosure can be used in selective barrier applications and / or selective padding applications. Some embodiments of this disclosure relate to selective barrier applications, such as copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and / or molybdenum (Mo) barrier applications.

[0086] See Figure 1A and Figure 1C In operation 14 of method 10, barrier layer 160 is selectively deposited on the sidewall 148 of gap 146. In one or more embodiments, barrier layer 160 has the same properties as barrier layer 120. In one or more embodiments, barrier layer 160 is not formed on the bottom 149 of gap 146 due to the presence of barrier layer 150.

[0087] Barrier layer 160 can be selectively deposited using any suitable deposition technique. In one or more embodiments, barrier layer 160 is selectively deposited by atomic layer deposition (ALD). Barrier layer 160 can have any suitable thickness. In one or more embodiments, barrier layer 160 has a thickness ranging from about 2 Å to about 10 Å. In some embodiments, barrier layer 160 is deposited in a single ALD cycle. In other embodiments, barrier layer 160 is deposited in 1 to 20 ALD cycles. In one or more embodiments, each of the 1 to 20 ALD cycles is configured to deposit a barrier layer 160 with a thickness of about 0.5 Å.

[0088] In one or more embodiments, when barrier layer 150 is absent, the deposition of barrier layer 160 is substantially conformal, such that barrier layer 160 is formed on the sidewalls 148 and bottom 149 of gap 146. As used herein, a “substantially conformal” layer means a layer in which the thickness is approximately the same throughout the layer (e.g., on the top, middle, and bottom of sidewall 148 and on the bottom 149 of gap 146). The thickness variation of a substantially conformal layer is less than or equal to about 5%, 2%, 1%, or 0.5%.

[0089] In one or more embodiments, due to the presence of barrier layer 150, barrier layer 160 is selectively deposited on a portion of sidewall 148 and not formed on bottom 149 of gap 146. In one or more embodiments, barrier layer 160 covers the entire sidewall 148.

[0090] It has been advantageously found that the presence of at least one additive in the barrier material enhances the selectivity of barrier layer 160 deposition. Without being bound by theory, it is considered that the presence of at least one additive in the barrier material enhances the selectivity of barrier layer 160 deposition compared to using a blocking compound (such as a saturated or unsaturated hydrocarbon) alone.

[0091] In one or more embodiments, when the barrier layer 160 is formed on the bottom 149 and the sidewall 148, there exists a ratio of the thickness of the barrier layer 160 on the sidewall 148 to the thickness of the barrier layer 160 on the bottom 149, which is greater than 6. In one or more embodiments, the ratio is greater than 5, greater than 4, greater than 3, greater than 2, or greater than 1.

[0092] In one or more embodiments, when barrier layer 150 is present, barrier layer 160 has a thickness ranging from 5 angstroms to 20 angstroms on sidewall 148 and a thickness of less than or equal to 5 angstroms on bottom 149. In one or more embodiments, when barrier layer 150 is present, barrier layer 160 has a thickness of less than or equal to 4 angstroms, less than or equal to 3 angstroms, less than or equal to 2 angstroms, or less than or equal to 1 angstrom on bottom 149. In one or more embodiments, when barrier layer 150 is present, barrier layer 160 is not formed on bottom 149.

[0093] Barrier layer 160 may comprise any suitable material that prevents the diffusion of conductive metals (such as, for example, one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo)) into dielectric layer 145. Suitable barrier layers for conductive metal barrier applications (such as one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo) barrier applications) include, but are not limited to, tantalum nitride (TaN) and manganese nitride (MnN). In some embodiments, barrier layer 160 comprises tantalum nitride (TaN) formed by atomic layer deposition (ALD). In some embodiments, the ALD of barrier layer 160 comprising tantalum nitride (TaN) comprises exposing substrate 110 to a tantalum-containing precursor (such as, for example, pentapenta(dimethylamino)tantalum (V) (PDMAT)) and a nitrogen-containing reactant (such as, for example, ammonia (NH3)).

[0094] For some selective barrier applications, suitable dopants include, but are not limited to, ruthenium (Ru), copper (Cu), cobalt (Co), manganese (Mn), aluminum (Al), tantalum (Ta), molybdenum (Mo), niobium (Nb), vanadium (V), or combinations thereof. Plasma treatment can be used after doping to promote the formation of intermetallic compounds between the matrix and the dopant, as well as to remove film impurities and improve the density of the barrier layer. In other embodiments, post-treatment may include, but is not limited to, physical vapor deposition (PVD), thermal annealing, chemical enhancement, or the like. In some selective barrier applications, high-frequency plasma (defined as greater than about 14 MHz or about 40 MHz or higher) can be used with any inert gas, including but not limited to one or more of neon (Ne), hydrogen (H2), and argon (Ar). In one or more embodiments, higher plasma frequencies (greater than about 13.56 MHz) can be used to prevent damage from low dielectric constants. In some embodiments, barrier layer 160 comprises tantalum nitride (TaN) doped with ruthenium (Ru).

[0095] In selective barrier and selective padding applications, the barrier material is selectively adsorbed onto the bottom 149 of the gap 146 as a barrier layer 150. The bottom 149 comprises a metallic surface, which includes, but is not limited to, one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo). The barrier material advantageously inhibits subsequent deposition, for example, by providing a nucleation delay on the bottom 149. Advantageously, there is no thermal reaction between the barrier material and the tantalum-containing precursor (e.g., pentapenta(dimethylamino)tantalum(V) (PDMAT)) and the nitrogen-containing reactant (e.g., ammonia (NH3)) used to form the barrier layer 160 comprising tantalum nitride (TaN).

[0096] Some implementations involve selective pad application. Without being bound by theory, reducing the thickness of the metal pad (e.g., metal pad 170) becomes crucial to meeting resistivity targets in order to maintain as much volume as possible in subsequent conductive gap filling processes.

[0097] See Figure 1A and Figure 1D At operation 15 of method 10, the metal liner 170 is selectively deposited on... Figure 1B The metal pad 170 is deposited on the barrier layer 160. In one or more embodiments, the metal pad 170 has the same properties as the metal layer 130. In one or more embodiments, the metal pad 170 is selectively deposited on the sidewalls 148 of the barrier layer 160. In one or more embodiments, due to the presence of the barrier layer 150, the metal pad 170 is not formed on the bottom 149 of the gap 146.

[0098] It has been found that selectively depositing metal pads 170 advantageously reduces the resistance of vias compared to vias in microelectronic components where metal pads are not selectively deposited.

[0099] It has been advantageously found that the presence of at least one additive in the barrier material enhances the selectivity of metal liner 170 deposition. Without being bound by theory, it is considered that the presence of at least one additive in the barrier material enhances the selectivity of metal liner 170 deposition compared to using a blocking compound (such as a saturated or unsaturated hydrocarbon) alone.

[0100] In one or more embodiments, the metal liner 170 comprises one or more of ruthenium (Ru), cobalt, molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the metal liner 170 comprises one or more of a monolayer of ruthenium (Ru) or a monolayer of cobalt (Co). In one or more embodiments, the metal liner 170 comprises a monolayer of ruthenium (Ru). In one or more embodiments, the metal liner 170 comprises a monolayer of ruthenium (Ru) selectively deposited on the sidewall 148 and not formed on the bottom 149 of the gap 146 due to the presence of the barrier layer 150.

[0101] In one or more embodiments, when the metal liner 170 comprises a monolayer of ruthenium (Ru) selectively deposited on the sidewall 148 and the barrier layer 150 is formed on the bottom 149, there exists a ratio greater than 3 between the thickness of the metal liner on the sidewall 148 and the thickness of the metal liner 170 on the bottom 149. In one or more embodiments, the ratio between the thickness of the metal liner on the sidewall 148 and the thickness of the metal liner on the bottom 149 is greater than 4, greater than 5, greater than 6, or greater than 7. In one or more embodiments, the metal liner 170 is not formed on the bottom 149 due to the presence of the barrier layer 150.

[0102] In one or more embodiments, when the metal liner 170 comprises a monolayer of selectively deposited ruthenium (Ru), the metal liner 170 has a thickness on the sidewall 148 ranging from 5 angstroms to 20 angstroms. In one or more embodiments, when the metal liner 170 comprises a monolayer of selectively deposited ruthenium (Ru), the metal liner 170 has a thickness of less than or equal to 5 angstroms on the bottom 149. In one or more embodiments, when the metal liner 170 comprises a monolayer of selectively deposited ruthenium (Ru), the metal liner 170 has a thickness of less than or equal to 4 angstroms, less than or equal to 3 angstroms, less than or equal to 2 angstroms, or less than or equal to 1 angstrom on the bottom 149. In one or more embodiments, due to the presence of the barrier layer 150, the metal liner 170 is not formed on the bottom 149.

[0103] In one or more embodiments, the metal gasket 170 comprises a multilayer film having a first gasket layer made of a first metal and a second gasket layer made of a second metal. Each of the first and second metals independently comprises one or more of ruthenium (Ru), cobalt, molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the first gasket layer comprises ruthenium (Ru) and the second gasket layer comprises cobalt (Co).

[0104] In one or more embodiments, when the metal pad 170 comprises a multilayer film having a first pad layer made of a first metal and a second pad layer made of a second metal, the multilayer film has a combined thickness in the range of 10 to 20 angstroms on the sidewall 148. In one or more embodiments, when the first pad layer comprises ruthenium (Ru) and the second pad layer comprises cobalt (Co), the multilayer film has a combined thickness in the range of 5 to 20 angstroms on the bottom 149. In one or more embodiments, when the first pad layer comprises ruthenium (Ru) and the second pad layer comprises cobalt (Co), the multilayer film is not formed on the bottom 149.

[0105] In some embodiments, the multilayer film comprises an alloy of two metals in a single layer. In one or more embodiments, the multilayer film comprises an alloy of one or more of ruthenium (Ru), cobalt, molybdenum (Mo), or tantalum (Ta), such as, for example, an alloy of ruthenium (Ru) and cobalt, an alloy of ruthenium (Ru) and molybdenum (Mo), an alloy of ruthenium (Ru) and tantalum (Ta), an alloy of cobalt (cobalt) and molybdenum (Mo), or an alloy of cobalt (Co) and tantalum (Ta).

[0106] Advantageously, the multilayer films according to one or more embodiments are ultrathin, for example, having a thickness of less than or equal to 20 angstroms, such as in the range of 5 to 20 angstroms, or in the range of 10 to 20 angstroms, between two metals, such as between barrier layer 160 and a conductive metal (e.g., gap filler material 180 for filling gap 146), the multilayer films provide better interfacial adhesion and mobility. The multilayer films and methods described according to one or more embodiments can be used in metal contact, interconnect, and overlay applications. The multilayer films according to one or more embodiments are thinner than current pads, which are typically greater than 20 angstroms and up to 30 angstroms.

[0107] The multilayer films described in this paper can extend metal-filled and capped applications to advanced nodes, such as enabling conductive metal reflow at 3 nm, 2 nm, 1.4 nm and smaller nodes, for example, one or more of copper (Cu), cobalt (Co), tungsten (W), ruthenium (Ru), and / or molybdenum (Mo) reflow, low resistivity in mid-stage processes (MOL) and back-end processes (BEOL), and memory applications.

[0108] Multilayer films can be formed using any suitable deposition technique, and may include one or more deposition techniques. In one or more embodiments, the first and second liner layers are formed using the same deposition technique. In one or more embodiments, the first and second liner layers are formed using different deposition techniques. Multilayer films can be formed in a single processing chamber or in multiple processing chambers. In one or more embodiments, multilayer films can be processed by various methods, including thermal treatment, plasma treatment, and / or chemical treatment.

[0109] In embodiments where the first metal comprises ruthenium (Ru) and the second metal comprises cobalt (Co), the first pad layer is formed by chemical vapor deposition (CVD), including exposing the substrate to...

[0110] (Methylcyclohexadiene tricarbonylruthenium) and hydrogen (H2), followed by CVD of cyclopentadienyl dicarbonyl cobalt (CpCo(CO)2). In selective liner applications, advantageously, there is no thermal reaction between the disclosed barrier material and the hydrogen (H2) used to form the first liner layer containing ruthenium (Ru).

[0111] In a specific embodiment, when the first pad layer comprises ruthenium (Ru) and the second pad layer comprises cobalt (Co), the first pad layer and the second pad layer are formed in the same processing chamber. In a specific embodiment, when the first pad layer comprises ruthenium (Ru) and the second pad layer comprises cobalt (Co), the first pad layer and the second pad layer are formed in the same chemical vapor deposition (CVD) chamber.

[0112] See Figure 1A and Figure 1E At operation 16 of method 10, the barrier layer 150 is removed. In one or more embodiments, removing the barrier layer 150 includes a plasma processing process. The plasma processing process can be any suitable process. In one or more embodiments, the plasma processing process includes a physical vapor deposition (PVD) process. In one or more embodiments, the plasma processing includes causing one or more of hydrogen (H2) or argon (Ar) to flow. In one or more embodiments, the plasma processing process increases the density of the barrier layer 160.

[0113] For example, one of the key challenges with some unsaturated hydrocarbon blocking compounds is surface contamination following the barrier layer removal step. For instance, integration problems may arise after the removal of some unsaturated hydrocarbon blocking compounds, which could be a point of failure in electrical testing.

[0114] Advantageously, any remaining barrier layer 150 after the plasma processing is substantially free of carbon (C). As used in this regard, “substantially free of” means, on an atomic basis, that the total composition of any remaining barrier layer 150 after removal (according to operation 16 of method 10) is less than about 5%, including less than about 4%, less than about 3%, less than about 2%, less than about 1%, less than about 0.5%, and less than about 0.1%, containing carbon (C).

[0115] See Figure 1A and Figure 1F Method 10 includes performing a gap-filling process to fill gap 146 (operation 17). The gap-filling process may include any suitable deposition technique. In one or more embodiments, the gap-filling process includes a physical vapor deposition (PVD) process. In one or more embodiments, the gap-filling process includes filling gap 146 using gap-filling material 180. Gap-filling material 180 may include any suitable material, such as a conductive material. In one or more embodiments, gap-filling material 180 includes one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo). In one or more embodiments, the gap-filling process includes filling gap 146 using one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo) by physical vapor deposition (PVD).

[0116] The gap filler material 180 is substantially free of seams and / or voids. As used herein, "substantially free of" means, on an atomic basis, that the total composition of the gap filler material 180 is less than about 5%, including less than about 4%, less than about 3%, less than about 2%, less than about 1%, less than about 0.5%, and less than about 0.1%, containing seams and / or voids. Advantageously, in one or more embodiments, the gap filler material 180 is free of seams and / or voids.

[0117] In one or more embodiments, after the gap 146 is filled with the gap filler material 180, a complete interconnect structure, such as interconnect structure 190, is formed, such that additional interconnect structures can be formed on top of or under interconnect structure 190.

[0118] In one or more embodiments, the methods described herein include optional post-processing operations. Optional post-processing operations may be, for example, processes for modifying film properties (e.g., annealing) or additional film deposition processes for growing additional films (e.g., additional ALD or CVD processes). In some embodiments, optional post-processing operations may be processes for modifying the properties of the deposited film / layer. In some embodiments, optional post-processing operations include annealing the substrate. In some embodiments, the annealing process is performed at temperatures in the range of about 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, 900°C, or 1000°C. The annealing environment in some embodiments includes one or more of the following: an inert gas (e.g., molecular nitrogen (N2), argon (Ar)) or a reducing gas (e.g., molecular hydrogen (H2) or ammonia (NH3)) or an oxidizing agent, such as, but not limited to, oxygen (O2), ozone (O3), or peroxides. Annealing can be performed for any suitable duration. In some embodiments, the substrate is annealed for a predetermined time ranging from about 15 seconds to about 90 minutes, or from about 1 minute to about 60 minutes. In some embodiments, the annealed substrate increases density, reduces resistivity, and / or increases the purity of layers (such as barrier layers and / or metal pads).

[0119] In some embodiments, a substrate (e.g., substrate 110) is moved from a first chamber to a separate next chamber for further processing. The substrate may be moved directly from the first chamber to a separate processing chamber, or it may be moved from the first chamber to one or more transfer chambers and then subsequently to a separate processing chamber. Thus, the processing apparatus may include multiple chambers communicating with transfer stations. Such an apparatus may be referred to as a “clustering tool” or a “clustering system,” and the like.

[0120] Typically, a clustering tool is a modular system comprising multiple chambers that perform various functions, including substrate centering and orientation, degassing, annealing, deposition, and / or etching. According to one or more embodiments, the clustering tool includes at least a first chamber and a central transfer chamber. The central transfer chamber houses a robot that can transfer substrates between and within the processing chamber and the load-locking chamber. The transfer chamber is typically maintained under vacuum conditions and provides an intermediate stage for transferring substrates from one chamber to another and / or positioning them at the front end of the clustering tool within the load-locking chamber. However, the actual arrangement and combination of the chambers may be modified for the purpose of performing the specific steps of the processes described herein.

[0121] Other processing chambers that can be used include, but are not limited to, cyclic deposition (including deposition steps and annealing or treatment steps), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, plasma nitriding, degassing, orientation, hydroxylation, and other substrate processes. By performing the process in a chamber on a cluster tool, surface contamination of the substrate due to atmospheric impurities can be avoided, preventing oxidation before the deposition of subsequent films.

[0122] According to one or more embodiments, the substrate remains under vacuum or "load-locked" conditions and is not exposed to ambient air when moving from one chamber to the next. The transfer chamber is therefore under vacuum and "evacuated" under vacuum pressure. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, the inert gas is used as a purge gas to remove some or all of the reactants (e.g., reactants). According to one or more embodiments, the purge gas is injected at the outlet of the deposition chamber to prevent reactants (e.g., reactants) from moving from the deposition chamber to the transfer chamber and / or additional processing chambers. Thus, the flow of inert gas forms a curtain at the outlet of the chamber.

[0123] Substrates can be processed in a single substrate deposition chamber, where a single substrate is loaded, processed, and unloaded before processing another substrate. Similar to a transport system, substrates can also be processed continuously, where multiple substrates are independently loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The shape of the chamber and the associated transport system can form a straight or curved path. Alternatively, the processing chamber can be a turntable, where multiple substrates move about a central axis and are exposed to processes such as deposition, etching, annealing, and cleaning throughout the turntable path.

[0124] The substrate can also be fixed or rotated during processing. Rotating the substrate can be continuous or in discrete steps (about the substrate axis). For example, the substrate can be rotated throughout the entire process, or it can be rotated slightly between exposures to different reactive and inert gases. Rotating the substrate during processing (continuously or in steps) helps to produce more uniform deposition or etching by minimizing the effects of localized variations in, for example, gas flow geometry.

[0125] Additional embodiments relate to clustering tools for manufacturing microelectronic components (e.g., microelectronic component 100) described herein and performing methods (e.g., method 10) described herein. In one or more embodiments, the clustering tool includes a pre-cleaning chamber for pre-cleaning a substrate and a deposition chamber for forming a dielectric layer including at least one feature defining a gap having sidewalls and a bottom. In one or more embodiments, a pre-cleaned substrate comprising a dielectric layer including at least one feature defining a gap having sidewalls and a bottom is provided.

[0126] In one or more embodiments, the clustering tool includes a deposition chamber for forming a barrier layer (e.g., barrier layer 150). In one or more embodiments, the clustering tool includes an atomic layer deposition (ALD) chamber for forming barrier layer 150. In one or more embodiments, the clustering tool includes an atomic layer deposition (ALD) chamber for selectively depositing a barrier layer (e.g., barrier layer 160). In one or more embodiments, the clustering tool includes a chemical vapor deposition (CVD) chamber for selectively depositing a metal liner (e.g., metal liner 170). In a specific embodiment, when the metal liner 170 comprises a multilayer film, a first liner layer and a second liner layer are formed in the same processing chamber. In a specific embodiment, the first liner layer and the second liner layer are formed in the same chemical vapor deposition (CVD) chamber.

[0127] In one or more embodiments, the cluster tool includes a chamber for removing the barrier layer 150. Advantageously, in one or more embodiments, the same processing chamber can be used for selectively depositing the barrier layer 160 and removing the barrier layer 150. In one or more embodiments, the cluster tool includes a deposition chamber for performing a gap-filling process to fill gaps 146 with gap-filling material 180. In one or more embodiments, the cluster tool includes a physical vapor deposition (PVD) chamber for performing a gap-filling process to fill gaps 146 with gap-filling material 180.

[0128] In one or more embodiments, one or more operations of the methods described herein are performed in situ without intermediate vacuum interruption. In one or more embodiments, each of the operations of the described methods is performed in situ without intermediate vacuum interruption. In one or more embodiments, one or more operations of the methods described herein are performed out of situ, such that one or more processes are performed in the event of an intermediate vacuum interruption.

[0129] Another aspect of this disclosure relates to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing system, cause the processing system to perform operations of the methods described herein. In one embodiment, a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing system, cause the processing system to perform operations of the methods described herein. Figures 1A to 1F The operation of the described method.

[0130] Although the disclosure herein has been described with reference to specific embodiments, it will be understood that these embodiments are merely illustrative of the principles and applications of this disclosure. Those skilled in the art will readily recognize that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing a microelectronic component, the method comprising: A dielectric layer is formed on a substrate, the dielectric layer including at least one feature defining a gap having sidewalls and a bottom; A barrier layer is formed on the bottom by exposing the substrate to a barrier substance comprising a hydrocarbon and at least one additive. A barrier layer is selectively deposited on the sidewall; Remove the barrier layer; as well as Perform a gap filling process to fill the gap using a gap filling material.

2. The method of claim 1, further comprising: pre-cleaning the substrate prior to forming the barrier layer.

3. The method of claim 1, wherein the hydrocarbon is an unsaturated hydrocarbon having a general formula (I) or (II). It has 1 to 25 carbon (C) atoms, wherein R and R' are each independently hydrogen (H), alkyl group, olefinic group, alkyne group, ether group, or amide group.

4. The method of claim 1, wherein the at least one additive comprises one or more of an oxygen-containing compound or a nitrogen-containing compound.

5. The method of claim 3, wherein the at least one additive has a general formula of formula (III), formula (IV), formula (V), formula (VI), or formula (VII). It has 1 to 18 carbon (C) atoms, wherein R1, R2, R3, and R4 are each independently hydrogen (H), alkyl group, olefin group, alkyne group, ether group, or amide group.

6. The method of claim 1, wherein the at least one additive has a concentration in the barrier substance ranging from 1 ppm to 200,000 ppm.

7. The method of claim 6, wherein the at least one additive has a concentration in the barrier substance ranging from 1 ppm to 1,500 ppm.

8. The method of claim 1, wherein the barrier layer comprises tantalum nitride (TaN) formed by atomic layer deposition (ALD).

9. The method of claim 1, further comprising: selectively depositing a metal liner on the barrier layer on the sidewall prior to removing the barrier layer.

10. The method of claim 9, wherein the metal gasket comprises one or more of ruthenium (Ru), cobalt, molybdenum (Mo), and tantalum (Ta).

11. The method of claim 10, wherein the metal liner comprises a single layer of ruthenium (Ru).

12. The method of claim 10, wherein the metal gasket comprises a multilayer film having a first gasket layer made of a first metal and a second gasket layer made of a second metal.

13. The method of claim 12, wherein the first metal comprises ruthenium (Ru) and the second metal comprises cobalt (Co).

14. The method of claim 1, wherein removing the barrier layer comprises a plasma processing process.

15. The method of claim 14, wherein the plasma processing increases the density of the barrier layer.

16. The method of claim 1, wherein the gap-filling material comprises one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo).

17. A method for manufacturing a microelectronic component, the method comprising: Pre-clean substrate; A dielectric layer is formed on the substrate, the dielectric layer including at least one feature defining a gap having sidewalls and a bottom; A barrier layer is formed on the bottom by exposing the substrate to a barrier substance comprising a hydrocarbon and at least one additive, wherein the at least one additive comprises one or more of an oxygen-containing compound and a nitrogen-containing compound. A barrier layer is selectively deposited on the sidewall, the barrier layer comprising tantalum nitride (TaN) formed by atomic layer deposition (ALD); A metal liner is selectively deposited on the barrier layer on the sidewall, the metal liner comprising one or more of ruthenium (Ru), cobalt (cobalt), molybdenum (Mo), and tantalum (Ta); Remove the barrier layer; as well as A gap-filling process is performed to fill the gap using a gap-filling material, the gap-filling material comprising one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), or molybdenum (Mo).

18. The method of claim 17, wherein the at least one additive has a general formula of formula (III), formula (IV), formula (V), formula (VI), or formula (VII). It has 1 to 18 carbon (C) atoms, wherein R1, R2, R3, and R4 are each independently hydrogen (H), alkyl group, olefin group, alkyne group, ether group, or amide group.

19. The method of claim 17, wherein the at least one additive has a concentration in the barrier substance ranging from 1 ppm to 200,000 ppm.

20. The method of claim 19, wherein the at least one additive has a concentration in the barrier substance ranging from 1 ppm to 1,500 ppm.

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