Chip, MEMS packaging structure and electronic device

Abstract

The application provides a chip, a MEMS packaging structure and an electronic device. The chip structure comprises a substrate, the substrate is provided with an acoustic hole; a diaphragm and a back plate, the diaphragm comprises a first diaphragm and a second diaphragm, the first diaphragm is connected to the substrate, the back plate is connected to one side of the first diaphragm away from the substrate, and the second diaphragm is connected to one side of the back plate away from the first diaphragm; the back plate is provided with a plurality of sound holes, the plurality of sound holes are arranged opposite to the acoustic hole; at least one first diaphragm corresponding to the sound hole is provided with a first through hole, and / or at least one second diaphragm corresponding to the sound hole is provided with a second through hole; a dielectric material, the dielectric material comprises a first dielectric material and a second dielectric material, the first dielectric material covers the first through hole, and / or the second dielectric material covers the second through hole. The application can improve the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

Description

Technical Field

[0001] This application relates to the field of MEMS packaging technology, and more specifically, to a chip, a MEMS packaging structure, and an electronic device. Background Technology

[0002] In existing technologies, MEMS (Micro Electro Mechanical System) packaging structures mainly consist of chips and packaging shells to achieve acoustic-to-electrical conversion. However, the packaging shell is usually adjacent to and opposite to the diaphragm in the chip. Within the confined packaging space, the two easily form coupled electric fields, resulting in unavoidable parasitic capacitance. Furthermore, the chip typically has multiple diaphragms, and adjacent diaphragms, also adjacent to and opposite to each other, easily form coupled electric fields within the confined packaging space, leading to unavoidable parasitic capacitance. Therefore, both types of parasitic capacitance degrade the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0003] Therefore, a new technical solution is needed to solve the above-mentioned technical problems. Summary of the Invention

[0004] One objective of this application is to provide a new technical solution for chips, MEMS packaging structures, and electronic devices.

[0005] According to a first aspect of this application, a chip is provided, wherein the chip comprises: A substrate, wherein the substrate is provided with acoustic holes; The diaphragm includes a first diaphragm and a second diaphragm. The first diaphragm is connected to the substrate, and the back plate is connected to the side of the first diaphragm away from the substrate. The second diaphragm is connected to the side of the back plate away from the first diaphragm. The back plate has a plurality of sound holes, which are arranged opposite to the sound holes. At least one of the sound holes has a first through hole at the first diaphragm, and / or at least one of the sound holes has a second through hole at the second diaphragm. The dielectric material includes a first dielectric material and a second dielectric material, wherein the first dielectric material covers the first via and / or the second dielectric material covers the second via.

[0006] Optionally, the first dielectric material is disposed on at least a portion of the first diaphragm on the side close to the substrate; And / or, the second dielectric material is disposed on at least a portion of the second diaphragm on the side adjacent to the substrate.

[0007] Optionally, the first dielectric material is disposed on at least a portion of the first diaphragm on the side opposite to the substrate, and a portion of the first dielectric material fills the first through-hole; And / or, the second dielectric material is disposed on at least a portion of the second diaphragm on the side opposite to the substrate, and a portion of the second dielectric material fills the second via.

[0008] Optionally, the first dielectric material includes a first sub-dielectric material and a second sub-dielectric material, the first sub-dielectric material is disposed on at least a portion of the first diaphragm on the side close to the substrate, the second sub-dielectric material is disposed on at least a portion of the first diaphragm on the side away from the substrate, and a portion of the second sub-dielectric material fills the first through-hole; And / or, the second dielectric material includes a third sub-dielectric material and a fourth sub-dielectric material, the third sub-dielectric material being disposed on at least a portion of the second diaphragm on the side close to the substrate, the fourth sub-dielectric material being disposed on at least a portion of the second diaphragm on the side away from the substrate, and a portion of the fourth sub-dielectric material filling the second via.

[0009] Optionally, the first sub-dielectric material and the second sub-dielectric material are made of the same material, or the first sub-dielectric material and the second sub-dielectric material are made of different materials; And / or, the third sub-dielectric material and the fourth sub-dielectric material are made of the same material, or the third sub-dielectric material and the fourth sub-dielectric material are made of different materials.

[0010] Optionally, the first sub-dielectric material covers the side of the first diaphragm close to the substrate, and the second sub-dielectric material covers the side of the first diaphragm away from the substrate; And / or, the third sub-dielectric material covers the side of the second diaphragm close to the substrate, and the fourth sub-dielectric material covers the side of the second diaphragm away from the substrate.

[0011] Optionally, the diameter of the first through hole and the diameter of the second through hole are the same, or the diameter of the first through hole and the diameter of the second through hole are different.

[0012] Optionally, the first dielectric material includes a fifth sub-dielectric material and a sixth sub-dielectric material, wherein the fifth sub-dielectric material fills the first through-hole, and the sixth sub-dielectric material is arranged in a ring and sandwiched between the fifth sub-dielectric material and the first diaphragm; And / or, the second dielectric material includes a seventh sub-dielectric material and an eighth sub-dielectric material, the seventh sub-dielectric material filling the second through-hole, and the eighth sub-dielectric material being arranged in a ring and sandwiched between the seventh sub-dielectric material and the second diaphragm.

[0013] Optionally, the central axis of the first dielectric material is offset from the central axis of the sound hole, and at least a portion of the orthographic projection of the first dielectric material toward the substrate coincides with at least a portion of the orthographic projection of the sound hole toward the substrate. And / or, the central axis of the second dielectric material is offset from the central axis of the sound hole, and at least a portion of the orthographic projection of the second dielectric material toward the substrate coincides with at least a portion of the orthographic projection of the sound hole toward the substrate.

[0014] Optionally, the cross-sectional shape of the first through hole is circular, annular, or polygonal; And / or, the cross-sectional shape of the second through hole is circular, annular, or polygonal.

[0015] Optionally, the first dielectric material fills the first through-hole, and / or the second dielectric material fills the second through-hole.

[0016] Optionally, the first dielectric material fills the first through-hole, and a portion of the first diaphragm covers the first dielectric material; And / or, the second dielectric material fills the second via, and a portion of the second diaphragm covers the second dielectric material.

[0017] Optionally, the dielectric material may be made of at least one of silicon nitride and silicon carbide.

[0018] According to a second aspect of this application, a MEMS packaging structure is provided, comprising a packaging shell and a chip as described in any of the first aspects, wherein the packaging shell forms a receiving cavity and the chip is disposed in the receiving cavity.

[0019] According to a third aspect of this application, an electronic device is provided, which includes a chip as described in any of the first aspects, or includes a MEMS packaging structure as described in the second aspect.

[0020] The chip in this application effectively removes the electric field lines of the diaphragm opposite to the sound hole by covering the first through hole with a first dielectric material and / or covering the second through hole with a second dielectric material, thereby reducing parasitic capacitance and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0021] Other features and advantages of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the present application and, together with their description, serve to explain the principles of the present application.

[0023] Figure 1 This is a schematic diagram of the chip structure in one embodiment of this application. Figure 1 .

[0024] Figure 2 yes Figure 1 A schematic diagram of the partial structure of the diaphragm.

[0025] Figure 3 yes Figure 1 partial cross-section Figure 1 .

[0026] Figure 4 yes Figure 1 partial cross-section Figure 2 .

[0027] Figure 5 yes Figure 1 partial cross-section Figure 3 .

[0028] Figure 6 yes Figure 1 partial cross-section Figure 4 .

[0029] Figure 7 yes Figure 1 partial cross-section Figure 5 .

[0030] Figure 8 yes Figure 1 partial cross-section Figure 6 .

[0031] Figure 9 yes Figure 1 partial cross-section Figure 7 .

[0032] Figure 10 yes Figure 1 partial cross-section Figure 8 .

[0033] Figure 11 yes Figure 1 partial cross-section Figure 9 .

[0034] Figure 12 yes Figure 1 partial cross-section Figure 10 .

[0035] Figure 13 yes Figure 1 partial cross-section Figure 10 one.

[0036] Figure 14 yes Figure 1 partial cross-section Figure 10 two.

[0037] Figure 15 yes Figure 1 partial cross-section Figure 10 three.

[0038] Figure 16 yes Figure 15 A cross-sectional view of the first diaphragm.

[0039] Figure 17 yes Figure 1 partial cross-section Figure 10 Four.

[0040] Figure 18 yes Figure 17 Cross-sectional view of the second diaphragm.

[0041] Figure 19 yes Figure 1 partial cross-section Figure 10 five.

[0042] Figure 20 yes Figure 1 partial cross-section Figure 10 six.

[0043] Figure 21 yes Figure 1 partial cross-section Figure 10 seven.

[0044] Figure 22 yes Figure 1 partial cross-section Figure 10 eight.

[0045] Figure 23 yes Figure 1 partial cross-section Figure 10 Nine.

[0046] Figure 24 yes Figure 23 A cross-sectional view of the first diaphragm.

[0047] Figure 25 yes Figure 1 partial cross-section Figure 2 ten.

[0048] Figure 26 yes Figure 25 Cross-sectional view of the second diaphragm.

[0049] Figure 27 yes Figure 1 partial cross-section Figure 2 eleven.

[0050] Figure 28 yes Figure 1 partial cross-section Figure 2 twelve.

[0051] Figure 29 yes Figure 1 partial cross-section Figure 2 Thirteen.

[0052] Figure 30 yes Figure 1 partial cross-section Figure 2 fourteen.

[0053] Figure 31 yes Figure 1 partial cross-section Figure 2 fifteen.

[0054] Figure 32 yes Figure 1 partial cross-section Figure 2 sixteen.

[0055] Figure 33 yes Figure 1 partial cross-section Figure 2 Seventeen.

[0056] Figure 34 This is a partial cross-sectional view of a chip in the prior art.

[0057] Figure 35 This is a partial cross-sectional view of a chip in one embodiment of this application.

[0058] Figure 36 This is a schematic diagram of the chip structure in one embodiment of this application. Figure 2 .

[0059] Explanation of reference numerals in the attached figures: 1. Substrate; 100. Acoustic aperture; 2. Diaphragm; 201. First diaphragm; 2011. First through hole; 202. Second diaphragm; 2021. Second through hole; 203. Third diaphragm; 3. Back plate; 300. Sound hole; 301. First back plate; 302. Second back plate; 4. Connecting column; 5. Insulation layer; 6. Electric field lines; 7. Dielectric material; 701, First dielectric material; 7011, First sub-dielectric material; 7012, Second sub-dielectric material; 7013, Fifth sub-dielectric material; 7014, Sixth sub-dielectric material; 702, Second dielectric material; 7021, Third sub-dielectric material; 7022, Fourth sub-dielectric material; 7023, Seventh sub-dielectric material; 7024, Eighth sub-dielectric material. Detailed Implementation

[0060] Various exemplary embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this application.

[0061] The embodiments of this application will now be described in detail, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0062] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0063] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0064] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0065] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0066] According to one embodiment of this application, a chip is provided, the chip comprising: a substrate 1 having sound holes 100; a diaphragm 2 and a backplate 3, the diaphragm 2 including a first diaphragm 201 and a second diaphragm 202, the first diaphragm 201 being connected to the substrate 1, the backplate 3 being connected to the side of the first diaphragm 201 facing away from the substrate 1, and the second diaphragm 202 being connected to the side of the backplate 3 facing away from the first diaphragm 201; the backplate 3 having a plurality of sound holes 300. 00 is disposed opposite to the sound hole 100; a first through hole 2011 is provided at at least one of the first diaphragms 201 corresponding to the sound hole 300, and / or a second through hole 2021 is provided at at least one of the second diaphragms 202 corresponding to the sound hole 300; dielectric material 7, the dielectric material 7 includes a first dielectric material 701 and a second dielectric material 702, the first dielectric material 701 covers the first through hole 2011, and / or the second dielectric material 702 covers the second through hole 2021.

[0067] Specifically, the chip described in this application embodiment can be applied to electronic devices such as mobile phones, tablets, personal digital assistants, televisions, smart wearable products, virtual reality terminal devices, augmented reality terminal devices, small rechargeable household appliances (such as soy milk makers and robot vacuum cleaners), drones, radar, aerospace equipment, or vehicle-mounted equipment, and its core function is sound-to-electricity conversion.

[0068] like Figure 1 and Figure 36 As shown, the substrate 1 can be a silicon-based substrate or a ceramic substrate. An acoustic aperture 100 is provided on the substrate 1, allowing external sound waves to pass through and enter the interior of the chip. The diaphragm 2 can be a silicon-based diaphragm or a metal diaphragm, and the diaphragm 2 can vibrate under the drive of external sound waves. The backplate 3 can be a fixed electrode plate made of conductive material, and the backplate 3 can be disposed opposite to the diaphragm 2 to form a capacitor structure between them.

[0069] Therefore, after external sound waves enter the interior of the chip through the sound hole 100, they can drive the diaphragm 2 to vibrate, thereby changing the distance between the diaphragm 2 and the back plate 3, and thus changing the capacitance value of the capacitor structure, thereby converting the sound signal into an electrical signal.

[0070] like Figure 1 and Figure 36 As shown, the backplate 3 is also provided with a plurality of sound holes 300. The plurality of sound holes 300 can be arranged opposite to the sound hole 100 to effectively reduce air damping, reduce sound wave transmission loss, and improve the sound-to-electric conversion efficiency of the chip.

[0071] However, in traditional MEMS packaging structures, the packaging shell of the MEMS packaging structure is usually adjacent to and opposite to the second diaphragm 202 of the chip, so that a coupled electric field is formed between the packaging shell and the second diaphragm 202. As a result, the electric field lines 6 of the coupled electric field can easily penetrate the sound hole 300 and act on the corresponding area of ​​the second diaphragm 202, forming additional parasitic capacitance, which in turn affects the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0072] Therefore, in this embodiment of the application, by setting at least one second through hole 2021 at the second diaphragm 202 corresponding to the sound hole 300, and then covering the second through hole 2021 with the second dielectric material 702, the second dielectric material 702 at the second diaphragm 202 corresponding to the sound hole 300 can effectively block the transmission of electric field lines 6, thereby achieving no effective electric field lines 6 at the sound hole 300, that is, further eliminating parasitic capacitance, thereby increasing the effective working capacitance ratio of the second diaphragm 202, and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0073] Furthermore, in traditional chips, multiple diaphragms 2 are typically provided. Adjacent diaphragms 2 are positioned close to each other and opposite each other, creating a coupled electric field between different diaphragms 2 within a small packaging space. This causes the electric field lines 6 of the coupled electric field to easily penetrate the sound hole 300 and act on the corresponding area of ​​the diaphragm 2 (e.g., Figure 33 As shown in the figure, additional parasitic capacitance is formed, which in turn affects the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0074] Therefore, since the diaphragm 2 includes a first diaphragm 201 and a second diaphragm 202, the first diaphragm 201 is connected to the substrate 1, the back plate 3 is connected to the side of the first diaphragm 201 facing away from the substrate 1, and the second diaphragm 202 is connected to the side of the back plate 3 facing away from the first diaphragm 201, in order to effectively eliminate parasitic capacitance, in this embodiment, at least one of the first diaphragm 201 corresponding to the sound hole 300 is provided with a first through hole 2011, thereby... Figure 2 As shown, the first dielectric material 701 covers the first through hole 2011, so that the first dielectric material 701 at the first diaphragm 201 corresponding to the sound hole 300 can effectively block the transmission of electric field lines 6, thus achieving no effective electric field lines 6 at the sound hole 300 (e.g., Figure 34 As shown in the figure, parasitic capacitance is effectively eliminated, which increases the proportion of effective working capacitance of the first diaphragm 201 and improves the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0075] In some embodiments, at least one of the second diaphragm 202 corresponding to the sound hole 300 is provided with a second through hole 2021, and the second through hole 2021 is covered by the second dielectric material 702, so that the second dielectric material 702 at the second diaphragm 202 corresponding to the sound hole 300 can effectively block the transmission of electric field lines 6, so that there are no effective electric field lines 6 at the sound hole 300, that is, the parasitic capacitance is effectively eliminated, thereby increasing the effective working capacitance ratio of the second diaphragm 202 and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0076] In some embodiments, a first through-hole 2011 is formed at at least one of the first diaphragms 201 corresponding to the sound hole 300, and a second through-hole 2021 is formed at at least one of the second diaphragms 202 corresponding to the sound hole 300. Then, the first through-hole 2011 is covered by the first dielectric material 701, and the second through-hole 2021 is covered by the second dielectric material 702. This allows the first dielectric material 701 at the first diaphragm 201 corresponding to the sound hole 300 to effectively block the transmission of the electric field line 6, and the second dielectric material 702 at the second diaphragm 202 corresponding to the sound hole 300 to effectively block the transmission of the electric field line 6. This achieves the absence of an effective electric field line 6 at the sound hole 300, effectively eliminating parasitic capacitance. This increases the effective working capacitance ratio of the first diaphragm 201 and the second diaphragm 202, thereby improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0077] In some embodiments, such as Figure 1 As shown, the chip forms a dual-diaphragm 2 structure by providing a first diaphragm 201 between the substrate 1 and the backplate 3, and providing a second diaphragm 202 on the side of the backplate 3 opposite to the first diaphragm 201.

[0078] Therefore, by using two independent diaphragms 2 in the dual-diaphragm 2 structure to capture sound details more accurately, the chip can have higher sensitivity, which makes it easier for the chip to capture a wider frequency range, resulting in a richer and more comprehensive sound performance.

[0079] In some embodiments, such as Figure 36 As shown, the chip also includes a third diaphragm 203; the backplate 3 includes a first backplate 301 and a second backplate 302, the first backplate 301 is disposed between the first diaphragm 201 and the second diaphragm 202, and the second backplate 302 is disposed between the second diaphragm 202 and the third diaphragm 203, so that the chip can form a three-diaphragm 2 structure.

[0080] Thus, by setting three independent diaphragms 2 in the three-diaphragm 2 structure, the application range of the chip is further expanded, enabling it to be more widely used in various electronic devices. Furthermore, based on the dielectric material 7 set in the three-diaphragm 2 structure, the generation of parasitic capacitance is effectively avoided, ensuring the sensitivity and signal-to-noise ratio of the three-diaphragm 2 structure.

[0081] Of course, in other embodiments, the chip may be provided with more diaphragms 2, which can be selected by those skilled in the art according to actual needs, and this application does not make specific limitations here.

[0082] In one embodiment, the first dielectric material 701 is disposed on at least a portion of the first diaphragm 201 on the side near the substrate 1; and / or, the second dielectric material 702 is disposed on at least a portion of the second diaphragm 202 on the side near the substrate 1.

[0083] Specifically, such as Figure 3 As shown, in this embodiment of the application, the first dielectric material 701 can be prepared before the first diaphragm 201 is formed. For example, the first dielectric material 701 can be formed first corresponding to the first through hole 2011 on the first diaphragm 201, and then the first diaphragm 201 can be prepared, so that the first dielectric material 701 can effectively cover the first through hole 2011 formed subsequently, without the need for an additional first through hole 2011 filling step.

[0084] Therefore, since the first dielectric material 701 is located on the substrate side of the first diaphragm 201, it can completely cover the first through hole 2011, thereby blocking the electric field line 6, avoiding the generation of parasitic capacitance, and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure. It can also play a supporting and stress compensation role in the fabrication process of the first diaphragm 201, reducing the warping or deformation of the first diaphragm 201 caused by the opening of the through hole, and further improving the flatness and mechanical stability of the first diaphragm 201.

[0085] In some embodiments, such as Figure 4 As shown, the second dielectric material 702 can also be prepared before the second diaphragm 202 is formed. For example, the second dielectric material 702 can be formed first corresponding to the second through hole 2021 on the second diaphragm 202, and then the second diaphragm 202 can be prepared, so that the second dielectric material 702 can effectively cover the second through hole 2021 formed subsequently, without the need for an additional second through hole 2021 filling step.

[0086] Therefore, since the second dielectric material 702 is located on the substrate side of the second diaphragm 202, it can completely cover the second through hole 2021, thereby blocking the electric field line 6, avoiding the generation of parasitic capacitance, and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure. It can also play a supporting and stress compensation role in the fabrication process of the second diaphragm 202, reducing the warping or deformation of the second diaphragm 202 caused by the opening of the through hole, and further improving the flatness and mechanical stability of the second diaphragm 202.

[0087] In some embodiments, such as Figure 5 As shown, the first dielectric material 701 is prepared before the formation of the first diaphragm 201, and the second dielectric material 702 is prepared before the formation of the second diaphragm 202. Therefore, based on the fact that the first dielectric material 701 is located on the substrate side of the first diaphragm 201 and the second dielectric material 702 is located on the substrate side of the second diaphragm 202, not only is the sensitivity and signal-to-noise ratio of the MEMS packaging structure effectively improved, but the flatness and mechanical stability of the first diaphragm 201 and the second diaphragm 202 are also improved.

[0088] In some embodiments, such as Figure 3 As shown, the first dielectric material 701 is disposed on a portion of the first diaphragm 201 on the side close to the substrate 1.

[0089] In some embodiments, the first dielectric material 701 is disposed on the side of the first diaphragm 201 near the substrate 1.

[0090] In some embodiments, such as Figure 4 As shown, the second dielectric material 702 is disposed on a portion of the second diaphragm 202 on the side close to the substrate 1.

[0091] In some embodiments, the second dielectric material 702 is disposed on the side of the second diaphragm 202 near the substrate 1.

[0092] In some embodiments, such as Figure 5 As shown, the first dielectric material 701 is disposed on a portion of the first diaphragm 201 near the substrate 1, and the second dielectric material 702 is disposed on a portion of the second diaphragm 202 near the substrate 1.

[0093] In some embodiments, the first dielectric material 701 is disposed on a portion of the first diaphragm 201 near the substrate 1, and the second dielectric material 702 is disposed on the second diaphragm 202 near the substrate 1.

[0094] In some embodiments, the first dielectric material 701 is disposed on the side of the first diaphragm 201 near the substrate 1, and the second dielectric material 702 is disposed on a portion of the second diaphragm 202 near the substrate 1.

[0095] In some embodiments, the first dielectric material 701 is disposed on the side of the first diaphragm 201 near the substrate 1, and the second dielectric material 702 is disposed on the side of the second diaphragm 202 near the substrate 1.

[0096] In one embodiment, the first dielectric material 701 is disposed on at least a portion of the first diaphragm 201 on the side opposite to the substrate 1, and a portion of the first dielectric material 701 fills the first through-hole 2011; and / or, the second dielectric material 702 is disposed on at least a portion of the second diaphragm 202 on the side opposite to the substrate 1, and a portion of the second dielectric material 702 fills the second through-hole 2021.

[0097] Specifically, such as Figure 6 As shown, in this embodiment of the application, the first dielectric material 701 can be prepared after the first diaphragm 201 is formed. For example, the first diaphragm 201 can be prepared first, and the first through hole 2011 can be opened on the first diaphragm 201. Then, the first dielectric material 701 can be formed corresponding to the first through hole 2011, such that the first dielectric material 701 is disposed on at least part of the first diaphragm 201 on the side away from the substrate 1, and part of the first dielectric material 701 is filled in the first through hole 2011.

[0098] Therefore, by filling and covering the first through hole 2011 with the first dielectric material 701, the electric field line 6 can be completely blocked, avoiding the generation of parasitic capacitance and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure. At the same time, the spatial gap inside the first through hole 2011 can be effectively eliminated, reducing sound wave reflection and interference, and improving the acoustic-electric conversion effect of the chip.

[0099] In some embodiments, such as Figure 7 As shown, the second dielectric material 702 can also be prepared after the second diaphragm 202 is formed. For example, the second diaphragm 202 can be prepared first, and the second through hole 2021 can be opened on the second diaphragm 202. Then, the second dielectric material 702 can be formed corresponding to the second through hole 2021, so that the second dielectric material 702 is disposed on at least part of the second diaphragm 202 on the side away from the substrate 1, and part of the second dielectric material 702 is filled in the second through hole 2021.

[0100] Therefore, by filling and covering the second via 2021 with the second dielectric material 702, the electric field line 6 can be completely blocked, avoiding the generation of parasitic capacitance and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure. At the same time, the spatial gap inside the second via 2021 can be effectively eliminated, reducing sound wave reflection and interference, and improving the acoustic-electric conversion effect of the chip.

[0101] In some embodiments, such as Figure 8 As shown, the first dielectric material 701 is prepared after the first diaphragm 201 is formed, and the second dielectric material 702 is prepared after the second diaphragm 202 is formed. Thus, the first through-hole 2011 is filled and covered by the first dielectric material 701, and the second through-hole 2021 is filled and covered by the second dielectric material 702. This not only effectively improves the sensitivity and signal-to-noise ratio of the MEMS packaging structure, but also enhances the acoustic-electric conversion effect of the chip.

[0102] In some embodiments, such as Figure 6 As shown, the first dielectric material 701 is disposed on the side of a portion of the first diaphragm 201 facing away from the substrate 1, and a portion of the first dielectric material 701 fills the first through hole 2011.

[0103] In some embodiments, the first dielectric material 701 is disposed on the side of the first diaphragm 201 opposite to the substrate 1, and a portion of the first dielectric material 701 fills the first through hole 2011.

[0104] In some embodiments, such as Figure 7 As shown, the second dielectric material 702 is disposed on the side of a portion of the second diaphragm 202 away from the substrate 1, and a portion of the second dielectric material 702 fills the second through hole 2021.

[0105] In some embodiments, the second dielectric material 702 is disposed on the side of the second diaphragm 202 away from the substrate 1, and a portion of the second dielectric material 702 fills the second through hole 2021.

[0106] In some embodiments, such as Figure 8 As shown, the first dielectric material 701 is disposed on a portion of the first diaphragm 201 on the side opposite to the substrate 1, and a portion of the first dielectric material 701 fills the first through hole 2011; at the same time, the second dielectric material 702 is disposed on a portion of the second diaphragm 202 on the side opposite to the substrate 1, and a portion of the second dielectric material 702 fills the second through hole 2021.

[0107] In some embodiments, the first dielectric material 701 is disposed on a portion of the first diaphragm 201 on the side opposite to the substrate 1, and a portion of the first dielectric material 701 fills the first through hole 2011; meanwhile, the second dielectric material 702 is disposed on the side of the second diaphragm 202 opposite to the substrate 1, and a portion of the second dielectric material 702 fills the second through hole 2021.

[0108] In some embodiments, the first dielectric material 701 is disposed on the side of the first diaphragm 201 away from the substrate 1, and a portion of the first dielectric material 701 fills the first through hole 2011; meanwhile, the second dielectric material 702 is disposed on the side of the second diaphragm 202 away from the substrate 1, and a portion of the second dielectric material 702 fills the second through hole 2021.

[0109] In some embodiments, the first dielectric material 701 is disposed on the side of the first diaphragm 201 away from the substrate 1, and a portion of the first dielectric material 701 fills the first through hole 2011; meanwhile, the second dielectric material 702 is disposed on the side of the second diaphragm 202 away from the substrate 1, and a portion of the second dielectric material 702 fills the second through hole 2021.

[0110] In one embodiment, the first dielectric material 701 includes a first sub-dielectric material 7011 and a second sub-dielectric material 7012. The first sub-dielectric material 7011 is disposed on at least a portion of the first diaphragm 201 on the side close to the substrate 1, and the second sub-dielectric material 7012 is disposed on at least a portion of the first diaphragm 201 on the side away from the substrate 1, and a portion of the second sub-dielectric material 7012 fills the first via 2011; and / or, the second dielectric material 702 includes a third sub-dielectric material 7021 and a fourth sub-dielectric material 7022. The third sub-dielectric material 7021 is disposed on at least a portion of the second diaphragm 202 on the side close to the substrate 1, and the fourth sub-dielectric material 7022 is disposed on at least a portion of the second diaphragm 202 on the side away from the substrate 1, and a portion of the fourth sub-dielectric material 7022 fills the second via 2021.

[0111] Specifically, such as Figure 9As shown, in this embodiment of the application, the first dielectric material 701 can be a double-layer dielectric material including the first sub-dielectric material 7011 and the second sub-dielectric material 7012, so as to simultaneously cover and fill the first through hole 2011 from both sides of the first diaphragm 201. Thus, not only are the electric field lines 6 on both sides of the first diaphragm 201 completely blocked, avoiding the generation of parasitic capacitance and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure, but the stress compensation of the first sub-dielectric material 7011 and the elimination of the air gap of the first through hole 2011 by the second sub-dielectric material 7012 are also taken into account, further optimizing the performance of the chip.

[0112] In some embodiments, such as Figure 10 As shown, the second dielectric material 702 can be a double-layer dielectric material including the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022, so as to simultaneously cover and fill the second through hole 2021 from both sides of the second diaphragm 202. Thus, it not only completely blocks the electric field lines 6 on both sides of the second diaphragm 202, avoiding the generation of parasitic capacitance and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure, but also takes into account the stress compensation of the third sub-dielectric material 7021 and the elimination of the air gap of the first through hole 2011 by the fourth sub-dielectric material 7022, further optimizing the performance of the chip.

[0113] In some embodiments, such as Figure 11 As shown, the first dielectric material 701 is a double-layer dielectric material including the first sub-dielectric material 7011 and the second sub-dielectric material 7012, and the second dielectric material 702 is a double-layer dielectric material including the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022. Therefore, since both the first dielectric material 701 and the second dielectric material 702 are double-layer dielectric materials, the sensitivity and signal-to-noise ratio of the MEMS packaging structure are further improved, and the performance of the chip is optimized.

[0114] In one embodiment, the first sub-dielectric material 7011 and the second sub-dielectric material 7012 are made of the same material, or the first sub-dielectric material 7011 and the second sub-dielectric material 7012 are made of different materials; and / or, the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 are made of the same material, or the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 are made of different materials.

[0115] Specifically, in this embodiment of the application, the first sub-dielectric material 7011 and the second sub-dielectric material 7012 can be made of the same material to simplify the fabrication process of the first diaphragm 201 and the first dielectric material 701 and reduce manufacturing costs; or, the first sub-dielectric material 7011 and the second sub-dielectric material 7012 can be made of different materials to allow for different dielectric materials 7 to be set for different electric field lines 6, or to perform stress compensation or gap filling for different requirements of the first diaphragm 201, thereby further optimizing the performance of the chip; at the same time, whether the first sub-dielectric material 7011 and the second sub-dielectric material 7012 are made of the same or different materials, it is also convenient to adapt to chips with different process conditions and performance requirements, thereby expanding the application range of the chip.

[0116] In some embodiments, the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 may be made of the same material to simplify the fabrication process of the second diaphragm 202 and the second dielectric material 702 and reduce manufacturing costs; alternatively, the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 may be made of different materials to allow for the setting of different dielectric materials 7 for different electric field lines 6, or to perform stress compensation or gap filling for different requirements of the second diaphragm 202, thereby further optimizing the performance of the chip; at the same time, whether the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 are made of the same or different materials also facilitates adaptation to chips with different process conditions and performance requirements, expanding the application range of the chip.

[0117] In some embodiments, the first sub-dielectric material 7011 and the second sub-dielectric material 7012 are made of the same material.

[0118] In some embodiments, the first sub-dielectric material 7011 and the second sub-dielectric material 7012 are made of different materials.

[0119] In some embodiments, the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 are made of the same material.

[0120] In some embodiments, the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 are made of different materials.

[0121] In some embodiments, the first sub-dielectric material 7011 and the second sub-dielectric material 7012 are made of the same material, and the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 are made of the same material.

[0122] In some embodiments, the first sub-dielectric material 7011 and the second sub-dielectric material 7012 are made of the same material, and the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 are made of different materials.

[0123] In some embodiments, the first sub-dielectric material 7011 and the second sub-dielectric material 7012 are made of different materials, and the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 are made of the same material.

[0124] In some embodiments, the first sub-dielectric material 7011 and the second sub-dielectric material 7012 are made of different materials, and the third sub-dielectric material 7021 and the fourth sub-dielectric material 7022 are made of different materials.

[0125] In one embodiment, the first sub-dielectric material 7011 covers the side of the first diaphragm 201 close to the substrate 1, and the second sub-dielectric material 7012 covers the side of the first diaphragm 201 away from the substrate 1; and / or, the third sub-dielectric material 7021 covers the side of the second diaphragm 202 close to the substrate 1, and the fourth sub-dielectric material 7022 covers the side of the second diaphragm 202 away from the substrate 1.

[0126] Specifically, such as Figure 12 As shown in the embodiment of this application, the side of the first diaphragm 201 closest to the substrate 1 can be completely covered by the first sub-dielectric material 7011, and the side of the first diaphragm 201 away from the substrate 1 can be completely covered by the second sub-dielectric material 7012. Therefore, not only can the electric field lines 6 on both sides of the first diaphragm 201 be completely blocked, avoiding the generation of parasitic capacitance and improving the sensitivity and signal-to-noise ratio of the chip, but also the sides of the first diaphragm 201 can be protected from corrosion and damage by the external environment, thereby improving the reliability and stability of the first diaphragm 201.

[0127] In some embodiments, such as Figure 13 As shown, the side of the second diaphragm 202 closest to the substrate 1 can be completely covered by the third sub-dielectric material 7021, and the side of the second diaphragm 202 away from the substrate 1 can be completely covered by the fourth sub-dielectric material 7022. Thus, not only can the electric field lines 6 on both sides of the second diaphragm 202 be completely blocked, avoiding the generation of parasitic capacitance and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure, but also the sides of the second diaphragm 202 can be protected from corrosion and damage by the external environment, thereby improving the reliability and stability of the first diaphragm 201.

[0128] In some embodiments, such as Figure 14As shown, the side of the first diaphragm 201 closest to the substrate 1 can be completely covered by the first sub-dielectric material 7011, and the side of the first diaphragm 201 away from the substrate 1 can be completely covered by the second sub-dielectric material 7012; and the side of the second diaphragm 202 closest to the substrate 1 can be completely covered by the third sub-dielectric material 7021, and the side of the second diaphragm 202 away from the substrate 1 can be completely covered by the fourth sub-dielectric material 7022; therefore, based on the full coverage of both sides of the first diaphragm 201 and both sides of the second diaphragm 202, the sensitivity and signal-to-noise ratio of the MEMS packaging structure, as well as the reliability and stability of the first diaphragm 201, are further improved.

[0129] In one embodiment, the diameter of the first through hole 2011 is the same as the diameter of the second through hole 2021, or the diameters of the first through hole 2011 and the second through hole 2021 are different.

[0130] Specifically, in this embodiment, the aperture of the first through-hole 2011 and the aperture of the second through-hole 2021 can be the same, so as to simplify the fabrication process of the first diaphragm 201 and the second diaphragm 202 and reduce manufacturing costs; or, the aperture of the first through-hole 2011 and the aperture of the second through-hole 2021 can be different, so as to flexibly set the dielectric material 7 according to the needs of different diaphragms and further optimize the performance of the chip; at the same time, the aperture of the first through-hole 2011 and the aperture of the second through-hole 2021 being the same or different also facilitates the adaptation to chips with different process conditions and performance requirements, and expands the application range of the chip.

[0131] In one embodiment, the first dielectric material 701 includes a fifth sub-dielectric material 7013 and a sixth sub-dielectric material 7014, the fifth sub-dielectric material 7013 filling the first through-hole 2011, and the sixth sub-dielectric material 7014 being arranged in a ring and sandwiched between the fifth sub-dielectric material 7013 and the first diaphragm 201; and / or, the second dielectric material 702 includes a seventh sub-dielectric material 7023 and an eighth sub-dielectric material 7024, the seventh sub-dielectric material 7023 filling the second through-hole 2021, and the eighth sub-dielectric material 7024 being arranged in a ring and sandwiched between the seventh sub-dielectric material 7023 and the second diaphragm 202.

[0132] Specifically, such as Figure 15 and Figure 16As shown, in this embodiment of the application, the first dielectric material 701 can also be a multi-region dielectric material including the fifth sub-dielectric material 7013 and the sixth sub-dielectric material 7014, so as to completely block the electric field line 6 through the fifth sub-dielectric material 7013, avoid the generation of parasitic capacitance, improve the sensitivity and signal-to-noise ratio of the MEMS packaging structure, and reinforce the edge of the first through hole 2011 through the sixth sub-dielectric material 7014, reduce stress concentration, and improve the mechanical strength and fatigue resistance of the first diaphragm 201.

[0133] In some embodiments, such as Figure 17 and Figure 18 As shown, the second dielectric material 702 can also be a multi-region dielectric material including the seventh sub-dielectric material 7023 and the eighth sub-dielectric material 7024, so as to completely block the electric field line 6 through the seventh sub-dielectric material 7023, avoid the generation of parasitic capacitance, improve the sensitivity and signal-to-noise ratio of the MEMS packaging structure, and reinforce the edge of the second through hole 2021 through the eighth sub-dielectric material 7024, reduce stress concentration, and improve the mechanical strength and fatigue resistance of the second diaphragm 202.

[0134] In some embodiments, such as Figure 19 As shown, the first dielectric material 701 is a multi-region dielectric material including the fifth sub-dielectric material 7013 and the sixth sub-dielectric material 7014, and the second dielectric material 702 is a multi-region dielectric material including the seventh sub-dielectric material 7023 and the eighth sub-dielectric material 7024. Therefore, based on the fact that both the first dielectric material 701 and the second dielectric material 702 are multi-region dielectric materials, the sensitivity and signal-to-noise ratio of the MEMS packaging structure are further improved, and the mechanical strength and fatigue resistance of the first diaphragm 201 and the second diaphragm 202 are enhanced.

[0135] In one embodiment, the central axis of the first dielectric material 701 is offset from the central axis of the sound hole 300, and at least a portion of the orthographic projection of the first dielectric material 701 toward the substrate 1 coincides with at least a portion of the orthographic projection of the sound hole 300 toward the substrate 1; and / or, the central axis of the second dielectric material 702 is offset from the central axis of the sound hole 300, and at least a portion of the orthographic projection of the second dielectric material 702 toward the substrate 1 coincides with at least a portion of the orthographic projection of the sound hole 300 toward the substrate 1.

[0136] Specifically, such as Figure 20As shown, in this embodiment of the application, the central axis of the first dielectric material 701 and the central axis of the sound hole 300 can be offset from each other. That is, the central axis of the first dielectric material 701 and the central axis of the sound hole 300 can not be completely aligned, but their projections still partially overlap. This not only ensures that the first dielectric material 701 can still cover the projection range of the sound hole 300, thereby eliminating parasitic capacitance, but also increases the effective capacitance area of ​​the first diaphragm 201, avoiding the situation where the electric field-free area of ​​the first diaphragm 201 is too large, resulting in poor capacitance value change of the capacitor structure.

[0137] In some embodiments, such as Figure 21 As shown, the central axis of the second dielectric material 702 and the central axis of the sound hole 300 can be offset from each other. That is, the central axis of the second dielectric material 702 and the central axis of the sound hole 300 can not be completely aligned, but their projections still partially overlap. This not only ensures that the second dielectric material 702 can still cover the projection range of the sound hole 300, thereby eliminating parasitic capacitance, but also increases the effective capacitance area of ​​the second diaphragm 202, avoiding the situation where the electric field-free area of ​​the second diaphragm 202 is too large, resulting in poor capacitance value change of the capacitor structure.

[0138] In some embodiments, such as Figure 22 As shown, the central axis of the first dielectric material 701 and the central axis of the second dielectric material 702 are both offset from the central axis of the sound hole 300, so as to further improve the sensitivity and signal-to-noise ratio of the MEMS packaging structure, and increase the effective capacitance area of ​​the first diaphragm 201 and the second diaphragm 202.

[0139] In one embodiment, the cross-sectional shape of the first through hole 2011 is circular, annular, or polygonal; and / or, the cross-sectional shape of the second through hole 2021 is circular, annular, or polygonal.

[0140] Specifically, the cross-sectional shape of the first through hole 2011 in this embodiment can be designed into various different shapes according to actual needs. For example, when the cross-sectional shape of the first through hole 2011 is circular, it can effectively ensure that the stress distribution of the first diaphragm 201 is uniform; or, as Figure 23 , Figure 24 and Figure 27As shown, when the cross-sectional shape of the first through hole 2011 is annular, the mechanical strength of the first diaphragm 201 can be effectively improved; or, when the cross-sectional shape of the first through hole 2011 is polygonal, the blocking effect of the electric field lines 6 can be optimized (for example, when the sound hole 300 is hexagonal, the first through hole 2011 can also be designed as hexagonal to achieve precise matching with the sound hole 300 and further improve the elimination effect of parasitic capacitance).

[0141] In some embodiments, the cross-sectional shape of the second through hole 2021 can be designed into various different shapes according to actual needs. For example, when the cross-sectional shape of the second through hole 2021 is circular, it can effectively ensure that the stress distribution of the second diaphragm 202 is uniform; or, as Figure 25 , Figure 26 and Figure 27 As shown, when the cross-sectional shape of the second through hole 2021 is annular, the mechanical strength of the second diaphragm 202 can be effectively improved; or, when the cross-sectional shape of the second through hole 2021 is polygonal, the blocking effect of the electric field lines 6 can be optimized (for example, when the sound hole 300 is hexagonal, the second through hole 2021 can also be designed as hexagonal to achieve precise matching with the sound hole 300 and further improve the elimination effect of parasitic capacitance).

[0142] In one embodiment, the first dielectric material 701 fills the first through-hole 2011, and / or the second dielectric material 702 fills the second through-hole 2021.

[0143] Specifically, such as Figure 28 As shown, in this embodiment of the application, the first dielectric material 701 can be directly filled into the first through hole 2011, so as to block the electric field line 6, avoid the generation of parasitic capacitance, improve the sensitivity and signal-to-noise ratio of the MEMS packaging structure, and also ensure the flatness of the first diaphragm 201.

[0144] In some embodiments, such as Figure 29 As shown, the second dielectric material 702 can be directly filled into the second through hole 2021 to block the electric field line 6, avoid the generation of parasitic capacitance, improve the sensitivity and signal-to-noise ratio of the MEMS packaging structure, and also ensure the flatness of the second diaphragm 202.

[0145] In some embodiments, such as Figure 30As shown, the first dielectric material 701 is filled in the first through-hole 2011, and the second dielectric material 702 is filled in the second through-hole 2021, so as to further improve the sensitivity and signal-to-noise ratio of the MEMS packaging structure, and ensure the flatness of the first diaphragm 201 and the second diaphragm 202.

[0146] In one embodiment, the first dielectric material 701 fills the first through-hole 2011, and a portion of the first diaphragm 201 covers the first dielectric material 701; and / or, the second dielectric material 702 fills the second through-hole 2021, and a portion of the second diaphragm 202 covers the second dielectric material 702.

[0147] Specifically, such as Figure 31 As shown, in this embodiment of the application, after the first dielectric material 701 is filled into the first through hole 2011, the first diaphragm 201 can also cover part of the first dielectric material 701, so that the two ends of the first dielectric material 701 are sandwiched between the first diaphragm 201. This not only blocks the electric field line 6, avoids the generation of parasitic capacitance, and improves the sensitivity and signal-to-noise ratio of the MEMS packaging structure, but also ensures the mechanical stability of the first dielectric material 701.

[0148] In some embodiments, such as Figure 32 As shown, after the second dielectric material 702 is filled into the second through hole 2021, the second diaphragm 202 can also cover part of the second dielectric material 702, so that the two ends of the second dielectric material 702 are sandwiched between the second diaphragm 202. This not only blocks the electric field line 6, avoids the generation of parasitic capacitance, and improves the sensitivity and signal-to-noise ratio of the MEMS packaging structure, but also ensures the mechanical stability of the second dielectric material 702.

[0149] In some embodiments, such as Figure 33 As shown, the two ends of the first dielectric material 701 are sandwiched between the first diaphragm 201, and the two ends of the second dielectric material 702 are sandwiched between the second diaphragm 202, so as to further improve the sensitivity and signal-to-noise ratio of the MEMS packaging structure, and ensure the mechanical stability of the first dielectric material 701 and the second dielectric material 702.

[0150] In one embodiment, the dielectric material 7 is made of at least one of silicon nitride and silicon carbide.

[0151] Specifically, the dielectric material 7 described in this application embodiment can be made of silicon nitride or silicon carbide, or a composite material of silicon nitride and silicon carbide, in order to effectively eliminate parasitic capacitance and improve the mechanical stability of the diaphragm 2 and the reliability of the chip.

[0152] In one embodiment, the backplate 3 is a single-layer backplate or a multi-layer backplate.

[0153] Specifically, such as Figure 1 and Figure 36 As shown, the backplate 3 described in this application embodiment can be a single-layer backplate, such as a single-layer conductive backplate 3; or the backplate 3 can also be a multi-layer backplate, such as a three-layer structure of "insulating layer-conductive layer-insulating layer".

[0154] Therefore, by limiting the backplate 3 to a single-layer backplate or a multi-layer backplate, not only can the applicability of the chip be effectively expanded, but it is also convenient to further optimize the acoustic damping performance of the backplate 3 according to the actual application requirements of the chip.

[0155] In some embodiments, the three-layer structure of "insulating layer-conductive layer-insulating layer" can not only effectively prevent short circuits when the diaphragm 2 contacts the back plate 3, but also facilitate the synergistic effect of multiple sound holes to further reduce sound wave transmission loss and block the transmission of electric field lines 6 between each layer and the diaphragm 2, thereby better cooperating with the differentiated regions of the diaphragm 2 to eliminate parasitic capacitance and achieve all-round parasitic capacitance elimination.

[0156] In one embodiment, the chip further includes an insulating layer 5, and multiple insulating layers 5 are provided; the insulating layer 5 is provided between the substrate 1 and the first diaphragm 201, between the first diaphragm 201 and the backplate 3, and between the backplate 3 and the second diaphragm 202.

[0157] Specifically, such as Figure 1 As shown in the embodiment of this application, the insulating layer 5 can be disposed between the substrate 1 and the first diaphragm 201, between the first diaphragm 201 and the backplate 3, and between the backplate 3 and the second diaphragm 202 to achieve electrical insulation, prevent short circuits between the substrate 1, the first diaphragm 201, the backplate 3 and the second diaphragm 202, and improve the reliability and stability of the chip.

[0158] Meanwhile, the insulating layer 5 can also adjust the initial capacitance distance between the substrate 1, the first diaphragm 201, the backplate 3 and the second diaphragm 202, thereby not only optimizing the acoustic-electric conversion performance, but also facilitating the coordination with the differentiated regions of the diaphragm 2 to further eliminate parasitic capacitance and improve the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0159] According to another embodiment of this application, a MEMS packaging structure is provided, the MEMS packaging structure including a packaging shell and the chip of this application, the packaging shell forming a receiving cavity, and the chip being disposed in the receiving cavity.

[0160] Specifically, the MEMS packaging structure described in this application embodiment includes a packaging shell and a chip. The packaging shell forms a receiving cavity, and the chip is disposed in the receiving cavity. Thus, since the diaphragm 2 is provided with dielectric material 7 at the position corresponding to the sound hole 300, the dielectric material 7 can effectively block the transmission of electric field lines 6, so that there are no effective electric field lines 6 at the sound hole 300, that is, the parasitic capacitance is effectively eliminated, thereby increasing the effective working capacitance ratio of the diaphragm 2 and improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0161] Of course, in other installation environments of the chip, as long as there is an external conductor that can generate parasitic capacitance between the chip's diaphragm 2, the above-mentioned settings in this application embodiment can effectively eliminate parasitic capacitance, thereby improving the sensitivity and signal-to-noise ratio of the MEMS packaging structure.

[0162] According to another embodiment of this application, an electronic device is provided, the electronic device including the chip of this application, or the electronic device including the MEMS packaging structure of this application.

[0163] The above embodiments mainly describe the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. For the sake of brevity, they will not be elaborated here.

[0164] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.

Claims

1. A chip disposed within a cavity formed by the encapsulation shell of a MEMS packaging structure, characterized in that, include: The substrate (1) has an acoustic hole (100). A diaphragm (2) and a back plate (3) are provided. The diaphragm (2) includes a first diaphragm (201) and a second diaphragm (202). The first diaphragm (201) is connected to the substrate (1). The back plate (3) is connected to the side of the first diaphragm (201) away from the substrate (1). The second diaphragm (202) is connected to the side of the back plate (3) away from the first diaphragm (201). The back plate (3) has a plurality of sound holes (300). The plurality of sound holes (300) are arranged opposite to the sound holes (100). A first through hole (2011) is provided at least one of the sound holes (300) corresponding to the first diaphragm (201), and / or a second through hole (2021) is provided at at least one of the sound holes (300) corresponding to the second diaphragm (202). The dielectric material (7) includes a first dielectric material (701) and a second dielectric material (702), wherein the first dielectric material (701) covers the first through hole (2011) and / or the second dielectric material (702) covers the second through hole (2021).

2. The chip according to claim 1, characterized in that, The first dielectric material (701) is disposed on at least a portion of the first diaphragm (201) on the side close to the substrate (1); And / or, the second dielectric material (702) is disposed on at least a portion of the second diaphragm (202) on the side close to the substrate (1).

3. The chip according to claim 1, characterized in that, The first dielectric material (701) is disposed on at least a portion of the first diaphragm (201) on the side opposite to the substrate (1), and a portion of the first dielectric material (701) is filled in the first through hole (2011); And / or, the second dielectric material (702) is disposed on at least a portion of the second diaphragm (202) on the side opposite to the substrate (1), and a portion of the second dielectric material (702) is filled in the second through hole (2021).

4. The chip according to claim 1, characterized in that, The first dielectric material (701) includes a first sub-dielectric material (7011) and a second sub-dielectric material (7012). The first sub-dielectric material (7011) is disposed on at least a portion of the first diaphragm (201) on the side close to the substrate (1), and the second sub-dielectric material (7012) is disposed on at least a portion of the first diaphragm (201) on the side away from the substrate (1). A portion of the second sub-dielectric material (7012) is filled in the first through hole (2011). And / or, the second dielectric material (702) includes a third sub-dielectric material (7021) and a fourth sub-dielectric material (7022), the third sub-dielectric material (7021) being disposed on at least a portion of the second diaphragm (202) on the side close to the substrate (1), the fourth sub-dielectric material (7022) being disposed on at least a portion of the second diaphragm (202) on the side away from the substrate (1), and a portion of the fourth sub-dielectric material (7022) filling the second via (2021).

5. The chip according to claim 4, characterized in that, The first sub-dielectric material (7011) and the second sub-dielectric material (7012) are made of the same material, or the first sub-dielectric material (7011) and the second sub-dielectric material (7012) are made of different materials; And / or, the third sub-dielectric material (7021) and the fourth sub-dielectric material (7022) are made of the same material, or the third sub-dielectric material (7021) and the fourth sub-dielectric material (7022) are made of different materials.

6. The chip according to claim 4, characterized in that, The first sub-dielectric material (7011) covers the side of the first diaphragm (201) close to the substrate (1), and the second sub-dielectric material (7012) covers the side of the first diaphragm (201) away from the substrate (1); And / or, the third sub-dielectric material (7021) covers the side of the second diaphragm (202) close to the substrate (1), and the fourth sub-dielectric material (7022) covers the side of the second diaphragm (202) away from the substrate (1).

7. The chip according to any one of claims 4-6, characterized in that, The diameter of the first through hole (2011) is the same as the diameter of the second through hole (2021), or the diameter of the first through hole (2011) is different from the diameter of the second through hole (2021).

8. The chip according to claim 1, characterized in that, The first dielectric material (701) includes a fifth sub-dielectric material (7013) and a sixth sub-dielectric material (7014). The fifth sub-dielectric material (7013) fills the first through hole (2011), and the sixth sub-dielectric material (7014) is arranged in a ring and sandwiched between the fifth sub-dielectric material (7013) and the first diaphragm (201). And / or, the second dielectric material (702) includes a seventh sub-dielectric material (7023) and an eighth sub-dielectric material (7024), the seventh sub-dielectric material (7023) filling the second through hole (2021), and the eighth sub-dielectric material (7024) being arranged in a ring and sandwiched between the seventh sub-dielectric material (7023) and the second diaphragm (202).

9. The chip according to claim 1, characterized in that, The central axis of the first dielectric material (701) is offset from the central axis of the sound hole (300), and at least a portion of the orthographic projection of the first dielectric material (701) toward the substrate (1) coincides with at least a portion of the orthographic projection of the sound hole (300) toward the substrate (1). And / or, the central axis of the second dielectric material (702) is offset from the central axis of the sound hole (300), and at least a portion of the orthographic projection of the second dielectric material (702) toward the substrate (1) coincides with at least a portion of the orthographic projection of the sound hole (300) toward the substrate (1).

10. The chip according to claim 1, characterized in that, The cross-sectional shape of the first through hole (2011) is circular, annular, or polygonal; And / or, the cross-sectional shape of the second through hole (2021) is circular, annular or polygonal.

11. The chip according to claim 1, characterized in that, The first dielectric material (701) is filled in the first through hole (2011), and / or the second dielectric material (702) is filled in the second through hole (2021).

12. The chip according to claim 1, characterized in that, The first dielectric material (701) fills the first through hole (2011), and a portion of the first diaphragm (201) covers the first dielectric material (701). And / or, the second dielectric material (702) fills the second through hole (2021), and a portion of the second diaphragm (202) covers the second dielectric material (702).

13. The chip according to claim 1, characterized in that, The dielectric material (7) is made of at least one of silicon nitride and silicon carbide.

14. A MEMS packaging structure, characterized in that, It includes a package housing and a chip as described in any one of claims 1-13, wherein the package housing forms a receiving cavity and the chip is disposed in the receiving cavity.

15. An electronic device, characterized in that, It includes the chip as described in any one of claims 1-13, or the MEMS packaging structure as described in claim 14.

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