A voltage sag fast detection method and system based on voltage envelope dynamic identification

Abstract

The application discloses a voltage sag fast detection method and system based on voltage envelope dynamic identification, and the method comprises the following steps: synchronously sampling and preprocessing three-phase phase voltage of a power grid, performing zero sequence component separation processing, and obtaining zero sequence three-phase voltage signals; inputting a low-bandwidth inertia phase-locked loop to obtain an instantaneous phase angle signal of a power grid fundamental positive sequence component; generating three-phase reference phases, and reconstructing three-phase voltage envelopes dynamically following the phase change of the power grid fundamental; detecting voltage transient events and outputting a global voltage transient event trigger signal; performing voltage recovery detection based on an adaptive recovery reference value and outputting a voltage recovery flag; and generating a voltage sag flag bit to indicate whether the current is in a voltage sag state or not. The application improves the detection accuracy under unbalanced and distorted conditions, and provides a reliable and efficient detection scheme for voltage sag treatment equipment.

Description

Technical Field

[0001] This invention belongs to the field of voltage sag detection technology, and relates to a rapid voltage sag detection method and system based on dynamic identification of voltage envelope. Background Technology

[0002] Voltage sag, also known as voltage dip, refers to the phenomenon where the voltage amplitude at a point in a power system drops to 10%–90% of its rated value within a short period (typically 0.5 cycles to 1 minute). It is one of the main disturbances affecting power quality for electricity users. Voltage sags can not only cause malfunctions or shutdowns in sensitive industrial equipment (such as programmable logic controllers, variable frequency drives, and computer systems), but can also lead to production interruptions, data loss, and even equipment damage, resulting in significant economic losses. Therefore, quickly and accurately detecting the start time, amplitude, duration, and phase transition characteristics of voltage sags is of great importance for fault diagnosis, compensation device control, and power quality assessment.

[0003] Among voltage sag detection methods, the most direct and traditional methods are the RMS method and the voltage deficit method. The RMS method calculates the root mean square (RMS) value of the voltage signal within a sliding time window (usually half a power frequency cycle or one cycle) and compares it to a set threshold to determine if a voltage sag has occurred. Because the RMS method requires a time window to reflect changes in the RMS value, it suffers from significant detection delay. The voltage deficit method in power systems calculates the difference between the actual voltage and the ideal rated voltage on the time axis to quickly detect voltage sags. However, the voltage deficit method cannot handle noise and harmonic issues, especially at zero-crossing points. Based on these two fundamental traditional methods, numerous improved detection algorithms have been developed to address noise or harmonic problems, timeliness issues, and the practicality of sag types; however, most methods have specific applicable environments.

[0004] Existing voltage sag detection methods can be summarized as follows: traditional time-domain RMS algorithms, voltage defect methods, dq transform methods, peak voltage detection methods, frequency-domain wavelet transform methods, Fourier transform methods, and improved schemes combining these methods with deep learning and neural network technologies. Furthermore, voltage signals in actual power grids are often subject to distortion and noise interference, thus requiring the use of analog or digital filters (such as traditional Butterworth low-pass filters) in detection methods. However, the time delay characteristics of these filters also hinder real-time monitoring of voltage sags. Specifically, RMS algorithms require at least half a cycle of data window, resulting in a delay of at least 10ms, which fails to meet real-time requirements. Voltage defect methods achieve rapid voltage sag detection based on the time-domain difference between the actual voltage and the rated voltage; however, this mechanism fails at zero-crossing points because the voltage difference approaches zero, and it cannot effectively suppress noise and harmonic interference, thus exhibiting insufficient reliability in noisy environments, harmonic pollution, and voltage zero-crossing regions. The dq transform method extracts amplitude information by transforming the three-phase voltage to a rotating coordinate system, which can quickly detect symmetrical sags. However, the detection accuracy drops significantly when there are asymmetrical sags (such as single-phase or two-phase sags) or large phase jumps. For single-phase faults, a common strategy is to introduce an angular delay on the original signal (such as delaying by 90° and then using αβ-dq transform, or delaying by 60° to construct a virtual three-phase voltage). However, this delay processing is essentially an artificial increase in detection delay, which inevitably affects real-time performance. Peak voltage detection methods are susceptible to harmonics, noise, and voltage fluctuations, resulting in a high false positive rate. Frequency domain methods such as wavelet transform have good time-frequency localization characteristics and can accurately capture the start and end times of sags. However, the selection of wavelet basis functions depends on experience and has a large computational load, making it difficult to apply in real time in embedded systems. The Fourier transform method is limited by a fixed window length and cannot simultaneously achieve both time and frequency resolution. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a rapid voltage sag detection method and system based on dynamic voltage envelope identification. By leveraging the phase adaptability of the dynamic envelope, anti-jitter and anti-interference mechanisms, and the adaptive calibration capability of the reference, the detection accuracy under unbalanced and distorted operating conditions is improved. The entire algorithm system is simple, resource-friendly for embedded systems, and features low latency, harmonic resistance, and full sag compatibility, providing a reliable and efficient detection solution for voltage sag mitigation equipment.

[0006] The present invention adopts the following technical solution.

[0007] A rapid voltage sag detection method based on dynamic voltage envelope identification includes: Step 1: Synchronously sample and preprocess the three-phase voltages of the power grid to obtain the per-unit value of each phase voltage, and perform zero-sequence component separation processing on the per-unit value of each phase voltage to obtain the zero-sequence three-phase voltage signal. Step 2: Input the zero-sequence three-phase voltage signal into a low-bandwidth inertial phase-locked loop for fundamental phase robust tracking to obtain a continuous and smooth instantaneous phase angle signal of the fundamental positive-sequence component of the power grid. Step 3: Generate a three-phase reference phase based on the instantaneous phase angle signal, and reconstruct the three-phase voltage envelope that dynamically follows the phase change of the grid fundamental wave based on the three-phase reference phase; Step 4: Detect voltage transient events based on the per-unit values ​​of each phase voltage and the three-phase voltage envelope, and output a global voltage transient event trigger signal; Step 5: Perform voltage recovery detection based on the adaptive recovery reference value on the effective value of the three-phase voltage and output a voltage recovery flag; Step 6: Generate a voltage sag flag bit based on the global voltage transient event trigger signal and the voltage recovery flag to indicate whether the current state is a voltage sag.

[0008] Preferably, step 1 specifically includes: Step 1.1: Synchronously sample and convert the three-phase phase voltages of the power grid to analog-to-digital conversion to obtain the original voltage sampling sequence; Step 1.2: Perform a per-unit transformation on the original voltage sampling sequence based on the rated voltage amplitude to obtain the per-unit value of each phase voltage; Step 1.3: Perform zero-sequence component separation processing on the per-unit values ​​of each phase voltage to obtain the zero-sequence three-phase voltage signal.

[0009] Preferably, the low-bandwidth inertial phase-locked loop described in step 2 employs an inertial topology with a low cutoff frequency to dynamically suppress disturbance components and maintain the stability of the phase-locking process. The parameter tuning of the low-bandwidth inertial phase-locked loop satisfies: When the grid voltage experiences a step sag, the instantaneous phase angle signal The change in the fundamental frequency and its corresponding frequency within half a power frequency cycle approaches zero.

[0010] Preferably, step 3 specifically includes: Step 3.1: Based on the instantaneous phase angle signal as the reference phase of phase A, perform fixed phase shift rotation transformations of 120° lag and 120° lead on the reference phase of phase A to generate the reference phases of phases B and C respectively. Then, feed the reference phase sequences of phases A, B, and C into the normalized cosine mapping function. After unit amplitude normalization, obtain the per-unit waveform sequences of the ideal fundamental voltage of phases A, B, and C respectively. , , ; Step 3.2: Apply a symmetrical amplitude deviation threshold to the ideal fundamental voltage per-unit waveform sequence to form the upper and lower boundaries of the three-phase voltage envelope that dynamically follow the phase change of the grid fundamental wave.

[0011] Preferably, step 4 specifically includes: Step 4.1: Compare the per-unit voltage values ​​of each phase with the upper and lower boundaries of the three-phase voltage envelope point by point. When N consecutive per-unit voltage values ​​of any phase voltage exceed the upper or lower boundary of the corresponding phase voltage envelope, it is determined that a voltage sag event has occurred in that phase, and a single-phase event flag is generated. Step 4.2: Perform logical OR arbitration on the three single-phase event flags corresponding to phases A, B, and C. If the single-phase event flag bit of any one of phases A, B, and C is at an active level, then output a global voltage transient event trigger signal.

[0012] Preferably, the value of N ranges from 3 to 10.

[0013] Preferably, step 5 specifically includes: Step 5.1: Perform full-cycle sliding window RMS recursive calculation on the per-unit value of each phase voltage to obtain the effective value of the three-phase voltage; Step 5.2: Calculate the adaptive reference voltage online based on recursive exponential smoothing and upper and lower limit clamping; Step 5.3: Calculate the phase-by-phase deviation between the effective value of each phase voltage and the adaptive reference voltage to obtain the corresponding deviation. When the absolute value of each corresponding deviation is lower than the preset threshold at the same time, the grid voltage is determined to be restored after anti-jitter delay, and a voltage recovery flag is output.

[0014] Preferably, the adaptive reference voltage in step 5.2 is calculated online using the following recursive exponential smoothing formula:

[0015] And introduce upper and lower clamps: ; in This represents the average value of the effective values ​​of the three-phase phase voltages, where n represents the sampling time. α This is a smoothing factor.

[0016] Preferably, in step 6, logical judgment and state locking are performed based on the global voltage transient event trigger signal and the voltage recovery flag to generate a binary voltage sag flag. The binary voltage sag flag is used to indicate whether the current voltage is in a sag state. When the binary voltage sag flag is "1", it indicates that the current voltage is in a sag state, and when it is "0", it indicates that the voltage is normal or has recovered.

[0017] A rapid voltage sag detection system based on dynamic voltage envelope identification includes: The voltage sampling and processing module is used to synchronously sample and preprocess the three-phase voltages of the power grid to obtain the per-unit value of each phase voltage, and to perform zero-sequence component separation processing on the per-unit value of each phase voltage to obtain the zero-sequence three-phase voltage signal. The fundamental phase tracking module is used to input the zero-sequence three-phase voltage signal into a low-bandwidth inertial phase-locked loop for fundamental phase robust tracking, so as to obtain a continuous and smooth instantaneous phase angle signal of the fundamental positive-sequence component of the power grid. The voltage envelope reconstruction module is used to generate a three-phase reference phase based on the instantaneous phase angle signal, and to reconstruct a three-phase voltage envelope that dynamically follows the change of the fundamental phase of the power grid based on the three-phase reference phase. The voltage transient event detection module is used to detect voltage transient events based on the per-unit values ​​of each phase voltage and the three-phase voltage envelope, and output a global voltage transient event trigger signal. The voltage recovery detection module is used to perform voltage recovery detection on the effective value of the three-phase voltage based on an adaptive recovery reference value and output a voltage recovery flag. The voltage sag flag module is used to generate a voltage sag flag bit based on the global voltage transient event trigger signal and the voltage recovery flag, indicating whether the current state is a voltage sag.

[0018] Compared with the prior art, the beneficial effects of the present invention include at least the following: When any N consecutive per-unit values ​​of the phase voltage exceed the upper or lower boundary of the corresponding phase voltage envelope, the present invention determines that a voltage sag event has occurred in that phase. The voltage sag event can be quickly determined with only a few hundred microseconds of anti-jitter delay, which has low latency and strong real-time performance. This invention involves no complex calculations, has a simple algorithm structure, is easy to implement, does not require excessive embedded resources, effectively saves interrupt handling time, and is resource-friendly for embedded controller systems. This invention inputs the zero-sequence three-phase voltage signal into a low-bandwidth inertial phase-locked loop for robust tracking of the fundamental phase, obtaining a continuous and smooth instantaneous phase angle signal of the positive-sequence component of the power grid fundamental wave; generates a three-phase reference phase based on the instantaneous phase angle signal, and reconstructs a three-phase voltage envelope that dynamically follows the changes in the fundamental phase of the power grid based on the three-phase reference phase. This invention can prevent false detection of power dips when the harmonic content of the power grid meets the power quality standards, and has anti-harmonic capability. This invention provides three-phase independent detection, which performs logical OR arbitration on the three single-phase event flags corresponding to phases A, B, and C, and calculates the phase-by-phase deviation between the effective value of each phase voltage and the adaptive reference voltage. It can fully adapt to various sag types. For asymmetrical faults such as single-phase ground faults, two-phase short-circuit faults, and two-phase ground faults, the detection speed and accuracy can reach the same level as three-phase symmetrical faults. Attached Figure Description

[0019] Figure 1 This is the main flowchart of a rapid voltage sag detection method based on dynamic identification of voltage envelope.

[0020] Figure 2 Here is a flowchart of a phase-locked loop (PLL). Figure 3 A comparison of slow PLL output and fast PLL output when a voltage dip occurs.

[0021] Figure 4 The flowchart shows the generation of phase voltage upper and lower limits and the detection of exceeding these limits.

[0022] Figure 5 This is a flowchart of the power grid voltage restoration process.

[0023] Figure 6 This is a real-time tracking diagram of the phase voltage waveforms when the grid voltage contains harmonics with a total harmonic distortion rate of 5%.

[0024] Figure 7 The testing time for actual treatment equipment under single-phase short-circuit asymmetrical fault conditions.

[0025] Figure 8 The actual testing time of the treatment equipment under three-phase symmetrical fault conditions.

[0026] Figure 9 The testing time for the actual treatment equipment under two-phase asymmetric fault conditions. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0028] Embodiment 1 of this invention provides a fast voltage sag identification method based on adaptive amplitude boundary over-limit detection. It employs a low-bandwidth inertial phase-locked loop to generate a three-phase reference waveform synchronized with the fundamental wave, and uses a symmetrical deviation threshold to construct a dynamic voltage envelope as the over-limit criterion. By comparing sampled values ​​point-by-point with the dynamic envelope, combined with a time-domain anti-jitter mechanism for continuous sampling point over-limit confirmation, a transient event flag is generated. In recovery detection, an adaptive reference voltage is obtained based on recursive exponential smoothing and upper and lower limit clamping. The recovery criterion is based on independent comparison of the three-phase effective values ​​while simultaneously satisfying the deviation threshold. Finally, an SR trigger integrates the transient flag and the recovery flag, outputting a binary sag flag of the locked state. Figure 1As shown, the main steps of the method are as follows: Step 1: Synchronously sample and preprocess the three-phase voltages of the power grid to obtain the per-unit value of each phase voltage, and perform zero-sequence component separation processing on the per-unit value of each phase voltage to obtain the zero-sequence three-phase voltage signal. More preferably, the three-phase voltage signal preprocessing and normalization transformation steps are as follows: Step 1.1: Synchronously sample and convert the three-phase phase voltages of the power grid to analog-to-digital conversion to obtain the original voltage sampling sequence; Specifically, the three-phase phase voltage of the power grid is synchronously sampled through a voltage transformer (PT), and then digitally converted by a high-speed analog-to-digital converter (ADC) to obtain the original voltage sampling sequence. Step 1.2: Perform a per-unit transformation on the original voltage sampling sequence based on the rated voltage amplitude to obtain the per-unit value of each phase voltage; Specifically, a per-unit transformation based on the rated voltage amplitude is adopted to convert the voltage of each phase into a per-unit value (pu), thereby eliminating the influence of different voltage levels on the test results and achieving standardized comparison. Step 1.3: Perform zero-sequence component separation processing on the per-unit values ​​of each phase voltage to obtain the zero-sequence three-phase voltage signal.

[0029] Specifically, the normalized three-phase voltage signal is subjected to zero-sequence component separation processing. After filtering out the zero-sequence component, the zero-sequence three-phase voltage is obtained. The zero-sequence three-phase voltage is used as the input reference for the subsequent low-bandwidth inertial fast phase-locked loop algorithm to complete the normalization and decoupling preprocessing of voltage sag characteristics.

[0030] Step 2: Input the zero-sequence three-phase voltage signal into a low-bandwidth inertial phase-locked loop for fundamental phase robust tracking to obtain a continuous and smooth instantaneous phase angle signal of the fundamental positive-sequence component of the power grid. More preferably, the fundamental phase robust tracking steps based on a low-bandwidth inertial phase-locked loop are as follows: The voltage signal, after zero-sequence component filtering, is input to the fundamental phase robust tracking module, which is based on a low-bandwidth inertial phase-locked loop. Its signal processing architecture and phase-locked loop process are as follows: Figure 2 As shown.

[0031] The low-bandwidth phase-locked loop adopts an inertial topology with a low cutoff frequency, which has a significantly reduced closed-loop bandwidth. It can dynamically suppress rapidly changing disturbance components such as voltage sag and harmonic distortion, thereby maintaining the transient stability of the phase-locking process under strong disturbance conditions.

[0032] The phase-locked loop outputs a continuous and smooth reference signal. This signal accurately extracts the steady-state frequency and instantaneous phase information of the fundamental positive sequence component of the power grid, which serves as the basis for subsequent dynamic voltage envelope waveform reconstruction.

[0033] like Figure 2 As shown, the low-cutoff-frequency inertial topology is a phase-locked loop structure based on a synchronous rotating coordinate system. It uses a low cutoff-frequency parameter to suppress the influence of voltage sags on the output results. It obtains the instantaneous phase angle signal of the continuous and smooth positive-sequence component of the grid fundamental wave based on the zero-sequence three-phase voltage signal. The process is as follows: the zero-sequence three-phase voltage signal undergoes coordinate transformation, and phase-locking is performed in a synchronous rotating coordinate system to obtain the instantaneous phase angle of the fundamental positive-sequence component. This phase-locked structure uses a low cutoff frequency parameter, and the resulting signal... It has a continuous and smooth characteristic to suppress interference at the moment when voltage dips occur.

[0034] By introducing the low-bandwidth inertial phase-locked loop, a highly robust tracking mechanism for the fundamental phase of the power grid is established, effectively avoiding misjudgments and malfunctions caused by instantaneous value jumps, phase jumps, or frequency shifts during voltage dips in traditional fast phase-locked loops.

[0035] The parameter tuning of the low-bandwidth inertial phase-locked loop follows the following constraints: When the grid voltage experiences a step sag, it is necessary to ensure that the changes in the fundamental frequency and phase angle within half a power frequency cycle are close to zero in order to maintain the phase consistency between the output reference waveform and the ideal fundamental frequency when the sag occurs.

[0036] This method is physically equivalent to embedding a phase inertial element in the voltage sag disturbance channel, which ensures the physical continuity of the reference signal during the disturbance process.

[0037] Figure 3 The diagram shows a comparison of the slow PLL output (red) and the fast PLL output (blue) during a voltage sag, illustrating the measured output waveform of the low-bandwidth inertial phase-locked loop (PLL) under typical voltage sag conditions. Experimental results demonstrate that, compared to the high-bandwidth fast PLL, the slow PLL, with its low loop bandwidth and high damping ratio, exhibits no visible phase abruptness or amplitude distortion in its output signal waveform during the transient moment of a sag event. This characteristic confirms that the PLL structure constructed in this scheme can effectively isolate the impact of disturbances on the phase-locking process under non-ideal power grid conditions, possessing robust locking capability and high-fidelity tracking performance as a voltage reference phase, providing a stable time-frequency reference for subsequent threshold value tuning.

[0038] Step 3: Generate a three-phase reference phase based on the instantaneous phase angle signal, and reconstruct the three-phase voltage envelope that dynamically follows the phase change of the grid fundamental wave based on the three-phase reference phase; More preferably, the dynamic voltage envelope reconstruction step is as follows: The dynamic voltage envelope reconstruction module (phase voltage upper and lower limit generation and cross-limit detection process as follows) Figure 4 (As shown) Receives the continuous smooth reference signal output by the fundamental phase robust tracking module, and constructs a three-phase dynamic voltage envelope based on the fundamental positive sequence phase information it carries.

[0039] The core of this module lies in: By utilizing the phase inertia holding characteristic of the low-bandwidth inertial phase-locked loop, the relative position of the threshold boundary and the ideal fundamental waveform is kept constant during voltage sag events, thereby avoiding detection offset caused by phase abrupt changes or frequency shifts due to voltage sags. Specifically, this includes the following sub-steps: Step 3.1: Homogeneous reconstruction and per-unit mapping of the three-phase reference phases: The fundamental instantaneous phase angle output by the low-bandwidth inertial phase-locked loop As the reference phase of phase A, a fixed phase shift rotation transformation with a lag of 120° and a lead of 120° is applied to the reference phase of phase A to generate the reference phases of phase B and phase C.

[0040] The aforementioned co-source reconstruction mechanism ensures that the three-phase reference phases strictly share the same phase disturbance propagation path, eliminating phase inconsistencies introduced by independent phase-locking or frequency drift.

[0041] The reconstructed three-phase reference phase sequences are fed into the normalized cosine mapping function (cosines are calculated for each of the three phases), and after unit amplitude normalization, the ideal fundamental voltage per-unit waveform sequences of phases A, B, and C are obtained. , , .

[0042] This waveform sequence strictly tracks the phase trajectory of the phase-locked loop output, possessing characteristics of unit amplitude, continuous smoothness, and no phase jump, thus forming an ideal reference substrate for the dynamic voltage envelope boundary.

[0043] Step 3.2: Apply a symmetrical amplitude deviation threshold to the per-unit waveform sequence of the ideal fundamental voltage to form the upper and lower boundaries of the three-phase voltage envelope that dynamically follows the phase change of the grid fundamental voltage; the dynamic voltage envelope generation process with symmetrical deviation constraints is as follows: A symmetrical amplitude deviation threshold is applied to the three-phase ideal per-unit waveform output in step 3.1 to form upper and lower envelope boundaries that dynamically follow the phase change of the fundamental wave of the power grid.

[0044] Among them, the upper limit bias coefficient is set. The lower limit bias coefficient is +0.1 (per unit value). It is -0.1 (per unit value).

[0045] The upper and lower limit bias thresholds are set with reference to the current national standard GB / T 30137-2024 regarding the amplitude definition range of voltage sag.

[0046] The upper and lower thresholds can also be flexibly set according to the actual needs of the engineering application site.

[0047] Through the upper and lower limit envelope generation mechanism, the detection threshold achieves high-precision time-frequency synchronous tracking with the fundamental phase of the power grid, fundamentally eliminating the adaptability defects of fixed threshold under phase disturbance, and significantly improving the reliability, accuracy and engineering practicality of voltage sag event identification under non-ideal power grid conditions.

[0048] Step 4: Detect voltage transient events based on the per-unit values ​​of each phase voltage and the three-phase voltage envelope, and output a global voltage transient event trigger signal; More preferably, the voltage transient event detection steps are as follows: Step 4.1: Compare the per-unit voltage values ​​of each phase with the upper and lower boundaries of the three-phase voltage envelope point by point. When N consecutive per-unit voltage values ​​of any phase voltage exceed the upper or lower boundary of the corresponding phase voltage envelope, it is determined that a voltage sag event has occurred in that phase, and a single-phase event flag is generated. The point-by-point instantaneous comparison and preliminary limit exceedance detection are detailed as follows: like Figure 4 As shown, the voltage transient event detection module receives the three-phase real-time voltage sampling sequence after per-unit processing, and performs point-by-point instantaneous comparison with the three-phase dynamic voltage envelope detection interval output by step 3 (dynamic voltage envelope generation module).

[0049] Its core detection principle is: when the instantaneous sampled value of any phase voltage exceeds the upper or lower boundary of the dynamic envelope of the corresponding phase, the initial transient event marker of that phase is triggered.

[0050] Adaptive temporal stabilization mechanism and cumulative decision: To suppress false triggering caused by power grid noise, harmonic distortion, and transient pulse disturbances, this step introduces an adaptive time-domain anti-jitter mechanism.

[0051] Specifically, a cumulative decision is made based on continuous sampling points for the initial out-of-limit signal of each phase: A real voltage sag event is confirmed to have occurred in a phase only when the voltage amplitude of N consecutive sampling points exceeds the dynamic envelope interval (i.e., the upper boundary or lower boundary condition is met simultaneously).

[0052] Anti-shake delay time is defined as .

[0053] in This refers to the real-time running cycle of the detection module algorithm. It is a preset integer parameter (preferably 3 to 10, which can be flexibly configured according to the protection sensitivity requirements of the engineering site).

[0054] Step 4.2: Perform logical OR arbitration on the three single-phase event flags corresponding to phases A, B, and C. If the single-phase event flag bit of any phase A, B, or C is at an active level, then output a global voltage transient event trigger signal. The generation of single-phase event flags and the logical OR arbitration are as follows: After the above anti-shake decision, three independent single-phase transient event flags are generated: A-phase transient event markers: ; B-phase transient event markers: ; C-phase transient event markers: ; Furthermore, the three single-phase flag bits are combined via a logic OR arbitration unit. That is, if , , If any flag bit is active, a global voltage transient event trigger signal will be output. The system determines that a voltage dip event has occurred in the current power grid.

[0055] This arbitration strategy ensures rapid detection of single-phase faults while avoiding complex decision-making delays caused by multi-phase cross-interference.

[0056] This step utilizes the frequency tracking robustness and phase-keeping characteristics of the low-bandwidth inertial phase-locked loop and the dynamic voltage envelope, combined with time-domain anti-jitter cumulative decision, to effectively isolate non-continuous disturbances and significantly improve the accuracy, reliability and anti-interference capability of voltage transient event detection.

[0057] Step 5: Perform voltage recovery detection based on the adaptive recovery reference value on the effective value of the three-phase voltage and output a voltage recovery flag; More preferably, the voltage recovery detection step based on the adaptive recovery reference value is as follows: Grid voltage restoration implementation strategies, such as Figure 5 As shown: Step 5.1: First, calculate the effective values ​​of the three-phase voltages after per-unit scaling using the full-cycle sliding window RMS recursive algorithm. , , ; By employing a recursive updating sliding window method for calculating effective values, the amount of computational data is reduced, thus reducing resource consumption in embedded development. Step 5.2: Calculate the adaptive reference voltage online based on recursive exponential smoothing and upper and lower limit clamping; The normalized reference value for voltage recovery adopts an adaptive algorithm. Traditional methods use a fixed rated value of 1.0 pu as the reference for recovery criteria.

[0058] However, in actual power grids, the rated voltage may drift slowly due to changes in system load, transformer tap adjustment, or measurement errors.

[0059] To address this, an adaptive reference voltage is introduced, which is updated online based on the long-term statistical characteristics of the fundamental amplitude of the three-phase voltage.

[0060] The long-term adaptive reference voltage is calculated using recursive exponential smoothing: .

[0061] in is the average of the effective values ​​of the three-phase voltages (i.e., the average of the three phase voltages), and n represents the sampling time; Basis for determining the smoothing factor value: Corresponding time constant Approximately 50 to 200 cycles ensure that the reference is insensitive to voltage dips and only responds to slow changes on the order of minutes.

[0062] To prevent excessive deviation from the physical rating, upper and lower clamps are introduced. ,Right now The adaptive reference value will not exceed ±5% of the rated value, ensuring operation within the normal voltage regulation range of the power grid.

[0063] Step 5.3: Calculate the phase-by-phase deviation between the effective value of each phase voltage and the adaptive reference voltage to obtain the corresponding deviation. When the absolute value of each corresponding deviation is lower than the preset threshold at the same time, the grid voltage is determined to be restored after anti-jitter delay, and a voltage recovery flag is output.

[0064] To avoid overall detection disturbances caused by phase imbalance, single-phase sags, or harmonic component diversity in the three-phase voltage, this invention employs a three-phase independent comparison strategy: The deviation between the effective value of each phase voltage and the reference value is calculated phase by phase, and a joint logic criterion is set if the deviations of all three phases are simultaneously below a preset threshold to determine that the grid voltage has recovered. The threshold value ranges from 0.02pu to 0.05pu, preferably 0.05pu.

[0065] Finally, a 20ms delay is applied to the logic signal to debouncing it, and a stable digital signal is output to indicate whether the mains voltage is within the normal range.

[0066] This strategy effectively decouples phase-to-phase interference, eliminates the risk of misjudgment caused by single-phase anomalies or harmonics, and significantly improves the accuracy, robustness and engineering adaptability of recovery event identification. It is especially suitable for high-reliability detection requirements under complex power grids and unbalanced operating conditions.

[0067] Step 6: Generate a voltage sag flag bit based on the global voltage transient event trigger signal and the voltage recovery flag to indicate whether the current state is a voltage sag.

[0068] More preferably, the voltage sag flag generation steps are as follows: Combining the voltage over / under limit flags output from step 4 and the grid voltage recovery flags output from step 5, logical judgment and state locking are performed (setting the SR flip-flop), ultimately generating a binary voltage dip flag (if the trigger signal is 1, the flag is 1; if the trigger signal is 0 and the recovery flag is 1, the flag is 0; if the trigger signal is 0 and the recovery flag is 0, the flag retains the value from the previous moment): A flag of "1" indicates that the current state is a voltage dip. A flag of "0" indicates that the voltage is normal or has been restored.

[0069] This flag can be used directly for the operation commands of voltage sag mitigation equipment, or for power quality event recording and analysis.

[0070] This invention has been practically deployed on a 10kV voltage sag mitigation device and has undergone systematic field testing.

[0071] To clearly and objectively demonstrate the technical advantages of this invention and its performance under actual working conditions, the following detailed explanation is provided, based on measured waveforms of the equipment, focusing on three aspects: operating efficiency, anti-harmonic interference capability, and response speed to various types of faults. Experimental results show that the interrupt resource overhead of the detection method of this invention on the ZYNQ7015 control platform is less than 1 μs. Compared with similar algorithms that rely on multiple frequency transformations or are combined with machine learning, the method of this invention has the characteristics of simple structure and easy deployment, and is naturally adapted to the real-time performance and resource constraints of embedded control systems.

[0072] In addition, it contributes very little to the computational load of the voltage management equipment controller, which can effectively ensure the efficient and stable operation of the system as a whole.

[0073] Figure 6 This demonstrates the real-time tracking of the voltage waveforms of each phase when the grid voltage contains a harmonic with a total harmonic distortion (THD) of 5% (taking the 11th harmonic as an example).

[0074] Test results show that the transient values ​​of each phase voltage did not exceed the preset upper and lower limit curves; When the method of this invention meets the power grid quality harmonic standards (taking the 11th harmonic as an example), it will not cause false detections due to harmonics. It can effectively filter out the interference of harmonic components on amplitude determination, thereby avoiding false detections of voltage sags caused by harmonic distortion.

[0075] This result demonstrates that the method of the present invention has good robustness in environments with moderate harmonic pollution and is suitable for complex power quality scenarios commonly encountered in industrial settings.

[0076] Figure 7 , Figure 8 , Figure 9 The images show the detection times of actual treatment equipment under single-phase short-circuit asymmetrical faults, three-phase symmetrical faults, and two-phase asymmetrical faults. The top image in each figure is a global view, and the bottom image is a magnified view of a specific area. The detection time for each figure is 300µs. Figure 7 For a single-phase short circuit in a neutral-point ungrounded system, Figure 8 Corresponding to a three-phase symmetrical short-circuit fault, Figure 9 This corresponds to a two-phase asymmetric fault. Specifically, it corresponds to the anti-shake parameter N in step 6 and the operating cycle of the method of this invention. The settings are as follows: .

[0077] Under this parameter setting, the device can function under all types of faults. It can accurately detect and lock the status of voltage sag events.

[0078] The detection method of this invention has the advantage of extremely high speed, which provides ample time window for subsequent operations such as off-grid disconnection and voltage support by the treatment equipment, ensuring that it can easily meet the typical response standard for voltage sag treatment in industrial processes - that is, to restore the effective voltage value to 90% of the rated value within 5ms.

[0079] Embodiment 2 of the present invention provides a fast voltage sag detection system based on dynamic voltage envelope identification, comprising: The voltage sampling and processing module is used to synchronously sample and preprocess the three-phase voltages of the power grid to obtain the per-unit value of each phase voltage, and to perform zero-sequence component separation processing on the per-unit value of each phase voltage to obtain the zero-sequence three-phase voltage signal. The fundamental phase tracking module is used to input the zero-sequence three-phase voltage signal into a low-bandwidth inertial phase-locked loop for fundamental phase robust tracking, so as to obtain a continuous and smooth instantaneous phase angle signal of the fundamental positive-sequence component of the power grid. The voltage envelope reconstruction module is used to generate a three-phase reference phase based on the instantaneous phase angle signal, and to reconstruct a three-phase voltage envelope that dynamically follows the change of the fundamental phase of the power grid based on the three-phase reference phase. The voltage transient event detection module is used to detect voltage transient events based on the per-unit values ​​of each phase voltage and the three-phase voltage envelope, and output a global voltage transient event trigger signal. The voltage recovery detection module is used to perform voltage recovery detection on the effective value of the three-phase voltage based on an adaptive recovery reference value and output a voltage recovery flag. The voltage sag flag module is used to generate a voltage sag flag bit based on the global voltage transient event trigger signal and the voltage recovery flag, indicating whether the current state is a voltage sag.

[0080] Embodiment 3 of the present invention provides a terminal, including a processor and a storage medium; the storage medium is used to store instructions; the processor is used to perform operations according to the instructions to execute the steps of the method.

[0081] Embodiment 4 of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method.

[0082] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0083] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0084] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0085] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A method for rapid detection of voltage sags based on dynamic identification of voltage envelope, characterized in that, include: Step 1: Synchronously sample and preprocess the three-phase voltages of the power grid to obtain the per-unit value of each phase voltage, and perform zero-sequence component separation processing on the per-unit value of each phase voltage to obtain the zero-sequence three-phase voltage signal. Step 2: Input the zero-sequence three-phase voltage signal into a low-bandwidth inertial phase-locked loop for fundamental phase robust tracking to obtain a continuous and smooth instantaneous phase angle signal of the fundamental positive-sequence component of the power grid. Step 3: Generate a three-phase reference phase based on the instantaneous phase angle signal, and reconstruct the three-phase voltage envelope that dynamically follows the phase change of the grid fundamental wave based on the three-phase reference phase; Step 4: Detect voltage transient events based on the per-unit values ​​of each phase voltage and the three-phase voltage envelope, and output a global voltage transient event trigger signal; Step 5: Perform voltage recovery detection on the three-phase voltage RMS value based on the adaptive recovery reference value and output a voltage recovery flag; Step 6: Generate a voltage sag flag bit based on the global voltage transient event trigger signal and the voltage recovery flag to indicate whether the current state is a voltage sag.

2. The method for rapid detection of voltage sag based on dynamic identification of voltage envelope according to claim 1, characterized in that: Step 1 specifically includes: Step 1.1: Synchronously sample and convert the three-phase phase voltages of the power grid to analog-to-digital conversion to obtain the original voltage sampling sequence; Step 1.2: Perform a per-unit transformation on the original voltage sampling sequence based on the rated voltage amplitude to obtain the per-unit value of each phase voltage; Step 1.3: Perform zero-sequence component separation processing on the per-unit values ​​of each phase voltage to obtain the zero-sequence three-phase voltage signal.

3. The method for rapid detection of voltage sags based on dynamic identification of voltage envelope according to claim 1, characterized in that: The low-bandwidth inertial phase-locked loop described in step 2 uses an inertial topology with a low cutoff frequency to dynamically suppress disturbance components and maintain the stability of the phase-locking process. The parameter tuning of the low-bandwidth inertial phase-locked loop satisfies: When the grid voltage experiences a step sag, the instantaneous phase angle signal The change in the fundamental frequency and its corresponding frequency within half a power frequency cycle approaches zero.

4. The method for rapid detection of voltage sag based on dynamic identification of voltage envelope according to claim 1, characterized in that: Step 3 specifically includes: Step 3.1: Based on the instantaneous phase angle signal as the reference phase of phase A, perform fixed phase shift rotation transformations of 120° lag and 120° lead on the reference phase of phase A to generate the reference phases of phases B and C respectively. Then, feed the reference phase sequences of phases A, B, and C into the normalized cosine mapping function. After unit amplitude normalization, obtain the per-unit waveform sequences of the ideal fundamental voltage of phases A, B, and C respectively. , , ; Step 3.2: Apply a symmetrical amplitude deviation threshold to the normalized waveform sequence of the ideal fundamental voltage to form the upper and lower boundaries of the three-phase voltage envelope that dynamically follow the phase change of the fundamental voltage of the power grid.

5. The method for rapid detection of voltage sag based on dynamic identification of voltage envelope according to claim 1, characterized in that: Step 4 specifically includes: Step 4.1: Compare the per-unit voltage values ​​of each phase with the upper and lower boundaries of the three-phase voltage envelope point by point. When N consecutive per-unit voltage values ​​of any phase voltage exceed the upper or lower boundary of the corresponding phase voltage envelope, it is determined that a voltage sag event has occurred in that phase, and a single-phase event flag is generated. Step 4.2: Perform logical OR arbitration on the three single-phase event flags corresponding to phases A, B, and C. If the single-phase event flag bit of any one of phases A, B, and C is at an active level, then output a global voltage transient event trigger signal.

6. The method for rapid detection of voltage sag based on dynamic identification of voltage envelope according to claim 5, characterized in that: The value of N ranges from 3 to 10.

7. The method for rapid detection of voltage sag based on dynamic identification of voltage envelope according to claim 1, characterized in that: Step 5 specifically includes: Step 5.1: Perform full-cycle sliding window RMS recursive calculation on the per-unit value of each phase voltage to obtain the effective value of the three-phase voltage; Step 5.2: Calculate the adaptive reference voltage online based on recursive exponential smoothing and upper and lower limit clamping; Step 5.3: Calculate the phase-by-phase deviation between the effective value of each phase voltage and the adaptive reference voltage to obtain the corresponding deviation. When the absolute value of each corresponding deviation is lower than the preset threshold at the same time, the grid voltage is determined to be restored after anti-jitter delay, and a voltage recovery flag is output.

8. The method for rapid detection of voltage sag based on dynamic identification of voltage envelope according to claim 7, characterized in that: The adaptive reference voltage described in step 5.2 is calculated online using the following recursive exponential smoothing formula: And introduce upper and lower clamps: ; in The average value of the three-phase phase voltage is given by n, where n represents the sampling time. α This is a smoothing factor.

9. The method for rapid detection of voltage sag based on dynamic identification of voltage envelope according to claim 1, characterized in that: In step 6, logical judgment and state locking are performed based on the global voltage transient event trigger signal and the voltage recovery flag to generate a binary voltage sag flag. The binary voltage sag flag is used to indicate whether the current voltage is in a sag state. When the binary voltage sag flag is "1", it indicates that the current voltage is in a sag state, and when it is "0", it indicates that the voltage is normal or has recovered.

10. A rapid voltage sag detection system based on dynamic voltage envelope identification, comprising the method described in any one of claims 1-9, characterized in that, The system includes: The voltage sampling and processing module is used to synchronously sample and preprocess the three-phase voltages of the power grid to obtain the per-unit value of each phase voltage, and to perform zero-sequence component separation processing on the per-unit value of each phase voltage to obtain the zero-sequence three-phase voltage signal. The fundamental phase tracking module is used to input the zero-sequence three-phase voltage signal into a low-bandwidth inertial phase-locked loop for fundamental phase robust tracking, so as to obtain a continuous and smooth instantaneous phase angle signal of the fundamental positive-sequence component of the power grid. The voltage envelope reconstruction module is used to generate a three-phase reference phase based on the instantaneous phase angle signal, and to reconstruct a three-phase voltage envelope that dynamically follows the change of the fundamental phase of the power grid based on the three-phase reference phase. The voltage transient event detection module is used to detect voltage transient events based on the per-unit values ​​of each phase voltage and the three-phase voltage envelope, and output a global voltage transient event trigger signal. The voltage recovery detection module is used to perform voltage recovery detection on the effective value of the three-phase voltage based on an adaptive recovery reference value and output a voltage recovery flag. The voltage sag flag module is used to generate a voltage sag flag bit based on the global voltage transient event trigger signal and the voltage recovery flag, indicating whether the current state is a voltage sag.

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