A transient traveling wave fault detection device and method combining low-speed pre-judgment and high-speed backtracking

Abstract

The application discloses a kind of low-speed pre-judgment and high-speed backtrack combined transient traveling wave fault detection device and method, it is related to distribution network fault detection and transient traveling wave acquisition technical field, with ZYNQ system on chip as core, PL side completes high-speed sampling, PPS time mark, high-low speed data flow shunt and DDR ring buffer write-in;UTC time stamp and the mapping relationship of cache sampling index are established on PS side, by master-slave machine collaborative transmission mechanism, using low-speed channel continuous pre-judgment transient mutation, trigger backtracking reading high-speed channel key waveform window, complete fault initial traveling wave head accurate positioning.The application gives consideration to high-frequency traveling wave capture capability and data transmission efficiency, improve the accuracy and real-time of multi-node synchronous detection.

Description

Technical Field

[0001] This invention relates to the field of power distribution network fault detection technology, and more specifically to a transient traveling wave fault detection device and method that combines low-speed prediction with high-speed backtracking. Background Technology

[0002] Traditional fault detection and protection methods for distribution networks typically rely on steady-state or quasi-steady-state electrical quantities such as power frequency voltage, current amplitude, phase, impedance, or zero-sequence components. However, in new distribution networks, the integration of distributed generation sources alters the amplitude and direction of fault currents, and the control characteristics of power electronic equipment also affect the transient fault process, causing the fault current to exhibit weakened, distorted, and uncertain characteristics. Therefore, fault detection methods relying solely on traditional power frequency or steady-state quantities are insufficient to meet the demands for rapid, accurate, and reliable fault detection in new distribution networks.

[0003] When a power distribution line experiences faults such as grounding, short circuits, or open circuits, a transient traveling wave signal containing abundant high-frequency components is generated at the fault point at the initial instant of the fault. This transient traveling wave propagates along the line to both ends, and its wavefront arrival time, polarity, amplitude, and high-frequency characteristics are closely related to the fault location, fault type, and line structure. Therefore, fault detection and location methods based on transient traveling waves have advantages such as fast response speed, less influence from power frequency steady-state quantities, and the ability to reflect information at the initial instant of the fault, and have become an important technical direction in the field of power distribution network fault detection.

[0004] However, transient traveling wave signals are characterized by short duration, high frequency components, and rapid wavefront changes, placing high demands on the sampling rate, synchronization accuracy, buffering capacity, and real-time processing capabilities of the acquisition device. To accurately capture the initial traveling wave of a fault, the acquisition device needs to continuously store high-frequency sampling data before and after the fault occurs, and quickly extract key data windows containing wavefront information after the fault occurs. Furthermore, in multi-point traveling wave detection or location scenarios, a unified time reference is required between different acquisition nodes; otherwise, the accuracy of comparing traveling wave arrival times and fault location results will be affected.

[0005] Existing transient traveling wave acquisition devices still have certain shortcomings: some devices mainly perform low-speed continuous recording, making it difficult to fully retain the high-frequency details of the initial moment of a fault; some devices adopt a full-time high-speed acquisition and uploading method, which, although able to retain transient information, generates a large amount of redundant data, putting significant pressure on local storage capacity, communication bandwidth, and backend processing capabilities; some devices, while possessing high-speed sampling capabilities, lack an effective mechanism for backtracking data before and after a fault, making it difficult to accurately extract waveform data within a specified time window according to a unified time reference. Furthermore, in multi-node distributed acquisition scenarios, the time synchronization, status synchronization, and waveform reading mechanisms between nodes are not perfect, and there is a lack of effective coordination between acquisition, caching, communication, and fault detection algorithms, affecting the system's real-time performance, reliability, and engineering applicability.

[0006] Therefore, it is necessary to provide a transient traveling wave high-frequency acquisition and fault detection technology solution suitable for new distribution networks, which can reduce the pressure of continuous high-speed data storage and transmission while ensuring effective acquisition of high-frequency traveling wave information, and realize time synchronization of multi-node data acquisition, backtracking reading of key waveform windows, and rapid detection of the initial traveling wave head of the fault. Summary of the Invention

[0007] In view of this, the present invention provides a transient traveling wave fault detection device and method that combines low-speed prediction and high-speed backtracking. The device utilizes the programmable logic side of ZYNQ to complete high-speed sampling, PPS time stamping, data preprocessing and DDR ring cache writing, and utilizes the processing system side to complete sampling parameter configuration, UTC time index maintenance, master-slave collaborative transmission and transient traveling wave fault detection, thereby realizing continuous acquisition, synchronous marking, time window back reading and fault initial wavefront detection of transient traveling wave signals in distribution networks.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: A transient traveling wave fault detection device combining low-speed prediction and high-speed backtracking includes: several acquisition devices distributed at different measurement points on a power distribution line, each acquisition device being equipped with a sampling unit, a timing unit, a storage unit, and a communication unit; each acquisition device uses a ZYNQ on-chip system as its control core, the ZYNQ on-chip system including a PL side and a PS side; The PL side is connected to the sampling unit, the timing unit and the storage unit respectively. It receives the high-frequency traveling wave sampling data output by the sampling unit, embeds the PPS second pulse flag output by the timing unit into the high-frequency traveling wave sampling data data stream to form sampling data with second-level time boundaries, performs preprocessing and splits the data streams to generate low-speed data stream and high-speed data stream, and writes the two data streams into the storage unit in a ring buffer manner. The PS side is connected to the PL side and the communication unit respectively, and a mapping relationship is established between the UTC timestamp and the sampling index of the ring buffer in the storage unit. The master-slave collaborative data interaction between the acquisition devices is realized through the communication unit. Based on the low-speed data stream, the fault transient change prediction is continuously performed. According to the mapping relationship, the high-speed data stream of the corresponding time window is read back to detect the fault and complete the accurate positioning of the initial traveling wave head of the fault.

[0009] Preferably, the PL side includes an ADC configuration module, an ADC data receiving module, a PPS generation module, a configuration register module, a dual-channel parallel data processing link, and an AXI interconnect unit; The ADC configuration module is used to configure the working mode and sampling parameters of the sampling unit; The ADC data receiving module is used to capture high-speed parallel sampling data and write the PPS flag output by the PPS generation module into the flag bit of the corresponding sampling point; The configuration register module is used to implement parameter distribution and operation status feedback between the PS side and the PL side; The dual-path parallel data processing links correspond to low-speed data streams and high-speed data streams respectively. Each path includes a data management unit, a ring address scheduling unit, and a DMA transport unit, which respectively complete data preprocessing, ring cache address calculation, and high-speed data bus transport. The AXI interconnect unit is used to construct bus interaction paths between modules on the PL side, the PS side, and the storage unit.

[0010] Preferably, the storage unit is a DDR memory, and each sampling channel corresponds to an independent cache start address and cache capacity; when writing data on the PL side, when the write address reaches the end of the current channel cache area, it automatically wraps back to the cache start address to continue writing. If a single write data crosses the end of the cache, it is written in segments and then spliced ​​to form a continuous ring cache structure that can be overwritten and updated.

[0011] Preferably, the PS side calculates the sampling index corresponding to each UTC second boundary by reading the PPS valid status, the corresponding sampling byte count and the current sampling transmission byte count fed back by the PL side configuration register module, and establishes a one-to-one mapping relationship between the UTC timestamp, the sampling index and the DDR read address, supporting the accurate reading of waveform data of a specified length according to the UTC time window.

[0012] Preferably, among the plurality of acquisition devices, one is the master and the rest are slaves; the master sends a data reading instruction to the slaves through a local wireless communication interface, the instruction including a UTC timestamp, channel number, relative sampling index and number of data points; after receiving the instruction, the slave reads the corresponding waveform data from the local circular buffer according to the mapping relationship and returns it to the master, thereby realizing time-aligned reading of data acquired by multiple acquisition devices.

[0013] A transient traveling wave fault detection method combining low-speed prediction and high-speed backtracking includes: S1, the PS side writes the analog-to-digital converter operating parameters, sampling channel parameters, moving average parameters, bias parameters, DDR cache start address and cache capacity to the ADC configuration module, data management unit and ring address scheduling unit on the PL side through the configuration register module, and starts the acquisition enable signal on the PL side; S2, the ADC data receiving module on the PL side acquires the digital value of the traveling wave signal output by the analog-to-digital converter, and the PPS generation module embeds the external PPS second pulse flag into the sampling data stream to form sampling data with second-level time boundary information. S3, the data management unit on the PL side preprocesses the sampled data and generates a low-speed data stream for continuous fault prediction and a high-speed data stream for fault wave head precision detection through dual-channel data processing link splitting; S4, the ring address scheduling unit of the dual data processing link calculates the cache write address of the two data streams respectively, and the corresponding DMA transfer unit writes the low-speed data stream and the high-speed data stream into the DDR memory through the AXI bus, and performs ring overwrite write according to the set cache start address and cache capacity. S5, the PS side reads the PPS valid status, the corresponding sampled byte count and sampled transmission byte count fed back by the configuration register module, and establishes the correspondence between the UTC timestamp and the DDR ring cache sampling index; S6, the host establishes a collaborative transmission link with the slave through the communication unit, and reads the low-speed channel waveform data of the host and all slaves according to the unified UTC time; S7, the PS side of the host performs normalization, superposition, differential and sliding window energy detection on the low-speed channel waveform data to determine whether there is a suspected fault initial transient change. S8, when a suspected transient change is detected in the low-speed channel, the PS side of the host determines the high-speed channel readback window parameters based on the low-speed change index and the ratio of the sampling rates of the high-speed channel and the low-speed channel. S9, the master sends a data read command containing UTC timestamp, channel number, relative sampling index and data point number to the slave through the communication unit. The slave's PS side reads the corresponding high-speed waveform data from the local DDR ring buffer according to the command and returns it to the master. S10: The PS side of the host performs normalization, filtering, differential analysis, and sliding window energy detection on the high-speed waveform data returned by itself and the slave to obtain the initial traveling wave head position of the fault and generate the fault detection result.

[0014] Preferably, when the data management unit in S3 performs extraction processing on the sampled data, if it detects the PPS flag in the sampled data, it resets the extraction count and forces the output of the current sampling point data, so that the extracted low-speed data stream retains complete PPS time boundary information.

[0015] Preferably, when the ring address scheduling unit in S4 performs address scheduling, when the write address reaches the end of the current channel buffer area, it automatically wraps back to the start address of the buffer to continue writing; if the single write data crosses the end of the buffer area, the remaining space before the end of the buffer is written first, and then the remaining data is written from the start address of the buffer.

[0016] Preferably, in step S5, the PS side determines the UTC second boundary based on the continuously detected valid PPS signals, calculates the sampling index corresponding to each UTC second boundary, and establishes a one-to-one mapping relationship between the UTC timestamp, the relative sampling index, and the DDR read address.

[0017] Preferably, in step S8, the low-speed mutation index is converted into the expected mutation index in the high-speed channel based on the ratio of the low-speed channel sampling rate to the high-speed channel sampling rate; based on the expected mutation index, the number of pre-sampling points and the number of post-sampling points are set respectively to determine the starting index and the total number of reading points for high-speed data; if the reading window crosses the DDR cache boundary or the UTC second boundary, segmented reading and splicing are performed according to the ring cache rule.

[0018] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a transient traveling wave fault detection device and method that combines low-speed prediction and high-speed backtracking, with the following beneficial effects: First, this invention utilizes the PL side of ZYNQ to complete high-speed sampling, PPS time stamping, data preprocessing, and DDR ring cache writing, and utilizes the PS side to complete parameter configuration, time index maintenance, master-slave collaborative transmission, and fault detection. It fully leverages the parallel real-time processing capability of the PL side and the flexible control capability of the PS side, thereby improving the real-time performance and engineering applicability of the high-frequency traveling wave acquisition system. Second, this invention embeds a PPS second pulse flag in the sampled data stream and records the corresponding sampled byte count for PPS. This enables the establishment of a correspondence between the UTC timestamp and the DDR ring cache sampling position, thereby achieving accurate back-reading of key waveform data before and after the fault according to UTC time, relative sampling index, and number of data points. This improves the accuracy of data alignment and waveform backtracking between multiple acquisition devices. Third, this invention uses a DDR ring cache to continuously store high-frequency traveling wave data and performs fault detection by combining low-speed prediction with high-speed precision detection. The low-speed channel is used to continuously monitor suspected transient changes, while the high-speed channel reads back the key window to perform wavefront detection after detecting a suspected change. This reduces the pressure on all-time high-speed data storage and transmission, and improves the ability to capture the initial traveling wavefront of a fault. Fourth, the present invention adopts a master-slave collaborative transmission mechanism. The master can send a data reading instruction containing UTC timestamp, channel number, relative sampling index and data point number to the slave. The slave can read the corresponding waveform data from the local DDR ring buffer according to the instruction and return it to the master. This realizes the collaborative acquisition of waveform data between multiple acquisition devices, which facilitates the comprehensive analysis of transient traveling wave signals at different acquisition locations. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the multi-machine collaborative data acquisition and communication deployment for power distribution lines provided by the present invention; Figure 2 This is a schematic diagram of the overall structure of the online power distribution terminal detection device provided by the present invention; Figure 3 A schematic diagram of the front-end current signal conditioning and AD9251 high-speed sampling link provided for this invention; Figure 4 This is a schematic diagram of the high-frequency traveling wave acquisition and buffering processing logic structure of the ZYNQ PL terminal provided by the present invention; Figure 5 This is a schematic diagram of the layered architecture of the PS-side software provided by the present invention; Figure 6 The state machine flowchart provided for this invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention discloses a transient traveling wave fault detection device that combines low-speed prediction and high-speed backtracking, comprising: several acquisition devices distributed at different measurement points on a power distribution line, each acquisition device being equipped with a sampling unit (current ADC sampling module, including AD9251 high-speed ADC), a timing unit (GNSS module), a storage unit (DDR3 memory), and a communication unit (local wireless communication interface and host computer communication interface); each acquisition device uses a ZYNQ on-chip system as its control core, the ZYNQ on-chip system including a PL side and a PS side; The PL side is connected to a sampling unit (current ADC sampling module, including AD9251 high-speed ADC), a timing unit (GNSS module), and a storage unit (DDR3 memory). It receives high-frequency traveling wave sampling data output by the sampling unit, embeds the PPS second pulse flag output by the timing unit into the high-frequency traveling wave sampling data stream to form sampling data with second-level time boundaries, performs preprocessing, splits the data streams to generate low-speed data streams and high-speed data streams, and writes the two data streams into the storage unit in a ring buffer manner. The PS side is connected to the PL side and the communication unit respectively, and a mapping relationship is established between the UTC timestamp and the sampling index of the ring buffer in the storage unit. The master-slave collaborative data interaction between the acquisition devices is realized through the communication unit. Based on the low-speed data stream, the fault transient change prediction is continuously performed. According to the mapping relationship, the high-speed data stream of the corresponding time window is read back to detect the fault and complete the accurate positioning of the initial traveling wave head of the fault.

[0023] In one specific embodiment, the PL side includes an ADC configuration module (ADC_Config2.v), an ADC data receiving module (AD9251.v), a PPS generation module (GnssUart2PPS.v), a configuration register module (BramCfg.v), a dual-channel parallel data processing link, and an AXI Interconnect unit. The ADC configuration module (ADC_Config2.v) is used to configure the working mode and sampling parameters of the sampling unit; The ADC data receiving module (AD9251.v) is used to capture high-speed parallel sampling data and write the PPS flag output by the PPS generation module (GnssUart2PPS.v) into the flag bit of the corresponding sampling point. The configuration register module (BramCfg.v) is used to implement parameter distribution and operation status feedback between the PS side and the PL side; The dual-path parallel data processing links correspond to low-speed data streams and high-speed data streams, respectively. Each path includes a data management unit (DataManager), a ring address scheduling unit (RollingTransfer), and a DMA transport unit (MyUiFdma), which respectively complete data preprocessing, ring cache address calculation, and high-speed data bus transport. The AXI Interconnect unit is used to construct bus interaction paths between modules on the PL side, the PS side, and the storage unit.

[0024] In one specific embodiment, the storage unit is a DDR memory (DDR3 memory), and each sampling channel corresponds to an independent cache start address and cache capacity. When writing data on the PL side, when the write address reaches the end of the current channel cache area, it automatically wraps back to the cache start address to continue writing. If a single write data crosses the end of the cache, it is written in segments and then spliced ​​together to form a continuous ring cache structure that can be overwritten and updated.

[0025] In one specific embodiment, the PS side reads the PPS valid status, the corresponding sampled byte count and the current sampled transmission byte count fed back by the PL side configuration register module (BramCfg.v), calculates the sampling index corresponding to each UTC second boundary, establishes a one-to-one mapping relationship between UTC timestamp, sampling index and DDR read address, and supports precise reading of waveform data of a specified length according to the UTC time window.

[0026] In one specific embodiment, one of the several acquisition devices is a master device, and the rest are slave devices. The master device sends a data reading instruction to the slave devices through a local wireless communication interface (WIFI module). The instruction includes a UTC timestamp, channel number, relative sampling index, and number of data points. After receiving the instruction, the slave devices read the corresponding waveform data from the local circular buffer according to the mapping relationship and return it to the master device, thereby realizing time-aligned reading of data collected by multiple acquisition devices.

[0027] like Figure 1 As shown, Figure 1This is a schematic diagram illustrating the multi-device collaborative data acquisition and communication deployment in a power distribution line according to the present invention. In this embodiment, multiple high-frequency traveling wave acquisition devices are installed at different measurement points along the power distribution line to acquire, process, and transmit transient signals of the line current. The devices communicate locally via Wi-Fi, with one device acting as the master and the others as slaves. The master device is responsible for slave status queries, time synchronization status confirmation, low-speed data reading, high-speed data readback, fault detection and handling, and result uploading. The slave devices are responsible for local front-end sampling, data caching, and returning waveform data within a specified time window as requested by the master device. The master device connects to the host computer via a 4G-based TCP / IP communication link and implements network communication services through an lwIP protocol stack running on the PS terminal, forming a field application link for front-end signal acquisition, ZYNQ processing, and uploading to the host computer for analysis and display.

[0028] exist Figure 1 In the deployment shown, each acquisition device is installed close to the measurement point on the power distribution line, enabling it to independently complete local current signal acquisition and buffering. The host interacts with the slave devices via Wi-Fi, reading waveform data from the slave devices' buffers according to a unified time base. When the host detects a suspected fault transient change, it requests high-speed waveform data from the slave devices for the corresponding time window before and after the fault, and combines this data with the locally acquired data to perform initial traveling wave front detection. The detection results and necessary waveform data can be uploaded to the host computer via a 4G network for subsequent display, analysis, and archiving.

[0029] like Figure 2 As shown, Figure 2 This is a schematic diagram of the overall structure of the online detection device for power distribution terminals of the present invention. The device mainly includes a current ADC sampling module, a GNSS module, a ZYNQ processing unit, a master-slave local communication interface, and a host computer communication interface. The current ADC sampling module receives the raw three-phase current signals and converts the analog signals into digital sampling signals before sending them to the ZYNQ. The GNSS module receives BeiDou satellite signals and provides time messages and PPS pulse signals to the system. The ZYNQ processing unit includes a PL terminal and a PS terminal. The PL terminal performs digital sampling signal reception, data preprocessing and downsampling, buffering and address scheduling, and high-speed bus transfer; the PS terminal performs time synchronization, local sampling data management, detection processing, and host computer services.

[0030] exist Figure 2In the structure shown, the PL terminal receives the digital signal output from the current ADC sampling module and uses it in conjunction with the PPS pulse signal to time-stamp the sampled data. The sampled data is then processed through "receiving digital signals," "data preprocessing and downsampling," "buffering and address scheduling," and "high-speed bus transport" before being written to the DDR3 buffer. BramCfg.v, as the PL terminal control and configuration module, receives configuration parameters from the PS terminal and provides feedback on the sampling status, PPS status, and buffer status. The PS terminal accesses the PL terminal status and DDR buffer data via the AXI bus and runs the time synchronization stream, the local sampling data stream, the detection processing stream, and the host computer service stream. Specifically, the time synchronization stream is used for time parsing, timestamp and sampling position maintenance; the local sampling data stream is used for status reading, buffer management, and data access; the detection processing stream is used for low-speed coarse detection, high-speed fine detection, and wavehead detection result output; and the host computer service stream is used to read the configuration status and waveform results and return them to the host computer.

[0031] like Figure 3 As shown, Figure 3 This diagram illustrates the front-end current signal conditioning and AD9251 high-speed sampling link. The front-end current signal first enters the front-end adaptation layer, which includes input protection, broadband gain matching, and dynamic range control. Input protection is used to suppress the impact of spikes, overcurrent, or clamping anomalies on the subsequent sampling link; broadband gain matching is used to adapt the input signal amplitude to the ADC input range; dynamic range control is used to improve the device's adaptability to different line operating conditions and different fault transient amplitudes.

[0032] The signal processed by the front-end adaptation layer enters the unified analog processing layer. This layer includes wideband anti-aliasing filtering, differential drive, and an ADC front-end RC network to reduce out-of-band interference, improve signal integrity, and meet the differential input requirements of the AD9251 high-speed ADC. Subsequently, the signal enters the ADC sampling layer. This layer includes the AD9251 high-speed ADC and the ZYNQPL data receiving logic. Under unified sampling clock and SPI configuration control, the AD9251 outputs parallel sampled data, DCO, and FCO signals. The ZYNQPL terminal uses these signals to complete high-speed data reception. This sampling link corresponds to the ADC_Config2.v configuration module and the AD9251.v data receiving module in the project.

[0033] like Figure 4 As shown, Figure 4This is a schematic diagram of the high-frequency traveling wave acquisition and buffer processing logic structure of the ZYNQ PL terminal. The PL terminal mainly includes ADC_Config2.v, AD9251.v, GnssUart2PPS.v, BramCfg.v, DataManager, RollingTransfer, MyUiFdma, master-slave communication module, AXI UART16550 IP core, AXI UART Lite IP core, and AXI Interconnect. ADC_Config2.v is used for initial configuration of AD9251, including ADC operating mode, output mode, test mode, and delay parameter configuration. AD9251.v is used to receive the parallel sampled data output by AD9251 and receive the PPS write signal generated by GnssUart2PPS.v. GnssUart2PPS.v generates a PPS flag signal that can be recognized by the PL terminal based on the time message and PPS signal output by the GNSS module, giving the sampled data stream second-level time boundary information.

[0034] BramCfg.v is the configuration and status interaction module between the PS (Power Supply) and PL (Power Producer) ends. The PS end uses this module to write parameters such as ADC test mode, delay mode, output mode, sampling and decimation parameters, averaging parameters, buffer start address, buffer size, bias value, front-end reset, sampling read enable, transmission enable, GNSS reset, 4G control, and PPS (Producer Positioning System) simulation enable. The PL end uses this module to feed back to the PS end the sample byte count, the sample byte count corresponding to the previous PPS, the most recent PPS sample value, the maximum value of the previous second, the minimum value of the previous second, and the PPS validity status. This configuration and status feedback corresponds to the PL configuration register access logic in the project.

[0035] exist Figure 4 In the PL-side structure shown, data output from AD9251.v enters two processing links: DataManager_0, RollingTransfer_0, MyUiFdma_0 and DataManager_1, RollingTransfer_1, MyUiFdma_1. DataManager is used for preprocessing and downsampling the sampled data. RollingTransfer is used for rolling address scheduling based on the cache start address and cache size. MyUiFdma is used to move data to the DDR3 cache via the AXI bus. These two processing links correspond to different sampling channels or data streams at different rates; one can be used for low-speed detection data caching, and the other for high-speed readback data caching. The AXI Interconnect connects the PL-side functional modules and the PS-side, enabling the PS-side to perform parameter configuration, status reading, and data access.

[0036] Figure 4 The AXI UART Lite IP core is connected to the GNSS module to receive GNSS time messages; the AXIUART16550 IP core is connected to the master-slave communication module for local communication data exchange between the master and slave devices. Thus, the PL end not only performs high-speed sampling and buffer writing, but also provides the hardware interface required for time synchronization, master-slave communication, and configuration control for the PS end.

[0037] like Figure 5 As shown, Figure 5 This is a schematic diagram of the layered architecture of the PS-side software. The PS-side software adopts a five-layer structure. Layer 0 is the hardware adaptation layer, which encapsulates the underlying hardware resources into a unified interface; Layer 1 is the device abstraction and data management layer, which abstracts the sampling hardware into device objects that can be started, stopped, and retrieved data by time, and is responsible for sampling buffer, time index, and waveform data management; Layer 2 is the system control layer, which is used to schedule the local sampling and detection process and switch the running state; Layer 3 is the communication protocol and service layer, which encapsulates the internal functions of the system into communication interfaces; Layer 4 is the application and scheduling layer, which serves as the main entry point for the PS-side program and is used for system assembly, initialization, and task startup.

[0038] The PS-side software runs on FreeRTOS and lwIP in the project. The master and slave devices reuse the underlying hardware access, device abstraction, data management, and communication service modules, and execute different upper-level control logic according to their respective roles. The master focuses on scheduling slave devices, aggregating waveforms, performing detection, and uploading results; the slave focuses on maintaining its local sampling state, responding to master requests, and returning specified waveform data. This layered structure decouples hardware access, data management, fault detection, and communication services, improving program maintainability and scalability.

[0039] like Figure 6 As shown, Figure 6 This is the state machine flowchart. After power-on, the system first enters the initialization state INIT, completing the initialization of basic resources on the PS side, peripherals, communication interfaces, and resetting the acquisition logic on the PL side. After initialization, it enters the parameter configuration state CFG, where the PS side writes sampling parameters, buffer parameters, ADC configuration parameters, and communication-related parameters to the PL side. The system then enters the waiting time synchronization state WAITING_GNSS, checking if the GNSS time message and PPS signal are valid. If the time synchronization is invalid, it enters the exception handling ERROR state; if the time synchronization is valid, it enters the waiting communication state WAITING_WIFI, checking if local communication between the master and slave devices is established. If communication is not established or the status is abnormal, it enters the exception handling ERROR state; if communication is normal, the system enters the idle state IDLE.

[0040] In the IDLE state, the system waits for a command to start sampling or detection. Once the start conditions are met, the system enters the RUN_GENERAL state for regular acquisition. In this state, the PL (Portable Logic Controller) continuously receives high-speed sampled data from the AD9251 and writes it to the DDR3 circular buffer via DataManager, RollingTransfer, and MyUiFdma; the PS (Portable Logic Controller) reads the PL's status, maintains the correspondence between UTC time and buffer location, and periodically reads low-speed channel data. When the host detects a suspected transient traveling wave change during regular acquisition, the system enters the RUN_WAVE_DATA_GET state for fault data acquisition. In this state, the host reads the corresponding high-speed waveform data from the local and slave buffers based on the detected UTC time and relative sampling location. The system then enters the RUN_WAVE_MAKE state for high-speed processing, filtering, smoothing, differential processing, and wavefront detection on the read-back high-speed waveform to generate fault detection results. After processing, the system enters the RUN_END state and, based on a new command, returns to the initialization state or enters the next round of acquisition and detection.

[0041] In the ERROR state, the system performs a reset or parameter reset based on the exception type. If the exception is caused by invalid time synchronization, the system returns to WAITING_GNSS to continue waiting for valid time synchronization; if the exception is caused by a communication exception, the system returns to WAITING_WIFI to wait for master-slave communication to be established again; if the exception is caused by a configuration or acquisition status exception, the system returns to CFG to rewrite the parameters. Through the above state machine, the system can achieve closed-loop control of initialization, time synchronization, communication, acquisition, fault data acquisition, high-speed processing, and exception recovery during field operation.

[0042] In a specific operational process, the host first configures and synchronizes the slave devices and periodically queries the slave devices' acquisition status. After confirming that the GNSS time is valid, the PPS signal is valid, the WIFI communication is normal, and the slave devices are in a readable state, the host starts sampling on both the host and slave devices. During sampling, the PL end continuously writes to the DDR3 circular buffer, and the PS end maintains the time index and periodically reads low-speed data. When the host detects a suspected sudden change in low speed, it reads back the high-speed waveform data according to the detected UTC time and relative sampling position, and performs wavefront detection on the high-speed waveforms of both the host and slave devices. The detection results can be uploaded to the host computer via a service stream. The uploaded content includes the device number, channel number, detection time, detection status, wavefront position, waveform data type, and necessary waveform data before and after the fault.

[0043] In this embodiment, the ADC model, ZYNQ model, GNSS module model, WIFI module model, 4G module model, DDR cache capacity, sampling rate, and detection parameters can all be adjusted according to actual engineering needs. For example, the high-speed ADC can be another high-speed analog-to-digital converter with the same function as the AD9251; the local communication method can be WIFI or other short-range wireless communication methods; and the remote communication method can be 4G, 5G, or wired Ethernet. As long as it can achieve high-speed sampling, PPS time stamping, DDR ring buffering, master-slave cooperative transmission, and fault initial traveling wave detection, it can be applied to the scope of this invention.

[0044] Through the above implementation methods, this invention realizes a complete engineering link for transient traveling wave signals of power distribution lines, from front-end current sampling, AD9251 high-speed conversion, real-time buffering at the ZYNQ PL terminal, detection and processing at the ZYNQ PS terminal, master-slave WIFI collaborative transmission, and 4G remote uploading to the host computer for display and analysis. This implementation method can continuously save high-frequency sampling data within the most recent time period during long-term operation in the field, and quickly read back the key high-speed waveform window after detecting a suspected fault, thereby achieving rapid capture and detection of the initial transient traveling wave head of the fault.

[0045] A transient traveling wave fault detection method combining low-speed prediction and high-speed backtracking includes: S1, the PS side writes the analog-to-digital converter operating parameters, sampling channel parameters, moving average parameters, bias parameters, DDR cache start address and cache capacity to the ADC configuration module, data management unit and ring address scheduling unit on the PL side through the configuration register module, and starts the acquisition enable signal on the PL side; S2, the ADC data receiving module on the PL side acquires the digital value of the traveling wave signal output by the analog-to-digital converter, and the PPS generation module embeds the external PPS second pulse flag into the sampling data stream to form sampling data with second-level time boundary information. S3, the data management unit on the PL side performs moving average, bias correction and extraction processing on the sampled data, and generates a low-speed data stream for continuous fault prediction and a high-speed data stream for fault wave head precision detection through dual-path data processing link splitting. S4, the ring address scheduling unit of the dual data processing link calculates the cache write address of the two data streams respectively, and the corresponding DMA transfer unit writes the low-speed data stream and the high-speed data stream into the DDR memory through the AXI bus, and performs ring overwrite write according to the set cache start address and cache capacity. S5, the PS side reads the PPS valid status, the corresponding sampled byte count and sampled transmission byte count fed back by the configuration register module, and establishes the correspondence between the UTC timestamp and the DDR ring cache sampling index; S6, the host establishes a collaborative transmission link with the slave through the communication unit, and reads the low-speed channel waveform data of the host and all slaves according to the unified UTC time; S7, the PS side of the host performs normalization, superposition, differential and sliding window energy detection on the low-speed channel waveform data to determine whether there is a suspected fault initial transient change. S8, when a suspected transient change is detected in the low-speed channel, the PS side of the host determines the high-speed channel readback window parameters based on the low-speed change index and the ratio of the sampling rates of the high-speed channel and the low-speed channel. S9, the master sends a data read command containing UTC timestamp, channel number, relative sampling index and data point number to the slave through the communication unit. The slave's PS side reads the corresponding high-speed waveform data from the local DDR ring buffer according to the command and returns it to the master. S10: The PS side of the host performs normalization, filtering, differential analysis, and sliding window energy detection on the high-speed waveform data returned by itself and the slave to obtain the initial traveling wave head position of the fault and generate the fault detection result.

[0046] In S1, both the master and slave units use ZYNQ as the core for data acquisition and control. The PL side is used for traveling wave signal acquisition, data preprocessing, and buffer writing, while the PS side is used for parameter configuration, status control, communication scheduling, and fault detection. During system initialization, the PS side writes the sampling interval, moving average window length, bias value, buffer start address, and buffer capacity for each channel to the PL side through the configuration register. Let the... c The original sampling frequency of the analog-to-digital converter for each sampling channel is f ADC,c The extraction interval is D c The effective sampling frequency after extraction of this channel is... f c for: (1) By configuring different sampling intervals, the system can form data channels with different sampling rates. The low-speed channel is used for continuous fault prediction, while the high-speed channel is used for critical window readback and wavehead precision detection after a fault occurs.

[0047] In S2, the PL side captures parallel digital sampling data based on the data clock output by the analog-to-digital converter and selects between unsigned and signed data interpretation methods according to the configuration, converting the sampled data into a unified data format within the system. Simultaneously, the PL side receives an external PPS second pulse signal and performs edge detection on the PPS signal. When a rising edge of PPS is detected, the PPS flag is written into the flag bit of the corresponding sampled data; if no rising edge of PPS is detected, the flag bit remains invalid. Let the... cThe first channel in the n The original sampled values ​​at each sampling time point are x c [ n The PPS logo is... p [ n The sampled data marked with the PPS flag are... X c [ n This can be represented as: (2) in, p [ n ]=1 indicates that the current sampling point corresponds to the rising edge of PPS. p [ n ]=0 indicates that the current sampling point does not correspond to the rising edge of PPS. In this way, the sampled data stream contains not only traveling wave amplitude information, but also second-level time boundary information.

[0048] In S3, the PL side performs moving average, bias correction, and decimation processing on the sampled data. Let the... c The moving average window length for each channel is N c The sampled value after moving average is: (3) Let the first c The bias value of each channel is B c Then the bias-corrected data y c [ n ]for: (4) The bias-corrected data are processed according to the sampling interval. D c Extract the data to obtain the output data. Y c [ m ]: (5) in, m This is the sequence number of the extracted data. When the PPS flag is detected during the extraction process, the PL side resets the extraction count and forces the current data to be output, so that the extracted data still retains the PPS time stamp and avoids the loss of second boundary information due to extraction.

[0049] In S4, the PL side writes the processed sampled data into the DDR memory. Each sampling channel is configured with a corresponding cache start address and cache capacity. Let the... c The starting address of the DDR cache for each channel is A0,c The cache capacity is M c The number of bytes occupied by a single sampled data is q c The current sampling index is i The write address of the sampled data in DDR is then... A c [ i ]for: (6) When the write address reaches the end of the current channel cache area, the write address automatically wraps back to the start address of the channel cache to continue writing. If the data written in one go crosses the end of the cache area, the remaining space before the end of the cache is written first, and then the remaining data continues to be written from the start address of the cache. Through this circular caching method, the system can continuously store high-frequency traveling wave sampling data from the most recent period within the limited DDR space.

[0050] In S5, the PS side periodically reads the PPS validity status, the corresponding sampled byte count for PPS, and the current sampled transmitted byte count from the PL side. When a valid PPS signal is continuously detected, the system determines that the time synchronization signal is valid. Let UTC time... T j The corresponding PPS sample byte count is C c (T j The number of bytes occupied by a single sampled data is q c Then the sampling index corresponding to the UTC second boundary I c ( T j )for: (7) When it is necessary to read time relative to UTC T j Offset Δi When sampling data, its target sampling index I read,c for: (8) Corresponding DDR read address A read,c for: (9) Through the above mapping relationship, the PS side can accurately read waveform data within a specified time window from the DDR circular cache based on the UTC timestamp, relative sampling index, and number of data points.

[0051] In S6, the master unit coordinates transmission with the slave unit via local wireless communication. The master unit first confirms that its own and the slave unit's PPS status, acquisition status, and buffer status are all valid, and then reads the low-speed channel waveform data according to a unified UTC time. Assume there are a total of... K Several data acquisition devices participate in the collaborative transmission, including a host computer and... K-1 Taiwan from the machine, the first k The device in UTC time T j The low-speed channel data read below is: (10) Where NL represents the number of low-speed sampling points within a UTC time window. When the host reads its own low-speed data, it directly reads from the local DDR ring buffer based on the local UTC time index. When the host reads the slave's low-speed data, it sends a data read command to the slave containing the UTC timestamp, channel number, relative sampling index, and number of data points. After receiving the command, the slave reads the corresponding data from the local DDR ring buffer and returns it to the host.

[0052] In S7, the host performs fault prediction on the low-speed channel waveform data. First, the low-speed waveforms of the host and each slave are normalized. Let the... k The maximum and minimum values ​​of the low-speed waveform of the device within the current analysis window are respectively x max,k,L and x min,k,L Then its amplitude center μ k,L and amplitude scale α k,L They are respectively: (11) (12) Normalized low-speed waveform z k,L [ n ]for: (13) in, ε To prevent extremely small positive numbers with a denominator of zero, the normalized low-speed waveforms of the master and slave devices are then combined and superimposed to obtain the composite low-speed waveform. s L [ n ]: (14) Then, perform a first-order differential on the composite low-speed waveform to obtain the differential signal. d L [n ]: (15) Finally, the differential signal energy is calculated within a sliding window of a preset length. E L [ n ]: (16) in, W L This is the length of the low-speed detection window. When... E L [ n The first time the preset low-speed detection threshold was exceeded Θ L At that time, determine if there is a suspected initial transient change of fault within the current UTC time window, and record the corresponding low-speed change index: (17) In S8, when a suspected transient change is detected in the low-speed channel, the host determines the high-speed channel readback window based on the low-speed change index. Let the low-speed channel sampling rate be... f L High-speed channel sampling rate f H The expected mutation index in the high-speed channel is: (18) To ensure that all valid information before and after the initial fault wavefront is included in the readback data, let the number of pre-sampling points in the high-speed readback window be... N pre The number of post-sampling points is N post Then the high-speed channel reads the starting index. and the number of data points read N H They are respectively: (19) (20) When the read start index falls before the current UTC second, or when the read window crosses the DDR cache boundary, the system performs cross-window or segmented reads according to the UTC time index and the ring cache rules.

[0053] In S9, the host sends a high-speed waveform read command to the slave. The read command includes at least a UTC timestamp, channel number, relative sampling index, and number of data points. Upon receiving the read command, the slave determines the sampling index corresponding to the second boundary based on the UTC timestamp, then calculates the read address in the DDR ring cache using the relative sampling index and the number of data points, and reads the corresponding high-speed waveform data from its local DDR cache. k High-speed waveform data returned by the slave device x k,H [ n This can be represented as: (twenty one) in, n=0,1,……,N H -1 If the read data crosses the end of the buffer, the slave device reads the data in segments according to the circular buffer rule, combines the segments, and returns them to the master device. After receiving the high-speed waveform data returned by the slave device, the master device stores it in the data buffer of the corresponding device for subsequent high-speed waveform detection.

[0054] In S10, the host performs initial traveling wave front precision detection on the high-speed waveform data returned by itself and the slave devices. First, the high-speed waveforms of each device are normalized to obtain normalized high-speed waveforms. z k,H [ n Then, the normalized high-speed waveform is filtered to reduce low-frequency components and interference; subsequently, the filtered high-speed waveform is subjected to first-order differential processing to obtain the high-speed differential signal. d k,H [ n Finally, the differential signal energy is calculated within a sliding window of a preset length. E k,H [ n ]: (twenty two) in, W H This is the length of the high-speed detection window. When... E k,H [ n The first time the preset high-speed detection threshold was exceeded Θ H When, the corresponding position is determined as the first. k Initial traveling wavefront position detected by the device : (twenty three) The absolute index of the initial traveling wave head in the original high-speed sampling sequence for: (twenty four) Corresponding wavefront arrival time for: (25) The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the methods disclosed in the embodiments; relevant parts can be found in the method section.

[0055] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A transient traveling wave fault detection device combining low-speed prediction and high-speed backtracking, characterized in that, include: Several data acquisition devices are distributed at different measurement points on the power distribution line. Each data acquisition device is equipped with a sampling unit, a timing unit, a storage unit, and a communication unit. Each data acquisition device uses a ZYNQ on-chip system as the control core. The ZYNQ on-chip system includes a PL side and a PS side. The PL side is connected to the sampling unit, the timing unit and the storage unit respectively. It receives the high-frequency traveling wave sampling data output by the sampling unit, embeds the PPS second pulse flag output by the timing unit into the high-frequency traveling wave sampling data data stream to form sampling data with second-level time boundaries, performs preprocessing and splits the data streams to generate low-speed data stream and high-speed data stream, and writes the two data streams into the storage unit in a ring buffer manner. The PS side is connected to the PL side and the communication unit respectively, and a mapping relationship is established between the UTC timestamp and the sampling index of the ring buffer in the storage unit. The master-slave collaborative data interaction between the acquisition devices is realized through the communication unit. Based on the low-speed data stream, the fault transient change prediction is continuously performed. According to the mapping relationship, the high-speed data stream of the corresponding time window is read back to detect the fault and complete the accurate positioning of the initial traveling wave head of the fault.

2. The transient traveling wave fault detection device combining low-speed prediction and high-speed backtracking according to claim 1, characterized in that, The PL side includes an ADC configuration module, an ADC data receiving module, a PPS generation module, a configuration register module, a dual-channel parallel data processing link, and an AXI interconnect unit. The ADC configuration module is used to configure the working mode and sampling parameters of the sampling unit; The ADC data receiving module is used to capture high-speed parallel sampling data and write the PPS flag output by the PPS generation module into the flag bit of the corresponding sampling point; The configuration register module is used to implement parameter distribution and operation status feedback between the PS side and the PL side; The dual-path parallel data processing links correspond to low-speed data streams and high-speed data streams respectively. Each path includes a data management unit, a ring address scheduling unit, and a DMA transport unit, which respectively complete data preprocessing, ring cache address calculation, and high-speed data bus transport. The AXI interconnect unit is used to construct bus interaction paths between modules on the PL side, the PS side, and the storage unit.

3. The transient traveling wave fault detection device combining low-speed prediction and high-speed backtracking according to claim 1, characterized in that, The storage unit is a DDR memory, and each sampling channel corresponds to an independent cache start address and cache capacity. When writing data on the PL side, when the write address reaches the end of the current channel cache area, it automatically wraps back to the cache start address to continue writing. If a single write data crosses the end of the cache, it is written in segments and then spliced ​​together to form a continuous ring cache structure that can be overwritten and updated.

4. The transient traveling wave fault detection device combining low-speed prediction and high-speed backtracking according to claim 2, characterized in that, The PS side reads the PPS valid status, the corresponding sampled byte count and the current sampled transmission byte count fed back by the PL side configuration register module, calculates the sampling index corresponding to each UTC second boundary, establishes a one-to-one mapping relationship between UTC timestamp, sampling index and DDR read address, and supports precise reading of waveform data of a specified length according to the UTC time window.

5. The transient traveling wave fault detection device combining low-speed prediction and high-speed tracing according to claim 2, characterized in that, In a plurality of acquisition devices, one is the master and the rest are slaves. The master sends a data reading instruction to the slaves through a local wireless communication interface. The instruction includes a UTC timestamp, channel number, relative sampling index, and number of data points. After receiving the instruction, the slave reads the corresponding waveform data from the local circular buffer according to the mapping relationship and returns it to the master, thereby realizing time-aligned reading of data acquired by multiple acquisition devices.

6. A transient traveling wave fault detection method combining low-speed prediction and high-speed backtracking, applied to the transient traveling wave fault detection device combining low-speed prediction and high-speed backtracking as described in claims 1-5, characterized in that, include: S1, the PS side writes the analog-to-digital converter operating parameters, sampling channel parameters, moving average parameters, bias parameters, DDR cache start address and cache capacity to the ADC configuration module, data management unit and ring address scheduling unit on the PL side through the configuration register module, and starts the acquisition enable signal on the PL side; S2, the ADC data receiving module on the PL side acquires the digital value of the traveling wave signal output by the analog-to-digital converter, and the PPS generation module embeds the external PPS second pulse flag into the sampling data stream to form sampling data with second-level time boundary information. S3, the data management unit on the PL side preprocesses the sampled data and generates a low-speed data stream for continuous fault prediction and a high-speed data stream for fault wave head precision detection through dual-channel data processing link splitting; S4, the ring address scheduling unit of the dual data processing link calculates the cache write address of the two data streams respectively, and the corresponding DMA transfer unit writes the low-speed data stream and the high-speed data stream into the DDR memory through the AXI bus, and performs ring overwrite write according to the set cache start address and cache capacity. S5, the PS side reads the PPS valid status, the corresponding sampled byte count and sampled transmission byte count fed back by the configuration register module, and establishes the correspondence between the UTC timestamp and the DDR ring cache sampling index; S6, the host establishes a collaborative transmission link with the slave through the communication unit, and reads the low-speed channel waveform data of the host and all slaves according to the unified UTC time; S7, the PS side of the host performs normalization, superposition, differential and sliding window energy detection on the low-speed channel waveform data to determine whether there is a suspected fault initial transient change. S8, when a suspected transient change is detected in the low-speed channel, the PS side of the host determines the high-speed channel readback window parameters based on the low-speed change index and the ratio of the sampling rates of the high-speed channel and the low-speed channel. S9, the master sends a data read command containing UTC timestamp, channel number, relative sampling index and data point number to the slave through the communication unit. The slave's PS side reads the corresponding high-speed waveform data from the local DDR ring buffer according to the command and returns it to the master. S10: The PS side of the host performs normalization, filtering, differential analysis, and sliding window energy detection on the high-speed waveform data returned by itself and the slave to obtain the initial traveling wave head position of the fault and generate the fault detection result.

7. The transient traveling wave fault detection method combining low-speed prediction and high-speed backtracking according to claim 6, characterized in that, When the data management unit in S3 performs extraction processing on the sampled data, if it detects the PPS flag in the sampled data, it resets the extraction count and forces the output of the current sampling point data, so that the extracted low-speed data stream retains complete PPS time boundary information.

8. The transient traveling wave fault detection method combining low-speed prediction and high-speed backtracking according to claim 6, characterized in that, When the ring address scheduling unit in S4 performs address scheduling, when the write address reaches the end of the current channel buffer area, it automatically wraps back to the start address of the buffer to continue writing; if the data written in a single operation crosses the end of the buffer area, the remaining space before the end of the buffer is written first, and then the remaining data is written from the start address of the buffer.

9. The transient traveling wave fault detection method combining low-speed prediction and high-speed backtracking according to claim 6, characterized in that, In S5, the PS side determines the UTC second boundary based on the continuously detected valid PPS signals, calculates the sampling index corresponding to each UTC second boundary, and establishes a one-to-one mapping relationship between the UTC timestamp, the relative sampling index, and the DDR read address.

10. The transient traveling wave fault detection method combining low-speed prediction and high-speed backtracking according to claim 6, characterized in that, In step S8, the low-speed mutation index is converted into the expected mutation index in the high-speed channel based on the ratio of the low-speed channel sampling rate to the high-speed channel sampling rate. Based on the expected mutation index, the number of pre-sampling points and the number of post-sampling points are set respectively to determine the starting index and the total number of reading points for high-speed data. If the reading window crosses the DDR cache boundary or the UTC second boundary, the data is read in segments and spliced ​​according to the ring cache rule.

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