Low cost, high precision, and standards compliant isolation parameter test system and method for semiconductor devices

Abstract

A system (100) includes a socket (108) having first and second terminals (115, 116) configured to connect to respective terminals of an electronic device (118), an AC voltage source (114) having a first output coupled to the first terminal (115) and a second output coupled to a reference node (117), a first circuit (120) having a high pass filter (121) coupled between the second terminal (116) and a first analog-to-digital converter (ADC) (123), a second circuit (130) having a low pass filter (132) coupled between the second terminal (116) and a second ADC (133), a third circuit (140) having another high pass filter (141) coupled between the second terminal (116) and a third ADC (143), and a processor (113) to determine partial discharge based on samples from the first ADC (123), to determine leakage current based on samples from the second ADC (133), and to determine arc current based on samples from the third ADC (143).

Description

Technical Field

[0001] This application generally relates to electronic devices, and more specifically, to test systems and methods for semiconductor devices. Background Technology

[0002] Manufacturing electronic devices such as integrated circuits and high-voltage isolation devices often requires testing for standards verification. For example, compliance with IEC 60747-17, VDE 0884-17, and UL 1577 requirements necessitates measuring partial discharge, leakage current, arcing, and operating (stress) voltage of semiconductor devices before shipment to customers. Isolation testing for each device significantly increases testing costs, and current solutions use separate measuring equipment for each test. This results in longer testing times and increased capital expenditure to support standards verification of electronic devices with high-voltage isolation characteristics. Summary of the Invention

[0003] In one aspect, a system includes: a socket having a first socket terminal and a second socket terminal configured to be connected to corresponding first and second terminals of an electronic device; an AC voltage source having a first output terminal coupled to the first socket terminal and a second output terminal coupled to a reference node; a first circuit having a first high-pass filter coupled between the second socket terminal and a first analog-to-digital converter (ADC); a second circuit having a low-pass filter coupled between the second socket terminal and a second ADC; a third circuit having a second high-pass filter coupled between the second socket terminal and a third ADC; and a processor connected to the outputs of the respective first, second, and third ADCs, the processor being configured to determine partial discharge of the electronic device based on samples from the first ADC, leakage current of the electronic device based on samples from the second ADC, and arc current of the electronic device based on samples from the third ADC.

[0004] In another aspect, a contactor interface board for testing an electronic device mounted in a socket includes: an AC voltage source having a first output terminal coupled to a first socket terminal and a second output terminal coupled to a reference node; a first circuit having a first high-pass filter coupled between a second socket terminal and a first analog-to-digital converter (ADC); a second circuit having a low-pass filter coupled between the second socket terminal and a second ADC; a third circuit having a second high-pass filter coupled between the second socket terminal and a third ADC; and a processor connected to the outputs of the respective first, second, and third ADCs, the processor being configured to determine partial discharge of the electronic device based on samples from the first ADC, leakage current of the electronic device based on samples from the second ADC, and arc current of the electronic device based on samples from the third ADC.

[0005] In another aspect, a method includes: applying an AC input signal to a first socket terminal of a socket; determining a partial discharge of an electronic device installed in the socket based on a high-pass filter voltage of a second socket terminal in response to applying the AC input signal to the first socket terminal; and determining a leakage current of the electronic device based on a low-pass filter voltage of the second socket terminal in response to determining the partial discharge, in response to applying the AC input signal to the first socket terminal. Attached Figure Description

[0006] Figure 1 This is a perspective view of a manufacturing test system used to test the electrical operating parameters of electronic devices.

[0007] Figure 1A yes Figure 1 A schematic diagram of the contactor interface board and load board of the system.

[0008] Figure 1B yes Figure 1 A perspective view of the contactor interface board and the mounted load board in the system.

[0009] Figure 2 It is a flowchart of an electronic device manufacturing method that includes testing of electronic devices based on concurrent signal processing.

[0010] Figure 3 This is a graph of the output signal of an example device under test (DUT).

[0011] Figure 4 yes Figure 1 A graph of an example partial discharge waveform in the system.

[0012] Figure 5 yes Figure 1 A graph showing an example leakage current waveform in the system.

[0013] Figure 6 yes Figure 1 A graph of an example electric arc waveform in the system. Detailed Implementation

[0014] In the figures, the same reference numerals refer to the same elements throughout, and the various features are not necessarily drawn to scale. Furthermore, the term "coupling" includes indirect or direct electrical or mechanical connections, or combinations thereof. For example, if a first device is coupled to or with a second device, the connection can be a direct electrical connection or an indirect electrical connection via one or more intervening devices and connections. The following describes one or more operational characteristics of various circuits, systems, and / or components in the context of function, which in some cases arise from the configuration and / or interconnection of various structures when the circuit system is energized and operated. Example structures include layers or materials described as being on or above another layer or material, which can be directly on and in contact with the other layer or material, wherein other materials (e.g., impurities or man-made products or residual materials from manufacturing processes) may be present between the layer or material and the other layer or material.

[0015] Unless otherwise stated, the words “about,” “approximately,” or “generally” preceding a value mean + / - 10% of the stated value. For ease of description in conjunction with specific drawings, one or more structures, features, aspects, components, etc., may be referred to herein as first, second, third, etc., such as first and second terminals, etc., but these should not be construed as limiting the claims. The various structures and methods disclosed herein can be advantageously applied to the manufacture of electronic devices, such as integrated circuits. While such examples may provide various improvements, this disclosure does not require a particular result unless expressly stated in a specific claim.

[0016] Figure 1-1B An electronic device manufacturing test system 100 is shown for testing the electrical operating parameters of electronic devices. Figure 1 A top perspective view of a test system 100 with a central controller 102 mounted on a turntable 103 is shown. A side-mounted motor driver 104 positions a turntable handler 106, which automatically installs and removes electronic devices (also referred to as devices under test or DUTs) from device sockets 108 or corresponding contactor interface boards 110 (CIBs). Figure 1BAs further shown, load plate 111 is mounted in each of the other CIBs 110. The example system 100 has 16 units, each with a corresponding CIB 110, load plate 111, and device socket 108, to accommodate the simultaneous testing of 16 electronic devices. Unlike existing test systems that require long cable connections (e.g., approximately 2 meters in length) from the test equipment to each individual DUT, the example system 100 provides automated socket insertion and removal, wherein a turntable 103 can rotate about a central axis to perform retrieval from the 16 simultaneous DUTs in loading positions and to perform rotation to align with the DUT socket 108 for automatically installing the electronic device for testing in the corresponding one of the CIBs 110.

[0017] System 100 also provides simultaneous testing or measurement of all isolation parameters at once, with 16 DUTs tested in parallel. This system configuration significantly reduces device testing time, thereby reducing device manufacturing costs. Furthermore, the example system 100 eliminates cable connections present in conventional test setups and provides close proximity between the device under test and the associated measurement circuitry to reduce adverse effects such as attenuation and noise associated with long cables used for partial discharge and other isolation tests, thus providing low-noise measurements with high accuracy and a high signal-to-noise ratio (SNR).

[0018] Figure 1A A schematic diagram of an example CIB 110 of the test system 100 and a mounted load board 111 is shown. The CIB 110 includes a device socket 108 having a first socket terminal 115 and a second socket terminal 116. In the example shown, the socket 108 has two rows of eight socket terminals configured to individually engage with corresponding device terminals along two opposite sides of an electronic device under test (DUT) 118 mounted in the socket 108. In the example shown, the terminals of each row of the socket 108 are electrically connected to each other to provide a first terminal connection 115 for connection to a first row of device leads of the mounted electronic device (DUT) 118 and a second terminal connection 116 for connection to a second row of device leads. In other embodiments, the socket 108 may have a different number of pins, wherein the first socket terminal 115 and the second socket terminal 116 are configured to connect to corresponding first and second terminals of the mounted electronic device 118.

[0019] AC voltage source 114 has a first output terminal coupled to a first socket terminal 115 and a second output terminal coupled to a reference node 117. In one example, reference node 117 may be the ground or common terminal of test system 100, but this is not a requirement for all possible implementations. In one example, the AC voltage source is connected to turntable handler 106 ( Figure 1The AC voltage source 114 is connected to the power supply of the CIB 110 and provides an AC voltage signal across the first and second output terminals. The AC voltage signal can be a sinusoidal or other AC signal waveform and may contain one or more spikes. In another embodiment, the AC voltage source 114 may be external to the CIB 110, and the CIB 110 may include terminal connections to allow the external AC voltage source 114 to be connected to the first terminal connection 115 and the reference node 117.

[0020] In one example of operation, AC voltage source 114 is configured to apply an AC input signal to a first terminal connection 115 (e.g., a voltage signal at a second output terminal referenced by AC voltage source 114 to a reference node 117). In one embodiment, AC voltage source 114 is configured to apply an AC input signal with a single amplitude, such as a high-frequency AC signal with or without spikes, having a single amplitude (e.g., within 10% of a specified RMS or peak-to-peak amplitude). In this embodiment or another embodiment, AC voltage source 114 is configured to apply an AC input signal with spikes to facilitate partial discharge testing. In one example, the spikes are superimposed on an AC waveform that would otherwise have an approximately constant amplitude.

[0021] Test system 100 advantageously applies a single AC input signal to DUT 118 and simultaneously filters and measures the response signal using multiple specially customized circuits 120, 130, and 140 in CIB 110 to obtain multiple measurement results for evaluating multiple operating parameters associated with the isolation performance of the DUT 118 in a single test. This provides significant cost savings in accelerating manufacturing production testing compared to conventional isolation test methods, which typically apply multiple separate AC input signals in a separately cable-connected test setup to perform individual measurements at once.

[0022] The CIB 110 in the example shown includes a first high-pass filter 121 (e.g., in...). Figure 1AA first circuit 120 (labeled "HPF") is described. A first high-pass filter 121 is coupled between a second socket terminal 116 and a first analog-to-digital converter 123 (e.g., labeled "ADC"). In this example, the first circuit 110 has a differential amplifier 122 coupled between the output of the first high-pass filter 121 and the input of the first analog-to-digital converter 123, but this is not a requirement for all possible implementations. The input of the first high-pass filter 121 is coupled to the second socket terminal 116, and the output of the first high-pass filter 121 is configured to provide a first high-pass filtered signal to the input of the differential amplifier 122 (e.g., or directly to the input of the first analog-to-digital converter 123) based on the voltage signal at the second socket terminal 116, in response to an AC input signal from the first socket terminal 115 of the AC voltage source 114. In one example, the first high-pass filter 121 has a cutoff frequency of approximately 1 MHz or greater.

[0023] The first analog-to-digital converter 123 has a clock circuit 124 coupled to receive a clock signal from the CIB 110 (e.g., in...). Figure 1A The clock input is marked "CLK". The first analog-to-digital converter 123 has a data output that provides digital samples of the received first high-pass filtered signal. Figure 1A As further shown, the load board 111 includes a power supply 112 and a processor (e.g., labeled "MCU"). The output of the first analog-to-digital converter 123 is coupled to the input of the processor 113 to provide a sample of the first high-pass filtered signal for processing and evaluation to determine the partial discharge performance of the DUT 118 under test.

[0024] like Figure 1A As further shown, CIB 110 in this example also includes a charge harvesting circuit 126 with a capacitor 128 configured to harvest charge in response to a partial discharge event associated with the DUT 118 under test. The capacitor 128 has an upper portion or first capacitor terminal coupled to a first socket terminal 115 and a lower portion or second capacitor terminal coupled to a reference node 117. A first high-pass filter 121 of the first circuit 120 filters the voltage signal at the second socket terminal 116 (e.g., the voltage at the first capacitor terminal of capacitor 128). The processor 113 receives samples of the first filtered signal from the first analog-to-digital converter 123 and is configured to determine the partial discharge of the electronic device 118 based on the samples from the first analog-to-digital converter 123, as described below. Figure 2-4 Further description.

[0025] Example CIB 110 includes a second circuit 130 with a first low-pass filter 132 coupled between a second socket terminal 116 and a second analog-to-digital converter 133. The input of the first low-pass filter 132 is coupled to the second socket terminal 116. The output of the first low-pass filter 132 is configured to provide a first low-pass filtered signal to the input of the second analog-to-digital converter 133 based on a voltage signal at the second socket terminal 116, in response to an AC input signal at the first socket terminal 115. In one example, the first low-pass filter 132 has a cutoff frequency of approximately 100 Hz or less.

[0026] CIB 110 also includes a leakage sensing circuit 139 with a resistor 138 for measuring leakage current. Resistor 138 has a first resistor terminal coupled to a second socket terminal 116 and a second resistor terminal coupled to a reference node 117. In response to an AC input signal applied by an AC voltage source 114, the resistor generates a voltage at the first resistor terminal based on the leakage current flowing from DUT 118.

[0027] The second analog-to-digital converter 133 has a clock input coupled to receive a clock signal from the clock circuit 124. The second analog-to-digital converter 133 has a data output that provides digital samples of a first low-pass filtered signal received from the first low-pass filter 132. The output of the second analog-to-digital converter 133 is coupled to the input of the processor 113 to provide samples of the first low-pass filtered signal. The processor 113 is configured to determine the leakage current of the electronic device 118 based on the samples from the second analog-to-digital converter 133, as described below. Figure 2 and 5 Further description.

[0028] Figure 1A CIB 110 also includes a third circuit 140 for arc detection. The third circuit 140 has a second high-pass filter 141 coupled between a second socket terminal 116 and a third analog-to-digital converter 143. In one example, the second high-pass filter 141 has a cutoff frequency of approximately 1 MHz or higher, for example, approximately 10 MHz or higher in one embodiment. The input of the second high-pass filter 141 is coupled to the second socket terminal 116. The output of the second high-pass filter 141 is configured to provide a second high-pass filtered signal to the input of the third analog-to-digital converter 143 based on a voltage signal at the second socket terminal 116, in response to an AC input signal at a first socket terminal 115.

[0029] In the illustrated example, the third circuit 140 has a differential amplifier 142 coupled between the output of the second high-pass filter 141 and the input of the third analog-to-digital converter 143. The second high-pass filter 141 provides the second high-pass filtered signal directly to the third analog-to-digital converter 143 or to the input of the differential amplifier 142. The third analog-to-digital converter 143 has a data output that, in response to an applied AC signal from the AC voltage source 114, provides digital samples of the received second high-pass filtered signal to a processor 113 on the load board 111 for arc detection. The processor 113 is connected to the output of the third analog-to-digital converter 143. The processor 113 is configured to determine the arc current of the electronics 118 based on the samples from the third analog-to-digital converter 143, as described below. Figure 2 and 6 Further discussion.

[0030] In one example, CIB 110 also includes clamping circuitry 146 coupled between a second receptacle terminal 116 and a reference node 117. Processor 113 is configured to determine the arc current of electronic device 118 based on the high-pass filtered voltage of clamping circuitry 146 in response to an AC input signal being applied to first receptacle terminal 115. The input of a second high-pass filter 141 is coupled to clamping circuitry 146. Any suitable clamping circuitry 146 can be used. Figure 1A The clamping circuit 146 in the illustrated example includes a corresponding first diode 147 and a second diode 148 connected in series between the second socket terminal 116 and the reference node 117. In one example, the first diode 147 and the second diode 148 each have a Zener diode connected in series with each other. In this example, the first diode 147 has a corresponding cathode coupled to each other, a first anode connected to the second socket terminal 116, and another anode connected to a tap node 149 between the first diode 147 and the second diode 148. The second diode 148 in the illustrated example includes another pair of Zener diodes connected in series, which have corresponding anodes coupled to each other, a first cathode connected to the tap node 149, and a second cathode connected to the reference node 117. The input of the second high-pass filter 141 of the third circuit 140 is coupled to the tap node 149. In operation, the clamping circuit 146 provides clamping to protect the second socket terminal 116 from significant overvoltage conditions, and the clamping circuit tap node 149 is used to measure arcs.

[0031] like Figure 1AAs further shown, the second circuit 130 may also include additional circuitry to measure the DUT stress voltage (also known as the operating voltage) in response to an AC input signal applied by the AC voltage source 114. In one example, the second circuit 130 of the CIB 110 includes a second low-pass filter 134 coupled between the first socket terminal 115 and the fourth analog-to-digital converter 135. In one example, the second low-pass filter 134 has a cutoff frequency of approximately 100 Hz or less. The second low-pass filter 134 has an output that provides a second low-pass filtered signal to the input of the fourth analog-to-digital converter 135. In this example, the CIB 110 also includes capacitive voltage divider circuits 136, 137, which have one or more upper capacitors 136 and one or more lower capacitors 137 to form a capacitive voltage divider circuit. The capacitors 136 and 137 are coupled in series with each other between the first socket terminal 115 and the reference node 117. The tap node 131 of the capacitive voltage divider circuits 136, 137 is coupled to the input of the second low-pass filter 134. Any suitable tap point can be used between the two adjacent capacitors in the capacitive voltage divider circuits 136 and 137. In one example, processor 113 is configured to determine the stress or operating voltage of DUT 118 based on samples from the fourth analog-to-digital converter 135, as described below. Figure 2 and 5 Further description.

[0032] In response to a single applied AC input signal from AC voltage source 114, the circuitry 120, 130, 140 of CIB 110 advantageously performs two or more isolation parameter measurements of the DUT 118 under test simultaneously. The illustrated example measures an electrical signal from the second socket terminal 116 (e.g., and in some examples also from input capacitor divider circuits 136, 137), and the measured signal is selectively filtered to split the sensed signal in the frequency domain, thereby obtaining multiple measurements in parallel (e.g., simultaneously and / or concurrently). Processor 113 obtains digital samples from multiple analog-to-digital converters 123, 133, 135, and / or 143 and performs one or more evaluations of the samples to determine any two or more parameters, such as partial discharge, leakage current, stress (e.g., operating) voltage, and / or arc detection, or other operating parameters of the DUT 118 under test.

[0033] Figure 1-1B Example system 100 can be adapted to a corresponding contactor interface board 110 (e.g., Figure 1The device can perform parallel testing on up to 16 DUTs 118, with each parallel test generating multiple concurrent measurements, thereby significantly accelerating device testing during manufacturing. In some examples, AC voltage source 114 provides an AC input signal to first socket terminal 115, and analog-to-digital converters 123, 133, 135, and 143 simultaneously sample the filtered signals of the corresponding first circuit 120, second circuit 130, and third circuit 140 in response to the AC input signal at the first socket terminal 115.

[0034] In addition, such as Figure 1 and 1B As shown, example CIB 110 is a compact circuit board (e.g., approximately 50 mm x 370 mm) with integrated filtering and other measurement circuitry, as well as one or more analog-to-digital converters. In other embodiments, two or more of the analog-to-digital converters 123, 133, 135, and 143 can be combined, for example, using a high-speed analog multiplexer circuitry to receive the filtered signals from circuits 120, 130, and 140, wherein the multiplexer selectively couples a selected one of the multiple filtered signals to the input of a shared analog-to-digital converter. In one example, processor 113 calculates various test parameters for the DUT 118 and reports pass and / or fail results for each individual DUT 118's test parameters. The CIB circuitry system occupies a small area and does not use any external measurement equipment to facilitate extremely parallel testing, with some examples reducing testing costs by five times or more compared to previous solutions requiring separate measurement equipment. Furthermore, the described examples can be easily scaled up to further reduce testing costs and increase testing speed.

[0035] In one example, individual CIB 110 includes an AC voltage source 114, a first circuit 110 having a first high-pass filter 121 coupled between a second socket terminal 116 and a first analog-to-digital converter 123, a second circuit 130 having a first low-pass filter 132 coupled between a second socket terminal 116 and a second analog-to-digital converter 133, and a third circuit 140 having a second high-pass filter 141 coupled between a second socket terminal 116 and a third analog-to-digital converter 143, and a processor 113 connected to the outputs of the respective first, second, and third analog-to-digital converters 123, 133, 135, and 143. The processor 113 determines partial discharge of electronic device 118 based on samples from the first analog-to-digital converter 123, leakage current of electronic device 118 based on samples from the second analog-to-digital converter 133, and arc current of electronic device 118 based on samples from the third analog-to-digital converter 143.

[0036] See also Figure 2-6 , Figure 2An example electronic device manufacturing method 200 is shown, which includes electronic testing and device classification based on the simultaneous measurement of multiple electrical operating parameters. Figure 3-6 An example signal in the waveform of an embodiment of system 100 is shown. (Refer to the above in conjunction with...) Figure 1-1B The test system 100 is described to describe the method 200.

[0037] Method 200 in Figure 2 Starting at point 202, an AC input signal is applied to the first socket terminal 115 of socket 108. In one example, AC voltage source 114 applies the AC input signal at 202 with a single amplitude. In this example or another example, AC voltage source 114 applies an AC input signal with spikes for partial discharge testing, but this is not a requirement for all possible implementations. In some implementations, AC voltage source 114 applies a single AC input signal with an approximately constant amplitude for a sufficient time to allow circuits 120, 130, and 140 to filter and sample the resulting signals at the second socket terminal 116 and the capacitor divider tap node 131 to facilitate simultaneous testing of two or more parameters associated with the isolation performance of DUT 118.

[0038] Method 200 illustrates an example implementation comprising simultaneously determining the partial discharge of DUT 118 at locations 204-208, the leakage current of DUT 118 at locations 210-214, the stress voltage of DUT 118 at locations 220-224, and the arc current of DUT 118 at locations 230-234, followed by determining a pass or fail result of DUT 118 at location 240. The simultaneous measurement and parameter determination are performed at the local CIB 110 and load board 111 at each station of a multi-station system, such as... Figure 1-1B The 16-station system 100.

[0039] Regarding partial discharge measurement and testing, Method 200 is included in Figure 2 At position 204, the DUT output signal is high-pass filtered (e.g., using...). Figure 1A The first high-pass filter 121 in the circuit, for example, high-pass filters the voltage at the upper terminal of the discharge capacitor (e.g., circuit 126). At 206, the partial discharge measurement includes, for example, using... Figure 1A The first analog-to-digital converter 123 samples the first high-pass filtered signal from the output of the first high-pass filter 121.

[0040] At 208, method 200 includes determining partial discharge of the installed electronic device or DUT 118 based on a high-pass filtered voltage of the second socket terminal 116 (e.g., using the processor 113 of the load board 111) in response to applying an AC input signal to the first socket terminal 115 at 202. Figure 3 A graph 300 is shown of an example device under test (DUT) output signal 301, which includes a negative spike 302 corresponding to a partial discharge event associated with DUT 118. Figure 4 It shows having Figure 1 The graph 400 shows an example partial discharge waveform 401 with a spike 402 in the system. In one example, waveform 401 corresponds to a first high-pass filtered signal provided at the output of the first high-pass filter 121 and the first circuit 120, which is buffered by the differential amplifier 122 and... Figure 1A The first analog-to-digital converter 123 samples the data. In one embodiment, the processor 113... Figure 2 At point 208, samples from the first analog-to-digital converter 123 are evaluated, and the peak amplitudes of spike 402 and waveform 401 are determined, which represent the peak partial discharge current of the DUT 118 in response to the applied AC input signal from AC voltage source 114.

[0041] Method 200 includes measuring and determining leakage current simultaneously with determining partial discharge. Figure 2 At position 210, one example includes low-pass filtering of the DUT output signal from the resistor (e.g., Figure 1A The resistor 138 in the circuit uses a first low-pass filter 132. The first low-pass filtered signal is sampled at 212 (e.g., using a second analog-to-digital converter 133). At 214, in response to an AC input signal applied to the first socket terminal 115, the DUT leakage current is determined based on a sample of the first low-pass filtered voltage signal at the second socket terminal 116 (e.g., using a processor 113). Figure 5 It shows having Figure 1 The example leakage current waveform 501 in the system is shown in graph 500. In one example, wafer 501 corresponds to the leakage current from... Figure 1A The first low-pass filtered signal of the first low-pass filter 132 is sampled at 212 by the second analog-to-digital converter 133. In one example, the processor 113 samples the first low-pass filtered signal at 214 based on the amplitude of the first low-pass filtered signal (e.g., ...). Figure 5 The curve 501 in the figure is used to determine the leakage current of the DUT, the amplitude of which represents the measured value. Figure 1A The leakage current of DUT 118 is the voltage across the sensing resistor 138.

[0042] In some examples, Figure 2 Method 200 also includes determining the DUT stress voltage at 220-224, which is performed simultaneously with any included leakage current and partial discharge measurements. At 220, method 200 includes low-pass filtering the DUT input signal from the capacitive voltage divider circuit (e.g., using...). Figure 1A The second low-pass filter 134 in the capacitor divider performs low-pass filtering on the signal at tap node 131 of capacitor dividers 136 and 137. Figure 2 At 222, method 200 includes sampling the second low-pass filtered signal using a fourth analog-to-digital converter 135. At 224, processor 113, in response to an AC input signal applied to a first socket terminal 115, determines the DUT stress voltage based on the second low-pass filtered voltage at the first socket terminal 115. In one example, the second low-pass filtered signal from the second low-pass filter 134 has an amplitude representing the operating voltage or stress voltage of the DUT 118 applied to the first socket terminal 115 during testing.

[0043] In some implementations, method 200 also includes Figure 2 The current at positions 230-234 is determined. At position 230, for example, using... Figure 1A The second high-pass filter 141 of the third circuit 140 performs high-pass filtering on the clamping output signal from the clamping voltage divider circuit 146. The second high-pass filter 141 provides the second high-pass filtered signal through any included differential amplifier 142 or directly to the input of the third analog-to-digital converter 143, which in... Figure 2 At position 232, the second high-pass filtered signal is sampled. At position 234, the processor 113, in response to applying an AC input signal to the first socket terminal 115, determines the arc current of the DUT 118 based on the high-pass filtered voltage of the clamping circuit 146. Figure 6 It shows Figure 1 A graph 600 of an example arc waveform 601 in system 100 has a spike 602 representing a second high-pass filtered signal sampled by a third analog-to-digital converter 143. In one example, processor 113 evaluates samples from the third analog-to-digital converter 143 and detects the presence of spike 602. In one embodiment, processor 113 determines whether the sampled second high-pass filtered signal exceeds a certain threshold, and if so, identifies the test as having an arcing event and determines the level of peak 602 as corresponding to the peak arc current experienced by DUT 118 during the test.

[0044] The described example provides a high-speed, highly parallel test system 100, a contactor interface board 110, and a method 200, which can be advantageously used to reduce test time in electronic device manufacturing by simultaneously measuring multiple parameters associated with the isolation performance of the device under test (DUT). Furthermore, the described example facilitates improved measurement accuracy by directly integrating circuits 120, 130, 140, 126, 136, and 146 onto the contactor interface board without any lengthy cable connections during testing. Integrating the measurement circuitry into the CIB 110 provides close proximity to the DUT 118 and avoids or mitigates inaccuracies associated with partial discharge of cables used in conventional test equipment. These and other advantages provide cost savings during electronic device manufacturing, as well as low signal-to-noise ratio measurements without the noise and attenuation associated with test cables in existing systems. Other benefits may include the ability to reduce calibration frequency and test system downtime due to the higher accuracy achieved by the described system 100. In some embodiments, this downtime reduction can be, for example, five times or more. Furthermore, the described system performs multiple measurements using a single interface circuit 110 by separating one or more runaway modes into multiple different frequency domains, while significantly reducing the overall system component size, resulting in lower capital expenditure for the test equipment compared to existing technologies. In addition, the described system provides robust and thorough evaluation of devices compliant with multiple standards (e.g., IEC 60747-17, VDE 0884-17, UL1577, etc.).

[0045] Within the scope of the claims, modifications may be made to the described examples, and other embodiments are possible.

Claims

1. A system comprising: A socket having a first socket terminal and a second socket terminal configured to connect to corresponding first and second terminals of an electronic device; An AC voltage source having a first output terminal coupled to the first socket terminal and a second output terminal coupled to the reference node; A first circuit having a first high-pass filter coupled between the second socket terminal and the first analog-to-digital converter; The second circuit has a low-pass filter coupled between the second socket terminal and the second analog-to-digital converter; The third circuit has a second high-pass filter coupled between the second socket terminal and the third analog-to-digital converter; as well as A processor connected to the outputs of the respective first analog-to-digital converter, the second analog-to-digital converter, and the third analog-to-digital converter is configured to determine the partial discharge of the electronic device based on samples from the first analog-to-digital converter, the leakage current of the electronic device based on samples from the second analog-to-digital converter, and the arc current of the electronic device based on samples from the third analog-to-digital converter.

2. The system of claim 1, wherein the AC voltage source is configured to provide an AC input signal to the first socket terminal, and the first analog-to-digital converter, the second analog-to-digital converter, and the third analog-to-digital converter simultaneously sample the filtered signals of the respective first circuit, the second circuit, and the third circuit in response to the AC input signal at the first socket terminal.

3. The system of claim 1, wherein the first circuit has a differential amplifier coupled between the output of the first high-pass filter and the input of the first analog-to-digital converter.

4. The system of claim 3, wherein the input of the first high-pass filter is coupled to the second socket terminal, and the output of the first high-pass filter is configured to provide a first high-pass filtered signal based on a voltage signal at the second socket terminal in response to an AC input signal at the first socket terminal.

5. The system of claim 1, wherein the first high-pass filter has a cutoff frequency of approximately 1 MHz or higher.

6. The system of claim 1 further includes a capacitor having a first capacitor terminal coupled to the first socket terminal and a second capacitor terminal coupled to the reference node.

7. The system of claim 1, wherein the input of the low-pass filter is coupled to the second socket terminal, and the output of the low-pass filter is configured to provide a low-pass filtered signal based on a voltage signal at the second socket terminal in response to an AC input signal at the first socket terminal.

8. The system of claim 7 further includes a resistor having a first resistor terminal coupled to the second socket terminal and a second resistor terminal coupled to the reference node.

9. The system according to claim 1, wherein: The low-pass filter is a first low-pass filter; and The system also includes a capacitive voltage divider circuit coupled between the first socket terminal and the reference node; The second circuit includes a second low-pass filter coupled between the capacitor divider circuit and the fourth analog-to-digital converter; The processor is connected to the output of the fourth analog-to-digital converter; and The processor is configured to determine the stress voltage of the electronic device based on samples from the fourth analog-to-digital converter.

10. The system of claim 9, wherein the second low-pass filter has a cutoff frequency of approximately 100 Hz or less.

11. The system of claim 1, wherein the low-pass filter has a cutoff frequency of approximately 100 Hz or less.

12. The system of claim 1, wherein the third circuit has a differential amplifier coupled between the output of the second high-pass filter and the input of the third analog-to-digital converter.

13. The system of claim 1, wherein the second high-pass filter has a cutoff frequency of approximately 1 MHz or higher.

14. The system of claim 1, further comprising a clamping circuit coupled between the second socket terminal and the reference node, wherein the input of the second high-pass filter is coupled to the clamping circuit.

15. The system of claim 14, wherein the clamping circuit comprises a first diode and a second diode connected in series between the second socket terminal and the reference node, and the input of the second high-pass filter is coupled to a tap point between the first diode and the second diode.

16. A contactor interface board for testing electronic devices installed in a socket, comprising: An AC voltage source having a first output terminal coupled to a first socket terminal and a second output terminal coupled to a reference node; A first circuit having a first high-pass filter coupled between a second socket terminal and a first analog-to-digital converter; The second circuit has a low-pass filter coupled between the second socket terminal and the second analog-to-digital converter; The third circuit has a second high-pass filter coupled between the second socket terminal and the third analog-to-digital converter; as well as A processor connected to the outputs of the respective first analog-to-digital converter, the second analog-to-digital converter, and the third analog-to-digital converter is configured to determine the partial discharge of the electronic device based on samples from the first analog-to-digital converter, the leakage current of the electronic device based on samples from the second analog-to-digital converter, and the arc current of the electronic device based on samples from the third analog-to-digital converter.

17. A method comprising: Apply the AC input signal to the first socket terminal of the socket; In response to the application of the AC input signal to the first socket terminal, partial discharge of the electronic device installed in the socket is determined based on the high-pass filtered voltage of the second socket terminal; as well as While determining the partial discharge, in response to applying the AC input signal to the first socket terminal, the leakage current of the electronic device is determined based on the low-pass filter voltage of the second socket terminal.

18. The method of claim 17, further comprising: While determining the partial discharge and the leakage current, in response to applying the AC input signal to the first socket terminal, the arc current of the electronic device is determined based on the high-pass filter voltage of the clamping circuit coupled between the second socket terminal and the reference node.

19. The method of claim 18, further comprising: The voltage of the clamping circuit is high-pass filtered at a cutoff frequency of approximately 1 MHz or higher.

20. The method of claim 18, further comprising: While determining the partial discharge and the leakage current, in response to applying the AC input signal to the first socket terminal, the stress voltage of the electronic device is determined based on the low-pass filter voltage of the first socket terminal.

21. The method of claim 20, further comprising low-pass filtering the voltage of the first socket terminal at a cutoff frequency of approximately 100 Hz or less.

22. The method of claim 17, further comprising: The voltage at the second socket terminal is high-pass filtered at a cutoff frequency of approximately 1 MHz or higher to provide a high-pass filtered signal; The partial discharge of the electronic device is determined based on the high-pass filtered signal; The voltage at the second socket terminal is low-pass filtered at a cutoff frequency of approximately 100 Hz or lower to provide a low-pass filtered signal; as well as The leakage current of the electronic device is determined based on the low-pass filtered signal.

23. The method of claim 17, further comprising: While determining the partial discharge and the leakage current, in response to applying the AC input signal to the first socket terminal, the stress voltage of the electronic device is determined based on the low-pass filter voltage of the first socket terminal.

24. The method of claim 17, further comprising applying the AC input signal at a single amplitude.

25. The method of claim 24, further comprising applying the AC input signal having spikes for partial discharge testing.

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