Chip delamination method and apparatus

Abstract

The application provides a chip fault layering method and device, wherein the method first acquires wafer-in-process test data, end-of-line test data, burn-in test data and equipment working condition data of a chip; then performs data format uniform processing and alignment according to a process time sequence of chip manufacturing and testing to obtain full-process data records indexed by a unique identifier of the chip; finally, in the case that the chip is determined to be faulty, according to the full-process data records, the occurrence timing of a fault parameter in the wafer-in-process stage, the end-of-line stage and the burn-in stage, the distribution characteristics of the fault parameter on the physical space of the chip, and the correlation between the fault parameter and the equipment working condition data, the fault type of the chip is determined, wherein the fault type includes wafer process fault, packaging process fault, test tool false fault and burn-in hidden fault. The chip fault type is accurately layered.

Description

Technical Field

[0001] This application belongs to the field of testing technology, and in particular relates to a method and apparatus for chip defect layering. Background Technology

[0002] In the mass production of integrated circuit chips, the causes of chip defects involve multiple stages, including wafer manufacturing, packaging processes, testing environment, and reliability aging. Accurately identifying the root cause of defective chips is a key prerequisite for improving product yield and process stability.

[0003] In related technologies, when determining whether a chip is defective, a binary judgment of pass or fail is usually made based on the test results of a single stage. When a defective parameter is detected in a certain test stage, the chip is determined to be defective.

[0004] However, the above-mentioned judgment method can only conclude whether the chip is qualified or not, and cannot effectively trace the specific links and real causes of defects. This results in insufficient ability to distinguish the types of chip defects and makes it difficult to accurately locate the root cause of the problem. Summary of the Invention

[0005] This application provides a chip defect stratification method and apparatus, which can achieve accurate stratification of chip defect types.

[0006] The first aspect of this application provides a chip defect stratification method, comprising: acquiring wafer mid-test data, final test data, aging test data, and equipment condition data of the chip; performing data format unification processing on the wafer mid-test data, final test data, aging test data, and equipment condition data, and aligning them according to the chip manufacturing and testing process sequence to obtain a full-process data record indexed by the chip's unique identifier; when a chip is determined to be defective, analyzing the timing of the occurrence of defective parameters in the wafer mid-test stage, final test stage, and aging stage, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment condition data based on the full-process data record to determine the chip defect type, wherein the defect type includes wafer process defects, packaging process defects, test fixture false defects, and aging latent defects.

[0007] In the technical solution of this application, the multi-source heterogeneous data of the entire chip manufacturing and testing process are integrated in a unified manner, and cross-analysis is performed from three dimensions of time, space and equipment correlation when defects occur, so as to achieve accurate stratification of chip defect types and make up for the shortcomings of traditional single-stage judgment methods that cannot trace the root cause of defects.

[0008] Optionally, in one possible implementation of the first aspect, the aforementioned analysis of the timing of defective parameters' occurrence during the wafer testing, final product testing, and aging stages, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment operating data, based on full-process data recording, is used to determine the chip's defect type. This includes determining the chip's defect type as a wafer process defect when: the defective parameter has been detected during the wafer testing stage, the defective chip corresponding to the defective parameter exhibits regional clustering on the wafer coordinates, and the defective parameter has been retested during the final product testing stage with the retest results consistent with the test results from the wafer testing stage. Thus, by combining the early detection timing of defective parameters, wafer space clustering characteristics, and cross-stage retest consistency for comprehensive judgment, native process defects originating from the wafer manufacturing process can be accurately identified.

[0009] Optionally, in another possible implementation of the first aspect, the aforementioned analysis of the timing of defective parameters' occurrence during the wafer testing, final product testing, and aging stages, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment operating condition data, based on the entire process data recording, is used to determine the chip's defect type. This includes determining the chip's defect type as follows: if the test results are normal during the wafer testing stage, and the defective parameter is detected during the final product testing stage, and the defective parameter is a parameter deviation related to mechanical stress, and the defective chips corresponding to the defective parameter are concentrated in the same packaging batch, then the chip's defect type is determined to be a packaging process defect. Thus, by comparing the normal test results at the wafer stage with newly discovered defective parameters at the finished product stage, and combining the stress-sensitive characteristics of parameter deviations and batch clustering analysis, mechanical stress damage defects introduced by the packaging process can be accurately identified.

[0010] Optionally, in another possible implementation of the first aspect, the aforementioned analysis of the timing of defective parameters during the wafer in-process testing, final product testing, and aging stages, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment operating condition data, based on the entire process data recording, is used to determine the chip's defect type. This includes cases where the test results are normal during the wafer in-process testing, the defective parameters are detected during the final product testing, the distribution of the defective chips corresponding to the defective parameters is correlated with the test channels, test sockets, or test temperature zones in the equipment operating condition data, and the defective chips return to normal after retesting, thus determining the chip's defect type as a false defect in the test fixture. Therefore, by associating the distribution characteristics of defective chips with equipment operating condition information such as test channels, test sockets, or test temperature zones, and verifying this with retest results, false defects caused by abnormal test fixtures or the test environment can be identified, preventing misjudgment and scrapping of chips.

[0011] Optionally, in another possible implementation of the first aspect, the aforementioned analysis of the timing of defective parameters' occurrence during the wafer in-wafer testing stage, the final product testing stage, and the aging stage, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment operating condition data, based on the entire process data recording, is used to determine the chip's defect type. This includes determining the chip's defect type as an aging-induced latent defect if the test results during the wafer in-wafer testing stage are normal, the chip's final product testing results under normal temperature conditions are normal, and at least one of the following conditions is met: the deviation of the defective parameters measured after the aging stage relative to the test results during the final product testing stage exceeds a preset deviation threshold; and the change in power consumption after the aging stage relative to the power consumption during the final product testing stage exceeds a preset change threshold. Thus, by comparing the test data before and after aging, and using whether the parameter deviation or power consumption change exceeds the preset threshold as the judgment criterion, potential chip reliability defects that cannot be exposed under conventional testing can be identified.

[0012] Optionally, in another possible implementation of the first aspect, the method further includes: constructing a process baseline model of equipment operating condition data based on historical full-process data records of historical chips; comparing the real-time collected equipment operating condition data with the process baseline model, and generating early warning information when the deviation trend meets preset early warning conditions. Thus, by constructing a process baseline based on historical data and monitoring the deviation trend of real-time equipment operating condition data, early warning information can be proactively generated before anomalies occur in the testing process, achieving preventative control.

[0013] Optionally, in another possible implementation of the first aspect, the equipment operating condition data includes electrical parameters of the test channel, contact state parameters of the test socket, and temperature control parameters of the test environment. The preset warning conditions include at least one of the following: the drift of the electrical parameters of the test channel exceeds a preset drift threshold; the degradation trend of the contact state parameters of the test socket exceeds a preset degradation threshold; and the fluctuation amplitude of the temperature control parameters of the test environment exceeds a preset fluctuation threshold. Therefore, by setting warning thresholds for electrical drift of the test channel, contact degradation of the test socket, and temperature control fluctuations respectively, precise warnings can be given for specific abnormal types of equipment operating conditions.

[0014] Optionally, in another possible implementation of the first aspect, the method further includes: performing cluster analysis on multiple chips identified as defective types; locating the corresponding process segment based on the clustering results; and outputting a corresponding process optimization strategy based on the located process segment. The process optimization strategy includes at least one of instructing rework and retesting, instructing line stoppage for equipment inspection, instructing feedback on the front-end wafer manufacturing process, or instructing replacement of the aging temperature zone or test socket. Thus, by clustering and statistically analyzing the stratified defective chips to locate specific process segments, and outputting targeted handling strategies based on the location results, a complete control loop from defect stratification to process optimization is formed.

[0015] Optionally, in another possible implementation of the first aspect, the alignment according to the chip manufacturing and testing process sequence includes: establishing a mapping relationship between the chip's wafer coordinate information and package barcode information; and mapping wafer-level test data, finished product final test data, aging test data, and equipment operating condition data to a unified timeline or process step sequence based on the mapping relationship. Thus, by establishing a mapping relationship between wafer coordinates and package barcodes, and mapping data from each stage to a unified timeline or process sequence, the accuracy and traceability of data association across process stages are ensured.

[0016] A second aspect of this application provides a chip defect layering apparatus, comprising: The data acquisition module is used to acquire wafer-level test data, finished product final test data, aging test data, and equipment operating condition data for the chip.

[0017] The record generation module is used to unify the data format of wafer mid-test data, finished product final test data, aging test data and equipment operating condition data, and align them according to the process sequence of chip manufacturing and testing to obtain a full-process data record indexed by the chip's unique identifier.

[0018] The layered processing module is used to analyze the timing of the occurrence of defective parameters in the wafer testing stage, the final product testing stage, and the aging stage, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment operating data when a chip is determined to be defective. The defect types include wafer process defects, packaging process defects, test fixture false defects, and aging latent defects.

[0019] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the chip defect layering method of the first aspect described above.

[0020] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the chip defect layering method of the first aspect described above.

[0021] The fifth aspect of this application provides a computer program product that, when run on an electronic device, causes the electronic device to execute the chip defect layering method of the first aspect described above.

[0022] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic flowchart of a chip defect layering method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a chip defect layering device provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0025] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0026] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0027] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0028] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0029] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0031] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0032] To facilitate understanding of the embodiments of this application, the relevant concepts involved in the embodiments of this application will be briefly explained first: In related technologies, when determining chip defects, a binary judgment of whether a chip is qualified or not is usually made based on the test results of a single stage. When a defective parameter is detected in a certain test stage, the chip is determined to be defective. However, the above judgment method can only conclude whether the chip is qualified or not, and cannot effectively trace the specific stage where the defect occurred and the true cause. This results in insufficient ability to distinguish the type of chip defect and makes it difficult to accurately locate the root cause of the problem.

[0033] In view of this, embodiments of this application provide a chip defect stratification method and apparatus. The method first acquires wafer mid-test data, final product test data, aging test data, and equipment condition data of the chip. Then, it performs data format unification processing on the wafer mid-test data, final product test data, aging test data, and equipment condition data, and aligns them according to the chip manufacturing and testing process sequence to obtain a complete process data record indexed by the chip's unique identifier. Finally, when a chip is determined to be defective, based on the complete process data record, it analyzes the timing of defective parameters in the wafer mid-test stage, final product test stage, and aging stage, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment condition data to determine the chip defect type. The defect types include wafer process defects, packaging process defects, test fixture false defects, and aging latent defects. Therefore, by unifying and integrating multi-source heterogeneous data from the entire chip manufacturing and testing process, and conducting cross-analysis from three dimensions—time, space, and equipment correlation—when defects occur, accurate stratification of chip defect types can be achieved, making up for the shortcomings of traditional single-stage judgment methods that cannot trace the root cause of defects.

[0034] The following example illustrates the application scenario of the chip defect stratification method provided in this application. During chip mass production testing, a batch of chips exhibits defects such as open circuits or impedance abnormalities in the final testing stage. Traditional judgment methods can only determine the chips as defective and scrap them based on the test results of a single stage. However, the solution in this application integrates wafer-level test data, final testing data, aging test data, and equipment condition data during the testing process for that batch of chips, establishing a complete data record indexed by each chip. When a chip is determined to be defective, cross-analysis is performed from three dimensions: the timing of the defective parameters at each testing stage, their spatial distribution characteristics on the wafer coordinates, and their correlation with the operating conditions of equipment such as test channels and test sockets. This accurately distinguishes whether the defect is due to native wafer process issues, packaging process damage, false defects in test fixtures, or potential reliability defects in the chip. This avoids batch misjudgments and material waste caused by false defects due to abnormal equipment conditions such as poor test socket contact.

[0035] To illustrate the technical solution of this application, specific embodiments are described below.

[0036] Reference Figure 1 The diagram illustrates a flowchart of a chip defect layering method provided in an embodiment of this application. Figure 1 As shown, the chip defect stratification method may include the following steps: Step 101: Obtain wafer-level test data, finished product final test data, aging test data, and equipment operating condition data for the chip.

[0037] In this embodiment, wafer-level test data refers to the data obtained by performing electrical tests on each chip on the wafer using a chip probe (CP) method after the wafer manufacturing stage is completed. Specifically, wafer-level test data may include the electrical parameters of each chip (e.g., threshold voltage, leakage current), initial yield classification (Bin) information, the chip's physical coordinates on the wafer, and the defect distribution corresponding to those coordinates.

[0038] In this embodiment, the final test data refers to the data obtained by performing full functional and electrical tests on the packaged chip during the final test (FT) stage after the chip has completed the packaging process. The final test data may include electrical parameters measured under different temperature conditions (e.g., room temperature, high temperature, low temperature), pass / fail results of functional tests, and the offset of each parameter relative to the corresponding parameters in the wafer intermediate test stage.

[0039] In this embodiment, aging test data refers to data collected during and after the high-temperature aging (burn-in) screening process of the chip, by applying temperature and electrical stress to accelerate the exposure of potential defects. Aging test data may include comparative data of electrical parameters before and after aging test, power consumption change data, and information on test points where failure occurred.

[0040] In this embodiment, equipment condition data refers to core parameters reflecting the operating status of the test equipment, test fixtures, and test environment, collected synchronously with the test actions during wafer in-wafer testing, final product testing, and aging testing. Equipment condition data may include: real-time loop impedance, signal transmission timing offset, and channel electrical attenuation parameters for each independent test channel of the test machine; real-time temperature fluctuation difference and temperature uniformity deviation data within the high and low temperature test chambers; and dynamic contact condition parameters such as the downward stroke, downward pressure, and contact flatness of the probe station and test socket. This type of data can comprehensively depict subtle changes in test conditions from the perspectives of test hardware, fixtures, and environment.

[0041] In one embodiment, in addition to the four types of data mentioned above, chip packaging process data can also be obtained. Packaging process data includes stress monitoring data generated during the packaging process, wire bonding process parameters, and molding batch information. Introducing packaging process data helps to more directly correlate process fluctuations in the packaging stage, providing auxiliary basis for determining packaging process damage in defective chips.

[0042] In one embodiment, during the data acquisition process, a unified test data platform can be built, using the unique identifier of each chip (such as the wafer ID or the barcode assigned after packaging) as an index, to synchronously collect and bind the wafer-level test data, final product test data, aging test data, and equipment condition data (as well as optional packaging process data) of the same chip, ensuring the accurate correspondence between multi-source data and individual chips.

[0043] Step 102: Perform unified data format processing on wafer mid-test data, finished product final test data, aging test data and equipment operating condition data, and align them according to the process sequence of chip manufacturing and testing to obtain a full-process data record indexed by the chip's unique identifier.

[0044] In this embodiment, data format unification processing refers to converting heterogeneous data from different testing equipment, software platforms, and data acquisition systems into a unified data structure and storage format. Since wafer testing machines, final product testing machines, aging testing equipment, and equipment condition monitoring systems are typically provided by different vendors, their output data files differ in field naming conventions, numerical precision, encoding methods, and timestamp formats. Directly using the original formats makes effective cross-stage correlation analysis impossible. Through data format unification processing, similar parameters in the above four types of data can be mapped to a unified parameter naming system, numerical precision can be unified to a preset number of decimal places, timestamps can be uniformly converted to Coordinated Universal Time (UTC) format, and defect classification identifiers with different encoding methods can be mapped to a unified defect type code. This eliminates format barriers between multi-source data, providing a consistent data foundation for subsequent cross-stage data correlation and comparison.

[0045] In this embodiment, alignment according to the chip manufacturing and testing process sequence means mapping wafer testing data, final product testing data, aging test data, and equipment condition data to the corresponding stages of this process sequence, based on the inherent process sequence of wafer manufacturing, wafer testing, packaging, final product testing, and aging testing that the chip actually undergoes. Since there are time intervals between each testing stage, and the testing times for different chips at the same process stage may differ, it is necessary to use the process stage as the alignment benchmark, rather than absolute time. By arranging the data for each stage of each chip according to the actual process steps it undergoes, and clearly defining the process stage label for each data record (e.g., "Wafer Testing Stage," "Final Product Testing Stage," "Aging Stage"), a complete data chain is formed, covering the entire process from wafer to aging and arranged according to the process sequence.

[0046] In one embodiment, the process of aligning according to the chip manufacturing and testing process sequence may specifically include: establishing a mapping relationship between the chip's wafer coordinate information and package barcode information; and mapping wafer-level test data, finished product final test data, aging test data, and equipment operating condition data to a unified timeline or process step sequence based on the mapping relationship. Thus, by establishing a mapping relationship between wafer coordinates and package barcodes, and mapping data from each stage to a unified timeline or process sequence, the accuracy and traceability of data association across process stages are ensured.

[0047] It's important to note that the chip identification system undergoes a fundamental change during the manufacturing process, from wafer to packaged product. At the wafer stage, each chip is uniquely identified by its wafer number and its row and column coordinates on the wafer. This identification is managed and associated through a probe station recording system within the wafer. In the dicing process, the wafer is cut into individual bare chips. In subsequent mounting, wire bonding, and encapsulation processes, each bare chip is individually placed into a packaging substrate and packaged. The packaged chip is then assigned a new packaging barcode as its unique identifier. Because the physical arrangement of the chips may be rearranged during dicing and packaging, the relationship between wafer coordinates and packaging barcodes is not a simple linear one. Therefore, a precise mapping relationship must be established between the two to achieve data flow across stages.

[0048] One specific implementation of the mapping relationship is as follows: Before the dicing process, the Manufacturing Execution System (MES) records the original wafer coordinate information of each chip. During the placement process, the placement equipment places the bare chips one by one into the corresponding positions on the packaging substrate according to a preset placement sequence, while the MES simultaneously records the source of the wafer coordinates corresponding to each packaging substrate position. In the packaging barcode marking process, the MES assigns a packaging barcode to each packaged chip and binds the packaging barcode to the position on the packaging substrate. Thus, the MES can automatically generate a complete bidirectional mapping table from wafer coordinates to packaging barcodes.

[0049] Furthermore, based on this bidirectional mapping table, the system can accurately associate the test data records identified by wafer coordinates in the wafer intermediate testing stage with the test data records identified by packaging barcodes in the final product testing stage and the aging stage. The system also maps the data from each of the above stages, as well as the equipment condition data collected synchronously in the corresponding stages, to a unified timeline or process step sequence according to the inherent process sequence of chip manufacturing and testing (wafer manufacturing → wafer intermediate testing → packaging → final product testing → aging testing), ultimately forming a complete data archive indexed by the chip's unique identifier and spanning the entire chip lifecycle.

[0050] In this embodiment of the application, through the above-mentioned unified data format processing and process timing alignment operation, the obtained full-process data record integrates the isolated data originally scattered in each independent test system into a structured data archive with single chip as the granularity and covering the entire life cycle test information, providing complete data support for subsequent multi-dimensional cross-analysis and defect type determination when the chip is determined to be defective.

[0051] Step 103: If the chip is determined to be defective, based on the full process data record, analyze the timing of the occurrence of defective parameters in the wafer testing stage, the final product testing stage, and the aging stage, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment operating data, in order to determine the defect type of the chip.

[0052] The types of defects include wafer process defects, packaging process defects, false defects in testing fixtures, and latent defects due to aging.

[0053] In this embodiment, defective parameters refer to various electrical parameters or functional indicators of the chip that deviate from the preset specification range during testing, such as threshold voltage deviation, excessive leakage current, abnormal impedance, and power consumption deviation. The timing of occurrence refers to the testing stage at which a defective parameter is first detected (mid-wafer testing stage, final product testing stage, or aging stage), reflecting the starting point of the defect in the chip's lifecycle. The distribution characteristics of the chip's physical space refer to the positional distribution pattern of defective chips on the wafer coordinates (e.g., whether it exhibits regional clustering), or the degree of concentration of defective chips in the packaging batch. The correlation between defective parameters and equipment operating condition data refers to whether the probability of defective chip occurrence or the degree of parameter deviation has a statistical correlation with specific equipment operating condition elements such as test channels, test sockets, and test temperature zones.

[0054] The logical correspondence between the three analytical dimensions and the four types of defects is as follows: Wafer process defects refer to defects originating from process deviations in the wafer manufacturing process. These defects typically exhibit early appearance (detected during the wafer testing stage), clustering on the wafer coordinates, and stable recurrence across stages. Packaging process defects refer to damage introduced during the packaging process due to mechanical stress, abnormal wire bonding, or molding defects, even though the chip wafer stage is normal. These defects are usually detected for the first time during the final testing stage and are concentrated in specific packaging batches. Test fixture false defects refer to chips that are actually good, but are misjudged as defective due to external testing conditions such as test equipment channel drift, test socket contact degradation, or abnormal test environment temperature. These defects are usually associated with specific test channels, test sockets, or test temperature zones and can be restored to good after retesting. Aging latent defects refer to chips that test normally during the final testing stage at room temperature, but exhibit parameter deviations or abnormal power consumption after high-temperature aging stress screening. This type of defect represents an early failure type where the chip itself has potential reliability defects.

[0055] In this embodiment of the application, by cross-integrating the analysis of the above three dimensions, the defect type of each defective chip can be accurately stratified, thereby distinguishing the process deviation problems that need to be fed back to the front-end wafer manufacturing process, the packaging damage problems that need to be improved in the packaging process parameters, the test condition problems that need to be maintained or replaced in the test fixtures, and the device hidden problems that need to be strengthened in the reliability screening standards, so as to provide a clear decision basis for targeted optimization of the mass production process.

[0056] In one embodiment, if a defective parameter is detected during the wafer pre-testing stage, and the defective chips corresponding to the defective parameter exhibit regional clustering on the wafer coordinates, and the defective parameter is retested during the final product testing stage with results consistent with those from the wafer pre-testing stage, then the chip defect type is determined to be a wafer process defect. Therefore, by combining the early detection timing of the defective parameter, wafer spatial clustering characteristics, and cross-stage retesting consistency for a comprehensive judgment, native process defects originating from the wafer manufacturing process can be accurately identified.

[0057] It should be noted that the determination of wafer process defects is based on the simultaneous fulfillment of the following three conditions. First, the defective parameters occur during the wafer testing stage, i.e., before the chip has undergone packaging. Defects detected at this stage exclude interference from packaging and subsequent testing, directly pointing to the wafer manufacturing process. In practical applications, the determination condition can be set as follows: if any electrical parameter (e.g., threshold voltage, leakage current) in the wafer testing data exceeds a preset specification range, it is considered a defective parameter has been detected. Second, defective chips exhibit regional clustering on the wafer coordinate system. Because wafer manufacturing process deviations (e.g., uneven lithography, different etching rates, doping concentration gradients) typically affect certain continuous areas on the wafer, native wafer process defects often manifest as batch failures within specific areas of the wafer, rather than random discrete distributions. In practical applications, clustering can be determined using statistical methods: the wafer is divided into multiple grid regions. When the density of defective chips in a certain grid region exceeds a preset multiple (e.g., 3 times) of the average defect density of the entire wafer, or the average distance between adjacent defective chips is less than a preset distance threshold, the defective chips in that region are considered to have regional clustering. Third, the defective parameters can be reproducibly reproduced in the final testing stage of the finished product. That is, for a chip with a defect record from wafer mid-testing, when the same parameters are tested again in the final testing stage, the test result is still defective, and the direction and amount of parameter offset are consistent with those in the wafer mid-testing stage. This cross-stage parameter consistency proves that the defect is an inherent defect of the chip itself, rather than an occasional testing error from the wafer mid-testing stage. When all three conditions are met, the influence of factors such as packaging process, test fixtures, and aging stress can be ruled out, and the root cause of the defect can be precisely pinpointed to the wafer manufacturing process.

[0058] In one embodiment, if the test results are normal during the wafer testing stage, and the defective parameter is detected during the final product testing stage, and the defective parameter is a parameter deviation related to mechanical stress, and the defective chips corresponding to the defective parameter are concentrated in the same packaging batch, then the defect type of the chip is determined to be a packaging process defect. Therefore, by comparing the normal test results at the wafer stage with the newly discovered defective parameters at the finished product stage, and combining this with the stress-sensitive characteristics of the parameter deviation and batch clustering analysis, mechanical stress damage defects introduced by the packaging process can be accurately identified.

[0059] It should be noted that the determination of packaging process defects is based on the simultaneous fulfillment of the following four conditions. First, all parameters in the wafer-level test data are within specifications, and the test results are normal, proving that the chip is a good product during the wafer manufacturing stage, ruling out the possibility of defects in the original wafer process. Second, the defective parameters are detected for the first time in the final product testing stage, meaning the defect appears only after the chip has undergone packaging processes such as dicing, mounting, wire bonding, and molding, indicating a causal relationship between the defect and the packaging process. Third, the detected defective parameters are parameter deviations related to mechanical stress. Parameter deviations related to mechanical stress refer to typical electrical anomalies exhibited by the chip after being subjected to mechanical stress, specifically including: open circuits or abnormally increased impedance (caused by poor wire bonding or broken leads), abnormally increased leakage current (caused by microcracks or interface state changes on the chip surface due to molding stress), and drift of specific analog circuit parameters (caused by packaging stress altering device matching characteristics or piezoresistive effects). The selection of the above parameter types is determined based on the physical mechanism of the impact of packaging mechanical stress on chip electrical performance. Fourth, defective chips are concentrated in the same packaging batch. In actual mass production, anomalies in the packaging process (such as deviations in wire bonding parameters, wear of molding dies, and abnormal curing temperature profiles) usually affect a batch of chips within the same packaging batch. Therefore, the batch concentration of defective chips is a key characteristic for distinguishing between packaging process defects and random defects. When all four conditions mentioned above are met, the defect can be determined to be damage introduced by the packaging process.

[0060] In one embodiment, if the test results are normal during the wafer in-wafer testing stage, and the defective parameters are detected during the final product testing stage, and the distribution of the defective chips corresponding to the defective parameters is correlated with the test channels, test sockets, or test temperature zones in the equipment operating condition data, and the defective chips return to normal after retesting, then the chip defect type is determined to be a false defect caused by the test fixture. Therefore, by correlating the distribution characteristics of defective chips with equipment operating condition information such as test channels, test sockets, or test temperature zones, and verifying this with retest results, false defects caused by abnormal test fixtures or the test environment can be identified, preventing chips from being mistakenly scrapped.

[0061] It should be noted that the determination of false defects in the testing fixture is based on the simultaneous fulfillment of the following four conditions. First, all parameters in the wafer-level test data of the chip are within the specification range, and the test results are normal, proving that the chip is a good product during the wafer manufacturing stage. Second, the defective parameters are detected during the final testing stage of the finished product. Third, the distribution of defective chips is correlated with a specific test channel, a specific test socket, or a specific test temperature zone in the equipment operating condition data, rather than being a random discrete distribution. In practical applications, the above correlation can be determined through statistical methods: for defective chips in the same batch, calculate their distribution ratio in different test channels, different test sockets, or different test temperature zones; when the defect ratio of a certain test channel exceeds a preset multiple (e.g., 2 times) of the average defect ratio of all channels, or the defect ratio of a certain test socket exceeds a preset multiple of the average defect ratio of all test sockets, or the defect ratio of a certain temperature zone exceeds a preset multiple of the average defect ratio of all temperature zones, it is determined that the distribution of defective chips is correlated with that test channel, test socket, or test temperature zone. The above distribution correlation characteristics indicate that the occurrence of defects is closely related to the local abnormality of the test hardware or environment, rather than a problem with the chip itself. Fourth, the defective chip returns to normal after retesting. Retesting refers to replacing the chip identified as defective with a test channel or socket that has been verified as normal for a second test. If the retest result is good, it proves that the chip itself is functionally normal, and the previous defect judgment was indeed a false defect caused by abnormal test fixtures or test environment. In practical applications, retesting can be further subdivided into two strategies: same-condition retesting and cross-condition retesting. Same-condition retesting involves keeping the defective chip in the original test channel and test socket for retesting to determine whether the defect is intermittent and unreproducible. Cross-condition retesting involves replacing the defective chip with a known normal test channel and test socket to determine whether the defect disappears with the change of test fixtures. When the same-condition retest result is still defective, but the cross-condition retest result is good, it can be further confirmed that the root cause of the defect is hardware aging or contact deterioration in the original test channel or test socket, rather than a defect in the chip itself. The system can automatically mark the test channel or test socket as needing maintenance based on the cross-condition retest result and generate corresponding test fixture maintenance prompts. When all four conditions are met, the defect can be determined to be a false defect of the testing fixture, and the corresponding defective chip does not need to be scrapped.

[0062] In one embodiment, if the test results during the wafer in-wafer testing stage are normal, and the test results during the final product testing stage at room temperature are also normal, and at least one of the following conditions is met, the chip's defect type is determined to be an aging-induced latent defect: the deviation of the defective parameters measured after the aging stage relative to the test results during the final product testing stage exceeds a preset deviation threshold; and the change in power consumption after the aging stage relative to the power consumption during the final product testing stage exceeds a preset change threshold. Therefore, by comparing the test data before and after aging, and using whether the parameter deviation or power consumption change exceeds the preset threshold as the criterion, potential chip reliability defects that cannot be exposed under conventional testing can be identified.

[0063] It should be noted that the determination of latent defects due to aging is based on the simultaneous fulfillment of the following conditions. First, the wafer-level test data of the chip is normal, and the final test data of the chip under normal temperature conditions is also normal, proving that before undergoing aging stress, all electrical parameters and functional indicators of the chip meet the specifications. Second, after undergoing high-temperature aging screening, the chip exhibits at least one of the following abnormal behaviors: First, the deviation of the defective parameter exceeds the preset deviation threshold. The preset deviation threshold refers to the upper limit of parameter deviation pre-set according to the chip product specifications and reliability requirements. For example, it is stipulated that the leakage current increase after aging should not exceed 200% of the value before aging, or the threshold voltage drift should not exceed 50 millivolts. When the change in the measured value of the defective parameter after aging relative to the baseline value in the final test stage exceeds the preset deviation threshold, it indicates that the chip has undergone performance degradation beyond the allowable range under aging stress. Second, the change in power consumption exceeds the preset change threshold. Abnormal power consumption drift is a typical manifestation of the activation of potential defects inside the chip (such as weak points in the gate oxide layer, metallization step cracks, impurity contamination, etc.) under high temperature and high stress conditions. The preset change threshold is also pre-set according to the chip product specifications. For example, it is stipulated that the power consumption increase after aging should not exceed 150% of the power consumption before aging. The above two abnormal behaviors capture the latent failure characteristics exposed by aging stress from two dimensions: parameter deviation and power consumption change. Meeting either one can trigger the judgment of latent aging defects. The judgment result of latent aging defects indicates that the chip has potential reliability defects. Such chips perform well under normal testing conditions, but have the risk of early failure under long-term use or stress conditions, and need to be eliminated according to reliability screening standards.

[0064] In one embodiment, a process baseline model for equipment operating conditions can be constructed based on historical full-process data records of historical chips. The real-time collected equipment operating conditions data is compared with the process baseline model, and an early warning message is generated when the deviation trend meets preset early warning conditions. Thus, by constructing a process baseline based on historical data and monitoring deviation trends in real-time equipment operating conditions, early warning messages can be proactively generated before anomalies occur in the testing process, achieving preventative control.

[0065] It should be noted that during mass production, as the testing equipment operates for an extended period, the electrical parameters of the test channels may slowly drift due to component aging; the test sockets may experience elastic fatigue and surface wear of the contact springs due to repeated chip insertion and removal, leading to a gradual increase in contact resistance; and the heating elements and temperature sensors in the aging chamber may experience performance degradation due to long-term use, resulting in decreased temperature uniformity or increased temperature fluctuations. The degradation process of these equipment conditions is typically gradual and insidious, and in the early stages of degradation, it does not directly cause abnormal chip test results, making it difficult to detect in a timely manner through traditional manual inspections or periodic maintenance.

[0066] To address the aforementioned issues, this application introduces an active early warning mechanism based on a process baseline model. The process baseline model is a standard reference model established based on a large amount of equipment operating condition data accumulated during long-term mass production on the production line under normal operating conditions. It is used to characterize the normal operating range of test equipment, test fixtures, and the test environment under stable and healthy conditions. The specific process of constructing the process baseline model includes: selecting historical full-process data records from continuous production batches that have stable yields, no abnormal alarms, and cover a sufficiently long production cycle as a benchmark sample set; performing statistical analysis on each parameter of the equipment operating condition data in the benchmark sample set, calculating the mean and standard deviation of each parameter under normal operating conditions; based on the statistical results, constructing the normal distribution range of each parameter, using a preset multiple of the standard deviation above and below the mean as the normal fluctuation range of the parameter, and using a preset multiple of the standard deviation above and below the mean for a wider range as the abnormal warning boundary of the parameter.

[0067] During real-time mass production testing, after each chip is tested, the synchronously collected equipment operating condition data is compared in real time with the process baseline model. The deviation of the current operating condition parameters from the baseline model's mean is calculated, and the deviation trend is analyzed. Preset warning conditions can include any of the following: the current parameter value exceeds the normal fluctuation range of the baseline model for a consecutive preset number of sampling points; the current parameter value, although not continuously exceeding the normal fluctuation range, exhibits a continuous unidirectional drift trend; the current parameter value exceeds the abnormal warning boundary of the baseline model on a single occasion. When any real-time monitored equipment operating condition parameter meets the preset warning condition, the system automatically generates a warning message, indicating an abnormal risk in the equipment channel, test socket, or temperature zone.

[0068] In one embodiment, the equipment operating condition data includes electrical parameters of the test channel, contact state parameters of the test socket, and temperature control parameters of the test environment. The preset warning conditions include at least one of the following: the drift of the electrical parameters of the test channel exceeds a preset drift threshold; the degradation trend of the contact state parameters of the test socket exceeds a preset degradation threshold; and the fluctuation amplitude of the temperature control parameters of the test environment exceeds a preset fluctuation threshold. Therefore, by setting warning thresholds for electrical drift of the test channel, contact degradation of the test socket, and temperature control fluctuations respectively, precise warnings can be issued for specific abnormal types of equipment operating conditions.

[0069] It should be noted that the electrical parameters of the test channels include the real-time loop impedance, signal transmission timing offset, and channel electrical attenuation parameters for each independent test channel. When the drift of the loop impedance value of a certain test channel relative to the baseline model mean exceeds the preset drift threshold, it indicates that the channel may have contact aging or abnormal line impedance, requiring channel calibration or maintenance. Test socket contact status parameters include the downward stroke, downward pressure, and contact flatness of the probe station or test socket. When the contact impedance value of a certain test socket shows a continuously increasing deterioration trend, and the slope or cumulative change of the deterioration trend exceeds the preset deterioration threshold, it indicates that the contact spring of the test socket may have fatigue deformation or surface oxidation, requiring cleaning or replacement. Test environment temperature control parameters include the real-time temperature fluctuation difference and temperature zone uniformity deviation data within the high and low temperature test chambers. When the temperature fluctuation amplitude of a certain temperature zone exceeds the preset fluctuation threshold, or the temperature uniformity deviation at different locations within the temperature zone exceeds the preset uniformity threshold, it indicates that the temperature control system for that temperature zone may have potential faults, requiring temperature zone calibration or heating element repair. By setting differentiated early warning thresholds for different equipment operating parameters as described above, it is possible to accurately identify which type of equipment is experiencing abnormal operating conditions and generate specific early warning information that includes the type of abnormal parameter, the location of the abnormality, and the degree of the abnormality. This facilitates maintenance personnel in quickly locating the problem and taking targeted measures.

[0070] In one embodiment, cluster analysis is performed on multiple chips identified as defective types. Based on the clustering results, the corresponding process segment for each defect type is located. Based on the located process segment, a corresponding process optimization strategy is output. This strategy includes at least one of the following: instructing rework and retesting, instructing line stoppage for equipment inspection, instructing feedback to the front-end wafer manufacturing process, or instructing replacement of the aging temperature zone or test socket. Thus, by clustering and statistically analyzing the stratified defective chips to locate specific process segments, and outputting targeted handling strategies based on the location results, a complete control loop from defect stratification to process optimization is formed.

[0071] It should be noted that cluster analysis refers to grouping multiple chips with identified defect types according to their feature similarity across multiple dimensions to discover clustering patterns and common causes of defective chips, and to determine whether the current defect is an isolated, single-point random event or a batch defect event caused by a systemic problem in a certain process step. The input data for cluster analysis is the multi-dimensional feature vector of multiple defective chips whose defect types have been identified through the aforementioned steps. This multi-dimensional feature vector includes at least a combination of the following dimensions: wafer batch, package batch, test machine number, test channel number, test socket number, aging temperature zone number, and defect type label. The algorithm used for cluster analysis can be a density-based spatial clustering of applications with noise (DBSCAN). This algorithm does not require pre-specifying the number of clusters, can automatically identify clusters of arbitrary shapes, and effectively distinguish noise points, making it suitable for discovering defect clustering patterns of different sizes and density distributions.

[0072] After clustering, the common characteristics of defective chips within each cluster are analyzed across various dimensions. If all defective chips within a cluster share the same wafer batch and the same defect type label (wafer process defect), the root cause can be located at the wafer manufacturing section corresponding to that wafer batch. If all defective chips within a cluster share the same test machine number and test channel number, and the defect type label is "test fixture false defect," the root cause can be located at the specific test channel of that test machine.

[0073] After locating the process segment corresponding to the root cause of the defect, the system automatically outputs the corresponding process optimization strategy based on the location result. For cases determined to be pseudo-defects in the testing fixture and located to a specific testing machine, testing channel, or testing socket, the system outputs a strategy instructing rework and retesting to restore the affected defective chips to good products and avoid erroneous material scrapping; simultaneously, it outputs a strategy instructing the replacement or maintenance of the corresponding testing socket or testing channel. For defective chips exhibiting significant clustering in a specific wafer batch and determined to be wafer process defects, the system outputs a strategy instructing feedback to the front-end wafer manufacturing process. For defective chips exhibiting significant clustering in a specific packaging batch and determined to be packaging process defects, the system outputs a strategy instructing line stoppage and equipment inspection. For defective chips exhibiting significant clustering in a specific aging temperature zone and determined to be aging latent defects, the system outputs a strategy instructing the replacement of the aging temperature zone or inspection of the aging equipment.

[0074] The chip defect stratification method disclosed in the above embodiments of this application first acquires wafer mid-test data, final product test data, aging test data, and equipment condition data of the chip. Then, it performs unified data format processing on the wafer mid-test data, final product test data, aging test data, and equipment condition data, and aligns them according to the chip manufacturing and testing process sequence to obtain a complete process data record indexed by the chip's unique identifier. Finally, when a chip is determined to be defective, based on the complete process data record, it analyzes the timing of defective parameters in the wafer mid-test stage, final product test stage, and aging stage, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment condition data to determine the chip defect type. The defect types include wafer process defects, packaging process defects, test fixture false defects, and aging latent defects. Therefore, by unifying and integrating multi-source heterogeneous data from the entire chip manufacturing and testing process, and performing cross-analysis from three dimensions—time, space, and equipment correlation—when defects occur, accurate stratification of chip defect types is achieved, overcoming the shortcomings of traditional single-stage determination methods that cannot trace the root cause of defects.

[0075] Furthermore, by introducing a real-time equipment condition comparison and deviation early warning mechanism based on the process baseline model, early warning information can be proactively generated and maintenance prompts can be issued before latent anomalies such as test equipment channel drift, test socket contact degradation, or aging temperature fluctuations lead to batch defects. This improves process control capabilities from passive post-event traceability to proactive pre-event prevention. In addition, by performing multi-dimensional clustering analysis and process segment location on stratified defective chips, and automatically outputting targeted process optimization strategies based on the location results, including rework and retesting, line stoppage investigation, feedback to upstream processes, or tooling equipment replacement, a complete intelligent control chain is formed from defect discovery, type determination, root cause location to closed-loop handling. This effectively shortens the production line anomaly investigation time, reduces the false judgment scrap rate, and improves the stability and yield of mass production testing.

[0076] See Figure 2 The diagram shows a schematic of a chip defect layering device provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0077] The chip defect stratification device may specifically include the following modules: The data acquisition module 201 is used to acquire wafer mid-test data, finished product final test data, aging test data and equipment operating condition data of the chip.

[0078] The record generation module 202 is used to process the data format of wafer mid-test data, finished product final test data, aging test data and equipment operating condition data in a unified manner, and align them according to the process sequence of chip manufacturing and testing to obtain a full-process data record indexed by the chip's unique identifier.

[0079] The layered processing module 203 is used to analyze the timing of the occurrence of defective parameters in the wafer testing stage, the final product testing stage, and the aging stage, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment operating data, based on the full-process data records when the chip is determined to be defective, in order to determine the defect type of the chip. The defect types include wafer process defects, packaging process defects, test fixture false defects, and aging latent defects.

[0080] The chip defect stratification device disclosed in the above embodiments of this application first acquires wafer mid-test data, final product test data, aging test data, and equipment condition data of the chip. Then, it performs unified data format processing on the wafer mid-test data, final product test data, aging test data, and equipment condition data, and aligns them according to the chip manufacturing and testing process sequence to obtain a complete process data record indexed by the chip's unique identifier. Finally, when a chip is determined to be defective, based on the complete process data record, it analyzes the timing of defective parameters in the wafer mid-test stage, final product test stage, and aging stage, the distribution characteristics of defective parameters in the chip's physical space, and the correlation between defective parameters and equipment condition data to determine the chip defect type. The defect types include wafer process defects, packaging process defects, test fixture false defects, and aging latent defects. Therefore, by unifying and integrating multi-source heterogeneous data from the entire chip manufacturing and testing process, and performing cross-analysis from three dimensions—time, space, and equipment correlation—when defects occur, accurate stratification of chip defect types is achieved, overcoming the shortcomings of traditional single-stage determination methods that cannot trace the root cause of defects.

[0081] Furthermore, in one possible implementation of this application embodiment, the above-mentioned layered processing module 203 may specifically include the following units: The first processing unit is used to determine the defect type of the chip as a wafer process defect when the defective parameters have been detected in the wafer testing stage, the defective chips corresponding to the defective parameters show regional clustering on the wafer coordinates, and the defective parameters have been retested in the final product testing stage and the retest results are consistent with the test results in the wafer testing stage.

[0082] Therefore, by combining the early detection timing of defective parameters, wafer space aggregation characteristics, and cross-stage retest consistency for comprehensive judgment, the original process defects originating from the wafer manufacturing process can be accurately identified.

[0083] Furthermore, in another possible implementation of this application embodiment, the above-mentioned layered processing module 203 may specifically include the following units: The second processing unit is used to determine the chip's defect type as a packaging process defect when the test results during the wafer testing stage are normal, the defective parameters are detected during the final product testing stage, the defective parameters are parameter deviations related to mechanical stress, and the defective chips corresponding to the defective parameters are concentrated in the same packaging batch.

[0084] Therefore, by comparing the normal test results at the wafer stage with the newly discovered defective parameters at the finished product stage, and combining the stress sensitivity characteristics and batch clustering of parameter deviations for analysis, mechanical stress damage defects introduced by the packaging process can be accurately identified.

[0085] Furthermore, in another possible implementation of this application embodiment, the above-mentioned layered processing module 203 may specifically include the following units: The third processing unit is used to determine the chip's defect type as a test fixture false defect when the test results during the wafer testing stage are normal, the defective parameters are detected during the final product testing stage, the distribution of defective chips corresponding to the defective parameters is related to the test channels, test sockets or test temperature zones in the equipment operating data, and the defective chips are normal after retesting.

[0086] Therefore, by associating the distribution characteristics of defective chips with the operating conditions of equipment such as test channels, test sockets, or test temperature zones, and verifying them using retest results, false defects caused by abnormal test fixtures or test environments can be identified, thus avoiding the misjudgment and scrapping of chips.

[0087] Furthermore, in another possible implementation of this application embodiment, the above-mentioned layered processing module 203 may specifically include the following units: The fourth processing unit is used to determine the chip's defect type as an aging latent defect if the test results during the wafer in-process testing stage are normal, the test results during the final product testing stage under normal temperature conditions are normal, and at least one of the following conditions is met: the deviation of the defect parameters measured after the aging stage from the test results during the final product testing stage exceeds a preset deviation threshold, and the change in power consumption after the aging stage from the power consumption during the final product testing stage exceeds a preset change threshold.

[0088] Therefore, by comparing the test data before and after aging, and using whether the parameter offset or power consumption change exceeds the preset threshold as the criterion, potential reliability defects of the chip that cannot be exposed under normal testing can be identified.

[0089] Furthermore, in another possible implementation of this application embodiment, the above-mentioned chip defect layering device may further include the following modules: The model processing module is used to construct a process baseline model of equipment operating data based on historical full-process data records of historical chips; it compares the real-time collected equipment operating data with the process baseline model, and generates early warning information when the deviation trend meets the preset early warning conditions.

[0090] Therefore, by constructing a process baseline based on historical data and monitoring deviation trends in real-time equipment operating data, early warning information can be proactively generated before abnormalities occur in the testing process, thus achieving preventive control.

[0091] Furthermore, in another possible implementation of this application embodiment, the equipment operating condition data includes test channel electrical parameters, test socket contact state parameters, and test environment temperature control parameters. The preset warning conditions include at least one of the following: the drift amount of the test channel electrical parameters exceeds a preset drift threshold, the deterioration trend of the test socket contact state parameters exceeds a preset deterioration threshold, and the fluctuation amplitude of the test environment temperature control parameters exceeds a preset fluctuation threshold.

[0092] Therefore, by setting early warning thresholds for electrical drift in the test channel, contact degradation of the test socket, and temperature control fluctuations, precise early warnings can be given for specific abnormalities in the equipment's operating conditions.

[0093] Furthermore, in another possible implementation of this application embodiment, the above-mentioned chip defect layering device may further include the following modules: The clustering analysis module is used to perform clustering analysis on multiple chips identified as defective types, locate the corresponding process segment based on the clustering results, and output the corresponding process optimization strategy based on the located process segment. The process optimization strategy includes at least one of the following: indicating rework and retesting, indicating line stoppage for equipment inspection, indicating feedback on the front-end wafer manufacturing process, or indicating replacement of aging temperature zone or test socket.

[0094] Therefore, by clustering and statistically analyzing the defective chips that have been stratified, the specific process stage can be located, and targeted handling strategies can be output based on the location results, thus forming a complete control loop from defect stratification to process optimization.

[0095] Furthermore, in another possible implementation of this application embodiment, the record generation module 202 may specifically include the following units: The fifth processing unit is used to establish the mapping relationship between the chip's wafer coordinate information and the packaging barcode information.

[0096] The sixth processing unit is used to map wafer mid-test data, finished product final test data, aging test data and equipment operating condition data to a unified time axis or process step sequence according to the mapping relationship.

[0097] Therefore, by establishing a mapping relationship between wafer coordinates and package barcodes, and mapping data from each stage to a unified timeline or process sequence, the accuracy and traceability of data association across process stages can be ensured.

[0098] The chip defect layering device provided in this application embodiment can be applied in the foregoing method embodiment. For details, please refer to the description of the above method embodiment, which will not be repeated here.

[0099] Figure 3 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 3 As shown, the electronic device 300 of this embodiment includes: at least one processor 310 ( Figure 3 The diagram shows only one processor, a memory 320, and a computer program 321 stored in the memory 320 and executable on the at least one processor 310. When the processor 310 executes the computer program 321, it implements the steps in the above-described chip defect layering method embodiment.

[0100] The electronic device 300 can be a desktop computer, laptop, handheld computer, cloud server, or other computing device. This electronic device may include, but is not limited to, a processor 310 and a memory 320. Those skilled in the art will understand that... Figure 3 This is merely an example of electronic device 300 and does not constitute a limitation on electronic device 300. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0101] The processor 310 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0102] In some embodiments, the memory 320 may be an internal storage unit of the electronic device 300, such as a hard disk or memory of the electronic device 300. In other embodiments, the memory 320 may be an external storage device of the electronic device 300, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 300. Furthermore, the memory 320 may include both internal and external storage units of the electronic device 300. The memory 320 is used to store operating systems, applications, boot loaders, data, and other programs, such as the program code of computer programs. The memory 320 can also be used to temporarily store data that has been output or will be output.

[0103] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0104] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0105] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0106] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0107] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0108] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0109] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0110] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the steps in the various method embodiments described above.

[0111] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A chip defect layering method, characterized in that, include: Acquire wafer-level test data, finished product final test data, aging test data, and equipment operating condition data for the chip; The wafer mid-test data, the finished product final test data, the aging test data, and the equipment operating condition data are processed to unify the data format and aligned according to the process sequence of chip manufacturing and testing to obtain a full-process data record indexed by the unique identifier of the chip. When a chip is determined to be defective, the timing of the occurrence of defective parameters in the wafer testing stage, the final product testing stage, and the aging stage is analyzed based on the full-process data records. The distribution characteristics of the defective parameters in the chip's physical space and the correlation between the defective parameters and the equipment operating data are also analyzed to determine the defect type of the chip. The defect type includes wafer process defects, packaging process defects, test fixture false defects, and aging latent defects.

2. The method according to claim 1, characterized in that, The step of analyzing the timing of defective parameters during the wafer testing stage, the final product testing stage, and the aging stage based on the full-process data records, the distribution characteristics of the defective parameters in the chip's physical space, and the correlation between the defective parameters and the equipment operating condition data, in order to determine the defect type of the chip, includes: If the defective parameter has been detected during the wafer testing stage, and the defective chips corresponding to the defective parameter show regional clustering on the wafer coordinates, and the defective parameter has been retested during the final product testing stage and the retest result is consistent with the test result of the wafer testing stage, then the defect type of the chip is determined to be a wafer process defect.

3. The method according to claim 1, characterized in that, The step of analyzing the timing of defective parameters during the wafer testing stage, the final product testing stage, and the aging stage based on the full-process data records, the distribution characteristics of the defective parameters in the chip's physical space, and the correlation between the defective parameters and the equipment operating condition data, in order to determine the defect type of the chip, includes: If the test results during the wafer testing stage are normal, and the defective parameter is detected during the final product testing stage, and the defective parameter is a parameter deviation related to mechanical stress, and the defective chips corresponding to the defective parameter are concentrated in the same packaging batch, then the defect type of the chip is determined to be a packaging process defect.

4. The method according to claim 1, characterized in that, The step of analyzing the timing of defective parameters during the wafer testing stage, the final product testing stage, and the aging stage based on the full-process data records, the distribution characteristics of the defective parameters in the chip's physical space, and the correlation between the defective parameters and the equipment operating condition data, in order to determine the defect type of the chip, includes: If the test results during the wafer testing stage are normal, and the defective parameter is detected during the final product testing stage, and the distribution of the defective chip corresponding to the defective parameter is related to the test channel, test socket, or test temperature zone in the equipment operating data, and the defective chip returns to normal after retesting, then the defect type of the chip is determined to be a false defect of the test fixture.

5. The method according to claim 1, characterized in that, The step of analyzing the timing of defective parameters during the wafer testing stage, the final product testing stage, and the aging stage based on the full-process data records, the distribution characteristics of the defective parameters in the chip's physical space, and the correlation between the defective parameters and the equipment operating condition data, in order to determine the defect type of the chip, includes: If the test results during the wafer in-process testing stage are normal, and the test results during the final product testing stage of the chip at room temperature are normal, and at least one of the following conditions is met, the defect type of the chip is determined to be the aging latent defect: The deviation of the defective parameters measured after the aging stage of the chip relative to the test results in the final test stage of the finished product exceeds a preset deviation threshold, and, The change in power consumption of the chip after the aging stage relative to the power consumption during the final test stage of the finished product exceeds a preset change threshold.

6. The method according to claim 1, characterized in that, The method further includes: Based on the historical full-process data records of historical chips, a process baseline model of the equipment operating condition data is constructed. The real-time collected equipment operating data is compared with the process baseline model, and an early warning message is generated when the deviation trend meets the preset early warning conditions.

7. The method according to claim 6, characterized in that, The equipment operating data includes electrical parameters of the test channel, contact status parameters of the test socket, and temperature control parameters of the test environment. The preset warning conditions include at least one of the following: The drift of the electrical parameters of the test channel exceeds a preset drift threshold, and, The degradation trend of the test seat contact state parameters exceeds the preset degradation threshold, and, The fluctuation range of the temperature control parameters in the test environment exceeded the preset fluctuation threshold.

8. The method according to claim 1, characterized in that, The method further includes: Cluster analysis is performed on multiple chips identified as defective, and the corresponding process segment is located based on the clustering results. Based on the located process segment, a corresponding process optimization strategy is output, wherein the process optimization strategy includes at least one of the following: instructing rework and retesting, instructing line stoppage and equipment inspection, instructing feedback on the front-end wafer manufacturing process, or instructing to replace the aging temperature zone or test socket.

9. The method according to claim 1, characterized in that, The alignment according to the chip manufacturing and testing process timing includes: Establish a mapping relationship between the wafer coordinate information and the packaging barcode information of the chip; Based on the mapping relationship, the wafer mid-test data, the finished product final test data, the aging test data, and the equipment operating condition data are mapped to a unified time axis or process step sequence.

10. A chip defect layering device, characterized in that, include: The data acquisition module is used to acquire wafer mid-test data, finished product final test data, aging test data, and equipment operating condition data of the chip. The record generation module is used to perform unified data format processing on the wafer mid-test data, the finished product final test data, the aging test data and the equipment operating condition data, and align them according to the process sequence of chip manufacturing and testing to obtain a full-process data record indexed by the unique identifier of the chip. The layered processing module is used to analyze the timing of the occurrence of defective parameters in the wafer testing stage, the final product testing stage, and the aging stage, the distribution characteristics of the defective parameters in the chip's physical space, and the correlation between the defective parameters and the equipment operating condition data, based on the full-process data records, when the chip is determined to be defective, in order to determine the defect type of the chip. The defect type includes wafer process defects, packaging process defects, test fixture false defects, and aging latent defects.

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