A method and system for latch detection based on FPGA

Abstract

This invention provides a latch-up detection method and system based on FPGA, belonging to the field of latch-up detection technology. The method includes: acquiring the current value and node temperature value of the power domain of the monitored chip, storing them in an FPGA shift register, and obtaining the difference between adjacent cycles to obtain current and temperature change information. The current sampled value is output from the shift register, and combined with the change information, current feature vectors and temperature feature vectors are constructed respectively. Using pre-trained weights and thresholds, the two feature vectors are weighted and accumulated to obtain current and temperature discrimination values, which are then compared with the thresholds to output the latch-up risk detection results for the corresponding channels. When the current channel is valid, the current discrimination result is used as the final output; otherwise, the output is forcibly switched to the temperature discrimination result as a backup output. This method uses current detection as the fast main channel and temperature detection as the backup channel in case of failure, and through arbitration and layered decision-making, effectively addresses the latch-up detection challenges under complex operating conditions such as different working modes.

Description

Technical Field

[0001] This invention relates to the field of latch detection technology, and more specifically to a latch detection method and system based on FPGA. Background Technology

[0002] Single-event latch-up is one of the common reliability failure modes in CMOS integrated circuits. In existing engineering systems, latch-up detection usually uses power supply current as the main observation object because the most direct external manifestation of latch-up in the early stage is usually an abnormal increase in power supply current.

[0003] FPGAs are widely used in spaceborne distributed systems, board-level control systems, and high-speed data acquisition systems. In existing technologies, FPGA-based current latch-up detection mainly adopts a fixed threshold detection scheme. However, the threshold setting relies on manually set thresholds and rules. Under actual operating conditions, the load current in integrated circuits often faces complex changes such as operating mode switching, noise superposition, or current failure. This manual single threshold setting method is prone to causing missed detections or false alarms. Summary of the Invention

[0004] This invention provides a latch-up detection method and system based on FPGA. The method uses current detection as a fast main detection channel and temperature detection as a backup channel when current detection fails. It also adopts a preset arbitration mechanism for hierarchical decision-making, which solves the problem of difficult latch-up detection in situations such as frequent switching of working modes, high noise environment, and current failure.

[0005] This invention proposes a latch detection method based on FPGA, which specifically includes the following steps: The current value of the power domain and the temperature value of the node region of the monitored chip are collected and stored in the FPGA shift register; the difference between the current value and the temperature value between adjacent clock cycles are obtained through a subtractor to obtain current change information and temperature change information. The FPGA shift register outputs the current and temperature values ​​for the current clock cycle, and the subtractor outputs the current and temperature change information within a preset sampling interval to construct current and temperature feature vectors respectively. Using the pre-trained weight parameters and thresholds stored in the FPGA's internal registers or on-chip memory, the current feature vector and temperature feature vector are weighted and accumulated through multipliers and adders to obtain the current discrimination value and temperature discrimination value; the discrimination value is compared with the threshold by a comparator, and the corresponding latch-up risk detection result is output respectively. When the current value of the power domain of the monitored chip is valid, the detection result of the current value is used as the final output; when the current value is invalid, the output is forcibly switched to the detection result of the temperature value as the backup output.

[0006] Preferably, the construction of the current feature vector includes the following steps: The current change information is obtained by subtracting the current value of the previous cycle from the current value of the next cycle of the FPGA shift register using a subtractor: ΔI(ki)=I(ki)-I(ki-1), where i=0,1,……,N-2; where N is the depth of the shift register; The current value I(k) is obtained from the FPGA shift register and together with the current change information ΔI(k), ΔI(k-1), ..., ΔI(k-N+2) within the preset sampling interval, they form the input vector: FI(k) = [I(k), ΔI(k), ΔI(k-1), ..., ΔI(k-N+2)].

[0007] Preferably, the current change information is stored in the gradient register of the FPGA, with the same depth and width as the FPGA shift register.

[0008] Preferably, the storage of the current value in the FPGA shift register includes the following steps: The current signal of the power domain of the monitored chip is acquired by a current sensor. The sampling ADC samples the current detected by the current sensor once per clock cycle according to the set sampling clock and outputs it to the FPGA interface. The shift register set inside the FPGA receives a current value sampled by the ADC every clock cycle and shifts it to the next shift register in the next clock cycle.

[0009] Preferably, the pre-trained weight parameters and thresholds include the following steps: By training the sensor on normal current or temperature samples and latch-up current or temperature samples, fixed weight parameters [wI0, wI1, ..., wI(N-1)], [wT0, wT1, ..., wT(M-1)] and current threshold θI or temperature threshold θT are obtained. After training is completed, the weights and thresholds are fixed-point processed and stored in the FPGA's internal registers or on-chip memory.

[0010] Preferably, the failure flag of the current value is EI(k), the detection result of the current value is OI(k), and the detection result of the temperature value is OT(k). Then, the arbitration logic of the final output O(k) is: O(k) = OI(k) OR [EI(k) AND OT(k)]; When a latch is detected by the current value, O(k) immediately outputs 1; when no latch is detected and the current value is monitored normally, the temperature value does not participate in the final decision; when the current value fails, if the temperature sensor outputs 1, then O(k) outputs 1 to achieve a backup detection.

[0011] This invention also proposes an FPGA-based latch detection system, the system comprising: The current sampling module is used to collect the current value in the power domain of the monitored chip; The current feature generation module is used to obtain the difference in current values ​​between adjacent clock cycles through a subtractor, thereby obtaining current change information. The current sensor module is used to perform weighted summation of the current feature vector using multipliers and adders based on pre-trained fixed weights to obtain a current discrimination value; and to compare the discrimination value with a threshold using a comparator to output the latch-up risk detection result corresponding to the current value. The temperature sampling module is used to collect the temperature value of the monitored chip node area; The temperature feature generation module is used to obtain the temperature difference between adjacent clock cycles through a subtractor to obtain temperature change information. The temperature sensor module is used to perform weighted summation of the temperature feature vector using multipliers and adders based on pre-trained fixed weights to obtain a temperature discrimination value; and to compare the discrimination value with a threshold using a comparator to output the latch-up risk detection result corresponding to the temperature value. The current path validity judgment flag is used to determine whether the current value in the power domain of the monitored chip has failed and to provide a valid flag for the current value. The latch arbitration module is used to arbitrate the detection results based on whether the current value is invalid. When the current value of the power domain of the monitored chip is valid, that is, when no failure flag of the current value is received, the detection result of the current value is used as the final output. When a failure flag of the current value is received, the detection result of the temperature value is forcibly switched as the backup output.

[0012] The beneficial effects of this invention are: This invention proposes a dual-channel classifier latch-up detection method based on rapid current detection and temperature fallback detection. Current detection is used as the main detection channel, which can quickly determine the latch-up by utilizing the rapid change in power domain current at the initial stage of latch-up. Temperature detection is used as the fallback detection channel, and a preset arbitration mechanism is adopted for hierarchical decision-making. This can perform fallback latch-up detection based on the thermal effect caused by latch-up when the chip's operating mode is switched or when the current channel fails due to high noise environment, thus avoiding missed detections or false alarms.

[0013] The threshold setting of this invention uses the current current sample value and the difference between adjacent samples (current change information) to form an input vector, which is obtained through perceptron training. This makes the threshold no longer dependent on manual setting and solves the problem that the existing threshold setting method cannot be set due to changes in the working environment.

[0014] Furthermore, the perceptron weights of this invention are trained offline and fixed online, eliminating the need to perform the training process on an FPGA, which facilitates low-resource, low-latency, and streaming deployment. The overall system of this invention adopts streaming transmission, resulting in low detection latency. The FPGA implementation is highly flexible, allowing adjustment of data bit width and register depth according to different task requirements and resource constraints. Attached Figure Description

[0015] Figure 1 This is a flowchart of the latch detection method based on FPGA according to an embodiment of the present invention; Figure 2 This is a system architecture diagram of an FPGA-based latch detection system according to an embodiment of the present invention; Figure 3 This is the data path of the FPGA-based latch detection system in this embodiment of the invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0017] Example 1 FPGAs are widely used in spaceborne distributed systems, board-level control systems, and high-speed data acquisition systems. FPGA-based latch-up detection offers advantages such as high real-time performance, high parallelism, and strong scalability. However, traditional deep neural networks or complex machine learning algorithms typically require numerous multipliers, memory, and control resources, making them unsuitable for long-term online operation on resource-constrained FPGA nodes. Therefore, how to achieve rapid identification and fallback detection of power domain latch-up states under limited hardware resources is the core issue addressed in this invention.

[0018] In the prior art: One existing technical solution is fixed threshold overcurrent detection. This type of solution compares the sampled current with a set threshold, outputs a latch-up alarm signal when an overcurrent occurs, and then performs power-off, delay, and power-on actions via a power switch, current limiter, or protection state machine. This solution is simple in structure, has a fast response, and low implementation cost, making it the most common latch-up detection protection method in current engineering projects.

[0019] Existing technical solution two is a detection scheme based on the rate of change of current or a dynamic threshold. This scheme, in addition to determining whether the current amplitude exceeds the threshold, can also determine whether the current increment, slope, or rate of change per unit time exceeds preset conditions, thereby reducing false judgments caused by normal load changes. Some schemes also process the current waveform using moving averages, sliding windows, filtering, or dual thresholds, enabling the detection logic to adapt to a certain degree of load fluctuation.

[0020] The third existing technical solution is an anomaly detection or protection scheme based on temperature monitoring. This scheme uses temperature sensors, thermistors, on-chip temperature sensing units, or external temperature monitors to collect device temperature, and issues alarms or power-off protection when the temperature exceeds a safety threshold. This scheme can reflect the thermal effect caused by abnormal current, but because heat accumulation and diffusion take time, it is generally not suitable as the sole rapid detection signal.

[0021] The fourth existing technical solution is a current anomaly identification scheme based on machine learning or neural networks. This scheme can use sampled current waveforms, statistical features, or time series features to train a classifier to distinguish between normal operating conditions and abnormal latch-up states. This type of method has certain advantages in identifying complex waveforms, but if complex neural networks, recurrent networks, or nearest neighbor algorithms that store a large number of samples are used, the detection latency and hardware overhead will often be greatly increased.

[0022] The existing technical solutions mentioned above have certain limitations. Fixed threshold overcurrent detection can lead to missed detections when the threshold is set too high, and false alarms when the threshold is set too low. They are unsuitable for power domains with multiple operating states such as idle, working, and high load. Relying solely on a single current amplitude threshold makes it difficult to simultaneously achieve low missed detection rates and low false alarm rates. Detection schemes based on current change rate or dynamic thresholds mainly rely on manually set thresholds and rules, which are unsuitable for situations where the load current itself randomly switches or is subject to noise superposition. Detection delays using only temperature thresholds are too long, making it impossible to quickly disconnect the power domain in the early stages of latch-up. Detection using only current signals is prone to failure when the current signal is severely affected by latch-up, increasing the risk of device damage. Therefore, this invention complements temperature and current detection, primarily relying on current for rapid detection, with temperature detection serving only as a protective measure. Complex neural networks or machine information methods can effectively identify and classify waveforms, but they significantly increase detection delays in engineering implementation. Direct implementation via FPGA also consumes considerable hardware resources, making it unsuitable for deployment in scenarios such as spaceborne distributed nodes and resource-constrained boards.

[0023] Therefore, this implementation provides a dual-channel classifier latch-up detection method based on rapid current detection and temperature fallback detection, as shown in the flowchart below. Figure 1 As shown, it includes the following steps: S1: Collect the current value of the power domain and the temperature value of the node region of the monitored chip and store them in the FPGA shift register; obtain the difference between the current value and the temperature value of adjacent clock cycles through the subtractor to obtain the current change information and temperature change information.

[0024] S2: Output the current and temperature values ​​of the current clock cycle from the FPGA shift register, and obtain the current and temperature change information within the preset sampling interval from the subtractor output, and construct the current feature vector and temperature feature vector respectively.

[0025] S3: Using the pre-trained weight parameters and thresholds stored in the FPGA's internal registers or on-chip memory, the current feature vector and temperature feature vector are weighted and accumulated through multipliers and adders to obtain the current discrimination value and temperature discrimination value; the discrimination value is compared with the threshold by a comparator, and the corresponding latch-up risk detection results are output respectively.

[0026] S4: When the current value of the power domain of the monitored chip is valid, the detection result of the current value is used as the final output; when the current value is invalid, the output is forcibly switched to the detection result of the temperature value as the backup output.

[0027] Specifically, the current sampling and current feature generation methods in S1 and S2 include: In the current sensing channel, the ADC samples the current detected by the current sensor once per clock cycle according to the set sampling clock and outputs it to the FPGA interface. Its internal shift register receives one current value sampled by the ADC each clock cycle and then shifts it to the next register in the next clock cycle. The shift register has a depth of N and a width of n bits, and can store the current values ​​for N cycles. Assuming k is the current clock cycle, the I(k) sampled by the ADC is stored in the shift register, and the other values ​​in the shift register are I(k-1), I(k-2), ..., I(k-N+1).

[0028] The current change information is stored in another set of registers. The gradient register also has a depth of N and a width of n bits. It is obtained by subtracting the current value of the previous cycle from the current value of the next cycle of the shift register, denoted as ΔI(ki)=I(ki)-I(ki-1), where i=0,1,……,N-2.

[0029] Therefore, the input of the current sensor includes the current value I(k) and the current variation trend ΔI(k), ΔI(k-1), ..., ΔI(k-N+2) over a certain period of time, which together form the input vector FI(k) = [I(k), ΔI(k), ΔI(k-1), ..., ΔI(k-N+2)]. This input vector simultaneously contains information on the current amplitude and the current variation information within the most recent N-1 sampling intervals, enabling the sensor to identify dynamic features such as latch-up current increases, continuous anomalies, and local abrupt changes.

[0030] The temperature sampling and temperature feature generation methods in S2 specifically include: The method for generating the temperature feature vector is the same as that for generating the current feature vector. The temperature value sampled in the k-th cycle is T(k). The shift register has a depth of M and a width of mbit, and can store the current values ​​for a total of M cycles. The input vector of the temperature sensor can be represented as:

[0031] FT(k)=[T(k),ΔT(k),ΔT(k-1),…,ΔT(k-M+2)].

[0032] Among them: ΔT(ki)=T(ki)-T(ki-1), i=0,1,…,M-2.

[0033] Furthermore, the FPGA implementation of the sensor in S3 specifically includes: The sensor uses pre-training to obtain fixed weights; no online training is performed on the FPGA, only fixed weight multiplication and threshold comparison are executed. The pre-training process is completed externally to the FPGA, training on normal current samples and latch-up current samples to obtain fixed weight parameters [wI0, wI1, ..., wI(N-1)], [wT0, wT1, ..., wT(M-1)], and thresholds θI and θT. After training on the host computer, the weights and thresholds are fixed-point processed and stored in the FPGA's internal registers or on-chip memory. During latch-up detection, only the written fixed weights are used.

[0034] Taking current as an example, in the k-th clock cycle, each component of the current input vector FI(k) is multiplied by the weight of the corresponding weight register to obtain multiple product terms, which are then accumulated to obtain the current discrimination value SI(k). Subsequently, the discrimination value SI(k) is compared with the threshold θI. If it is greater than the threshold θI, 1 is output, indicating that latch-up risk has been detected in the current; if it is less than the threshold, 0 is output, indicating that latch-up risk has not been detected from the current channel.

[0035] Because the weights are fixed values, this invention does not require backpropagation, gradient updates, or complex control processes when implemented on an FPGA. Multiplication can be implemented using DSP resources, LUT multipliers, or shift-add structures based on fixed coefficients; summation can be implemented using adders; and threshold determination can be implemented using comparators. Therefore, this perceptron structure is suitable for deployment in an FPGA with a streaming data path, and can continuously output detection results along with the ADC sampling clock.

[0036] This embodiment proposes a latch-up arbitration module to fuse the detection results of the current channel and the temperature channel. Let the final latch-up detection output be O(k), the current sensor output be OI(k), the temperature sensor output be OT(k), and the current channel failure flag be EI(k). In one embodiment, the arbitration logic can be expressed as O(k) = OI(k) OR [EI(k) AND OT(k)]. When the current sensor detects a latch-up, O(k) immediately outputs 1; when the current sensor does not output a latch-up and the current channel is normal, the temperature channel does not participate in the final decision; when the current channel fails, if the temperature sensor outputs 1, then O(k) outputs 1 to achieve a baseline detection.

[0037] The final latch-up detection output O(k) can be connected to the power management module, power-off control module, neighbor node notification module, fault recording module, or upper-level system. When O(k) = 1, the system can perform protective operations such as cutting off the monitored power domain, limiting the supply current, recording the fault time, notifying neighboring nodes, entering isolation state, or waiting for the temperature to recover before re-energizing. The above protective actions are not the only execution method required by this invention; the core of this invention lies in generating a reliable latch-up detection output through main current detection and temperature fallback detection. The data path of this invention is as follows: Figure 3 As shown

[0038] In this invention, the parameters of the shift register, such as depth N / M, data bit width, and sampling frequency, can be specifically configured according to the actual working environment of the monitored chip and the latch-up detection delay requirements. A larger register depth contains more historical information, and a larger data bit width results in higher sampling resolution, but also higher hardware resource consumption. The resource consumption of a specific example is shown in Table 1.

[0039] Table 1. Shift Register Resource Consumption Statistics This embodiment also proposes an FPGA implementation device based on rapid current detection and temperature fallback detection. The device includes a current sampling module, a current feature generation module, a current sensor module, a temperature sampling module, a temperature feature generation module, a temperature sensor module, a current channel validity judgment flag, and a latch arbitration module. The connection relationships of each module are as follows: Figure 2 As shown, the current sensor, temperature sensor, and sampling ADC are all analog signal acquisition parts, while the remaining signal processing algorithms are digital signal parts implemented by FPGA.

[0040] The system comprises several modules: a current sampling module to monitor the current in the measured power domain and convert it into a digital signal that can be processed by the FPGA; a current sensor and a sampling ADC to acquire the current signal; and a current feature generation module to generate current and differential current feature vectors, consisting of a shift register and a subtractor. A current sensor module to determine whether the current state is latched based on pre-trained fixed weights. A temperature sampling module to acquire the temperature of the monitored chip or node, which is also processed into a digital signal by the ADC. A temperature feature generation module to generate the current temperature and its differential temperature features. A temperature sensor module to provide a fallback decision in case of current detection failure. A latch-up arbitration module to generate the final latch-up detection result based on the current sensor output, the temperature sensor output, and the current channel validity flag.

[0041] This invention employs a layered detection logic, using current as the primary detection channel for rapid detection and temperature as a backup detection channel for fallback detection. When the chip is operating in a steady state, the current detection channel serves as the primary output, ensuring detection speed. When the chip is switching operating modes or the current detection channel is unavailable, the temperature detection channel acts as a safety protection mechanism, preventing overheating and chip burnout.

[0042] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A latch detection method based on FPGA, characterized in that, Includes the following steps: The current value of the power domain and the temperature value of the node region of the monitored chip are collected and stored in the FPGA shift register; the difference between the current value and the temperature value between adjacent clock cycles are obtained through a subtractor to obtain current change information and temperature change information. The FPGA shift register outputs the current and temperature values ​​for the current clock cycle, and the subtractor outputs the current and temperature change information within a preset sampling interval to construct current and temperature feature vectors respectively. By using the pre-trained weight parameters and thresholds stored in the FPGA's internal registers or on-chip memory, the current feature vector and temperature feature vector are weighted and accumulated through multipliers and adders to obtain the current discrimination value and temperature discrimination value. The discriminant value is compared with the threshold by a comparator, and the corresponding latch-up risk detection results are output respectively; wherein, the weight parameters and threshold are obtained by training the sensor on normal current or temperature feature vector samples and latch-up current or temperature feature vector samples. When the current value of the power domain of the monitored chip is valid, the detection result of the current value is used as the final output; when the current value is invalid, the output is forcibly switched to the detection result of the temperature value as the backup output.

2. The latch detection method based on FPGA according to claim 1, characterized in that, The construction of the current feature vector includes the following steps: The current change information is obtained by subtracting the current value of the previous cycle from the current value of the next cycle of the FPGA shift register using a subtractor: ΔI(ki)=I(ki)-I(ki-1), where i=0,1,……,N-2; where N is the depth of the shift register; The current value I(k) is obtained from the FPGA shift register and together with the current change information ΔI(k), ΔI(k-1), ..., ΔI(k-N+2) within the preset sampling interval, they form the input vector: FI(k) = [I(k), ΔI(k), ΔI(k-1), ..., ΔI(k-N+2)].

3. The latch detection method based on FPGA according to claim 2, characterized in that, The current change information is stored in the gradient register of the FPGA, with the same depth and width as the FPGA shift register.

4. The latch detection method based on FPGA according to claim 1, characterized in that, The storage of the current value in the FPGA shift register includes the following steps: The current signal of the power domain of the monitored chip is acquired by a current sensor. The sampling ADC samples the current detected by the current sensor once per clock cycle according to the set sampling clock and outputs it to the FPGA interface. The shift register set inside the FPGA receives a current value sampled by the ADC every clock cycle and shifts it to the next shift register in the next clock cycle.

5. The latch detection method based on FPGA according to claim 1, characterized in that, The pre-trained weight parameters and thresholds include the following steps: By training the sensor on normal current or temperature samples and latch-up current or temperature samples, fixed weight parameters [wI0, wI1, ..., wI(N-1)], [wT0, wT1, ..., wT(M-1)] and current threshold θI or temperature threshold θT are obtained. After training is completed, the weights and thresholds are fixed-point processed and stored in the FPGA's internal registers or on-chip memory.

6. The latch detection method based on FPGA according to claim 1, characterized in that, The failure flag for the current value is EI(k), the detection result of the current value is OI(k), and the detection result of the temperature value is OT(k). Then the arbitration logic for the final output O(k) is: O(k) = OI(k) OR [EI(k) AND OT(k)]; When a latch is detected by the current value, O(k) immediately outputs 1; when no latch is detected and the current value is monitored normally, the temperature value does not participate in the final decision; when the current value fails, if the temperature sensor outputs 1, then O(k) outputs 1 to achieve a backup detection.

7. A latch detection system based on FPGA, characterized in that, The system includes: The current sampling module is used to collect the current value in the power domain of the monitored chip; The current feature generation module is used to obtain the difference in current values ​​between adjacent clock cycles through a subtractor, thereby obtaining current change information. The current sensor module is used to perform weighted summation of the current feature vector using multipliers and adders based on pre-trained fixed weights to obtain a current discrimination value; and to compare the discrimination value with a threshold using a comparator to output the latch-up risk detection result corresponding to the current value. The temperature sampling module is used to collect the temperature value of the monitored chip node area; The temperature feature generation module is used to obtain the temperature difference between adjacent clock cycles through a subtractor to obtain temperature change information. The temperature sensor module is used to perform weighted summation of the temperature feature vector using multipliers and adders based on pre-trained fixed weights to obtain a temperature discrimination value; and to compare the discrimination value with a threshold using a comparator to output the latch-up risk detection result corresponding to the temperature value. The current path validity judgment flag is used to determine whether the current value in the power domain of the monitored chip has failed and to provide a valid flag for the current value. The latch arbitration module is used to arbitrate the detection results based on whether the current value is invalid. When the current value of the power domain of the monitored chip is valid, that is, when no failure flag of the current value is received, the detection result of the current value is used as the final output. When a failure flag of the current value is received, the detection result of the temperature value is forcibly switched as the backup output.

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