Radar system and intelligent driving vehicle

Abstract

The application provides a radar system and an intelligent driving vehicle, and relates to the technical field of radars.The radar system comprises a reference clock generator, a timing generator and a synchronization state machine;the reference clock generator is used for generating a reference clock signal;the timing generator is used for generating a start pulse signal based on the reference clock signal;the synchronization state machine is used for carrying out multi-path delay on the start pulse signal to obtain a multi-path delay pulse signal, and outputting a target delay pulse signal in the multi-path delay pulse signal which is synchronized with the edge of the reference clock signal as a target start pulse signal.The radar system can dynamically detect and offset systematic timing drift introduced by high and low temperatures, voltage fluctuations and process angle deviation in real time, eliminate timing random jitter across clock domains, and significantly improve the robustness and ranging and speed measurement accuracy of the radar system under complex working conditions.

Description

Technical Field

[0001] This application relates to the field of radar technology, and more particularly to a radar system and an intelligent driving vehicle. Background Technology

[0002] Frequency-modulated continuous wave (FM-CW) radar is widely used in vehicle systems, UAV obstacle avoidance systems, industrial non-destructive testing, and intelligent security. Signal processing across clock domains in radar systems can easily introduce timing jitter. This jitter causes random shifts in the timing of the FM-CW chirp signal, resulting in varying degrees of delay in the start times of different chirp signals. This significantly reduces velocity measurement resolution and can even affect the ability to detect targets.

[0003] In existing technologies, a fixed-delay calibration solution based on hardware storage units is used to address the timing random offset jitter problem of chirped signals. This technology eliminates jitter through a fixed-delay link, but lacks adaptive dynamic compensation capabilities, resulting in a slowly accumulating systematic timing deviation in the intra-frame chirped signal. Summary of the Invention

[0004] This application provides a radar system and an intelligent driving vehicle that can dynamically detect and counteract systematic timing drift caused by high and low temperatures, voltage fluctuations and process angle deviations in real time, and eliminate random timing jitter across clock domains.

[0005] In a first aspect, this application provides a radar system, including a reference clock generator, a timing generator, and a synchronization state machine; wherein the reference clock generator is connected to the timing generator and the synchronization state machine respectively, and the timing generator is connected to the synchronization state machine.

[0006] The reference clock generator is used to generate a reference clock signal;

[0007] The timing generator is used to generate a start pulse signal based on the reference clock signal;

[0008] The synchronous state machine is used to perform multiple delays on the start pulse signal to obtain multiple delayed pulse signals, and based on the reference clock signal, outputs the target delayed pulse signal that is synchronized with the edge of the reference clock signal among the multiple delayed pulse signals as the target start pulse signal.

[0009] Optionally, the synchronization state machine includes a delay chain and a synchronization selector; the delay chain is connected to the synchronization selector.

[0010] The delay chain is used to delay the start pulse signal in multiple ways to obtain the multi-delayed pulse signal;

[0011] The synchronization selector is used to determine, based on the reference clock signal, a target delayed pulse signal that is synchronized with the edge of the reference clock signal from the multiple delayed pulse signals, and output the target delayed pulse signal as the target start pulse signal.

[0012] Optionally, the synchronization selector includes a synchronizer and a selector; the synchronizer is connected to the selector, the delay chain, and the reference clock generator respectively, and the selector is connected to the delay chain;

[0013] The synchronizer is used to sample the inverse signal of the reference clock signal based on the multi-channel delayed pulse signal to obtain a multi-channel synchronization signal;

[0014] The selector is used to detect the multiple synchronization signals to determine the target synchronization signal that is synchronized with the edge of the reference clock signal, and outputs the target delay pulse signal corresponding to the target synchronization signal as the target start pulse signal.

[0015] Optionally, the synchronizer includes an inverter and multiple flip-flops;

[0016] The input terminal of the inverter is connected to the reference clock generator, and the output terminal of the inverter is connected to the data terminal of each of the flip-flops; the clock terminal of each of the flip-flops is connected to the delay chain respectively.

[0017] The trigger is used to output the synchronization signal on the rising edge of the delayed pulse signal.

[0018] Optionally, the selector includes a delay detector and a multiplexer; the delay detector is connected to the multiplexer, the delay detector is connected to the synchronizer, and the multiplexer is connected to the delay chain;

[0019] The delay detector is used to detect the multiple synchronization signals and determine the target synchronization signal that is synchronized with the edge of the reference clock signal;

[0020] The multiplexer is used to output the target delay pulse signal corresponding to the target synchronization signal as the target start pulse signal.

[0021] Optionally, the delay detector is used to sample the multiple synchronization signals and determine the target synchronization signal based on the sampled values ​​of the multiple synchronization signals.

[0022] Optionally, the delay detector is used to concatenate the sample values ​​of the first synchronization signal and a plurality of second synchronization signals following the first synchronization signal into an array, and when the first sample value in the array is 0 and the other sample values ​​are 1, the first synchronization signal is determined as the target synchronization signal.

[0023] Optionally, the multi-channel delayed pulse signal is a multi-channel equally spaced delayed pulse signal.

[0024] Optionally, the delay time range of the multi-channel delayed pulse signal is greater than or equal to the period of the reference clock signal.

[0025] Optionally, it further includes: a synthesizer phase-locked loop; the synthesizer phase-locked loop is connected to the reference clock generator, and the synthesizer phase-locked loop is connected to the synchronization state machine;

[0026] The synthesizer phase-locked loop is used to output a carrier signal based on the reference clock signal, the target start pulse signal, and the feedback clock signal of the synthesizer phase-locked loop.

[0027] Optionally, the synthesizer phase-locked loop includes: a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a feedback frequency divider, and a delta-sigma modulator;

[0028] The phase frequency detector, the charge pump, the low-pass filter, and the voltage-controlled oscillator are connected in sequence. The phase frequency detector is connected to the reference clock generator, the phase frequency detector is connected to the feedback divider, the voltage-controlled oscillator is connected to the feedback divider, the feedback divider is connected to the delta-sigma modulator, and the delta-sigma modulator is connected to the synchronization state machine.

[0029] Optionally, it further includes: a frequency multiplier unit; the frequency multiplier unit is connected to the synthesizer phase-locked loop;

[0030] The frequency multiplier unit is used to up-frequency the carrier signal and output a chirped signal.

[0031] Optionally, it further includes: a receiver; the receiver is connected to the reference clock generator, and the receiver is used to receive the echo signal reflected by the target.

[0032] Optionally, it further includes: a processor, the processor being configured to determine the distance to the target based on the beat frequency of the beat frequency signal of the chirped signal and the echo signal, and / or to determine the speed of the target based on the phase difference of the beat frequency signal.

[0033] Secondly, this application provides an intelligent driving vehicle, including: the radar system as described in the first aspect.

[0034] The radar system and intelligent driving vehicle provided in this application use a synchronous state machine to multi-delay the start pulse signal to obtain multiple delayed pulse signals. Based on a reference clock signal, the target delayed pulse signal that is synchronized with the edge of the reference clock signal is output as the target start pulse signal. This achieves a constant phase delay between the feedback clock signal and the target start pulse signal. By dynamically detecting and adaptively selecting the target delayed pulse signal that is aligned with the edge of the reference clock signal as the target start pulse signal, it can offset the systematic timing drift introduced by high and low temperatures, voltage fluctuations and process angle deviations, eliminate random timing jitter across clock domains, and significantly improve the robustness and ranging and speed measurement accuracy of the radar system under complex operating conditions. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0036] Figure 1 A schematic diagram of a continuous wave chirped signal provided in an embodiment of this application;

[0037] Figure 2 A schematic diagram of a continuous wave chirped signal data frame provided in an embodiment of this application;

[0038] Figure 3 A radar system transmitter assembly diagram provided for an embodiment of this application;

[0039] Figure 4 This application provides a schematic diagram of the structure of a radar system according to an embodiment of the present application.

[0040] Figure 5 Timing diagrams of various signals of the radar system provided in the embodiments of this application;

[0041] Figure 6 This is a schematic diagram of the composition structure of the synchronization state machine provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of the composition structure of the synchronization selector provided in the embodiments of this application;

[0043] Figure 8 This is a schematic diagram of the synchronizer structure provided in an embodiment of this application;

[0044] Figure 9 This is a schematic diagram of the selector structure provided in an embodiment of this application;

[0045] Figure 10 A phase-locked loop connection diagram of a radar system synthesizer is provided for embodiments of this application;

[0046] Figure 11 This is a schematic diagram of the synthesizer phase-locked loop structure provided in the embodiments of this application;

[0047] Figure 12 A connection diagram of a radar system frequency multiplier unit is provided for an embodiment of this application;

[0048] Figure 13 A radar system receiver connection diagram provided in this application embodiment;

[0049] Figure 14 This is a radar system processor connection diagram provided for an embodiment of this application.

[0050] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0051] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0052] The radar system proposed in this application is widely used in vehicle systems, drone obstacle avoidance systems, industrial non-destructive testing and intelligent security. Taking vehicle-mounted millimeter-wave radar as an example, vehicle-mounted millimeter-wave radar is one of the core sensors of advanced driver assistance systems and autonomous driving. It is usually installed in front, behind or at the corner of the vehicle to detect targets in the surrounding environment in real time, and can provide the target's distance, speed and angle information.

[0053] Radar systems typically employ a Frequency Modulated Continuous Wave (FMCW) mechanism, transmitting a chirped signal whose frequency varies linearly with time. (See reference...) Figure 1 The diagram shows a continuous wave chirped signal. The horizontal axis represents time, and the vertical axis represents frequency; the fundamental frequency 11 represents the starting frequency of each chirped signal; the maximum frequency 13 represents the highest frequency at the end of the frequency sweep of each chirped signal; and chirped signal 12 represents one linear frequency modulation process from the fundamental frequency 11 to the maximum frequency 13. Figure 1The frequency is represented by a sloping line; the duration 15 represents the time it takes for a single chirp signal to rise from the base frequency 11 to the maximum frequency 13; the idle time 14 represents the time from the end of the current chirp signal to the start of the next chirp signal, during which the frequency remains near the base frequency; the pulse repetition interval 16 represents the interval between the start of the previous chirp signal and the start of the next chirp signal, which is equal to the sum of the duration 15 and the idle time 14, and determines the maximum Doppler range detectable by the radar system. Each linearly rising ramp from low to high is a chirp signal 12, with the frequency starting from the base frequency 11, rising to the maximum frequency 13 after a duration of 15, then quickly returning to the base frequency, and maintaining the base frequency 11 during the idle time 14, waiting for the start of the next chirp signal 12. The radar system receives the echo chirp signal reflected back from the target. Due to the propagation delay, there is a time difference between the echo chirp signal and the transmitted chirp signal. After the two are mixed, a beat frequency signal is generated. The frequency of the beat frequency signal is proportional to the target distance. The beat frequency signal is also superimposed with Doppler frequency shift, which reflects the relative speed of the target.

[0054] A combination of multiple chirped signals is called a continuous wave chirped signal data frame, as referenced. Figure 2 The diagram shows a continuous wave chirped signal data frame. The horizontal axis represents time, and the vertical axis represents frequency. Figure 2 A complete data frame 23 is divided into an acquisition period 21 and an inter-frame period 22. Within the acquisition period 21, the signal frequency rises linearly in a sawtooth wave pattern. Each ramp from the fundamental frequency to the maximum frequency and then rapidly falls back constitutes a chirp signal; multiple chirp signals together form the transmission sequence of the data frame. The inter-frame period 22 is the idle time between two frames. During the idle time, the radar system does not transmit chirp signals and is typically used to complete signal processing, parameter updates, or wait for the next measurement.

[0055] Figure 3This diagram shows the components of a radar system transmitter. The transmitter consists of a crystal oscillator 111, a frequency synthesizer 112, a signal transmitter 113, and a time engine 114. The signal generator 113 includes a phase-frequency detector 1131, a charge pump 1132, a loop filter 1133, a voltage-controlled oscillator 1134, a frequency divider 1135, and a modulator 1136. The crystal oscillator 111 generates a fundamental frequency, which, after being multiplied by the frequency synthesizer 112, provides a reference clock signal for the time engine 114 and the signal generator 113. The time engine 114 sends a start pulse signal to trigger the chirp signal, driving the modulator 1136 inside the signal transmitter 113. The modulator 1136 samples the start pulse signal based on the feedback clock signal provided by the frequency divider 1135, dynamically changing the division ratio of the frequency divider 1135 to generate a linearly modulated chirp signal. The phase frequency detector 1131 compares the phase difference between the reference clock signal and the feedback clock signal of the frequency divider 1135, converting it into a charging and discharging current signal, which is then converted into a smooth DC control voltage by the charge pump 1132 and the loop filter 1133. The DC control voltage acts on the voltage-controlled oscillator 1134, causing it to output a chirp signal whose frequency changes linearly with time. The reference clock signal generated by the frequency synthesizer 112 in the radar system transmitter and the feedback clock signal provided by the frequency divider 1135 in the signal transmitter 113 belong to different clock domains. Affected by process-voltage-temperature (PVT) factors, the timing of the frequency-modulated continuous wave chirped signal will change randomly due to the two different clock domains, resulting in different degrees of delay in the start time of different chirped signals.

[0056] Existing technologies employ asynchronous dual-clock register read / write to reduce chirp jitter by forcibly setting a fixed offset for the First-In-First-Out (FIFO) read / write pointers. This offset is a hardware-fixed constant and cannot be dynamically adjusted after factory release. While this method eliminates jitter through a fixed-delay link, it cannot suppress systematic drift errors introduced by automotive high / low temperatures, voltage fluctuations, and process corner deviations. When chip process deviations are large, clock frequency shifts occur, or extreme high / low temperature conditions cause significant phase shifts in the dual-clock domains, the fixed offset ratio is no longer the optimal timing point. This can easily lead to insufficient timing margins, violations of critical timing establishment and maintenance rules, and potential timing collapse risks under extreme conditions.

[0057] To address the aforementioned problems, this application proposes a radar system. This radar system includes a reference clock generator, a timing generator, and a synchronization state machine. The reference clock generator generates a reference clock signal; the timing generator generates a start-up pulse signal based on the reference clock signal; the synchronization state machine performs multi-path delay on the start-up pulse signal and, based on the reference clock signal, selects the edge-synchronized target delayed pulse signal from the multi-path delayed pulse signals as the target start-up pulse signal for output. This system effectively solves the phase randomness problem of cross-domain clock signals, achieves dynamic synchronization and alignment of the start-up pulse signal, and meets the stability requirements of high-precision imaging radar under all temperature and operating conditions.

[0058] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0059] Figure 4 A schematic diagram of the structure of a radar system provided in this application embodiment. Figure 4 . Reference Figure 4 As shown, the radar system includes: a reference clock generator 100, a timing generator 200, and a synchronization state machine 300.

[0060] The reference clock generator 100 is connected to the timing generator 200 and the synchronization state machine 300 respectively, and the timing generator 200 is connected to the synchronization state machine 300.

[0061] Reference clock generator 100 generates a reference clock signal; timing generator 200 generates a start pulse signal based on the reference clock signal; synchronization state machine 300 performs multiple delays on the start pulse signal to obtain multiple delayed pulse signals, and outputs the target delayed pulse signal that is synchronized with the edge of the reference clock signal among the multiple delayed pulse signals as the target start pulse signal based on the reference clock signal.

[0062] The reference clock generator 100 serves as the frequency reference source for the radar system. The reference clock generator 100 may include, for example, a quartz crystal resonator, a phase-locked loop (PLL) circuit, and a drive circuit. The quartz crystal resonator converts the mechanical vibrations of the crystal into a stable fundamental frequency signal and outputs it to the PLL circuit. The PLL circuit synthesizes the fundamental frequency signal into a high-frequency signal and outputs it to the drive circuit. The drive circuit shapes the high-frequency signal input to the PLL into a square wave with steep edges, amplifies and drives it, and outputs the reference clock signal to the timing generator 200 and the synchronization state machine 300. The reference clock signal is the sole time base source for the radar system, and its rising / falling edges provide a time reference for timing operations in all subsequent embodiments.

[0063] The timing generator 200 is the timing engine of the radar system, which may include a programmable counter and a numerical comparator. The timing generator 200 can generate a start pulse signal with a specific pulse width and repetition period based on a reference clock signal. For example, the programmable counter is driven by the rising edge of the input reference clock signal and accumulates the count value periodically. The numerical comparator monitors the count value in real time. When the count value reaches a preset threshold M, the numerical comparator triggers the output level to flip, that is, from low level to high level, generating the rising edge of the start pulse signal. When the count value continues to accumulate to another preset value, the numerical comparator triggers the output level to flip, that is, from high level to low level, generating the falling edge of the start pulse signal, completing a complete pulse signal cycle. The programmable counter is then cleared and restarts counting, realizing the periodic output of the start pulse signal. The timing generator 200 transmits the start pulse signal to the synchronization state machine 300.

[0064] The synchronous state machine 300 copies the input start pulse signal into multiple signals and adds different delay amounts to each signal to generate multiple delayed pulse signal outputs. Using the edge of the reference clock signal as a unified time base, the edge positions of the multiple delayed pulse signals are determined in parallel, and the delayed pulse signal that is synchronized with the edge of the reference clock signal (i.e., phase synchronized) is selected as the target delayed pulse signal. The selected target delayed pulse signal is locked as the final output target start pulse signal, achieving strict alignment between the start pulse signal and the edge of the reference clock signal. It should be noted that, in this embodiment, selecting the delayed pulse signal synchronized with the edge of the reference clock signal from the multiple delayed pulse signals means selecting the delayed pulse signal whose edge phase is closest to that of the reference clock signal.

[0065] Example, Figure 5 The timing diagrams for various signals of the radar system provided in this application embodiment include a reference clock signal (REFCLK) 702, an inverted clock signal (REFCLK') 703, a start pulse signal (CHIRP-START) 706, a multi-channel delayed pulse signal (CHIRP_START_DELAY_CHAIN) 708, a multi-channel synchronization signal (CHIRP_START_SYN) 710, a target start pulse signal (CHIRP_START_OUT) 712, and a feedback clock signal (FBCLK) 704. Figure 5 It can be seen that the multi-channel delayed pulse signal 708 is a multi-channel signal with different delay amounts corresponding to the start pulse signal 706. The target start pulse signal 712 is a delayed pulse signal 708 determined from the multi-channel delayed pulse signal 708 that is synchronized with the falling edge of the reference clock signal 702. Figure 5Other timing signals illustrated herein will be described in subsequent embodiments.

[0066] In this embodiment, the synchronization state machine 300 performs multi-stage cascaded delay on the start pulse signal 706 output by the timing generator 200, generating a set of multi-path delayed pulse signals 708 with increasing phase intervals. Using the edge of the reference clock signal 702 as a reference, it performs phase filtering, selecting in real time the target delayed pulse signal 712 that is phase-synchronized with the edge of the reference clock signal 702, and dynamically locking the output as the target start pulse signal. This mechanism enables the synchronization state machine 300 to dynamically track and compensate for static timing deviations introduced by absolute delay drift of the delay path under complex operating conditions such as high and low temperatures in vehicles, power supply voltage fluctuations, and chip process corner deviations, thus meeting the full-temperature, full-domain stability requirements of high-precision imaging radar.

[0067] In one implementation, reference Figure 6 As shown, the synchronous state machine 300 includes a delay chain 301 and a synchronization selector 302; the delay chain 301 is connected to the synchronization selector 302.

[0068] Delay chain 301 is used to delay the start pulse signal 706 in multiple ways to obtain multiple delayed pulse signals 708;

[0069] Synchronization selector 302 is used to determine the target delay pulse that is synchronized with the edge of the reference clock signal 702 from the multiple delay pulse signals 708 based on the reference clock signal 702, and output the target delay pulse as the target start pulse signal 712.

[0070] The delay chain 301 can be composed of multiple delay units connected in series. For example, multiple delay units are connected in series from the first delay unit, with the output of the previous delay unit connected to the input of the next delay unit, until the last delay unit. Each delay unit in the delay chain 301 outputs a delayed pulse signal 708. For example, when a start pulse signal 706 is input to the delay chain 301, the start pulse signal 706 is transmitted sequentially through the multiple series-connected delay units. During transmission, the output of each delay unit generates a delayed pulse signal 708 with a different delay amount relative to the original start pulse signal 706. The multiple delayed pulse signals 708 output from each delay unit are simultaneously sent to the synchronization selector 302.

[0071] The arrival time of the start pulse signal 706 relative to the edge of the reference clock signal 702 is often random, and there is an unpredictable phase difference between the two. The delay chain 301 expands the start pulse signal 706 into a series of pulses with increasing phase intervals, namely, multiple delayed pulse signals 708. The synchronization selector 302 selects the one that is synchronized with the edge of the reference clock signal 702 as the output, effectively eliminating the phase deviation between the start pulse signal and the reference clock signal.

[0072] Synchronization selector 302 receives multiple delayed pulse signals 708 from delay chain 301 and simultaneously receives reference clock signal 702. For example, synchronization selector 302 detects the falling edge of reference clock signal 702 and, based on the arrival time of the falling edge, selects a target delayed pulse from the multiple delayed pulse signals 708 whose phase is synchronized with that edge, and outputs the target delayed pulse as target start pulse signal 712.

[0073] Optionally, the synchronization selector 302 can use a trigger array to sample the output signals of each delay unit in the delay chain 301. The specific implementation process can be described in detail in subsequent embodiments.

[0074] In one implementation, reference Figure 7 As shown, the synchronization selector 302 includes a synchronizer 3021 and a selector 3022; the synchronizer 3021 is connected to the selector 3022, the delay chain 301, and the reference clock generator 100 respectively, and the selector 3022 is connected to the delay chain 301.

[0075] Synchronizer 3021 is used to sample the inverse signal of reference clock signal 702 based on multi-channel delayed pulse signal 708 to obtain multi-channel synchronization signal 710.

[0076] Selector 3022 is used to detect the multiple synchronization signals 710 to determine the target synchronization signal that is synchronized with the edge of the reference clock signal 702, and outputs the target delay pulse signal 712 corresponding to the target synchronization signal as the target start pulse signal 712.

[0077] For example, synchronizer 3021 receives multiple delayed pulse signals 708 from delay chain 301, and simultaneously receives the inverse signal of reference clock signal 702 provided by reference clock generator 100, i.e., inverted clock signal 703. Synchronizer 3021 samples inverted clock signal 703 using the edges of the multiple delayed pulse signals 708 as sampling trigger times. Specifically, when the rising edge of the multiple delayed pulse signals 708 arrives, synchronizer 3021 latches the level state of inverted clock signal 703 at the current sampling time, forming multiple synchronization signals 710 which are output to selector 3022. This allows selector 3022 to determine the target synchronization signal that is synchronized with the edge of inverted clock signal 703, i.e., synchronized with the edge of reference clock signal 702, from the multiple synchronization signals 710. Then, it outputs one delayed pulse signal 708 corresponding to the target synchronization signal as target start pulse signal 712. It should be noted that, in the embodiments of this application, selecting one synchronization signal 710 from the multiple synchronization signals 710 that is synchronized with the edge of the reference clock signal 702 means selecting the synchronization signal 710 from the multiple synchronization signals 710 that is closest in phase to the edge of the reference clock signal 702.

[0078] The embodiments of this application utilize the complementary relationship between the edge of the inverted clock signal 703 and the edge of the reference clock signal 702 to make the sampling time of the synchronizer 3021 and the reference time for the subsequent edge detection of the selector 3022 staggered in time, so as to reserve sufficient setup time and hold time margin for the sampling output of the synchronizer 3021, and avoid timing conflicts or metastability problems caused by the simultaneous occurrence of sampling and detection.

[0079] For example, after receiving the multiple synchronization signals 710 output by the synchronizer 3021, the selector 3022 detects the multiple synchronization signals 710. During the detection process, the selector 3022 compares the level states of each synchronization signal 710 in sequence: for the multiple synchronization signals 710 arranged in order of delay time, the selector 3022 detects the level of each of the multiple synchronization signals 710 starting from the first one. When a transition from low to high is detected in the level of an adjacent multiple synchronization signal 710, the position of the transition is recorded. The selector 3022 determines the corresponding synchronization signal number based on the transition position, and then selects the corresponding one from the multiple delayed pulse signals 708 input to the delay chain 301 according to the synchronization signal number, and outputs the target delayed pulse as the target start pulse signal 712.

[0080] In one implementation, reference Figure 8 As shown, the synchronizer 3021 includes an inverter 30211 and N flip-flops 30212 (flip-flops 30212-1 to flip-flops 30212-N).

[0081] The input of inverter 30211 is connected to reference clock generator 100, and the output of inverter 30211 is connected to the data terminals of N flip-flops 30212; the clock terminals of the N flip-flops 30212 are respectively connected to delay chain 301.

[0082] N flip-flops 30212 are used to output a synchronization signal on the rising edge of the multi-channel delayed pulse signal 708.

[0083] For example, the reference clock signal 702 output by the reference clock generator 100 first enters the inverter 30211. The inverter 30211 inverts the reference clock signal 702 to form an inverted clock signal 703, which is then output to the data terminals of N flip-flops 30212. The inverted clock signal 703 serves as the input signal to be sampled by the N flip-flops 30212, and its level is always opposite to the original level of the reference clock signal 702.

[0084] Simultaneously, the multiple delayed pulse signals 708 output by the delay chain 301 are respectively connected to the clock terminals of N flip-flops 30212. Since each signal in the multiple delayed pulse signals 708 is delayed by one unit relative to the previous one, the clock terminals of flip-flops 30212-1 to 30212-N will receive rising edges sequentially at different times. When the clock terminals of flip-flops 30212-1 to 30212-N receive the rising edge of the delayed pulse signal 708, the flip-flops immediately sample the inverted clock signal 703 currently received at the data terminal, latch the sampled level state, and output it from the output terminal to form multiple synchronization signals 710.

[0085] In one implementation, reference Figure 9 As shown, selector 3022 includes delay detector 30221 and multiplexer 30222; delay detector 30221 is connected to multiplexer 30222, delay detector 30221 is connected to synchronizer 3021, and multiplexer 30222 is connected to delay chain 301.

[0086] The delay detector 30221 is used to detect the multi-channel synchronization signal 710 and determine the target synchronization signal that is synchronized with the edge of the reference clock signal 702.

[0087] The multiplexer 30222 is used to output the target delay pulse corresponding to the target synchronization signal 710 as the target start pulse signal 712.

[0088] For example, delay detector 30221 receives multiple synchronization signals 710 output by synchronizer 3021. The number of multiple synchronization signals 710 is the same as the number of multiple synchronization delay signals 708 output by delay chain 301, and they are labeled as signals 1 to N respectively. The average voltage level of each signal in multiple synchronization signals 710 has been latched by synchronizer 3021, and the signal level remains stable during processing by delay detector 30221.

[0089] In one embodiment, the delay detector 30221 is used to sample the multi-channel synchronization signal 710 and determine the target synchronization signal based on the sampled values ​​of the multi-channel synchronization signal 710.

[0090] The delay detector 30221 samples the first to Nth synchronization signals of the input multi-channel synchronization signals 710 simultaneously, acquiring the level state of each synchronization signal and distinguishing high and low levels into two different logic states. The first to Nth synchronization signals of the multi-channel synchronization signals 710 are arranged in ascending order of delay time, with the first synchronization signal having the smallest delay and its edge appearing earliest, while the Nth synchronization signal has the largest delay and its edge appearing latest.

[0091] After sampling, the delay detector 30221 arranges the level states of the first to Nth synchronization signals sequentially from the first to the Nth signal, and then performs sliding splicing in groups of four adjacent signals to form multiple four-bit data combinations. The data splicing method is as follows: the first, second, third, and fourth signals form the first combination; the second, third, fourth, and fifth signals form the second combination; the third, fourth, fifth, and sixth signals form the third combination, and so on, sliding one bit to the right until the last four signals are covered. For each spliced ​​four-bit combination, the delay detector 30221 performs specific state pattern matching detection, determining whether the combination exhibits a level distribution characteristic where the first bit is low and the last three bits are high. When the delay detector 30221 detects a four-bit combination that exactly matches this state distribution, it indicates that there is a low-to-high level transition in the four signals corresponding to that combination. The transition indicates that the edge of the delayed pulse corresponding to the first signal in the combination has not yet reached the edge of the reference clock signal 702, while the edges of the delayed pulses corresponding to the subsequent three signals have all passed the edge of the reference clock signal 702. The position of this transition directly indicates that the edge of the reference clock signal 702 falls exactly within the delay interval corresponding to the first and second signals in the combination.

[0092] When the delay detector 30221 detects a four-bit combination that matches the aforementioned state characteristic of the first bit being low and the last three bits being high, it determines that the synchronization signal corresponding to the first bit in that combination is the target synchronization signal. Specifically, if the combination formed by splicing the nth, n+1th, n+2th, and n+3th channels exhibits this specific state characteristic, then the delay detector 30221 determines the signal corresponding to the value n as the target synchronization signal. Subsequently, the delay detector 30221 generates a corresponding gating control signal at its output terminal based on the number of the target synchronization signal. This gating control signal is output in binary code form and continuously and stably transmitted to the control terminal of the multiplexer 30222.

[0093] The delay detector 30221 re-detects and judges the multiple synchronization signals 710 output by the synchronizer 3021 in each reference clock cycle, and the multiplexer 30222 dynamically updates the selected channel accordingly. When environmental factors such as radar system temperature and power supply voltage change, causing the delay amount of the delay chain 301 to drift, the jump position detection result of the delay detector 30221 will shift forward or backward accordingly, and the multiplexer 30222 will automatically switch to the new corresponding channel output, so that the system always outputs a target start pulse signal synchronized with the edge of the reference clock, realizing dynamic compensation for changes in process, voltage, and temperature.

[0094] The delay detector 30221 repeats the above sampling, arranging, grouping, identification and output process to ensure that the gating control signal can be updated in real time according to the actual level of each synchronization signal at the current moment, thereby realizing dynamic tracking of the edge position of the reference clock signal 702.

[0095] Multiplexer 30222 receives a gating control signal from delay detector 30221 at its control terminal, while its multiple data input terminals receive multiple delayed pulse signals 708 from delay chain 301. Multiplexer 30222 internally decodes the gating control signal received at its control terminal to extract the number specified by delay detector 30221. For example, if the received gating control signal corresponds to number 4, the internal decoding logic of multiplexer 30222 turns on the path connected to data input terminal 4 in its internal switch matrix. Based on the decoding result, multiplexer 30222 establishes gating connections between the multiple data input terminals, switching the corresponding analog or digital switches to the on state, thus turning on the delayed pulse signal path connected to data input terminal 4 and disconnecting the paths of all other data input terminals. Multiplexer 30222 transmits the gating and turned-on delayed pulse signal 708 from its input terminal to its output terminal. Since the switching of the internal switch of the multiplexer 30222 is completed after the gating control signal stabilizes, its output terminal follows the level change of the fourth delayed pulse signal 708 in real time after the switch is turned on, and sends out the signal completely as the target start pulse signal 712 from the output terminal of the selector 3022.

[0096] In one embodiment, the delay detector 30221 is used to concatenate the sampled values ​​of the first synchronization signal and a plurality of second synchronization signals following the first synchronization signal in the multi-channel synchronization signal 710 into an array, and when the first sampled value in the array is 0 and the other sampled values ​​are 1, the first synchronization signal is determined as the target synchronization signal.

[0097] For example, the delay detector 30221 simultaneously samples the input multi-channel synchronization signals chirp_START_SYN[0:N] to obtain the current level state of each channel. Since each signal has been latched by the synchronizer 3021, the sampled values ​​are stable, where a high level is represented by 1 and a low level by 0.

[0098] The delay detector 30221 samples the multiple level values ​​from channel 0 and arranges them sequentially according to their delay time. It then slides and splices the samples into groups of four adjacent channels to form multiple four-channel arrays. Specifically, the delay detector 30221 sequentially splices chirp_START_SYN[n], chirp_START_SYN[n+1], chirp_START_SYN[n+2], and chirp_START_SYN[n+3] into a four-digit array.

[0099] The delay detector 30221 performs pattern matching detection on each of the four arrays obtained by splicing to determine whether the value of the array is equal to

[0111] . The position of the

[0111] array marks the transition position from low to high in the synchronization signal sequence, indicating that the edge of the delayed pulse signal 708 corresponding to the first path in the group lags behind the edge of the reference clock signal 702, while the subsequent three paths have all crossed the edge of the reference clock signal 702.

[0100] When the delay detector 30221 detects that the value of a certain array is equal to

[0111] , it determines that the synchronization signal corresponding to the starting index n of the array is the target synchronization signal. At this time, the delay detector 30221 outputs the feedback detection value n to the control terminal of the multiplexer 30222 via a signal.

[0101] The delay detector 30221 uses array matching detection

[0111] to accurately locate the level transition position in the multi-channel synchronization signal sequence and accurately identify the candidate signal that is synchronized with the edge of the reference clock signal 702. The multiplexer 30222 selects and outputs the corresponding nth delayed pulse chirp_START_OUT[n] based on the detection value n, ensuring that the edge of the final output target start pulse signal 712 is strictly aligned with the edge of the reference clock signal 702, thus eliminating the random phase deviation between the original start pulse signal 706 and the reference clock signal 702 from the source.

[0102] The delay detector 30221 samples multiple synchronous signals simultaneously, avoiding detection errors caused by inconsistent arrival times of the signals. It employs a sliding splicing of four adjacent signals and performs array matching

[0111] , making a comprehensive judgment within four consecutive synchronous delay signals. Compared to methods relying on comparison of a single pair of adjacent synchronous delay signals, this four-channel mode detection effectively avoids misjudgments caused by edge jitter or noise in a single signal, significantly improving the robustness and anti-interference capability of the delay detector 30221.

[0103] After the delay detector 30221 completes its judgment, it outputs a feedback detection value n, which is a stable digital code. The multiplexer 30222, as a pure combinational logic selection circuit, directly selects the corresponding channel based on the value n. Its signal transmission delay from input to output is only the switch turn-on delay, without any serial judgment processing time, minimizing the delay of the critical output path. The target start pulse signal 712 can quickly respond to changes in the detection result, which is beneficial for achieving timing convergence at high operating frequencies.

[0104] In one embodiment, the multiple delayed pulse signals 708 are multiple equally spaced delayed pulse signals. The multiple delayed pulse signals 708 output by the delay chain 301 are multiple equally spaced delayed pulse signals. Specifically, the delay chain 301 is composed of multiple delay units connected in series, each delay unit having the same unit delay. After the start pulse signal 706 passes through each delay unit in sequence, the delayed pulse signal 708 output from the output of each delay unit has a delay time that increases by a fixed unit delay relative to the original start pulse signal 706. The time interval between two adjacent delayed pulse signals 708 is equal to each other, that is, the delayed pulse signals 708 are arranged at equal intervals on the time axis. For example, assume that the delay chain 301 is composed of N delay units connected in series, each delay unit providing the same unit delay ΔT. After the start pulse signal 706 is input to the delay chain 301, a first delayed pulse signal 708 is obtained from the output of the first delay unit, which is delayed by ΔT relative to the original start pulse; a second delayed pulse signal 708 is obtained from the output of the second delay unit, which is delayed by 2×ΔT; and so on, until the Nth delayed pulse signal 708 is obtained from the output of the Nth delay unit, which is delayed by N×ΔT. Thus, the first to the Nth delayed pulse signals 708 are arranged sequentially at equal intervals in time, with the time interval between any two adjacent signals being ΔT.

[0105] In one embodiment, the delay time range of the multiplexed delayed pulse signal 708 is greater than or equal to the period of the reference clock signal 702.

[0106] The delay chain 301 is composed of multiple cascaded delay units. The output of each delay unit outputs a delayed pulse signal 708, which together constitute multiple delayed pulse signals 708. Specifically, the delay time range of the multiple delayed pulse signals 708 refers to the difference between the total delay of the delayed pulse signal 708 output by the last delay unit in the delay chain 301 relative to the start pulse signal 706 and the delay of the delayed pulse signal 708 output by the first delay unit relative to the last delay unit. This difference is equal to the total time span covered by the delay chain from the first stage input to the last stage output, that is, the sum of the delays of all cascaded delay units.

[0107] Specifically, assuming that the delay chain 301 consists of N delay units connected in series, each delay unit providing the same unit delay ΔT, the first delayed pulse signal 708 is delayed by ΔT relative to the original start pulse signal 706, the second is delayed by 2×ΔT, and so on, with the Nth being delayed by N×ΔT. Therefore, the delay time range of the multiple delayed pulse signals 708 is (N-1)×ΔT (approximately N×ΔT when N is large). This embodiment requires that this delay time range be greater than or equal to one complete cycle T of the reference clock signal 702.

[0108] The position of the edge of the reference clock signal 702 on the time axis is periodic, but within each period, its arrival time relative to the start pulse signal 706 may be random. If the delay time range of the multiplexed delayed pulse signals 708 is less than one period of the reference clock signal 702, the reference clock edge may fall outside the coverage range of the delay chain, causing the synchronizer 3021 to fail to sample valid transition information, thus preventing synchronization. This embodiment ensures that, by setting the delay time range to cover at least one complete period, there is a corresponding delayed pulse available regardless of where the reference clock edge falls, fundamentally guaranteeing the reliability of the synchronization operation.

[0109] In one implementation, reference Figure 10 The radar system in this application embodiment also includes a synthesizer phase-locked loop 400; the synthesizer phase-locked loop 400 is connected to the reference clock generator 100 and the synthesizer phase-locked loop 400 is connected to the synchronization state machine 300.

[0110] The synthesizer phase-locked loop 400 is used to output a carrier signal based on the reference clock signal 702, the target start pulse signal 712, and the feedback clock signal 704 of the synthesizer phase-locked loop 400.

[0111] For example, the synthesizer phase-locked loop 400 receives a reference clock signal 702 from the reference clock generator 100 and a target start pulse signal 712 from the synchronization state machine 300. The synthesizer phase-locked loop 400 locks the reference clock signal 702 at the start of the data frame and maintains this lock throughout the data frame generation process. Triggered by the target start pulse signal 712, the synthesizer phase-locked loop 400 initiates frequency synthesis. In the locked state, the synthesizer phase-locked loop 400 compares the frequency and phase of the reference clock signal 702 with the feedback clock signal 704, adjusting the frequency of its output carrier signal according to the comparison result until the feedback clock signal 704 and the reference clock signal 702 are locked in both frequency and phase. Specifically, when the phase of the feedback clock signal 704 leads the reference clock signal 702, the synthesizer phase-locked loop 400 decreases the output frequency; when the phase of the feedback clock signal 704 lags the reference clock signal 702, the synthesizer phase-locked loop 400 increases the output frequency. Through this closed-loop adjustment, the frequency of the carrier signal output by the synthesizer phase-locked loop 400 maintains a fixed multiple relationship with the frequency of the reference clock signal 702, and the phase of the carrier signal has a definite synchronization relationship with the phase of the reference clock signal 702. The frequency of the feedback clock signal 704 generated by the synthesizer phase-locked loop 400 is equal to the frequency of the reference clock signal 702, and the phase delay between them remains constant. This process effectively solves the problem of random timing of chirped signals caused by cross-clock sampling.

[0112] Specifically, refer to Figure 11 The synthesizer phase-locked loop 400 includes a phase frequency detector 401, a charge pump 402, a low-pass filter 403, a voltage-controlled oscillator 404, a feedback frequency divider 405, and a delta-sigma modulator 406.

[0113] A phase frequency detector 401, a charge pump 402, a low-pass filter 403, and a voltage-controlled oscillator 404 are connected in sequence. The first input terminal of the phase frequency detector 401 is connected to the reference clock generator 100, and the second input terminal of the phase frequency detector 401 is connected to the feedback frequency divider 405. The voltage-controlled oscillator 404 is connected to the feedback frequency divider 405, the feedback frequency divider 405 is connected to the delta-sigma modulator 406, and the delta-sigma modulator 406 is connected to the synchronization state machine 300.

[0114] For example, triggered by the target start pulse signal 712, the delta-sigma modulator 406 starts working and outputs a division ratio control signal to the feedback divider 405. Based on this division ratio control signal, the feedback divider 405 divides the phase-locked loop output signal from the voltage-controlled oscillator 404 to generate a feedback clock signal 704. The frequency of this feedback clock signal 704 is equal to the frequency of the synthesizer phase-locked loop output signal divided by the division coefficient N. The feedback divider 405 sends the generated feedback clock signal 704 to both the second input terminal of the phase-frequency detector 401 and the delta-sigma modulator 406.

[0115] The phase frequency detector 401 receives a reference clock signal 702 from the reference clock generator 100 at its first input terminal and a feedback clock signal 704 from the feedback divider 405 at its second input terminal. The phase frequency detector 401 compares the phase and frequency of the reference clock signal 702 and the feedback clock signal 704, detecting the phase difference between them. When a phase difference is detected, the phase frequency detector 401 generates a corresponding error signal based on the comparison result. When the phase of the feedback clock signal 704 lags behind the reference clock signal 702, it outputs an error signal indicating a low frequency; when the phase of the feedback clock signal 704 leads the reference clock signal 702, it outputs an error signal indicating a high frequency. The error signal is sent to the charge pump 402. The charge pump 402 receives the error signal output by the phase frequency detector 401 and converts it into a current signal. Specifically, the charge pump 402 controls the opening direction of its internal current source according to the polarity of the error signal, outputting a positive or negative pulse current. The pulsed current is sent to the low-pass filter 403; the low-pass filter 403 receives the pulsed current signal output by the charge pump 402, performs low-pass filtering on it to remove high-frequency noise and spurious components, and smooths it into a stable DC control voltage, which is sent to the control terminal of the voltage-controlled oscillator 404; the voltage-controlled oscillator 404 adjusts the frequency of its output carrier signal according to the control voltage output by the low-pass filter 403, the output frequency increases when the control voltage increases, and decreases when the control voltage decreases; the phase-locked loop output signal output by the voltage-controlled oscillator 404 is used as the transmit carrier signal output of the radar system on the one hand, and is fed back to the input terminal of the feedback frequency divider 405 on the other hand, forming a closed-loop feedback path.

[0116] The triangular-sigma modulator 406 receives a feedback clock signal 704 from the feedback divider 405. Driven by this feedback clock signal 704, the triangular-sigma modulator 406 samples the target start pulse signal 712 output by the synchronization state machine 300. Based on the sampling result, the triangular-sigma modulator 406 controls the scanning of the feedback divider 405 by controlling the division coefficient N, thereby realizing frequency ramp modulation of the frequency-modulated continuous wave chirped signal. Specifically, the triangular-sigma modulator 406 dynamically switches between multiple integer division ratios, causing the average division ratio of the feedback divider 405 to change continuously with time according to a preset slope, causing the output frequency of the voltage-controlled oscillator 404 to change linearly with time, forming a rising ramp with a linearly increasing frequency or a falling ramp with a linearly decreasing frequency, i.e., a frequency-modulated continuous wave chirped signal. By changing the rate of change of the division ratio in the triangular-sigma modulator 406, the frequency ramp slope of the chirped signal can be adjusted, thereby realizing a frequency-modulated continuous wave chirped signal with adjustable slope.

[0117] When the synthesizer phase-locked loop 400 is locked, it ignores minute phase differences. The phase delay between the reference clock signal 702 and the feedback clock signal 704 is constant within the data frame, and their rising edges are aligned. The error signal output by the phase frequency detector 401 is zero. The control voltage output by the charge pump 402 and the low-pass filter 403 remains stable. The output frequency of the voltage-controlled oscillator 404 is stable in the locked state, and the frequency-modulated continuous wave chirp signal 12 is output according to the frequency division ratio change law set by the delta-sigma modulator 406. The rising edge of the feedback clock signal 704 can robustly sample the target start pulse signal 712 that is stable on the falling edge, avoiding the problem of chirp signal phase jitter.

[0118] In one implementation, reference Figure 12 The radar system of this application also includes a frequency multiplier unit 500; the frequency multiplier unit 500 is connected to the synthesizer phase-locked loop 400.

[0119] The frequency multiplier unit 500 is used to up-frequency the carrier signal and output a chirped signal.

[0120] Optionally, the frequency multiplier unit 500 can be composed of multiple cascaded frequency multipliers to achieve a higher frequency multiplication factor. For example, the frequency multiplier unit 500 may include a first second frequency multiplier circuit, a second second frequency multiplier circuit, a third second frequency multiplier circuit, and a fourth second frequency multiplier circuit cascaded in sequence. The first second frequency multiplier circuit receives a first frequency carrier signal output from the synthesizer phase-locked loop 400 and doubles it to generate a second frequency; the second second frequency multiplier circuit receives the second frequency and doubles it to generate a third frequency; the third second frequency multiplier circuit receives the third frequency and doubles it to generate a fourth frequency; the fourth second frequency multiplier circuit receives the fourth frequency and doubles it to generate a fifth frequency. Through the above cascaded structure, the frequency multiplier unit 500 can progressively boost the input frequency to the desired frequency band.

[0121] After receiving the carrier signal output from the synthesizer phase-locked loop 400, the frequency multiplier unit 500 performs frequency multiplication on the signal. Specifically, it boosts the frequency of the input signal to M times its original value. Optionally, M is an integer greater than 1, such as a second harmonic, a third harmonic, etc. The input carrier signal passes through each stage of the frequency multiplier sequentially, doubling its frequency with each stage, ultimately obtaining the desired frequency band signal. The bandpass filter in the frequency multiplier unit 500 filters the up-frequency carrier signal, suppressing unwanted harmonic components and outputting a chirped signal 12.

[0122] In one implementation, reference Figure 13 The radar system of this application includes a receiver 600; the receiver 600 is connected to a reference clock generator 100 and is used to receive the echo signal reflected by the target.

[0123] The chirped signal 12 emitted by the radar system is radiated outward through the transmitting antenna and generates a reflected echo upon encountering a target. This echo signal is received by the receiving antenna and input to the radio frequency input terminal of the receiver 600. Upon receiving the echo signal, the receiver 600 uses the reference clock signal 702 obtained from the reference clock generator 100 to perform down-mixing processing on the echo signal. Specifically, the receiver 600 generates a local oscillator signal based on the reference clock signal 702, mixes this local oscillator signal with the received echo signal, down-converting the echo signal from the high-frequency radio frequency band to the intermediate frequency or baseband band for subsequent analog-to-digital conversion and digital signal processing. Because the receiver 600 and the transmitting link share the same reference clock signal 702, the local oscillator signal generated by the receiver 600 maintains a defined phase relationship with the transmitted signal generated by the transmitting link, ensuring that the mixed intermediate frequency signal contains the phase difference information between the transmitted signal and the echo signal. After downmixing, the receiver 600 filters the output signal to remove unwanted spurious components and out-of-band interference, and extracts the beat frequency signal containing target distance and speed information.

[0124] In one implementation, reference Figure 14The radar system of this application includes a processor 700. The processor 700 is used to determine the range of a target based on the beat frequency of the beat frequency signal of the chirped signal and the echo signal.

[0125] Optionally, the processor 700 may consist of an analog-to-digital conversion module, a spectrum analysis module, a target detection module, a distance calculation module, and a control and configuration module. Each functional module may be implemented through software programs, hardware logic circuits, or a combination of both.

[0126] For example, the beat frequency signal output by receiver 600 is sent to processor 700. Upon receiving the beat frequency signal, processor 700 converts the analog beat frequency signal into a digital signal using an analog-to-digital converter module. A spectrum analysis module performs a spectrum transformation on the digitized beat frequency signal, converting the signal from the time domain to the frequency domain, and extracts the frequency components of the beat frequency signal from the spectrum to obtain the beat frequency value. Optionally, when there are multiple targets in the radar system, the beat frequency signal contains multiple frequency components, each corresponding to a target. The target detection module separates and identifies each frequency component through spectrum analysis, extracting the beat frequency corresponding to each target. The distance calculation module receives the beat frequency values ​​corresponding to each valid target output by the target detection module. Based on the proportional relationship between beat frequency and distance, the distance calculation module converts each beat frequency value into a corresponding target distance value. The control and configuration module outputs the target distance information as the detection result.

[0127] In one implementation, the processor 700 compares the phase difference of the beat frequency signal within multiple consecutive chirping cycles, and uses the phase regularity shift generated when the moving target reflects the signal to inversely deduce and calculate the relative motion speed of the target.

[0128] For example, after receiving the beat frequency signal output by the receiver 600, the processor 700 extracts the beat frequency corresponding to each target through spectrum analysis to determine the distance of each target. Based on the distance dimension, the processor 700 performs phase extraction on the beat frequency signal in the same distance unit within multiple consecutive chirped signal periods. Specifically, the processor 700 performs a Fast Fourier Transform on the beat frequency signal in each chirped signal period to locate the peak position corresponding to each target in the distance-dimensional spectrum. The processor 700 extracts and records the phase value of the same peak position in different chirped signal periods in the slow time dimension to obtain a phase change sequence over time. The phase difference between adjacent periods in this phase change sequence reflects the Doppler frequency shift caused by the target motion. The processor 700 converts the extracted phase difference value into the target velocity value according to the correspondence between the phase difference between adjacent periods and the target velocity. When there are multiple targets, the processor 700 performs the above phase extraction and velocity calculation process on the distance unit corresponding to each target to obtain the velocity information of each target. The processor 700 outputs the target velocity information and distance information together.

[0129] This application also provides an intelligent driving vehicle that includes the radar system of any of the foregoing embodiments.

[0130] This application also provides a computer-readable storage medium, which may include various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), and a random access memory (RAM). Specifically, the computer-readable storage medium stores program instructions, which are used to implement the actions of the above-described method implementation.

[0131] This application also provides a computer program product, which includes a computer program that, when executed by a processor, performs the actions of the above-described method implementation.

[0132] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0133] When an integrated unit / module is implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors. Unless otherwise specified, the processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.

[0134] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), and portable hard drives.

[0135] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0136] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM and RAM.

Claims

1. A radar system, characterized in that, include: A reference clock generator, a timing generator, and a synchronization state machine are provided; wherein the reference clock generator is connected to the timing generator and the synchronization state machine respectively, and the timing generator is connected to the synchronization state machine. The reference clock generator is used to generate a reference clock signal; The timing generator is used to generate a start pulse signal based on the reference clock signal; The synchronous state machine is used to perform multiple delays on the start pulse signal to obtain multiple delayed pulse signals, and based on the reference clock signal, outputs the target delayed pulse signal that is synchronized with the edge of the reference clock signal among the multiple delayed pulse signals as the target start pulse signal. The synchronization state machine includes a delay chain, a synchronizer, and a selector; the synchronizer is connected to the selector, the delay chain, and the reference clock generator respectively, and the selector is connected to the delay chain. The delay chain is used to delay the start pulse signal in multiple ways to obtain the multi-delayed pulse signal; The synchronizer is used to sample the inverse signal of the reference clock signal based on the multi-channel delayed pulse signal to obtain a multi-channel synchronization signal; The selector is used to detect the multiple synchronization signals to determine the target synchronization signal that is synchronized with the edge of the reference clock signal, and outputs the target delay pulse signal corresponding to the target synchronization signal as the target start pulse signal.

2. The radar system according to claim 1, characterized in that, The synchronizer includes an inverter and multiple flip-flops; The input terminal of the inverter is connected to the reference clock generator, and the output terminal of the inverter is connected to the data terminal of each of the flip-flops; the clock terminals of each of the flip-flops are respectively connected to the delay chain. The trigger is used to output the synchronization signal on the rising edge of the delayed pulse signal.

3. The radar system according to claim 1, characterized in that, The selector includes a delay detector and a multiplexer; the delay detector is connected to the multiplexer, the delay detector is connected to the synchronizer, and the multiplexer is connected to the delay chain; The delay detector is used to detect the multiple synchronization signals and determine the target synchronization signal that is synchronized with the edge of the reference clock signal; The multiplexer is used to output the target delay pulse signal corresponding to the target synchronization signal as the target start pulse signal.

4. The radar system according to claim 3, characterized in that, The delay detector is used to sample the multi-channel synchronization signals and determine the target synchronization signal based on the sampled values ​​of the multi-channel synchronization signals.

5. The radar system according to claim 4, characterized in that, The delay detector is used to concatenate the sample values ​​of the first synchronization signal and a plurality of second synchronization signals following the first synchronization signal into an array. When the first sample value in the array is 0 and the other sample values ​​are 1, the first synchronization signal is determined as the target synchronization signal.

6. The radar system according to any one of claims 1-5, characterized in that, The multi-channel delayed pulse signal is a multi-channel equally spaced delayed pulse signal.

7. The radar system according to any one of claims 1-5, characterized in that, The delay time range of the multi-channel delayed pulse signal is greater than or equal to the period of the reference clock signal.

8. The radar system according to any one of claims 1-5, characterized in that, Also includes: Synthesizer phase-locked loop; The synthesizer phase-locked loop is connected to the reference clock generator, and the synthesizer phase-locked loop is connected to the synchronization state machine; The synthesizer phase-locked loop is used to output a carrier signal based on the reference clock signal, the target start pulse signal, and the feedback clock signal of the synthesizer phase-locked loop.

9. The radar system according to claim 8, characterized in that, The synthesizer phase-locked loop includes: a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a feedback frequency divider, and a delta-sigma modulator; The phase frequency detector, the charge pump, the low-pass filter, and the voltage-controlled oscillator are connected in sequence. The phase frequency detector is connected to the reference clock generator, the phase frequency detector is connected to the feedback divider, the voltage-controlled oscillator is connected to the feedback divider, the feedback divider is connected to the delta-sigma modulator, and the delta-sigma modulator is connected to the synchronization state machine.

10. The radar system according to claim 8, characterized in that, Also includes: Frequency multiplier unit; the frequency multiplier unit is connected to the phase-locked loop of the synthesizer; The frequency multiplier unit is used to up-frequency the carrier signal and output a chirped signal.

11. The radar system according to claim 10, characterized in that, Also includes: A receiver; the receiver is connected to the reference clock generator and is used to receive the echo signal reflected by the target.

12. The radar system according to claim 11, characterized in that, Also includes: A processor configured to determine the distance to a target based on the beat frequency of the beat frequency signal of the chirped signal and the echo signal, and / or to determine the velocity of the target based on the phase difference of the beat frequency signal.

13. An intelligent driving vehicle, characterized in that, include: The radar system as described in any one of claims 1-12.

Images