Array substrate and display device

Abstract

An array substrate, comprising: a first electrode including a portion of a first conductive film; a first insulating film disposed on an upper layer side of the first conductive film; a second electrode including a portion of a second conductive film disposed on an upper layer side of the first insulating film, and a portion of which is disposed in overlap with the first electrode; a second insulating film disposed on an upper layer side of the second conductive film; a third electrode including a portion of a third conductive film disposed on an upper layer side of the second insulating film, and a portion of which is disposed in overlap with a portion of the second electrode which does not overlap with the first electrode; and a fourth electrode including a portion of the first conductive film, does not overlap with the first electrode, and is disposed in overlap with the portion of the second electrode which does not overlap with the first electrode, a first contact hole connecting the first electrode and the second electrode is provided in the first insulating film, and a second contact hole connecting the second electrode and the third electrode is provided in the second insulating film at a position which does not overlap with the first contact hole.

Description

Technical Field

[0001] The technology disclosed in this specification relates to array substrates and display devices that are less prone to poor connectivity. Background Technology

[0002] Conventionally, as an example of an array substrate included in a liquid crystal display device, the array substrate described in Patent Document 1 is known. The semiconductor device comprising the array substrate described in Patent Document 1 includes: a thin-film transistor; an interlayer insulating layer including a first insulating layer; a first transparent conductive layer formed on the interlayer insulating layer and having a first opening; a dielectric layer covering the side surface of the first transparent conductive layer at the first opening; and a second transparent conductive layer overlapping at least a portion of the first transparent conductive layer across the dielectric layer. The dielectric layer has a second opening, the first insulating layer has a third opening, the interlayer insulating layer and the dielectric layer have a first contact hole, the sidewall of the first contact hole includes the side surface of the second opening and the side surface of the third opening, at least a portion of the side surface of the third opening is aligned with the side surface of the second opening, the second transparent conductive layer contacts the drain electrode within the first contact hole and forms a contact portion, and when viewed from the normal direction of the substrate, at least a portion of the contact portion overlaps with the gate wiring layer. Existing technical documents Patent documents

[0003] Patent Document 1: International Publication No. 2013 / 073619 Summary of the Invention The problem the invention aims to solve

[0004] In the semiconductor device described in Patent Document 1, the first contact hole is connected to a total of three layers: two interlayer insulating layers and a dielectric layer. Therefore, the portion of the second transparent conductive layer disposed within the first contact hole is prone to film breakage. To prevent such film breakage, a structure could be considered such that an intermediate electrode is disposed using a metal layer or transparent electrode layer existing between the drain electrode and the second transparent conductive layer, and the drain electrode and the second transparent conductive layer are connected to the intermediate electrode. However, when the space for the intermediate electrode is limited, it is sometimes necessary to position the two openings respectively disposed in the first and second insulating layers in a position that overlaps with the opening in the dielectric layer. In this case, the opening of the dielectric layer needs to be disposed within the openings of the first and second insulating layers. Therefore, when disposing of the opening in the dielectric layer, it is difficult to form the opening properly; for example, the cross-sectional shape of the opening edge of the dielectric layer opening may become an inverted cone shape. This could potentially lead to poor connection between the intermediate electrode and the second transparent conductive layer.

[0005] The technology described in this manual is based on the above-mentioned conditions and is intended to minimize the occurrence of poor connections. Solution for solving the problem

[0006] (1) The array substrate described in this specification includes: a first electrode comprising a portion of a first conductive film; a first insulating film disposed on the upper side of the first conductive film; a second electrode comprising a portion of a second conductive film disposed on the upper side of the first insulating film, and a portion thereof overlapping the first electrode; a second insulating film disposed on the upper side of the second conductive film; and a third electrode comprising a portion of a third conductive film disposed on the upper side of the second insulating film, and a portion thereof overlapping the portion of the second electrode that does not overlap with the first electrode. The first electrode comprises a portion of the first conductive film, which does not overlap with the first electrode and overlaps with the portion of the second electrode that does not overlap with the first electrode. A first contact hole connecting the first electrode and the second electrode is provided at a position in the first insulating film that overlaps with both the first electrode and the second electrode. A second contact hole connecting the second electrode and the third electrode is provided at a position in the second insulating film that overlaps with both the second electrode and the third electrode and does not overlap with the first contact hole.

[0007] (2) Alternatively, the array substrate described above may be, based on (1) above, comprise: a semiconductor portion comprising a portion of a semiconductor film disposed on the lower side of the first conductive film and connected to the first electrode; and a cover portion comprising a portion of the second conductive film and covering the semiconductor portion, the second conductive film comprising a metallic material, the cover portion being disposed overlapping a portion of the fourth electrode, and a third contact hole connecting the cover portion and the fourth electrode being provided at a position in the first insulating film that overlaps with both the cover portion and the fourth electrode.

[0008] (3) Alternatively, the array substrate described above may be, based on (2) above, wherein the first electrode extends from a position overlapping a portion of the semiconductor portion along a first direction to a position at least overlapping a portion of the second electrode, the cover portion extends from a position overlapping the semiconductor portion along a second direction intersecting the first direction to a position overlapping a portion of the fourth electrode, the fourth electrode extends from a position overlapping a portion of the cover portion along the first direction to a position at least spaced apart from the first electrode in the second direction, and the second electrode has: a first extension portion extending from a position overlapping the first electrode away from the first electrode along the second direction; and a second extension portion extending from the first extension portion along the first direction to a position at least spaced apart from the cover portion in the second direction.

[0009] (4) Alternatively, the array substrate described above may be, based on any one of (1) to (3) above, comprising: a semiconductor portion comprising a portion of a semiconductor film disposed on the lower layer side of the first conductive film and connected to the first electrode; a third insulating film disposed on the lower layer side of the semiconductor film; a fifth electrode comprising a portion of a fourth conductive film disposed on the lower layer side of the third insulating film and disposed overlapping the semiconductor portion; and a sixth electrode comprising a portion of the fourth conductive film, the sixth electrode overlapping a portion of the first electrode and disposed overlapping with each of the second, third, and fourth electrodes, wherein a fourth contact hole is provided in the third insulating film at a position overlapping with both the first and sixth electrodes to connect the first electrode and the sixth electrode.

[0010] (5) The display device described in this specification includes: an array substrate as described in any one of (1) to (4) above; a counter substrate disposed opposite to the array substrate; and a display layer disposed between the array substrate and the counter substrate for displaying an image.

[0011] (6) Alternatively, the above-described display device may, based on (5) above, include: a 7th electrode disposed on the opposing substrate and opposite to the 3rd electrode; a 1st wiring disposed on the array substrate, including a portion of the 3rd conductive film and opposite to a portion of the 7th electrode; and a connecting portion disposed between the opposing substrate and the array substrate and connected to the 7th electrode and the 1st wiring.

[0012] (7) Alternatively, the above-mentioned display device may be, based on (6) above, wherein the third conductive film is configured as a transparent electrode film including a transparent electrode material.

[0013] (8) Alternatively, the above-mentioned display device may be, based on any one of (5) to (7) above, wherein the display layer is an electronic paper layer containing a plurality of microcapsules or microcuplets containing charged particles, and the second electrode and the third electrode are each arranged in a manner that overlaps with the plurality of microcapsules or microcuplets respectively. Invention Effects

[0014] According to the techniques described in this manual, poor connections are less likely to occur. Attached Figure Description

[0015] Figure 1 This is a top view of the electronic paper display according to Embodiment 1. Figure 2 This is a cross-sectional view showing the cross-sectional structure of the microcapsule layer constituting the electronic paper display according to Embodiment 1. Figure 3 This is a circuit diagram showing the electrical configuration of the array substrate constituting the electronic paper display according to Embodiment 1. Figure 4 This is a top view showing the pixel arrangement of the array substrate according to Embodiment 1. Figure 5 It is the array substrate involved in embodiment 1. Figure 4 The cross-sectional diagram of the vv line. Figure 6 It is the array substrate involved in embodiment 1. Figure 4 The cross-sectional view of the vi-vi line. Figure 7 It is the array substrate involved in embodiment 1. Figure 4 The cross-sectional view of line vii-vii. Figure 8 It is the array substrate involved in embodiment 1. Figure 4 The cross-sectional view of line viii-viii. Figure 9 This is a cross-sectional view of the end of the electronic paper display in the X-axis direction according to Embodiment 1. Explanation of reference numerals in the attached figures 10…Electronic paper display (display device), 20…Counter substrate, 20A…Counter electrode (7th electrode), 21…Array substrate, 22A…Gate electrode (5th electrode), 22C…Drain electrode (1st electrode), 22D…Semiconductor section, 23A…1st electrode section (6th electrode), 23B…2nd electrode section (2nd electrode), 23B1…1st extension, 23B2…2nd extension, 23C…3rd electrode section (3rd electrode), 28A…Capacitor electrode body (4th electrode), 28B…Cover section, 29B…2nd dry wiring configuration section (First wiring), 30… Gate insulating film (third insulating film), 31… First interlayer insulating film (first insulating film), 32… Planarization film (first insulating film), 33… Second interlayer insulating film (second insulating film), CHC1… First capacitor contact hole (third contact hole), CHP1… First pixel contact hole (first contact hole), CHP2… Second pixel contact hole (second contact hole), CHP3… Third pixel contact hole (fourth contact hole), EP… Conductive particles (connector), MC… Microcapsule, MCR… Microcapsule layer (display layer, electronic paper layer). Detailed Implementation

[0016] <Implementation Method 1> pass Figures 1 to 9 Embodiment 1 will be described below. In this embodiment, an electronic paper display (display device, EPD) 10 will be exemplified. Furthermore, the X-axis, Y-axis, and Z-axis are shown in a portion of each figure, depicted such that the directions of each axis correspond to the directions shown in each figure. Additionally, ... Figure 2 , Figures 5 to 9 The top side is the front side (positive side), and the bottom side of the diagram is the back side (negative side).

[0017] like Figure 1 As shown, the electronic paper display 10 has a horizontally elongated rectangular shape. In this embodiment, the electronic paper display 10 operates using a microcapsule-type electrophoresis method. The central portion of the main surface of the electronic paper display 10 is designated as the display area AA for displaying images. In contrast, the outer peripheral portion of the main surface of the electronic paper display 10, which surrounds the display area AA, is designated as the non-display area NAA, where no images are displayed.

[0018] like Figure 1 As shown, the electronic paper display 10 includes: an array substrate 21 serving as a backplane; and a counter substrate 20, which is attached to and opposite the array substrate 21. Both the counter substrate 20 and the array substrate 21 are, for example, substrates made of substantially transparent synthetic resin (resin substrates). Figure 2As shown, the microcapsule layer (display layer) MCR, containing microcapsules MC encapsulated with charged particles, is configured between the opposing substrate 20 and the array substrate 21. Furthermore, in Figure 2 The illustrations of the two substrates 20 and 21 are omitted. The microcapsule layer MCR has a pair of films F1 and F2 and a plurality of microcapsules MC sandwiched between the two films F1 and F2. The microcapsules MC contain at least: positively charged particles (e.g., titanium oxide particles) PP, which are white pigments and are positively charged; and negatively charged particles (e.g., carbon black particles) NP, which are black pigments and are negatively charged. In addition, a counter electrode (7th electrode) 20A is provided on the inner surface of the substrate 20 (the side opposite to the array substrate 21). The counter electrode 20A comprises a transparent electrode material and is formed in a full-surface manner in the inner surface of the substrate 20, extending at least over the entire area of ​​the display area AA. Although details are described later, the counter electrode 20A is arranged opposite to the plurality of pixel electrodes 23 provided on the array substrate 21 across the microcapsule layer MCR.

[0019] like Figure 1 As shown, the short side dimension of the relative substrate 20 is shorter than the short side dimension of the array substrate 21. The relative substrate 20 is attached to the array substrate 21 with one end aligned in the short side direction (Y-axis direction). Therefore, the other end in the short side direction of the array substrate 21 is provided as an exposed portion 21A that protrudes laterally relative to the relative substrate 20. The entire area of ​​this exposed portion 21A is a non-display area NAA, on which a driver (signal supply unit) 11 for supplying various signals and a flexible substrate 12 are mounted. A sealing portion S is provided around the entire circumference between the outer peripheral ends of the relative substrate 20 and the array substrate 21. The sealing portion S extends along the outer shape of the relative substrate 20 and the array substrate 21 and is square in shape when viewed from above. Figure 1 In the illustration, the formation range of the sealing part S is shown in shaded form.

[0020] like Figure 1 As shown, in the portion of the array substrate 21 covered by the opposing substrate 20, a frame-shaped capacitor trunk line (common trunk line) 29 is provided, which is one size larger than the display area AA and one size smaller than the opposing substrate 20. The capacitor trunk line 29 includes a first trunk line component 29A and a second trunk line component (first line) 29B disposed on the outer periphery of the first trunk line component 29A. The first trunk line component 29A and the second trunk line component 29B are interconnected. The first trunk line component 29A is connected to the capacitor control line 26 of the array substrate 21, which will be described later. The second trunk line component 29B is disposed overlapping with the sealing portion S, and although details will be described later, it is connected to the opposing electrode 20A of the opposing substrate 20.

[0021] The driver 11 includes an LSI chip with internal driving circuitry. The driver 11 processes various signals transmitted from the flexible substrate 12. The driver 11 is located on one side of the exposed portion 21A of the array substrate 21 relative to the display area AA in the Y-axis direction. Figure 1 The array substrate 11 is arranged adjacent to the display area AA on its lower side, and is sandwiched between the flexible substrate 12 and the display area AA in the Y-axis direction. The driver 11 has a horizontally elongated square shape. The driver 11 is capable of supplying various signals to the various wirings provided on the array substrate 21. The flexible substrate 12 is configured to have a plurality of wiring patterns formed on a substrate including an insulating and flexible synthetic resin material (e.g., polyimide resin). One end of the flexible substrate 12 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit board (control board, etc., not shown).

[0022] Next, use Figure 3 To illustrate the electrical configuration of the array substrate 21. For example... Figure 3 As shown, at least TFTs (thin-film transistors, switching elements) 22 and pixel electrodes 23 are disposed on the inner surface side of the display area AA of the array substrate 21. Multiple TFTs 22 and pixel electrodes 23 are arranged in a matrix (row-column) configuration with open intervals along the X-axis and Y-axis directions. Around these TFTs 22 and pixel electrodes 23, mutually orthogonal (crossing) gate wiring (scan wiring) 24, source wiring (image wiring, signal wiring) 25, capacitor control lines 26, and gate connection wiring 27 are arranged. The TFT 22 has: a gate electrode (fifth electrode) 22A connected to the gate wiring 24; a source electrode 22B connected to the source wiring 25; a drain electrode (first electrode) 22C connected to the pixel electrode 23; and a semiconductor portion 22D connected to the source electrode 22B and the drain electrode 22C. Furthermore, the TFT 22 is driven based on the scan signal supplied from the gate wiring 24 to the gate electrode 22A. Therefore, the potential related to the image signal supplied from the source wiring 25 to the source electrode 22B is supplied to the drain electrode 22C via the semiconductor section 22D. As a result, the pixel electrode 23 is charged to the potential related to the image signal. Furthermore, the scan signal contains a potential higher than the threshold voltage of the TFT 22. In addition, a capacitor electrode 28 is provided on the inner surface side of the display area AA of the array substrate 21 to form an electrostatic capacitance with the pixel electrode 23. In addition, the described capacitor dry wiring 29 is provided on the inner surface side of the non-display area NAA of the array substrate 21.

[0023] like Figure 3As shown, both the gate wiring 24 and the capacitor dominator line 26 extend along the X-axis direction (first direction). The gate wiring 24 and the capacitor dominator line 26 are arranged in a manner that alternates and repeats with open intervals in the Y-axis direction (a second direction intersecting the first direction). One TFT 22 and one pixel electrode 23 are sandwiched between adjacent gate wiring 24 and capacitor dominator line 26 with open intervals in the Y-axis direction. The number of gate wiring 24 and capacitor dominator line 26 is set to be roughly equal to the number of pixel electrodes 23 arranged in the Y-axis direction. The gate wiring 24 is connected to the gate electrode 22A of the TFT 22 in the display area AA. The gate wiring 24 is connected to the electrode 22A of the TFT 22 located on the upper side relative to the gate wiring 24. Figure 3 The pixel electrode 23 (on the upper side) is connected to the gate electrode 22A of the TFT 22, and to the lower side of the gate wiring 24. Figure 3 The gate electrode 22A of the TFT 22 is connected to the pixel electrode 23 (located on the lower side). In other words, a scan signal is supplied by a gate wiring 24 to the gate electrode 22A of each TFT 22 connected to the pixel electrode 23 that constitutes two adjacent rows in the Y-axis direction.

[0024] like Figure 3 As shown, the capacitor dominator line 26 is configured across the display area AA and the non-display area NAA, and is connected to the capacitor electrode 28 in the display area AA. The end of the capacitor dominator line 26 that extends to the non-display area NAA is connected to the portion of the first trunk wiring configuration 29A of the capacitor trunk wiring 29 that extends along the Y-axis. All the capacitor dominator lines 26 are connected in a spaced-apart manner in the Y-axis direction in the first trunk wiring configuration 29A. The capacitor dominator line 26 is supplied with a predetermined reference potential signal (common potential signal) from the first trunk wiring configuration 29A. Therefore, the capacitor electrode 28 is supplied with a reference potential signal from the first trunk wiring configuration 29A via the capacitor dominator line 26. In addition, the capacitor trunk wiring 29 is connected to the driver 11 or the flexible substrate 12, and is supplied with a reference potential signal from the driver 11 or an external circuit board. The capacitor electrode 28, which is supplied with a reference potential signal from the capacitor dominator line 26, can maintain the potential of the charged pixel electrode 23 by forming an electrostatic capacitance between itself and the pixel electrode 23. The two ends of the capacitor control line 26 in the X-axis direction are respectively connected to the first trunk wiring configuration section 29A.

[0025] like Figure 3As shown, both the source wiring 25 and the gate connection wiring 27 extend along the Y-axis direction. Two source wirings 25 are arranged between adjacent pixel electrodes 23 in the X-axis direction. Furthermore, the source wirings 25 are also positioned at intervals relative to the pixel electrodes 23 located at their X-axis ends in the display area AA towards the non-display area NAA. Therefore, the number of source wirings 25 is approximately twice the number of pixel electrodes 23 arranged in the X-axis direction. The source wirings 25 are arranged across the display area AA and the non-display area NAA, with the ends leading to the non-display area NAA connected to the driver 11. Image signals are supplied to the source wirings 25 from the driver 11.

[0026] like Figure 3 As shown, one gate connection wiring 27 is disposed between each of adjacent pixel electrodes 23 in the X-axis direction. The gate connection wiring 27 disposed between adjacent pixel electrodes 23 in the X-axis direction is sandwiched between two source wirings 25 disposed between adjacent pixel electrodes 23 in the X-axis direction. Furthermore, the gate connection wiring 27 is also disposed at a position that leaves a gap relative to the source wirings 25 located at their X-axis ends in the display area AA towards the non-display area NAA. The number of gate connection wirings 27 is the same as the number of pixel electrodes 23 arranged in the X-axis direction, and at least as many as the number of gate wirings 24. The gate connection wiring 27 is disposed across the display area AA and the non-display area NAA, and is connected to the gate wirings 24 in the display area AA. One or more gate connection wirings 27 are connected to each of the gate wirings 24 disposed in the display area AA. The ends of the gate connection wirings 27 that are led out to the non-display area NAA are connected to the driver 11. The gate connection wiring 27 is supplied with a scan signal from the driver 11. Therefore, the gate wiring 24 is supplied with a scan signal from the driver 11 via the gate connection wiring 27.

[0027] use Figure 4 To illustrate the detailed planar configuration of the array substrate 21. For example... Figure 4 As shown, the gate electrode 22A of the TFT 22 disposed in the display area AA of the array substrate 21 is provided in a form that extends along the Y-axis direction from a portion near the intersection of the gate wiring 24 and the source wiring 25. The source electrode 22B of the TFT 22 is provided in a form that extends along the X-axis direction from a portion near the intersection of the source wiring 25 and the gate wiring 24. The source electrode 22B is disposed at one end of the TFT 22 in the X-axis direction. The source electrode 22B overlaps a portion of the gate electrode 22A and is connected to the semiconductor portion 22D.

[0028] like Figure 4As shown, the drain electrode 22C of the TFT 22 is positioned at a distance in the X-axis direction from the source electrode 22B, that is, at the other end of the TFT 22 in the X-axis direction. The drain electrode 22C extends along the X-axis direction, with its end on the source electrode 22B side being configured to overlap with a portion of the gate electrode 22A and connected to the semiconductor portion 22D. The end of the drain electrode 22C opposite to the source electrode 22B side is connected to the pixel electrode 23. In other words, the drain electrode 22C extends along the X-axis from a position overlapping a portion of the semiconductor portion 22D to a position overlapping a portion of the pixel electrode 23 (second electrode portion 23B). The semiconductor portion 22D of the TFT 22 has a horizontally elongated shape extending along the X-axis direction. The semiconductor portion 22D is configured to overlap with the gate electrode 22A when viewed from above. One end portion of the semiconductor portion 22D in the X-axis direction is connected to the source electrode 22B, and the other end portion in the X-axis direction is connected to the drain electrode 22C. Furthermore, TFT22 includes a portion relative to gate wiring 24 in Figure 4 The upper adjacent TFT 22 and the gate wiring 24 are in Figure 4 The TFTs 22 adjacent to each other on the lower side, but these TFTs 22 are in Figure 4 The top and bottom, left and right sides are reversed respectively.

[0029] like Figure 4 As shown, the pixel electrode 23, disposed in the display area AA of the array substrate 21, is located in the region surrounded by the gate wiring 24, the capacitor dominance line 26, and two source wirings 25. The pixel electrode 23 is generally elongated square in shape. The pixel electrode 23 has excellent light reflectivity and is separated from the opposing substrate 20 (see reference 20) by the microcapsule layer MCR. Figure 1 The relative electrodes 20A of the electronic paper display 10 are arranged opposite each other. When the pixel electrode 23 is charged, each charged particle NP, PP moves within the microcapsule MC according to the polarity and potential of the pixel electrode 23. Light incident from the outside of the electronic paper display 10 onto the microcapsule layer MCR via the relative substrate 20 is transmitted or absorbed within the microcapsule MC by the charged particles NP, PP located on the relative substrate 20 side in the Z-axis direction. Thus, the amount of reflected light is controlled according to each pixel electrode 23, and a predetermined image is displayed in the display area AA. Furthermore, if a color filter is provided on the relative substrate 20, color image display is possible.

[0030] like Figure 4As shown, the capacitor electrode 28 extends along the Y-axis direction and, when viewed from above, overlaps with a plurality of pixel electrodes 23 arranged along the Y-axis direction. The capacitor electrode 28 extends across at least two pixel electrodes 23 in the Y-axis direction and overlaps with these two pixel electrodes 23. Specifically, the capacitor electrode 28 has: a capacitor electrode body (fourth electrode) 28A, which overlaps with two pixel electrodes 23 sandwiched between two adjacent gate lines 24 spaced apart in the Y-axis direction; and a cover portion 28B, which overlaps with a portion of the capacitor electrode body 28A and covers a portion of the TFT 22. The capacitor electrode body 28A extends along the Y-axis direction across two pixel electrodes 23 and traverses a capacitor dominance line 26 extending along the X-axis direction. Although details are described later, the portion of the capacitor electrode body 28A overlapping with the capacitor dominance line 26 is connected. A plurality of capacitor electrode bodies 28A are arranged at predetermined intervals in the Y-axis direction. The number of capacitor electrode bodies 28A is approximately half the number of pixel electrodes 23 arranged in the Y-axis direction.

[0031] like Figure 4 As shown, the cover portion 28B extends along the Y-axis from a position overlapping a portion of the capacitor electrode body 28A (the first capacitor contact hole CHC1 described later) toward the TFT 22 side, covering at least the semiconductor portion 22D in the TFT 22. Although details are described later, the portion of the cover portion 28B overlapping the capacitor electrode body 28A is connected. The cover portion 28B has light-blocking properties, preventing light from directly incident on the semiconductor portion 22D. As a result, the characteristics of the TFT 22 are less likely to deteriorate. Multiple capacitor electrodes 28 configured in this way are arranged at open intervals in the X-axis direction.

[0032] like Figure 4 As shown, the capacitor dominator line 26 extends approximately straight along the X-axis in the display area AA, traversing all the capacitor electrodes 28 arranged along the X-axis. The capacitor dominator line 26 is connected to all the capacitor electrodes 28 arranged along the X-axis. In the non-display area NAA, the capacitor dominator line 26 is connected to the portion of the first trunk wiring configuration 29A of the capacitor trunk wiring 29 extending along the Y-axis (see reference). Figure 3 ).

[0033] like Figure 4As shown, both the source wiring 25 and the gate connection wiring 27 extend approximately straight along the Y-axis in the display area AA, intersecting with all the gate wirings 24 and capacitor dominator lines 26 arranged along the Y-axis. The source wiring 25 is positioned at a predetermined interval relative to the pixel electrode 23 and capacitor electrode 28 in the X-axis direction. The gate connection wiring 27 is positioned at a distance from the source wiring 25 in the X-axis direction, opposite to the pixel electrode 23 and capacitor electrode 28. The gate connection wiring 27 has a larger linewidth than the source wiring 25.

[0034] Here, use Figure 5 This will illustrate the various films that are stacked on the inner surface of the array substrate 21. Figure 5 This is a cross-sectional view of the vicinity of TFT 22 on the array substrate 21. In the array substrate 21, as... Figure 5 As shown, starting from the lower layer side (resin substrate side), at least the following layers are stacked in sequence: a first metal film (fourth conductive film), a gate insulating film (third insulating film) 30, a semiconductor film, a second metal film (first conductive film), a first interlayer insulating film (first insulating film) 31, a planarization film (first insulating film) 32, a third metal film (second conductive film), a second interlayer insulating film (second insulating film) 33, and a transparent electrode film (third conductive film).

[0035] The first, second, and third metal films are respectively configured as single-layer films containing one metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or as laminated films or alloys containing different types of metal materials, thereby possessing conductivity and light-shielding properties. The first metal film constitutes a part of the pixel electrode 23, a part of the gate wiring 24, the gate electrode 22A of the TFT 22, a part of the gate connection wiring 27, a part of the capacitor dry wiring 29, etc. The second metal film constitutes a part of the gate wiring 24, the source wiring 25, the source electrode 22B and drain electrode 22C of the TFT 22, a part of the gate connection wiring 27, a part of the capacitor electrode 28, a part of the capacitor dry wiring 29, etc. The third metal film constitutes a part of the pixel electrode 23, the capacitor dominance line 26, a part of the capacitor electrode 28, etc.

[0036] The semiconductor film includes oxide semiconductor materials, such as the semiconductor section 22D constituting the TFT 22. The semiconductor film may contain at least one metal element selected from In, Ga, and Zn, for example, an In-Ga-Zn-O semiconductor (e.g., indium gallium zinc oxide). The In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, for example, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, etc. The In-Ga-Zn-O semiconductor used in the semiconductor film can be amorphous or crystalline. The semiconductor film may also contain other oxide semiconductors instead of the In-Ga-Zn-O semiconductor. For example, it may contain In-Sn-Zn-O semiconductors (e.g., In₂O₃-SnO₂-ZnO; InSnZnO). In-Sn-Zn-O semiconductors are ternary oxides of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may also include: In-W-Zn-O semiconductors containing W (tungsten), In-W-Sn-Zn-O semiconductors, In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, etc. Compared to polycrystalline silicon semiconductors, oxide semiconductor materials have higher resistivity in the off-state (no voltage applied). Furthermore, oxide semiconductor materials exhibit higher electron mobility compared to amorphous silicon semiconductors.

[0037] The gate insulating film 30, the first interlayer insulating film 31, and the second interlayer insulating film 33 each comprise silicon nitride (SiN). xThe gate insulating film 30 maintains the lower-side first metal film in an insulating state with the upper-side semiconductor film and second metal film. The first interlayer insulating film 31, together with the planarization film 32 (described later), maintains the lower-side semiconductor film and second metal film in an insulating state with the upper-side third metal film. The second interlayer insulating film 33 maintains the third metal film in an insulating state with the transparent electrode film. The planarization film 32 includes organic materials such as PMMA (acrylic resin). The planarization film 32, which includes organic materials, has a larger film thickness than any of the gate insulating film 30, the first interlayer insulating film 31, and the second interlayer insulating film 33, which include inorganic materials. Specifically, the film thickness of the gate insulating film 30, the first interlayer insulating film 31, and the second interlayer insulating film 33 is, for example, in the range of tens of nm to hundreds of nm, while the film thickness of the planarization film 32 is, for example, in the range of 1 μm to 3 μm. The planarization film 32, together with the first interlayer insulating film 31, keeps the lower semiconductor film and the second metal film in an insulating state with the upper third metal film.

[0038] Next, the cross-sectional structure of TFT22 will be explained. For example... Figure 5 As shown, the gate electrode 22A of the TFT 22 includes a portion of a first metal film. The semiconductor portion 22D of the TFT 22 includes a portion of a semiconductor film and is disposed on the upper layer side, overlapping the gate electrode 22A with respect to the gate insulating film 30. The source electrode 22B of the TFT 22 includes a portion of a second metal film and is directly connected from the upper layer side to one end portion of the semiconductor portion 22D in the X-axis direction. The drain electrode 22C of the TFT 22 includes a portion of a second metal film and is directly connected from the upper layer side to the other end portion of the semiconductor portion 22D in the X-axis direction.

[0039] The cross-sectional structure of the pixel electrode 23 will be explained. For example... Figure 5 As shown, the pixel electrode 23 has: a first electrode portion (sixth electrode) 23A, which includes a portion of a first metal film; a second electrode portion (second electrode) 23B, which includes a portion of a third metal film; and a third electrode portion (third electrode) 23C, which includes a portion of a transparent electrode film. The first electrode portion 23A, the second electrode portion 23B, and the third electrode portion 23C are configured to largely overlap each other.

[0040] like Figure 4 and Figure 5As shown, a portion of the second electrode portion 23B overlaps with approximately the entire region of the end of the drain electrode 22C opposite to the source electrode 22B side. A first pixel contact hole (first contact hole) CHP1 is provided at the position where it overlaps with both the second electrode portion 23B and the drain electrode 22C in the first interlayer insulating film 31 and planarization film 32 between the second electrode portion 23B and the drain electrode 22C. The second electrode portion 23B and the drain electrode 22C are connected through the first pixel contact hole CHP1. Furthermore, the detailed configuration of the second electrode portion 23B will be described again later.

[0041] like Figure 4 and Figure 5 As shown, the third electrode portion 23C is configured to overlap not only with the entire area of ​​the first electrode portion 23A, the second electrode portion 23B, and the TFT 22, but also with a portion of the two source wirings 25 sandwiching the pixel electrode 23, and not with the gate wiring 24, the capacitor dominator line 26, and the gate connection wiring 27. Specifically, the third electrode portion 23C is disposed in the Y-axis direction from the gate wiring 24 to the capacitor dominator line 26, and in the X-axis direction within the area sandwiched by the two gate connection wirings 27 adjacent to the two source wirings 25 sandwiching the pixel electrode 23. A second pixel contact hole (second contact hole) CHP2 is provided at the position where it overlaps with both the third electrode portion 23C and the second electrode portion 23B in the second interlayer insulating film 33 between the third electrode portion 23C and the second electrode portion 23B. The third electrode portion 23C and the second electrode portion 23B are connected through the second pixel contact hole CHP2. The third electrode portion 23C is located on the uppermost layer of the array substrate 21 and is configured to be closer to the opposing electrode 20A of the opposing substrate 20 than the first electrode portion 23A and the second electrode portion 23B. Therefore, when the pixel electrode 23 is charged, an electric field is generated between the opposing third electrode portion 23C and the opposing electrode 20A, and thus an image can be displayed through the microcapsule layer MCR using this electric field.

[0042] like Figure 4 and Figure 5As shown, a portion of the first electrode portion 23A overlaps with a portion of the end of the drain electrode 22C opposite to the source electrode 22B. Specifically, the first electrode portion 23A has a smaller forming range in the Y-axis direction compared to the second electrode portion 23B, and is configured not to overlap with the first pixel contact hole CHP1. A third pixel contact hole (fourth contact hole) CHP3 is provided at an opening in the gate insulating film 30 between the first electrode portion 23A and the drain electrode 22C, at a position where it overlaps both the first electrode portion 23A and the drain electrode 22C but does not overlap with the first pixel contact hole CHP1. The first electrode portion 23A and the drain electrode 22C are connected through the third pixel contact hole CHP3. The first pixel contact hole CHP1 and the third pixel contact hole CHP3 are arranged with a gap in the Y-axis direction. In detail, the third pixel contact hole CHP3 is configured at the drain electrode 22C to be farther from the semiconductor section 22D than the first pixel contact hole CHP1.

[0043] The cross-sectional configuration of capacitor electrode 28 will be explained. For example... Figure 4 and Figure 7 As shown, the capacitor electrode body 28A includes a portion of the second metal film. The capacitor electrode body 28A overlaps with the first electrode portion 23A across the gate insulating film 30, and overlaps with the second electrode portion 23B across the first interlayer insulating film 31 and the planarization film 32. That is, the capacitor electrode body 28A is configured to be sandwiched between the first electrode portion 23A and the second electrode portion 23B in the Z-axis direction. Since electrostatic capacitances are formed between the capacitor electrode body 28A and the first electrode portion 23A, and between the capacitor electrode body 28A and the second electrode portion 23B, the potentials of the pixel electrodes 23 (first electrode portion 23A, second electrode portion 23B, and third electrode portion 23C) after charging can be well maintained. Figures 4 to 6 As shown, the cover portion 28B constituting the capacitor electrode 28 includes a portion of the third metal film. The cover portion 28B is disposed overlapping the source electrode 22B, the drain electrode 22C, and the semiconductor portion 22D, separated by the first interlayer insulating film 31 and the planarization film 32. The cover portion 28B can effectively block light attempting to enter the semiconductor portion 22D (especially the portion constituting the channel region). At the position where the first interlayer insulating film 31 and the planarization film 32 overlap both the capacitor electrode body 28A and the cover portion 28B, a first capacitor contact hole (third contact hole) CHC1 is provided. The capacitor electrode body 28A and the cover portion 28B are connected through the first capacitor contact hole CHC1.

[0044] like Figure 4 and Figure 7As shown, the capacitor dominance line 26 includes a portion of the third metal film. In the display area AA, the capacitor dominance line 26 extends along the X-axis, traversing the source wiring 25, the gate connection wiring 27, and the capacitor electrode body 28A. Specifically, the capacitor dominance line 26 intersects the source wiring 25, the gate connection wiring 27, and the capacitor electrode body 28A across the first interlayer insulating film 31 and the planarization film 32, and intersects the gate connection wiring 27 across the gate insulating film 30. A second capacitor contact hole CHC2 is provided at an opening in the first interlayer insulating film 31 and the planarization film 32 between the capacitor dominance line 26 and the capacitor electrode body 28A, where it overlaps with both the capacitor dominance line 26 and the capacitor electrode body 28A. The capacitor dominance line 26 is connected to the capacitor electrode body 28A through the second capacitor contact hole CHC2. Multiple second capacitor contact holes CHC2 are arranged at intervals along the X-axis.

[0045] like Figure 4 and Figure 8 As shown, the gate connection wiring 27 extends along approximately the entire length of the display area AA in the X-axis direction, intersecting the source wiring 25 and the gate connection wiring 27 respectively, separated by the gate insulating film 30. Gate contact holes CHG are provided at the locations in the gate insulating film 30 where they overlap with both the gate connection wiring 27 and the gate wiring 24, which are interconnected. The gate connection wiring 27 is connected to the gate wiring 24, which is the interconnected part, through the gate contact holes CHG. No gate contact holes CHG are provided at the locations in the gate insulating film 30 where they overlap with both the gate connection wiring 27 and the gate wiring 24, which are not interconnected parts.

[0046] In addition, such as Figure 9 As shown, the sealing portion S includes: a sealing substrate SB, which includes a photocurable resin material or a thermocurable resin material; and a plurality of conductive particles (connecting portions) EP, which are dispersed and mixed within the sealing substrate SB. The conductive particles EP are formed, for example, by performing a conductive plating treatment such as gold plating on the surface of particles made of synthetic resin. The particle size of the conductive particles EP is set to a value approximately equal to the spacing between the opposing substrate 20 and the array substrate 21 (the thickness of the microcapsule layer MCR). The second dry wiring configuration 29B of the capacitor dry wiring 29 provided on the array substrate 21 is electrically connected to the opposing electrode 20A provided on the opposing substrate 20 via the conductive particles EP. The reference potential signal transmitted by the capacitor dry wiring 29 is supplied from the second dry wiring configuration 29B to the opposing electrode 20A via the conductive particles EP.

[0047] So, if Figure 5As shown, a portion of the third electrode portion 23C, which includes a portion of the transparent electrode film of the array substrate 21 according to this embodiment, is configured to overlap with a portion of the second electrode portion 23B, which includes a portion of the third metal film, that does not overlap with the drain electrode 22C. That is, the third electrode portion 23C includes at least a portion that overlaps with the drain electrode 22C and a portion that does not overlap with the drain electrode 22C but overlaps with the second electrode portion 23B. Furthermore, the third electrode portion 23C also includes portions that do not overlap with either the drain electrode 22C or the second electrode portion 23B. In contrast, the capacitor electrode body 28A, which includes a portion of the second metal film, does not overlap with the drain electrode 22C, which includes a portion of the second metal film, and overlaps with a portion of the second electrode portion 23B, which includes a portion of the third metal film, that does not overlap with the drain electrode 22C. That is, the capacitor electrode body 28A includes at least a portion that does not overlap with the drain electrode 22C but overlaps with the second electrode portion 23B.

[0048] Based on this structure, such as Figure 5 As shown, the second electrode portion 23B has a first overlapping portion 23B3 that does not overlap with the drain electrode 22C, overlaps with the third electrode portion 23C, and overlaps with the capacitor electrode body 28A. In other words, the second electrode portion 23B is positioned within a range that overlaps with both the third electrode portion 23C and the capacitor electrode body 28A. By positioning the second electrode portion 23B within such a range, the degree of freedom related to the arrangement or number of locations connected to the drain electrode 22C via the first pixel contact hole CHP1 and to the third electrode portion 23C via the second pixel contact hole CHP2 can be increased. Therefore, the first pixel contact hole CHP1 and the second pixel contact hole CHP2 can be configured to not overlap, making it easier to achieve an appropriate cross-sectional shape for the opening edge of the second pixel contact hole CHP2 in the second interlayer insulating film 33. As a result, poor connection is less likely to occur between the interconnected second electrode portion 23B and the third electrode portion 23C, thus maintaining the display quality of the electronic paper display 10 effectively.

[0049] In this embodiment, such as Figure 4 and Figure 6As shown, the cover portion 28B covering the semiconductor portion 22D is connected to the capacitor electrode body 28A through the first capacitor contact hole CHC1 of the first interlayer insulating film 31 and the planarization film 32. When such a cover portion 28B is provided, although it is difficult to arrange the first pixel contact hole CHP1 or the second pixel contact hole CHP2 at a position overlapping with the semiconductor portion 22D, by setting the second electrode portion 23B in the range overlapping with both the third electrode portion 23C and the capacitor electrode body 28A as described above, the degree of freedom related to the arrangement or number of the first pixel contact hole CHP1 and the second pixel contact hole CHP2 is increased. Therefore, even if the cover portion 28B is provided, the arrangement or number of the first pixel contact hole CHP1 and the second pixel contact hole CHP2 is not easily limited.

[0050] like Figure 4 As shown, the capacitor electrode body 28A extends from a position overlapping a portion of the cover portion 28B (the first capacitor contact hole CHC1) along the X-axis direction to a position at least a distance away from the drain electrode 22C in the Y-axis direction. This avoids short circuits with the drain electrode 22C while ensuring sufficient coverage of the capacitor electrode body 28A. Furthermore, the second electrode portion 23B has: a first extension portion 23B1 extending from the position overlapping the drain electrode 22C (the first pixel contact hole CHP1) along the Y-axis direction away from the drain electrode 22C; and a second extension portion 23B2 extending from the first extension portion 23B1 along the X-axis direction to a position at least a distance away from the cover portion 28B in the Y-axis direction. This avoids short circuits with the cover portion 28B while ensuring sufficient coverage of the second electrode portion 23B. By defining the overlapping second electrode portion 23B and capacitor electrode body 28A within such a forming range, the degree of freedom in the arrangement or number of first pixel contact holes CHP1 and second pixel contact holes CHP2 can be further increased. Furthermore, the first extension portion 23B1 overlaps with a portion of the capacitor electrode body 28A. That is, the first overlapping portion 23B3 in the second electrode portion 23B, which overlaps with both the third electrode portion 23C and the capacitor electrode body 28A, exists in a portion of the first extension portion 23B1 (the portion overlapping with the capacitor electrode body 28A) and approximately the entire area of ​​the second extension portion 23B2. By having the first overlapping portion 23B3 within such a range, the degree of freedom in the arrangement or number of first pixel contact holes CHP1 and second pixel contact holes CHP2 can be further increased.

[0051] Furthermore, in this embodiment, the transparent electrode film located at the top layer of the array substrate 21 constitutes the third electrode portion 23C of the pixel electrode 23 and the second dry wiring portion 29B of the capacitor dry wiring 29. The second dry wiring portion 29B supplies a reference potential signal to the opposing electrode 20A via the conductive particles EP of the sealing portion S. Compared to the case where the second dry wiring portion 29B includes a portion of the metal film, it is less susceptible to corrosion even if the second dry wiring portion 29B is exposed in the top layer of the array substrate 21. The third electrode portion 23C generates an electric field with the opposing electrode 20A, and the spacing (distance) between the third electrode portion 23C and the opposing electrode 20A is narrower than that of the second electrode portion 23B, which includes a portion of the third metal film. Therefore, compared to the case where the third electrode portion 23C is omitted, the electric field strength involved in the electric field generated between the pixel electrode 23 and the opposing electrode 20A can be further improved, thus achieving excellent display quality.

[0052] As described above, the array substrate 21 of this embodiment includes: a drain electrode (first electrode) 22C, which includes a portion of a second metal film (first conductive film); a first interlayer insulating film 31 and a planarization film 32, which serve as a first insulating film and are disposed on the upper side of the second metal film; a second electrode portion (second electrode) 23B, which includes a portion of a third metal film (second conductive film) disposed on the upper side of the planarization film 32, which serves as the first insulating film, and a portion thereof overlaps with the drain electrode 22C; a second interlayer insulating film (second insulating film) 33, which is disposed on the upper side of the third metal film; and a third electrode portion (third electrode) 23C, which includes a portion of a transparent electrode film (third conductive film) disposed on the upper side of the second interlayer insulating film 33, and a portion thereof overlaps with the drain electrode 22C in the second electrode portion 23B. The 2C electrode is partially overlapped; and the capacitor electrode body (fourth electrode) 28A includes a portion of the second metal film, which does not overlap with the drain electrode 22C and is partially overlapped with the drain electrode 22C in the second electrode portion 23B. A first pixel contact hole (first contact hole) CHP1 is provided at a position in the first interlayer insulating film 31 and planarization film 32, which are the first insulating film, where it overlaps with both the drain electrode 22C and the second electrode portion 23B. A second pixel contact hole (second contact hole) CHP2 is provided at a position in the second interlayer insulating film 33, where it overlaps with both the second electrode portion 23B and the third electrode portion 23C and does not overlap with the first pixel contact hole CHP1.

[0053] The second electrode portion 23B is connected to the drain electrode 22C through a first pixel contact hole CHP1, which serves as the first insulating film, the first interlayer insulating film 31, and the planarization film 32, and is connected to the third electrode portion 23C through a second pixel contact hole CHP2, which serves as the second interlayer insulating film 33. An electrostatic capacitance is formed between the second electrode portion 23B, which overlaps with the capacitor electrode body 28A across the first interlayer insulating film 31 and the planarization film 32. The second electrode portion 23B has a portion that does not overlap with the drain electrode 22C but overlaps with the third electrode portion 23C; this portion is configured to overlap with the capacitor electrode body 28A. In other words, the second electrode portion 23B is provided in the overlapping range relative to both the third electrode portion 23C and the capacitor electrode body 28A, thus increasing the degree of freedom related to the arrangement or number of portions connected to the drain electrode 22C through the first pixel contact hole CHP1 and to the third electrode portion 23C through the second pixel contact hole CHP2. Therefore, the first pixel contact hole CHP1 and the second pixel contact hole CHP2 can be configured to not overlap each other. As a result, the cross-sectional shape of the opening edge of the second pixel contact hole CHP2 in the second interlayer insulating film 33 is easy to become an appropriate shape. Consequently, poor connection is less likely to occur in the interconnected second electrode portion 23B and third electrode portion 23C.

[0054] Additionally, the device includes: a semiconductor section 22D, which includes a portion of a semiconductor film disposed on the lower side of the second metal film and connected to the drain electrode 22C; and a cover section 28B, which includes a portion of a third metal film and covers the semiconductor section 22D. The third metal film comprises a metallic material. The cover section 28B is disposed overlapping a portion of the capacitor electrode body 28A. A first capacitor contact hole (third contact hole) CHC1 is provided at a position in the first interlayer insulating film 31 and the planarization film 32, which serve as the first insulating film, where it overlaps with both the cover section 28B and the capacitor electrode body 28A. By covering the semiconductor section 22D with the cover section 28B formed from a portion of the third metal film comprising a metallic material, light reaching the semiconductor section 22D can be blocked by the cover section 28B. Therefore, the characteristics of the semiconductor section 22D are less likely to change due to light irradiation. When such a cover portion 28B is provided, although it is difficult to arrange the first pixel contact hole CHP1 or the second pixel contact hole CHP2 at the position overlapping with the semiconductor portion 22D, by arranging the second electrode portion 23B in the range overlapping with both the third electrode portion 23C and the capacitor electrode body 28A as described above, the degree of freedom related to the arrangement or number of the first pixel contact hole CHP1 and the second pixel contact hole CHP2 is increased. Therefore, even with the cover portion 28B provided, the arrangement or number of the first pixel contact hole CHP1 and the second pixel contact hole CHP2 is not easily limited.

[0055] Additionally, the drain electrode 22C extends from a position overlapping a portion of the semiconductor portion 22D along a first direction to a position at least overlapping a portion of the second electrode portion 23B, the cover portion 28B extends from a position overlapping the semiconductor portion 22D along a second direction intersecting the first direction to a position overlapping a portion of the capacitor electrode body 28A, the capacitor electrode body 28A extends from a position overlapping a portion of the cover portion 28B along a first direction to a position at least spaced apart from the drain electrode 22C in the second direction, and the second electrode portion 23B has: a first extension portion 23B1 that extends from the position overlapping the drain electrode 22C away from the drain electrode 22C along a second direction; and a second extension portion 23B2 that extends from the first extension portion 23B1 along a first direction to a position at least spaced apart from the cover portion 28B in the second direction. Since the capacitor electrode body 28A extends along the first direction from a position overlapping a portion of the cover portion 28B of the connected object to a position at least a distance away from the drain electrode 22C in the second direction, short circuits with the drain electrode 22C can be avoided while ensuring sufficient formation range of the capacitor electrode body 28A. The second electrode portion 23B has: a first extension portion 23B1 that extends along the second direction from a position overlapping with the drain electrode 22C away from the drain electrode 22C; and a second extension portion 23B2 that extends along the first direction from the first extension portion 23B1 to a position at least a distance away from the cover portion 28B in the second direction. Therefore, short circuits with the cover portion 28B can be avoided while ensuring sufficient formation range of the second electrode portion 23B. By setting the overlapping second electrode portion 23B and capacitor electrode body 28A to such formation ranges, the freedom of arrangement or number of first pixel contact holes CHP1 and second pixel contact holes CHP2 can be further increased.

[0056] Additionally, the device includes: a semiconductor portion 22D, which includes a portion of a semiconductor film disposed on the lower side of the second metal film and connected to the drain electrode 22C; a gate insulating film (third insulating film) 30, which is disposed on the lower side of the semiconductor film; a gate electrode (fifth electrode) 22A, which includes a portion of a first metal film (fourth conductive film) disposed on the lower side of the gate insulating film 30 and overlaps with the semiconductor portion 22D; and a first electrode portion (sixth electrode) 23A, which includes a portion of the first metal film. The first electrode portion 23A overlaps with a portion of the drain electrode 22C and is disposed overlapping with each of the second electrode portion 23B, the third electrode portion 23C, and the capacitor electrode body 28A. A third pixel contact hole (fourth contact hole) CHP3 is provided in the gate insulating film 30 at a position overlapping with both the drain electrode 22C and the first electrode portion 23A, connecting the drain electrode 22C and the first electrode portion 23A. When a signal is supplied to the gate electrode 22A, a channel region is generated in the semiconductor section 22D, and the signal is supplied to the drain electrode 22C. The second electrode section 23B and the first electrode section 23A, connected to the drain electrode 22C, are both charged to a potential based on the signal supplied to the drain electrode 22C. In addition to forming an electrostatic capacitance between the second electrode section 23B, which overlaps with the first interlayer insulating film 31 and the planarization film 32 (which serve as the first insulating film), and the capacitor electrode body 28A, which overlaps with the gate insulating film 30, an electrostatic capacitance is also formed between the capacitor electrode body 28A and the first electrode section 23A. This effectively maintains the potential of the second electrode section 23B and the first electrode section 23A.

[0057] The electronic paper display (display device) 10 of this embodiment includes: an array substrate 21 as described above; a counter substrate 20 disposed opposite to the array substrate 21; and a microcapsule layer (display layer) MCR disposed between the array substrate 21 and the counter substrate 20 for displaying images. With such an electronic paper display 10, since poor connection is less likely to occur between the interconnected second electrode portion 23B and the third electrode portion 23C, display quality is well maintained.

[0058] Additionally, the device includes: a counter electrode (7th electrode) 20A disposed on a counter substrate 20, opposite to the 3rd electrode portion 23C; a second dry wiring configuration portion (1st wiring) 29B disposed on an array substrate 21, including a portion of a transparent electrode film, opposite to a portion of the counter electrode 20A; and conductive particles (connecting portions) EP, which are disposed between the counter substrate 20 and the array substrate 21 and connected to the counter electrode 20A and the second dry wiring configuration portion 29B. Signals transmitted by the second dry wiring configuration portion 29B are supplied to the counter electrode 20A via the conductive particles EP. An image can be displayed using the electric field generated between the opposing 3rd electrode portion 23C and the counter electrode 20A via a microcapsule layer MCR. Since the 3rd electrode portion 23C is formed from a portion of the transparent electrode film constituting the counter electrode 20A, the gap between the 3rd electrode portion 23C and the counter electrode 20A can be minimized. Therefore, the electric field strength involved in the electric field generated between the third electrode section 23C and the opposite electrode 20A can be made to be a sufficiently high electric field strength, thus achieving excellent display quality.

[0059] Furthermore, the third conductive film is configured as a transparent electrode film comprising a transparent electrode material. Compared to the case where a metallic material is assumed to be used as the material of the third conductive film, corrosion is less likely to occur in the second dry wiring configuration 29B even when the second dry wiring configuration 29B is exposed on the surface of the array substrate 21.

[0060] Furthermore, the display layer is a microcapsule layer (electronic paper layer) MCR containing multiple microcapsules (MCs) or microcups containing charged particles. Multiple second electrode portions 23B and third electrode portions 23C are each arranged in a manner that overlaps with the multiple microcapsules (MCs) or microcups. The charged particles contained in the multiple microcapsules (MCs) or microcups can be circulated by voltages applied to the multiple second electrode portions 23B and the multiple third electrode portions 23C. Therefore, a predetermined image can be displayed on the microcapsule layer MCR.

[0061] <Other Implementation Methods> The technology disclosed in this specification is not limited to the embodiments described above and the accompanying drawings. For example, the following embodiments are also included in the scope of the technology.

[0062] (1) A metal film can also be used instead of the transparent electrode film located on the top layer in the array substrate 21.

[0063] (2) The gate wiring 24 can also be arranged in each row of pixel electrodes 23, including a plurality of pixel electrodes 23 arranged along the X-axis direction. In this case, the number of gate wirings 24 is the same as the number of rows of pixel electrodes 23. Similarly, the source wirings 25 can be arranged in each column of pixel electrodes 23, including a plurality of pixel electrodes 23 arranged along the Y-axis direction, so that the number of source wirings 25 is the same as the number of columns of pixel electrodes 23. Furthermore, the capacitor dominator lines 26 are arranged overlapping the specified gate wirings 24. Additionally, the number of gate connection wirings 27 can also be varied depending on the number of gate wirings 24.

[0064] (3) Alternatively, an inspection wiring for checking whether the gate wiring 24 has broken wires can be provided on the array substrate 21. The inspection wiring is located in the non-display area NAA and is connected to the end of the gate wiring 24.

[0065] (4) Alternatively, a source driver that supplies image signals to the source wiring 25 and a gate driver that supplies scan signals to the gate connection wiring 27 may be provided on the array substrate 21 respectively.

[0066] (5) Alternatively, the gate connection wiring 27, which is arranged in the form of traversing the display area AA, can be omitted, and a gate drive circuit connected to the end of the gate wiring 24 can be arranged in the non-display area NAA. The gate drive circuit directly supplies scan signals to the gate wiring 24. In addition, a gate driver can also be used in addition to the gate drive circuit.

[0067] (6) The material of the semiconductor film constituting the semiconductor part 22D may also be polycrystalline silicon (LTPS) or amorphous silicon, etc.

[0068] (7) In the relative substrate 20 and the array substrate 21, a glass substrate can also be used instead of a resin substrate.

[0069] (8) The driver 11 can also be mounted on the flexible substrate 12 in a COF (Chip On Film) manner.

[0070] (9) The planar shape of the electronic paper display 10 can also be a long rectangle, square, circle, semicircle, long oval, ellipse, trapezoid, etc.

[0071] (10) The operation mode of the electronic paper display 10 can also be a microcup type electrophoresis method. The electronic paper display 10 with microcup type electrophoresis method has an electronic paper layer configured as follows. That is, the electronic paper layer has: a substrate having microcup; a sealing part that is assembled to the substrate in a manner that closes the microcup; and a counter electrode that is stacked on the surface of the substrate. The substrate has microcup including a transparent synthetic resin material and the like, which opens toward the inward side. In detail, the substrate has a grid-like partition when viewed from above, and the spaces separated by the partition constitute microcup. A plurality of microcup are arranged in a matrix-like planar arrangement in the main surface of the substrate. The plurality of microcup are stacked relative to the pixel electrodes 23 provided on the array substrate 21. The microcup contains positively charged particles and negatively charged particles, as well as an insulating fluid including silicone oil. In the electronic paper display 10 with such a configuration, the same function and effect as in Embodiment 1 described above can also be obtained.

[0072] (11) In addition to (10) above, the operating mode of the electronic paper display 10 can also be appropriately changed to electronic powder fluid mode, electrowetting mode, cholesteric liquid crystal mode, etc.

[0073] (12) It may also be a display device other than electronic paper display 10 (e.g., liquid crystal panel or organic EL display panel, etc.).

Claims

1. An array substrate, characterized in that, have: The first electrode includes a portion of the first conductive film; A first insulating film is disposed on the upper side of the first conductive film; The second electrode includes a portion of a second conductive film disposed on the upper side of the first insulating film, and a portion thereof overlaps with the first electrode. A second insulating film is disposed on the upper side of the second conductive film; The third electrode includes a portion of a third conductive film disposed on the upper side of the second insulating film, and a portion thereof overlaps with a portion of the second electrode that does not overlap with the first electrode. as well as The fourth electrode includes a portion of the first conductive film, does not overlap with the first electrode, and is configured to overlap with the portion of the second electrode that does not overlap with the first electrode. A first contact hole is provided in the first insulating film at a position overlapping both the first electrode and the second electrode, connecting the first electrode and the second electrode. A second contact hole is provided in the second insulating film at a position that overlaps with both the second electrode and the third electrode but does not overlap with the first contact hole, connecting the second electrode and the third electrode.

2. The array substrate according to claim 1, wherein, It includes: a semiconductor section comprising a portion of a semiconductor film disposed on the lower layer side of the first conductive film and connected to the first electrode; as well as The covering portion, which includes a portion of the second conductive film, covers the semiconductor portion. The second conductive film comprises a metallic material. The covering portion is configured to overlap with a portion of the fourth electrode. A third contact hole is provided in the first insulating film at a position overlapping both the cover portion and the fourth electrode, connecting the cover portion and the fourth electrode.

3. The array substrate according to claim 2, wherein, The first electrode extends along a first direction from a position overlapping a portion of the semiconductor portion to a position at least overlapping a portion of the second electrode. The covering portion extends from a position overlapping the semiconductor portion along a second direction intersecting the first direction to a position overlapping a portion of the fourth electrode. The fourth electrode extends along the first direction from a position overlapping a portion of the cover portion to a position at least spaced apart from the first electrode in the second direction. The second electrode has: a first extension that extends along the second direction from a position overlapping with the first electrode in a manner away from the first electrode; And a second extension that extends from the first extension along the first direction to a position at least spaced apart from the cover in the second direction.

4. The array substrate according to any one of claims 1 to 3, wherein, It includes: a semiconductor section comprising a portion of a semiconductor film disposed on the lower layer side of the first conductive film and connected to the first electrode; A third insulating film is disposed on the lower side of the semiconductor film; The fifth electrode includes a portion of the fourth conductive film disposed on the lower side of the third insulating film, and is disposed overlapping the semiconductor portion; as well as The sixth electrode includes a portion of the fourth conductive film. The sixth electrode overlaps a portion of the first electrode and is configured to overlap with each of the second, third, and fourth electrodes. A fourth contact hole is provided in the third insulating film at a position overlapping both the first electrode and the sixth electrode to connect the first electrode and the sixth electrode.

5. A display device, characterized in that, have: The array substrate according to any one of claims 1 to 3; The substrate is positioned opposite to the array substrate; and A display layer, which is configured to be sandwiched between the array substrate and the opposing substrate, is used to display images.

6. The display device according to claim 5, wherein, It includes: a 7th electrode disposed on the opposing substrate, opposite to the 3rd electrode; The first wiring is disposed on the array substrate and includes a portion of the third conductive film, which is opposite to a portion of the seventh electrode; as well as A connecting portion, which is configured to be sandwiched between the opposing substrate and the array substrate, is connected to the 7th electrode and the 1st wiring.

7. The display device according to claim 6, wherein, The third conductive film is configured as a transparent electrode film comprising a transparent electrode material.

8. The display device according to claim 5, wherein, The display layer is an electronic paper layer containing multiple microcapsules or microcups containing charged particles. The second electrode and the third electrode are each configured in multiple ways, overlapping with the multiple microcapsules or microcup respectively.

Images