An electronic paper and an electronic paper display device

Abstract

The application discloses electronic paper and an electronic paper display device, and belongs to the technical field of display, and is used for improving display effect. The electronic paper comprises a display area and a boundary area arranged around the display area. The electronic paper comprises a driving substrate, an electronic paper film layer and a common electrode layer which are arranged in layers. In the driving substrate, a plurality of normal pixels are arranged in the display area, and a plurality of virtual pixels are arranged in the boundary area. The normal pixels and the virtual pixels are arranged in a matrix mode. The electronic paper film layer covers the normal pixels and the virtual pixels, and the common electrode layer covers the normal pixels and the virtual pixels. In the orthographic projection of the plane where the driving substrate is located, the size of at least part of the virtual pixels is greater than the size of the normal pixels.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to electronic paper and an electronic paper display device. Background Technology

[0002] Electronic paper, as a reflective display technology, boasts advantages such as ultra-low power consumption and a paper-like visual experience, and is widely used in electronic price tags, advertising signs, and other fields. However, the display quality of current electronic paper still needs further improvement. Summary of the Invention

[0003] This application provides an electronic paper and an electronic paper display device to improve display performance.

[0004] The first aspect of this application provides an electronic paper, which includes a display area and a boundary area surrounding the display area; the electronic paper includes a driving substrate, an electronic paper film layer and a common electrode layer stacked together. In the driving substrate, the display area is provided with a plurality of normal pixels, the boundary area is provided with a plurality of virtual pixels, and the normal pixels and the virtual pixels are arranged in a matrix; the electronic paper film layer covers the normal pixels and the virtual pixels, and the common electrode layer covers the normal pixels and the virtual pixels; In the orthographic projection of the plane where the driving substrate is located, at least some of the virtual pixels are larger than the normal pixels.

[0005] In some embodiments, the plurality of virtual pixels includes: a first virtual pixel and a second virtual pixel; In the orthographic projection of the plane where the driving substrate is located, the size of the second virtual pixel is larger than the size of the normal pixel; the size of the first virtual pixel is equal to the size of the normal pixel.

[0006] In some embodiments, the boundary area includes a first region located on both sides of the display area along the row direction, and a second region located on both sides of the display area along the column direction; The first virtual pixel is located in the first region, and the second virtual pixel is located in the second region; or The second virtual pixel is located in the first region, and the first virtual pixel is located in the second region.

[0007] In some embodiments, the first virtual pixel is located in the first region, and the second virtual pixel is located in the second region; the horizontal width of the second virtual pixel is equal to the horizontal width of the normal pixel; and The vertical length of the second virtual pixel is greater than the vertical length of the normal pixel.

[0008] In some embodiments, the second virtual pixel is located in the first region, and the first virtual pixel is located in the second region; the horizontal width of the second virtual pixel is greater than the horizontal width of the normal pixel; and The vertical length of the second virtual pixel is equal to the vertical length of the normal pixel.

[0009] In some embodiments, the boundary area includes a first region located on both sides of the display area along the row direction, and a second region located on both sides of the display area along the column direction; Each row of normal pixels is electrically connected to a first gate scan line, and each column of normal pixels is electrically connected to a first data scan line. Both the first gate scan line and the first data scan line are electrically connected to the driver IC. In this context, the virtual pixels located in the first region share the first gate scan line with the normal pixels located in the same row; Each row of virtual pixels located in the second region is connected to an independent second gate scan line, which is electrically connected to the driver IC.

[0010] In some embodiments, the sources of all the virtual pixels are connected to the same second data scan line, which is electrically connected to the driver IC.

[0011] In some embodiments, the virtual pixel includes: a first TFT, a first storage capacitor, a first insulating layer, a first via, and a boundary pixel electrode; wherein the first TFT and the first storage capacitor are disposed on the bottom layer of the driving substrate, the first insulating layer covers the first TFT and the first storage capacitor, the boundary pixel electrode is disposed on the side of the first insulating layer near the electronic paper film layer, and the first via penetrates the first insulating layer. The gate of the first TFT is electrically connected to the corresponding gate scan line, and the source of the first TFT is electrically connected to the second data scan line. The drain of the first TFT is electrically connected to the first terminal of the first storage capacitor, and the drain of the first TFT is also electrically connected to the boundary pixel electrode through the first via. The second end of the first storage capacitor is electrically connected to the common electrode layer.

[0012] In some embodiments, the virtual pixel includes: a first TFT, a first storage capacitor, a first via, a first insulating layer, and a boundary pixel electrode; the normal pixel includes: a second TFT, a second storage capacitor, a second via, a second insulating layer, and a normal pixel electrode. The virtual pixel and the normal pixel must satisfy at least one of the following: With reference to the pixel boundary of each pixel, the first TFT and the second TFT are in the same position within their respective pixels; With reference to the pixel boundary of each pixel, the first storage capacitor and the second storage capacitor are located in the same position within their respective pixels; The first insulating layer and the second insulating layer have the same film thickness within their respective pixels; The first via and the second via have the same position, aperture, and number within their respective pixels; The boundary pixel electrode and the pixel electrode have the same planar shape and / or area within their respective pixels; The channel area of ​​the first TFT is the same as that of the second TFT; The channel width-to-length ratio of the first TFT is the same as that of the second TFT.

[0013] In some embodiments, each row of normal pixels is electrically connected to a first gate scan line, and each column of normal pixels is electrically connected to a first data scan line. Both the first gate scan line and the first data scan line are electrically connected to a driver IC. The first side and the second side are the two sides of the display area that are opposite each other along the column direction; The virtual pixels located on the first side are arranged in a row in the row direction, and this row of virtual pixels shares the same first gate scan line with the normal pixels located in the first row of the display area; and / or The virtual pixels located on the second side are set as a row in the row direction, and the row of virtual pixels shares the same first gate scan line with the normal pixels located at the end of the display area.

[0014] In some embodiments, the number of gate scan signal output pins of the driver IC is equal to the number of rows of normal pixels in the display area.

[0015] A second aspect of this application also provides an electronic paper display device, including the electronic paper described in the first aspect of this application.

[0016] The beneficial effects of this application embodiment are as follows: The electronic paper provided in this application embodiment effectively improves the display effect of the boundary area by setting multiple virtual pixels in the boundary area. Specifically, this embodiment changes the original ITO direct power supply structure in the boundary area to the same pixel structure as the display area, so that the virtual pixels in the boundary area have the same charging and discharging function as normal pixels, effectively reducing the voltage difference between the pixel electrodes in the boundary area and the pixel electrodes in the display area, thereby improving the color difference problem when the boundary area and the display area display the same color.

[0017] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0019] Figure 1 This is a schematic diagram of the structure of an electronic paper proposed in the embodiments of this application; Figure 2 This is a schematic diagram of the film layer structure of electronic paper proposed in the embodiments of this application; Figure 3 This is a schematic diagram of a first virtual pixel and a second virtual pixel proposed in the embodiments of this application; Figure 4 This is a schematic diagram of another first virtual pixel and a second virtual pixel proposed in the embodiments of this application; Figure 5 This is a schematic diagram of a first gate scan line and a first data scan line proposed in an embodiment of this application; Figure 6 This is a top view of a virtual pixel proposed in the embodiments of this application; Figure 7 This is a schematic diagram of a film structure for a virtual pixel proposed in an embodiment of this application. Detailed Implementation

[0020] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, not limited in number; for example, the first object can be one or at least two. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0022] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] The first aspect of this application provides an electronic paper, referring to... Figure 1 , Figure 1 A schematic diagram of the structure of an electronic paper is shown, such as Figure 1 As shown, the electronic paper includes: The electronic paper includes a display area and a boundary area surrounding the outer periphery of the display area; the electronic paper includes a driving substrate, an electronic paper film layer, and a common electrode layer stacked together. In the driving substrate, the display area is provided with a plurality of normal pixels, the boundary area is provided with a plurality of virtual pixels, and the normal pixels and the virtual pixels are arranged in a matrix; the electronic paper film layer covers the normal pixels and the virtual pixels, and the common electrode layer covers the normal pixels and the virtual pixels; In the orthographic projection of the plane where the driving substrate is located, at least some of the virtual pixels are larger than the normal pixels.

[0025] Specifically, such as Figure 1 As shown, the electronic paper includes a display area AA and a border area BB, with the border area BB surrounding the display area AA. The display area AA is used to display image content. The border area BB, or border zone, is used to display a solid color (usually white or black). For example, the width of the border area BB can be 0.5mm. After the entire device is assembled, the casing cannot cover the display area AA. By making the gap between the casing and the display area AA (i.e., the border area BB) display a solid color, the product's appearance can be cleaner and more aesthetically pleasing. The periphery of the border area BB also has signal traces such as scan lines and data lines for transmitting drive signals.

[0026] Reference Figure 2 , Figure 2 A schematic diagram of the film structure of electronic paper is shown, as follows. Figure 2 As shown, the electronic paper includes a driving substrate 1, an electronic paper film layer 2, and a common electrode layer 3 stacked along the thickness direction. The driving substrate 1 serves as the array substrate of the electronic paper, providing driving signals to each pixel. The electronic paper film layer 2 is disposed on one side of the driving substrate 1 and encapsulates charged particles for image display under the influence of an electric field. The common electrode layer 3 is disposed on the side of the electronic paper film layer 2 facing away from the driving substrate 1. The common electrode layer 3 is a continuous transparent conductive layer that forms a driving electric field on both sides of the electronic paper film layer 2.

[0027] The common electrode layer 3 can be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), and its thickness can be set according to actual needs, for example, from 50nm to 150nm. The common electrode layer 3 covers the entire display area AA and the boundary area BB, and is a continuous electrode structure. When driven, a common voltage (Vcom) is applied, forming a vertical electric field between it and each pixel electrode, driving the charged particles in the electronic paper film layer 2 to move to achieve display.

[0028] The display area AA contains multiple normal pixels 5, and the boundary area BB contains multiple virtual pixels 4. The normal pixels 5 and virtual pixels 4 are arranged in a matrix. The electronic paper film layer 2 covers both the normal pixels 5 in the display area AA and the virtual pixels 4 in the boundary area BB. The common electrode layer 3 covers both the display area AA and the boundary area BB. The normal pixels 5 are used to display image content, and the virtual pixels 4 are used to make the boundary area BB display a single color, achieving an aesthetically pleasing bezel effect after the entire device is assembled.

[0029] Specifically, the working principle of this electronic paper is as follows: A common voltage (Vcom) is applied to the common electrode layer 3 during electronic paper operation. This common voltage is a constant reference voltage. Each pixel electrode (including the pixel electrode 501 of normal pixel 5 and the boundary pixel electrode 401 of virtual pixel 4) is respectively applied a data voltage corresponding to the displayed grayscale. The common electrode layer 3 and each pixel electrode are located on opposite sides of the electronic paper film layer 2, forming a vertical electric field perpendicular to the plane of the driving substrate 1. This vertical electric field drives the charged particles 201 encapsulated within the electronic paper film layer 2 to move along the direction of the electric field, causing the charged particles to displace in the thickness direction of the electronic paper film layer 2, thereby causing the electronic paper film layer 2 to display corresponding grayscale or color, achieving image display. When the charged particles 201 move to the side closer to the common electrode layer 3 or closer to the pixel electrode, the electronic paper film layer 2 displays the corresponding grayscale or color. By precisely controlling the data voltage of each pixel electrode, each pixel can display different grayscale levels, achieving image display; by controlling the data voltage of the boundary pixel electrode to a fixed value, the boundary area BB can display a single color. That is, since the common electrode layer 3 is a continuous electrode structure, the common voltage applied to it acts on both the display area AA and the boundary area BB. Therefore, when displaying the same color, the voltage consistency between the pixel electrode of the normal pixel 5 and the boundary pixel electrode of the virtual pixel 4 determines the display uniformity between the display area 1 and the boundary area 2.

[0030] In related technologies, the boundary region BB is provided with a ring of boundary pixel electrodes surrounding region AA 1. These boundary pixel electrodes are typically formed from a continuous ITO (indium tin oxide) transparent conductive layer. This ITO electrode is directly electrically connected to the Border signal pin of the driver IC; that is, the Border signal output by the driver IC is directly applied to the ITO electrode (boundary pixel electrode) of the boundary region BB. Since there is a direct conductive connection between the ITO electrode and the driver IC, and no switching device exists in between, the voltage on the ITO electrode is almost equal to the Border signal voltage (i.e., the output voltage) output by the driver IC.

[0031] During the electronic paper display process, a common voltage (Vcom) is applied to the common electrode layer 3 located above the electronic paper film layer 2. The voltage difference between the ITO electrode and the common electrode layer 3 forms a vertical electric field on both sides of the electronic paper film layer 2. This vertical electric field drives the charged particles inside the electronic paper film layer 2 of the boundary region BB to move, thereby making the boundary region BB display a solid color.

[0032] The normal pixels in display area AA have a 1T1C circuit structure, where the pixel voltage is maintained by a gate switch. During pixel charging, due to the parasitic capacitance (Cgs) of the TFT, the gate signal transition is coupled to the pixel electrode through this parasitic capacitance. This causes the actual pixel voltage of the normal pixel to be more negative than the output voltage of the driver IC, i.e., a feedthrough effect exists. To compensate for this effect, the Vcom voltage is usually set to a non-zero value to ensure symmetrical positive and negative frame driving. Therefore, the actual voltage of the pixel electrode of the normal pixel is not equal to the data voltage output by the driver IC; the actual pixel voltage is more negative than the output voltage of the driver IC.

[0033] Because the output voltages of the Border signal (data signal for the boundary area) and the Source signal (data signal for the display area) of the driver IC are equal, but the pixel voltage of the display area AA is lower than the IC output voltage due to the feedthrough effect, the voltage difference between the normal pixel voltage of the display area AA and Vcom is inconsistent with the voltage difference between the ITO electrode of the boundary area BB and Vcom. Ultimately, the two areas produce a color difference when displaying the same color.

[0034] To address the aforementioned issues, this embodiment divides the boundary region (originally a single surface of ITO electrode material) into multiple virtual electrodes, making the structure of the virtual pixels identical to that of the normal pixels. Specifically, each virtual electrode has a corresponding individual boundary pixel electrode 401. This boundary pixel electrode 401 is electrically connected to the drain of the virtual pixel TFT within the driving substrate and receives a fixed voltage signal from the driving IC through the source of the virtual pixel TFT. Simultaneously, each virtual pixel also has a storage capacitor disposed opposite to the boundary pixel electrode 401, enabling each virtual pixel to form the same 1T1C pixel structure as the normal pixels in the display area. Therefore, each virtual pixel in the boundary region possesses the same charging and discharging characteristics as the normal pixels, and the difference between its pixel electrode voltage and the pixel electrode voltage in the display area is eliminated or significantly reduced, thereby improving the color difference between the boundary region and the display area.

[0035] In this embodiment, in the orthographic projection of the plane where the driving substrate is located, at least some of the virtual pixels are larger than the normal pixels. Specifically, since the boundary region BB is usually a ring-shaped area with a limited width (e.g., about 0.5 mm), if the size of the virtual pixel 4 is the same as the size of the normal pixel 5, the number of rows of virtual pixels 4 that can be arranged in the boundary region is large, and correspondingly, more gate scan lines are needed to drive these virtual pixels 4. However, the number of gate scan signal output pins of the driving IC is usually limited, making it difficult to support a large number of additional gate scan lines. To reduce the requirement for the number of driving IC pins, this application designs the size of at least some of the virtual pixels 4 to be larger than the size of the normal pixel 3, thereby reducing the number of rows or columns of virtual pixels 4 in the boundary region. This allows only a smaller number of rows of virtual pixels 4 to fill the boundary region within a limited width, and the required number of gate scan lines is also reduced. Thus, this application can improve color difference while taking into account the compatibility of the driving IC, reducing design costs and implementation difficulty.

[0036] In some embodiments, the plurality of virtual pixels includes: a first virtual pixel and a second virtual pixel; In the orthographic projection of the plane where the driving substrate is located, the size of the second virtual pixel is larger than the size of the normal pixel; the size of the first virtual pixel is equal to the size of the normal pixel.

[0037] In some embodiments, the boundary area includes a first region located on both sides of the display area along the row direction, and a second region located on both sides of the display area along the column direction; The first virtual pixel is located in the first region, and the second virtual pixel is located in the second region; or The second virtual pixel is located in the first region, and the first virtual pixel is located in the second region.

[0038] Reference Figure 3 , Figure 3 A schematic diagram of a first region and a second region is shown, such as Figure 3 As shown, the first region B1 refers to the region located on the left and right sides of the display area along the row direction, and the second region B2 is the region located on both sides of the display area along the column direction.

[0039] The first virtual pixel 41 is located in the first region B1, and the second virtual pixel 42 is located in the second region B2. The first virtual pixel 41 is located on the left and right sides of the display area AA along the row direction (first region B1); the second virtual pixel 42 is located on the top and bottom sides of the display area along the column direction (second region B2). In the orthographic projection of the plane where the driving substrate is located, the size of the second virtual pixel 42 is larger than the size of the normal pixel 5, while the size of the first virtual pixel 41 is equal to the size of the normal pixel 5.

[0040] Since the second virtual pixels 42 on the upper and lower sides of the display area AA require additional independent gate scan lines, their size is designed to be larger than that of the normal pixel 5 to reduce the number of additional gate scan lines. By increasing the area of ​​the second virtual pixels 42, the number of rows required for the second virtual pixels 42 can be reduced within the limited width boundary area BB, thereby reducing the number of additional gate scan lines and lowering the requirements for the number of driver IC pins.

[0041] In some embodiments, the first virtual pixel is located in the first region, and the second virtual pixel is located in the second region; the horizontal width of the second virtual pixel is equal to the horizontal width of the normal pixel; and The vertical length of the second virtual pixel is greater than the vertical length of the normal pixel.

[0042] In this embodiment, as Figure 3 As shown, the horizontal width d1 of the second virtual pixel 42 in the second region B2 is the same as the horizontal width d2 of the normal pixel 5 in the same column, and the vertical length d3 of the second virtual pixel 42 is greater than the vertical length d4 of the normal pixel 5 in the same column. That is to say, the second virtual pixel 42 is only stretched in the column direction, while its width in the row direction remains unchanged.

[0043] The reason for this design is that the width of the boundary area is limited (typically about 0.5mm), and the second virtual pixel 42 is located on the top and bottom sides of the display area AA (i.e., the second region B2), with its vertical length direction consistent with the width direction of the boundary area BB. By increasing the size of the second virtual pixel 42 only in the column direction, the number of rows required for the second virtual pixel 42 in the column direction can be effectively reduced without increasing the area occupied by the boundary area BB in the width direction. At the same time, keeping the width in the row direction unchanged is beneficial for maintaining consistency with the normal pixels 5 in the same column in terms of manufacturing process, reducing the manufacturing difficulty.

[0044] For example, the vertical length of the second virtual pixel can be 2 to 5 times that of the normal pixel. Taking a normal pixel size of 100μm × 100μm and a boundary area width of 500μm as an example, if the vertical dimension of the second virtual pixel is 100μm, then 5 rows of second virtual pixels are needed on both the top and bottom sides, requiring a total of 10 additional gate scan lines; if the vertical dimension of the second virtual pixel is increased to 250μm, then only 2 rows of second virtual pixels are needed on both the top and bottom sides, requiring a total of only 4 additional gate scan lines, significantly reducing the pin requirements of the driver IC.

[0045] The second virtual pixel is located in the first region, and the first virtual pixel is located in the second region.

[0046] In this embodiment, the second virtual pixel is located on the left and right sides of the display area (first region) along the row direction, and the first virtual pixel is located on the top and bottom sides of the display area (second region) along the column direction. That is, in this embodiment, virtual pixels with a size larger than normal pixels are located on the left and right sides of the display area 1 (first region), rather than on the top and bottom sides (second region).

[0047] When the display area AA of the electronic paper is large in the row direction, the width of the boundary areas BB on the left and right sides is relatively wide, or the data signal output pins of the driver IC are more scarce, increasing the size of the virtual pixels located on both sides of the display area AA along the row direction can reduce the number of columns of virtual pixels on the left and right sides, thereby reducing the number of data scan lines required and reducing the demand on the data pins of the driver IC.

[0048] In some embodiments, the second virtual pixel is located in the first region, and the first virtual pixel is located in the second region; the horizontal width of the second virtual pixel is greater than the horizontal width of the normal pixel; and The vertical length of the second virtual pixel is equal to the vertical length of the normal pixel.

[0049] Reference Figure 4 , Figure 4 A schematic diagram of a first virtual pixel and a second virtual pixel is shown, as follows: Figure 4 As shown, in this embodiment, the second virtual pixel 42 is located in the first region B1, and the first virtual pixel 41 is located in the second region B2; the horizontal width D1 of the second virtual pixel 42 is greater than the horizontal width D2 of the normal pixel 5 in the same row, and the vertical length D3 of the second virtual pixel 42 is equal to the vertical length D4 of the normal pixel 5 in the same row. That is, the second virtual pixel 42 is only stretched in the row direction (horizontal), while its length in the column direction (vertical) remains unchanged.

[0050] The second virtual pixel 42 is located on the left and right sides of the display area AA (first area B1), and its horizontal width direction is consistent with the width direction of the boundary area BB (second area B2). By increasing the size of the second virtual pixel 42 only in the row direction, the number of columns required for the second virtual pixel 42 in the row direction can be effectively reduced without increasing the area occupied in the width direction of the boundary area, thereby reducing the number of data scan lines required. At the same time, keeping the vertical length unchanged is beneficial to maintaining consistency with the normal pixel 5 in the same row in terms of manufacturing process. For example, the horizontal width of the second virtual pixel 42 can be 2 to 5 times the horizontal width of the normal pixel 5.

[0051] In some embodiments, the boundary area includes a first region located on both sides of the display area along the row direction, and a second region located on both sides of the display area along the column direction; Each row of normal pixels is electrically connected to a first gate scan line, and each column of normal pixels is electrically connected to a first data scan line. Both the first gate scan line and the first data scan line are electrically connected to the driver IC. In this context, the virtual pixels located in the first region share the first gate scan line with the normal pixels located in the same row; Each row of virtual pixels located in the second region is connected to an independent second gate scan line, which is electrically connected to the driver IC.

[0052] Reference Figure 5 , Figure 5 A schematic diagram of a first gate scan line and a first data scan line is shown, as follows: Figure 5 As shown, each row of normal pixels 5 is electrically connected to a first gate scan line (e.g. Figure 5 G0 to G shown n+5 Each column of normal pixels (5 pixels) is electrically connected to a first data scan line (e.g., ...). Figure 5 S0 to S shown n+2 Both the first gate scan line and the first data scan line are electrically connected to the driver IC. The driver IC provides a gate scan signal to the normal pixel 5 through the first gate scan line and a data voltage signal to the normal pixel 5 through the first data scan line.

[0053] In this configuration, the virtual pixels 4 located in the first region share the same first gate scan line as the normal pixels 5 located in the same row. Specifically, the virtual pixels 4 on the left and right sides of the display area AA are aligned with the normal pixels 5 located in the same horizontal direction (same row) in the row direction, and their gate layers are electrically connected to the same first gate scan line. In this way, when the driver IC outputs a gate scan signal through the first gate scan line, the normal pixels 5 in that row and the virtual pixels 4 on the left and right sides are simultaneously selected, without the need to add additional gate scan lines for the virtual pixels 4 on the left and right sides.

[0054] Each row of virtual pixels located in the second region is connected to an independent second gate scan line (i.e., a border signal line), which is also electrically connected to the driver IC. Specifically, the virtual pixels located on the upper and lower sides of display area AA can be connected to different second gate scan lines. These second gate scan lines are newly added gate scan lines, set independently of the first gate scan lines. The driver IC provides gate scan signals to the virtual pixel 4 through the second gate scan lines to control the TFT of the virtual pixel 4 to turn on or off.

[0055] In this embodiment, the virtual pixels located on the left and right sides of the display area share the gate scan lines of the normal pixels in the AA area, without adding additional gate scan lines. However, the virtual pixels located on the top and bottom sides of the display area do not have corresponding normal pixels to share in the row direction, so independent second gate scan lines need to be added for driving. In some embodiments, the size of the virtual pixels 4 located on the top and bottom sides of the display area is designed to be larger than the size of the normal pixels 5. The number of rows of virtual pixels 4 (in this case, the second virtual pixel 42) is smaller, and the number of additional second gate scan lines required is also reduced accordingly. This achieves the Border area 1T1C pixel structure while minimizing the additional requirements for the number of driver IC pins.

[0056] It is understood that in other embodiments (e.g., when the driver IC has a sufficient number of spare pins), the size of the virtual pixel can be kept the same as that of the normal pixel, while correspondingly increasing the number of second gate scan lines, which can also achieve the technical effects of this application. Those skilled in the art can make the selection according to actual needs.

[0057] In some embodiments, the sources of all the virtual pixels are connected to the same second data scan line, which is electrically connected to the driver IC.

[0058] The driver IC provides data signals to the source layer of all virtual pixels 4 through the second data scan line.

[0059] In this embodiment, the sources of all virtual pixels (i.e., the source layers of the virtual pixel TFTs) are connected to the same second data scan line, which is electrically connected to the driver IC. That is, the sources of the first virtual pixel 41 and the second virtual pixel 42 are both connected to the same second data scan line, and the sources of each virtual pixel 4 receive data signals from the driver IC through this common second data scan line.

[0060] Unlike the first data scan line connected to the normal pixels 5 in display area AA, which consists of multiple independent signal lines, each corresponding to a column of normal pixels 5, the driver IC outputs different data voltage signals to each first data scan line according to the image display content to achieve different grayscale levels. In contrast, there is only one second data scan line, which is shared by all virtual pixels 4. The driver IC only needs to output a single voltage value to the second data scan line, eliminating the need for a separate data scan line for each column of virtual pixels 4. For example, the value of this constant voltage signal can be preset according to the desired display effect. For instance, when set to the first voltage value, the boundary area BB is displayed as white; when set to the second voltage value, the boundary area BB is displayed as black; and when set to the third voltage value, the boundary area BB is displayed as a certain intermediate grayscale level. Therefore, this embodiment can significantly reduce the number of data scan lines, reduce wiring complexity, and save data output pin resources of the driver IC.

[0061] In some embodiments, the virtual pixel includes: a first TFT, a first storage capacitor, a first insulating layer, a first via, and a boundary pixel electrode; wherein the first TFT and the first storage capacitor are disposed on the bottom layer of the driving substrate, the first insulating layer covers the first TFT and the first storage capacitor, the boundary pixel electrode is disposed on the side of the first insulating layer near the electronic paper film layer, and the first via penetrates the first insulating layer; The gate of the first TFT is electrically connected to the corresponding gate scan line, and the source of the first TFT is electrically connected to the second data scan line. The drain of the first TFT is electrically connected to the first terminal of the first storage capacitor, and the drain of the first TFT is also electrically connected to the boundary pixel electrode through the first via. The second end of the first storage capacitor is electrically connected to the common electrode layer.

[0062] In this embodiment, the virtual pixel has the same structure as the normal pixel, both being a 1T1C structure. (Refer to...) Figure 6 and Figure 7 , Figure 6 A top view of a virtual pixel is shown. Figure 7 A schematic diagram of a film structure for a virtual pixel is shown, as follows. Figure 6 and Figure 7 As shown, the virtual pixel 4 includes a first TFT, a first storage capacitor, a first insulating layer, a first via 402, and a boundary pixel electrode 401.

[0063] The first TFT and the first storage capacitor are both disposed on the bottom layer of the driving substrate (i.e., the side of the driving substrate closest to the glass substrate), and the first insulating layer 403 (i.e. Figure 7The PVX in the first TFT and the first storage capacitor are covered above the boundary pixel electrode 401 (i.e., Figure 7 The ITO in the first insulating layer 403 is disposed on the side of the first insulating layer near the electronic paper film layer (i.e., the upper surface of the first insulating layer), and the first via 402 is disposed through the first insulating layer 403.

[0064] The first TFT includes a gate, a source, and a drain. The gate is electrically connected to a corresponding gate scan line (first gate scan line or second gate scan line), the source is electrically connected to a second data scan line, and the drain is electrically connected to a first terminal of a first storage capacitor. The drain is also electrically connected to a boundary pixel electrode 401 through a first via penetrating the first insulating layer. The second terminal of the first storage capacitor is electrically connected to a common electrode layer (i.e., connected to a common voltage Vcom).

[0065] When the gate scan line provides a gate scan signal, the first TFT is turned on, and the voltage signal on the second data scan line is transmitted to the boundary pixel electrode through the source and drain, simultaneously charging the first storage capacitor. When the gate scan signal ends, the first TFT is turned off, and the voltage on the boundary pixel electrode is maintained by the first storage capacitor. Thus, virtual pixel 4 has the same charging and discharging function as normal pixel 5.

[0066] Unlike existing technologies where the entire ITO electrode in the boundary region is directly connected to the Border signal pin of the driver IC without passing through a TFT switch, in this embodiment, the boundary pixel electrode of the virtual pixel 4 is charged through the first TFT. Its voltage build-up process is exactly the same as that of the normal pixel 5, both being affected by TFT switching characteristics and feedthrough effects. Therefore, under the same driving signal, the actual holding voltage of the boundary pixel electrode tends to be consistent with the actual holding voltage of the pixel electrode of the normal pixel 5, and the voltage difference between the boundary pixel electrode and the common electrode layer tends to be the same as that between the pixel electrode and the common electrode layer of the normal pixel 5, thereby eliminating the color difference between the boundary region and the display area.

[0067] In some embodiments, the virtual pixel includes: a first TFT, a first storage capacitor, a first via, a first insulating layer, and a boundary pixel electrode; the normal pixel includes: a second TFT, a second storage capacitor, a second via, a second insulating layer, and a normal pixel electrode. The virtual pixel and the normal pixel must satisfy at least one of the following: A-1, with reference to the pixel boundary of each pixel, the first TFT and the second TFT are in the same position within their respective pixels; Specifically, within the pixel region of virtual pixel 4, the position of the first TFT (including its gate, source, drain, and semiconductor layer) relative to the four boundaries of virtual pixel 4 is consistent with the position of the second TFT relative to its pixel boundaries in normal pixel 3. By ensuring that the TFTs occupy the same relative positions within the pixel, it is beneficial to the consistency of the fabrication process.

[0068] A-2, with reference to the pixel boundary of each pixel, the first storage capacitor and the second storage capacitor are located in the same position within their respective pixels; Specifically, by ensuring that the storage capacitors occupy the same relative position within the pixel, the capacitance values ​​of both are not affected by positional offset, thus guaranteeing consistent charging and discharging characteristics.

[0069] A-3, the first insulating layer and the second insulating layer have the same film thickness within their respective pixels; Specifically, the thickness of the insulating layer directly affects the gate insulation capacitance and the capacitance value of the storage capacitor in the TFT. Making the insulating layer thickness the same for both ensures that the electrical parameters of the TFT, such as the threshold voltage, are consistent, and also ensures that the capacitance value of the storage capacitor is consistent.

[0070] A-4, the first via and the second via have the same position, aperture and number within their respective pixels; Specifically, vias are used to achieve electrical connections between different conductive layers. Their location, aperture size, and number affect contact resistance and connection reliability. Ensuring that the above parameters of the vias are the same ensures consistent contact resistance between the pixel electrode layer and the TFT drain, avoiding voltage differences caused by variations in contact resistance.

[0071] A-5, the boundary pixel electrode and the pixel electrode have the same planar shape and / or area within their respective pixels; Specifically, the planar shape and area of ​​the pixel electrode determine the pixel's aperture ratio and the capacitance between it and the common electrode layer. Making both shapes and / or areas identical ensures that the storage capacitance and electric field distribution are consistent under the same voltage, contributing to a uniform display effect.

[0072] A-6, the channel area of ​​the first TFT is the same as the channel area of ​​the second TFT; Specifically, the channel area, equal to the product of the channel length and the channel width, determines the magnitude of the on-state current of the TFT. Ensuring identical channel areas guarantees that the first and second TFTs have the same current driving capability and can achieve the same charging voltage within the same charging time.

[0073] A-7, the channel width-to-length ratio of the first TFT is the same as that of the second TFT.

[0074] Specifically, the channel width-to-length ratio (W / L) is a core parameter determining the driving capability of a TFT, directly influencing its on-state current and transconductance. Even with the same channel area, different W / L ratios will result in different current-voltage characteristics for the TFT. Ensuring the same channel width-to-length ratio guarantees that the first and second TFTs have identical electrical characteristics.

[0075] In some embodiments, each row of normal pixels is electrically connected to a first gate scan line, and each column of normal pixels is electrically connected to a first data scan line. Both the first gate scan line and the first data scan line are electrically connected to a driver IC. The first side and the second side are the two sides of the display area that are opposite each other along the column direction; The virtual pixels located on the first side are arranged in a row in the row direction, and this row of virtual pixels shares the same first gate scan line with the normal pixels located in the first row of the display area; and / or The virtual pixels located on the second side are set as a row in the row direction, and the row of virtual pixels shares the same first gate scan line with the normal pixels located at the end of the display area.

[0076] The virtual pixels located on the first side are arranged in a single row in the row direction, meaning that the virtual pixels located on the upper side of the display area are arranged in a single row. This row of virtual pixels shares the same first gate scan line with the normal pixels 5 located in the first row (i.e., the first row) of the display area. In other words, the gate layer of the normal pixels 5 in the first row of the display area and the virtual gate layer of the virtual pixels located on the first side are electrically connected through the same first gate scan line.

[0077] The virtual pixels located on the second side are also arranged in a single row in the row direction. That is, the virtual pixels located at the bottom of the display area are arranged in a single row. This row of virtual pixels shares the same first gate scan line with the normal pixels 5 located at the end of the display area (i.e., the nth row, where n is the total number of rows of normal pixels in the display area). In other words, the gate layer of the normal pixels 5 at the end of the display area and the virtual gate layer of the virtual pixels located on the second side are electrically connected through the same first gate scan line.

[0078] In some implementations, only the virtual pixels on the first side share the first gate scan line with the normal pixels in the first row of the display area, while the virtual pixels on the second side are driven by a separate second gate scan line. In other implementations, only the virtual pixels on the second side share the first gate scan line with the normal pixels in the last row of the display area, while the virtual pixels on the first side are driven by a separate second gate scan line. In a preferred implementation, the virtual pixels on the first and second sides share the first gate scan line with the normal pixels in the first and last rows of the display area, respectively, to minimize the number of driver IC pins required.

[0079] This embodiment achieves gate driving of the virtual pixels on the top and bottom sides by compressing the virtual pixels on both sides into a single row and sharing the gate scan line with the edge rows (first or last row) of the display area. This is done without adding any gate scan lines. Because the vertical dimension of the virtual pixel is designed to be larger than that of a normal pixel, even if the virtual pixel is set to only one row, its vertical length can cover the width of the entire boundary area, ensuring that the boundary area is completely filled without gaps. This balances display quality with compatibility with the driver IC.

[0080] In some embodiments, the number of gate scan signal output pins of the driver IC is equal to the number of rows of normal pixels in the display area.

[0081] In this embodiment, the number of gate scan signal output pins of the driver IC is equal to the number of rows of normal pixels 5 in the display area. That is, all the gate scan signal output pins of the driver IC are completely occupied by the first gate scan lines corresponding to each row of normal pixels 5 in the display area, and there are no extra pins that can be used to independently add gate scan lines for virtual pixels.

[0082] In this scenario, if virtual pixels require additional gate scan lines, a driver IC with more gate pins must be replaced, increasing costs and potentially limiting package size. This application addresses this by sharing the same first gate scan line between the virtual pixels on the first and second sides and the normal pixels 5 in the first and last rows of the display area, respectively. Furthermore, by setting the virtual pixels as a single row in the row direction, gate driving of the virtual pixels is achieved without occupying additional gate pins. This makes the technical solution compatible with existing driver ICs, eliminating the need for replacement or customization of special driver chips.

[0083] A second aspect of this application also provides an electronic paper display device, including the electronic paper described in the first aspect of this application.

[0084] The electronic paper provided in this application embodiment effectively improves the display effect in the boundary area by setting multiple virtual pixels in the boundary area. Specifically, this embodiment changes the original ITO direct power supply structure in the boundary area to the same pixel structure as the display area, so that the virtual pixels in the boundary area have the same charging and discharging function as normal pixels, effectively reducing the voltage difference between the pixel electrodes in the boundary area and the pixel electrodes in the display area, thereby improving the color difference problem when the boundary area and the display area display the same color.

[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0086] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0087] The above provides a detailed description of an electronic paper and an electronic paper display device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0088] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0089] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0090] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0091] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0092] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An electronic paper, characterized in that, The electronic paper includes a display area and a boundary area surrounding the outer periphery of the display area; the electronic paper includes a driving substrate, an electronic paper film layer, and a common electrode layer stacked together. In the driving substrate, the display area is provided with a plurality of normal pixels, the boundary area is provided with a plurality of virtual pixels, and the normal pixels and the virtual pixels are arranged in a matrix; the electronic paper film layer covers the normal pixels and the virtual pixels, and the common electrode layer covers the normal pixels and the virtual pixels; In the orthographic projection of the plane where the driving substrate is located, at least some of the virtual pixels are larger than the normal pixels.

2. The electronic paper according to claim 1, characterized in that, The plurality of virtual pixels includes: a first virtual pixel and a second virtual pixel; In the orthographic projection of the plane where the driving substrate is located, the size of the second virtual pixel is larger than the size of the normal pixel; the size of the first virtual pixel is equal to the size of the normal pixel.

3. The electronic paper according to claim 2, characterized in that, The boundary area includes a first region located on both sides of the display area along the row direction, and a second region located on both sides of the display area along the column direction; The first virtual pixel is located in the first region, and the second virtual pixel is located in the second region; or The second virtual pixel is located in the first region, and the first virtual pixel is located in the second region.

4. The electronic paper according to claim 3, characterized in that, The first virtual pixel is located in the first region, and the second virtual pixel is located in the second region; the horizontal width of the second virtual pixel is equal to the horizontal width of the normal pixel; and The vertical length of the second virtual pixel is greater than the vertical length of the normal pixel.

5. The electronic paper according to claim 3, characterized in that, The second virtual pixel is located in the first region, and the first virtual pixel is located in the second region; the horizontal width of the second virtual pixel is greater than the horizontal width of the normal pixel; and The vertical length of the second virtual pixel is equal to the vertical length of the normal pixel.

6. The electronic paper according to claim 1, characterized in that, The boundary area includes a first region located on both sides of the display area along the row direction, and a second region located on both sides of the display area along the column direction; Each row of normal pixels is electrically connected to a first gate scan line, and each column of normal pixels is electrically connected to a first data scan line. Both the first gate scan line and the first data scan line are electrically connected to the driver IC. In this context, the virtual pixels located in the first region share the first gate scan line with the normal pixels located in the same row; Each row of virtual pixels located in the second region is connected to an independent second gate scan line, which is electrically connected to the driver IC.

7. The electronic paper according to claim 1, characterized in that, The sources of all the virtual pixels are connected to the same second data scan line, which is electrically connected to the driver IC.

8. The electronic paper according to claim 1, characterized in that, The virtual pixel includes: a first TFT, a first storage capacitor, a first insulating layer, a first via, and a boundary pixel electrode; wherein, the first TFT and the first storage capacitor are disposed on the bottom layer of the driving substrate, the first insulating layer covers the first TFT and the first storage capacitor, the boundary pixel electrode is disposed on the side of the first insulating layer near the electronic paper film layer, and the first via penetrates the first insulating layer; The gate of the first TFT is electrically connected to the corresponding gate scan line, and the source of the first TFT is electrically connected to the second data scan line. The drain of the first TFT is electrically connected to the first terminal of the first storage capacitor, and the drain of the first TFT is also electrically connected to the boundary pixel electrode through the first via. The second end of the first storage capacitor is electrically connected to the common electrode layer.

9. The electronic paper according to claim 1, characterized in that, The virtual pixel includes: a first TFT, a first storage capacitor, a first via, a first insulating layer, and a boundary pixel electrode; the normal pixel includes: a second TFT, a second storage capacitor, a second via, a second insulating layer, and a normal pixel electrode. The virtual pixel and the normal pixel must satisfy at least one of the following: With reference to the pixel boundary of each pixel, the first TFT and the second TFT are in the same position within their respective pixels; With reference to the pixel boundary of each pixel, the first storage capacitor and the second storage capacitor are located in the same position within their respective pixels; The first insulating layer and the second insulating layer have the same film thickness within their respective pixels; The first via and the second via have the same position, aperture, and number within their respective pixels; The boundary pixel electrode and the pixel electrode have the same planar shape and / or area within their respective pixels; The channel area of ​​the first TFT is the same as that of the second TFT; The channel width-to-length ratio of the first TFT is the same as that of the second TFT.

10. The electronic paper according to claim 1, characterized in that, Each row of normal pixels is electrically connected to a first gate scan line, and each column of normal pixels is electrically connected to a first data scan line. Both the first gate scan line and the first data scan line are electrically connected to the driver IC. The first side and the second side are the two sides of the display area that are opposite each other along the column direction; The virtual pixels located on the first side are arranged in a row in the row direction, and this row of virtual pixels shares the same first gate scan line with the normal pixels located in the first row of the display area; and / or The virtual pixels located on the second side are set as a row in the row direction, and the row of virtual pixels shares the same first gate scan line with the normal pixels located at the end of the display area.

11. The electronic paper according to claim 10, characterized in that, The number of gate scan signal output pins of the driver IC is equal to the number of rows of normal pixels in the display area.

12. An electronic paper display device, characterized in that, Includes the electronic paper as described in any one of claims 1-11.

Images