Photomask set, semiconductor manufacturing method, resonator, filter, and apparatus

Abstract

The present disclosure provides a photomask set, a semiconductor manufacturing method, a resonator, a filter and an apparatus. The photomask set comprises at least one main photomask and at least one multiplexing photomask. Each main photomask comprises at least one pattern group, and the number of pattern groups in the at least one main photomask is greater than or equal to 2. The multiplexing photomask comprises a light-transmitting region and a non-light-transmitting region, and the multiplexing photomask itself or after being combined forms a selected region. For any pattern group in each main photomask, there is a selected region covering the pattern group and not covering other pattern groups in the main photomask. The selected region refers to: an overlapping part between the light-transmitting regions in all or part of the multiplexing photomask; or, an overlapping part between the non-light-transmitting regions in all or part of the multiplexing photomask; or, an overlapping part between the light-transmitting regions in part of the multiplexing photomask and the non-light-transmitting regions in another part of the multiplexing photomask. The number of photomasks can be reduced, and the cost can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a photomask assembly, a semiconductor manufacturing method, a resonator, a filter, and an apparatus. Background Technology

[0002] With the development of semiconductor technology, the variety and complexity of device parameters in electronic devices have increased. For example, a single electronic device may contain multiple similar devices of different sizes, such as through-silicon vias (TSVs) of different depths in a semiconductor chip or resonators of different thicknesses in a filter. Due to their different shape parameters, these TSVs and resonators require different masks for fabrication. For filters containing resonators of varying thicknesses, the number of masks required during the manufacturing process is also greater, resulting in higher costs. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a photomask assembly, a semiconductor manufacturing method, a resonator, a filter, and an apparatus.

[0004] In a first aspect, embodiments of this disclosure provide a photomask assembly, the photomask assembly comprising at least one main photomask and at least one multiplexed photomask; each main photomask comprises at least one pattern group, and the number of pattern groups in at least one main photomask is greater than or equal to 2; the multiplexed photomask comprises a transparent area and a non-transparent area, the multiplexed photomask itself or formed by combination to form a selected area; for any pattern group in each main photomask, there exists a selected area that covers the pattern group but does not cover other pattern groups in the main photomask to which it belongs; the selected area refers to: the overlapping portion between the transparent areas in all or part of the multiplexed photomasks; or, the overlapping portion between the non-transparent areas in all or part of the multiplexed photomasks; or, the overlapping portion between the transparent areas in a portion of the multiplexed photomasks and the non-transparent areas in another portion of the multiplexed photomasks.

[0005] In some embodiments, in any of the main photomasks, each pattern in the pattern group is used to fabricate a semiconductor unit; the semiconductor units corresponding to patterns in the same pattern group have the same thickness, and the semiconductor units corresponding to patterns in different pattern groups have different thicknesses; or, the semiconductor units corresponding to patterns in the same pattern group have the same depth, and the semiconductor units corresponding to patterns in different pattern groups have different depths.

[0006] In some embodiments, the photomask set is used to fabricate semiconductor cells of N thicknesses and / or depths, where N is a positive integer greater than or equal to 4; each master photomask includes at most a pattern groups, and the minimum number of multiplexed photomasks is the result of a / 2 rounded up; where a is a positive integer greater than or equal to 2; the minimum number of master photomasks is the result of N / a rounded up.

[0007] In some embodiments, at most A layers of photoresist are present simultaneously during the fabrication of the semiconductor unit, and a main photomask is used to pattern a layer of photoresist; (A-1) multiplexed photomasks are used one-to-one to pattern (A-1) layers of photoresist; A is a positive integer greater than or equal to 2.

[0008] In some embodiments, the photomask assembly is used to prepare semiconductor cells of N thicknesses and / or depths, where N is a positive integer; if N is odd, then A = the floor of a / 2; if N is even, then A = a / 2 + 1.

[0009] In some embodiments, when a=4, the main photomask is divided into a first region, a second region, a third region and a fourth region, each region having at most one of the graphic groups, and at least one of the regions having the graphic groups.

[0010] The multiplexing photomask is also divided into a first region, a second region, a third region, and a fourth region. For the first multiplexing photomask, the first region and the second region together serve as the light-transmitting area, and the remaining regions are the non-light-transmitting areas; or, the first region and the second region together serve as the non-light-transmitting area, and the remaining regions are the light-transmitting areas. For the second multiplexing photomask, the second region and the third region together serve as the light-transmitting area, and the remaining regions are the non-light-transmitting areas; or, the second region and the third region together serve as the non-light-transmitting area, and the remaining regions are the light-transmitting areas.

[0011] In some embodiments, the photomask assembly is used to fabricate resonators of different thicknesses in a filter; the photomask assembly is used to form the bottom electrode layer of different resonators; and / or, the photomask assembly is used to form the piezoelectric layer of different resonators; and / or, the photomask assembly is used to form the top electrode layer of different resonators.

[0012] In some embodiments, where the photomask assembly is used to fabricate resonators of different thicknesses in a filter, the photomask assembly further includes a device photomask for forming the shape and electrical connections of each of the resonators.

[0013] In some embodiments, the photomask assembly is used to fabricate through-silicon via (TSV) connection structures of different depths.

[0014] In a second aspect, embodiments of this disclosure provide a semiconductor manufacturing method applied to the photomask assembly described in the first aspect, the method comprising:

[0015] Provide the material layer to be processed;

[0016] The material layer is patterned using a main photomask and b selected multiplex photomasks to obtain a semiconductor structure containing a first semiconductor unit; b is a positive integer and b is less than or equal to the total number of multiplex photomasks in the photomask set.

[0017] The material layer is subjected to a second patterning process using the same main photomask and b multiplex photomasks to obtain a semiconductor structure containing the first semiconductor unit and the second semiconductor unit; the second patterning process does not change the first semiconductor unit;

[0018] The first semiconductor unit and the second semiconductor unit have different depths or thicknesses.

[0019] In some implementations, the first patterning process of the material layer using a main photomask and a selected b multiplexed photomasks includes:

[0020] A first photoresist layer is deposited on the material layer, and the first photoresist layer is exposed using the main photomask; b second photoresist layers are then deposited, and the first protective layer is obtained after exposure using b multiplex photomasks; wherein, after depositing the i-th second photoresist layer, the second photoresist layer is exposed using the i-th multiplex photomask; i≤b, i is a positive integer;

[0021] The material layer is subjected to morphology control based on the first protective layer, and the first photoresist layer and all second photoresist layers are removed after the morphology control process to obtain a semiconductor structure containing a first semiconductor unit.

[0022] In some implementations, the second patterning process of the material layer using the same master photomask and a selected b multiplex photomasks includes:

[0023] A third photoresist layer is deposited on the semiconductor structure, and the third photoresist layer is exposed using the main photomask; b fourth photoresist layers are then deposited, and a second protective layer is obtained after exposure using b multiplex photomasks; wherein, after depositing the i-th fourth photoresist layer, the fourth photoresist layer is exposed using the i-th multiplex photomask.

[0024] The material layer is subjected to morphology control based on the second protective layer, and the third and fourth photoresist layers are removed after the morphology control process to obtain a semiconductor structure containing the first semiconductor unit and the second semiconductor unit.

[0025] In some implementations, the photoresist layer is a positive photoresist layer or a negative photoresist layer; wherein, the morphology control process includes one or more of the following: etching process, material deposition process, and thinning process.

[0026] Thirdly, embodiments of this disclosure provide an electronic device manufactured using the semiconductor manufacturing method described in the first aspect.

[0027] Fourthly, embodiments of this disclosure provide a filter including a plurality of resonators as described in the third aspect, wherein the plurality of resonators have different thicknesses; the plurality of resonators share a set of photomask assembly, wherein the photomask assembly is as described in the first aspect.

[0028] Fifthly, embodiments of this disclosure provide an electronic device including the filter as described in the fourth aspect.

[0029] This disclosure provides a photomask assembly, a semiconductor manufacturing method, a resonator, a filter, and an apparatus. Since the main photomask in the photomask assembly has at least one pattern group, and a main photomask is used in conjunction with a partially / fully multiplexed photomask, the selected area formed can cover only one pattern group, allowing subsequent fabrication processes to be performed separately for that pattern group. In this way, semiconductor units with different shape parameters can share a single main photomask, eliminating the need for separate photomasks for each type of semiconductor unit, reducing the number of photomasks and lowering costs. Attached Figure Description

[0030] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0031] Figures 1-4 This is a schematic diagram of a photomask assembly provided in an embodiment of this disclosure.

[0032] Figure 5 and Figure 6 This is a schematic diagram of an independent photomask.

[0033] Figure 7 A schematic diagram of the resonator provided in the embodiments of this disclosure;

[0034] Figure 8 A schematic flowchart of a semiconductor device formation method provided in an embodiment of this disclosure;

[0035] Figure 9 and Figure 10 This is a schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure;

[0036] Figure 11 This is a schematic diagram of the structure of a filter provided in an embodiment of the present disclosure.

[0037] Figure 12This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0038] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0039] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0040] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. When a second element, component, region, layer, or portion is discussed, it does not imply that a first element, component, region, layer, or portion necessarily exists in this disclosure.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] The semiconductor devices and their formation methods in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0043] In one embodiment of this disclosure, see Figure 1 This illustrates a schematic diagram of a photomask assembly provided in an embodiment of this disclosure. Figure 1 As shown, the photomask assembly includes at least one main photomask and at least one multiplex photomask; each main photomask includes at least one pattern group, and the number of pattern groups in at least one main photomask is greater than or equal to 2, allowing some main photomasks to have only 1 pattern group; the multiplex photomask includes a light-transmitting area and a non-light-transmitting area.

[0044] It should be noted that, Figure 1 The photomask set includes three main photomasks (main photomask a, main photomask b, and main photomask c) and two multiplexed photomasks (multiplexed photomask d1 and multiplexed photomask e1). Each main photomask contains four pattern groups, and the quantities of all these elements can be varied. The number of patterns in each pattern group is unlimited, and different pattern groups are independent of each other. That is, the number, position, and size of patterns in each pattern group need to be determined based on the actual application scenario.

[0045] In one example, for any master mask, the specific graphic in the graphic group represents the light-transmitting area that allows light to pass through, and the part outside the graphic represents the non-light-transmitting area that does not allow light to pass through.

[0046] In another example, for any master mask, the specific graphic represents the non-transparent area that does not allow light to pass through, and the part outside the graphic represents the transparent area that allows light to pass through.

[0047] In another example, for one part of the main photomask, the specific graphic in the graphic group represents the non-transparent area that does not allow light to pass through, and the part outside the graphic represents the transparent area that allows light to pass through; for another part of the main photomask, the specific graphic in the graphic group represents the transparent area that allows light to pass through, and the part outside the graphic represents the non-transparent area that does not allow light to pass through.

[0048] At the same time, the positions of the non-transparent and transparent areas in the reusable photomask can be interchanged.

[0049] The transparent areas on the photomask allow light to pass through, forming the exposure area on the photoresist; the non-transparent areas block light from passing through, protecting the unexposed areas of the photoresist.

[0050] It should be noted that the selected area is formed by the multiplexed photomask itself or by combining photomasks. The selected area refers to: the overlapping portion between the transparent areas in all or part of the multiplexed photomask; or the overlapping portion between the non-transparent areas in all or part of the multiplexed photomask; or the overlapping portion between the transparent areas in one part of the multiplexed photomask and the non-transparent areas in another part of the multiplexed photomask. For any pattern group in each master photomask, there exists a selected area that covers the pattern group but does not cover other pattern groups in its master photomask.

[0051] Please see Figure 2 The overlapping portion of the light-transmitting area of ​​multiplex mask d1 and the light-transmitting area of ​​multiplex mask e1 forms a selected area 1, which covers pattern group 3 in each master mask but does not cover pattern groups 1, 2 and 4 in each master mask.

[0052] The overlapping portion of the non-transparent area of ​​multiplex mask d1 and the transparent area of ​​multiplex mask e1 forms a selected area 2, which covers pattern group 1 in each master mask but does not cover pattern groups 2, 3 and 4 in each master mask.

[0053] The overlapping portion of the non-transparent area of ​​multiplex mask d1 and the non-transparent area of ​​multiplex mask e1 forms a selected area 3, which covers pattern group 2 in each master mask but does not cover pattern groups 1, 3 and 4 in each master mask;

[0054] The overlapping portion of the light-transmitting area of ​​multiplexed mask d1 and the non-light-transmitting area of ​​multiplexed mask e1 forms a selected area 4. This selected area 4 covers pattern group 4 in each master mask but does not cover pattern groups 1, 2 and 3 in each master mask.

[0055] In some embodiments, the number of multiplexed masks can be further reduced by rotating the multiplexed mask. Figure 1 For example, assuming the multiplexing mask is a regular square, only multiplexing mask d1 is needed. Multiplexing mask d1 can be rotated by 90° to become multiplexing mask e1. Therefore, the aforementioned selected area also includes the multiplexing mask, the multiplexing mask itself after rotation, and the overlapping areas of other multiplexing masks and / or the overlapping parts between non-selected areas.

[0056] Thus, for this mask set, a main mask and some or all of the multiplexed masks are used in combination. By exposing a selected area of ​​a pattern set, subsequent fabrication processes can be performed solely on that pattern set. For example, as Figure 1As shown, using the transparent areas of the main photomask a, the multiplexed photomask d1, and the multiplexed photomask e1, the pattern group 3 in the main photomask a can be fabricated to form a semiconductor unit; using the opaque areas of the main photomask a, the multiplexed photomask d1, and the multiplexed photomask e1, the pattern group 1 in the main photomask a can be fabricated to form a semiconductor unit; using the opaque areas of the main photomask a, the multiplexed photomask d1, and the multiplexed photomask e1, the pattern group 2 in the main photomask a can be fabricated to form a semiconductor unit; using the transparent areas of the main photomask a, the multiplexed photomask d1, and the multiplexed photomask e1, the pattern group 4 in the main photomask a can be fabricated to form a semiconductor unit… In this way, different semiconductor units can share a single main photomask, and the corresponding semiconductor units can be precisely fabricated through the combined use of the main photomask and the multiplexed photomask. Therefore, semiconductor cells with different shape parameters can share a single main photomask, eliminating the need for separate photomasks for each type of semiconductor cell, thus reducing the number of photomasks and lowering costs.

[0057] It should be noted that the light-transmitting area, the non-light-transmitting area, and the selected area are not necessarily regular areas. For example, Figure 1 The multiplexed mask in the mask assembly shown can also be replaced with Figure 3 Multiplexing masks d2 and e2. At this time, the transparent area (or non-transparent area in other examples) in the multiplexing mask includes multiple discrete patterns, and pattern 1 in multiplexing mask d2 covers... Figure 1 Pattern group 3 of each master mask is covered by pattern 2 in mask d2. Figure 1 Each master mask pattern group 4 is covered by pattern 1 in mask e2. Figure 1 Pattern group 2 of each master mask is covered by pattern 2 in mask e2. Figure 1 The graphic group 4 for each main photomask.

[0058] For the main photomask, each specific pattern in the pattern set is used to fabricate a semiconductor cell.

[0059] If the semiconductor unit is a convex structure (e.g., cylindrical), then the semiconductor units corresponding to the patterns in the same pattern group have the same thickness, while the semiconductor units corresponding to the patterns in different pattern groups have different thicknesses.

[0060] If the semiconductor unit is a recessed structure (e.g., a hole), then the semiconductor units corresponding to the patterns in the same pattern group have the same depth, while the semiconductor units corresponding to the patterns in different pattern groups have different depths.

[0061] Thus, for Figure 1 The photomask assembly shown can fabricate 12 types (total number of pattern sets) of semiconductor units with different thicknesses / depths.

[0062] In particular, for Figure 1 The number of pattern groups is the same for different master photomasks, but this is only an example and does not constitute a limitation. The number of pattern groups for different master photomasks is allowed to be different. For example, for a photomask set, which includes 3 master photomasks, the first master photomask includes 3 pattern groups, the second master photomask includes 2 pattern groups, and the third master photomask includes 1 pattern group. In this case, a total of 6 types (total number of pattern groups) of semiconductor cells with different thicknesses / depths can be fabricated.

[0063] In another example, see Figure 4 The photomask assembly includes four main photomasks (main photomask f, main photomask g, main photomask h, and main photomask i) and three multiplexed photomasks (multiplexed photomask j, multiplexed photomask p, and multiplexed photomask q). Main photomask f includes five pattern groups, main photomask g includes five pattern groups, main photomask h includes four pattern groups, and main photomask i includes three pattern groups, enabling the fabrication of 17 different types (total number of pattern groups) of semiconductor cells with varying thicknesses / depths.

[0064] Thus, as Figure 4 As shown, using the transparent areas of the main photomask f, the multiplexed photomask j, and the non-transparent areas of the multiplexed photomask k, the pattern group 1 in the main photomask f can be fabricated to form a semiconductor unit. Using the non-transparent areas of the main photomask f, the multiplexed photomask j, and the multiplexed photomask l, the pattern group 2 in the main photomask f can be fabricated to form a semiconductor unit. Using the transparent areas of the main photomask f, the multiplexed photomask j, and the multiplexed photomask k, the pattern group 3 in the main photomask f can be fabricated to form a semiconductor unit. Using the non-transparent areas of the main photomask f, the multiplexed photomask k, and the transparent areas of the multiplexed photomask l, the pattern group 4 in the main photomask f can be fabricated to form a semiconductor unit. Using the transparent areas of the main photomask f, the multiplexed photomask k, and the multiplexed photomask l, the pattern group 5 in the main photomask f can be fabricated to form a semiconductor unit.

[0065] In particular, for each overall pattern, the mask assembly has multiple possible design options; the patterns of the main mask and the multiplexer mask are not unique. Figure 1 , Figure 4 This is merely an example and does not constitute a fixed limitation.

[0066] In the above embodiments, a main photomask f is paired with two multiplexed photomasks to fabricate the corresponding semiconductor unit, but this is not a limitation. For specific photomask sets and required pattern sets, the main photomask may be paired with different numbers of multiplexed photomasks.

[0067] As mentioned above, the non-transparent and transparent areas in each multiplexed mask are only one example. The positions of the non-transparent and transparent areas in each multiplexed mask can be interchanged, and different multiplexed masks are independent of each other.

[0068] As can be seen from the above, in scenarios involving the fabrication of similar semiconductor units with different shape parameters, the photomask assembly provided in this disclosure can reduce the number of photomasks. The following provides a minimum number of photomasks for a specific scenario. Of course, this is merely a preferred option and not a limitation.

[0069] The photomask set is used to fabricate semiconductor cells of N thicknesses and / or depths, where N is a positive integer greater than or equal to 4; each master photomask includes at most a pattern sets, and the minimum number of reused photomasks is the result of a / 2 rounded up; where a is a positive integer greater than or equal to 2; the minimum number of master photomasks is the result of N / a rounded up.

[0070] Here are a few examples:

[0071] When N is an integer multiple of a:

[0072] (1) Assume N = 12, a = 4, please refer to Figure 1 At this point, the minimum number of primary masks is 3, and the minimum number of reused masks is 2. That is, the mask set must contain at least 5 masks. However, if using individual masks, please refer to [link to relevant documentation]. Figure 5 12 sheets are needed.

[0073] (2) Assuming N = 16 and a = 4, the minimum number of master masks is 4 and the number of multiplexed masks is 2.

[0074] (3) Assuming N = 18 and a = 3, the minimum number of primary photomasks is 6 and the number of multiplexed photomasks is 2.

[0075] (4) Assuming N = 20 and a = 5, the minimum number of primary masks is 4 and the number of multiplexed masks is 3.

[0076] In addition, to achieve the minimum number, when N is an integer multiple of a, all master photomasks include N / a pattern groups.

[0077] When N is not an integer multiple of a:

[0078] (1) Assume N = 17, a = 5, please refer to Figure 4 At this point, the minimum number of primary masks is 4, and the minimum number of reused masks is 3, meaning the mask set must contain at least 7 masks. However, if using individual masks, please refer to [link to relevant documentation]. Figure 6 17 sheets are needed.

[0079] (2) Assuming N = 10 and a = 3, the minimum number of master masks is 4 and the number of multiplexed masks is 2.

[0080] (3) Assuming N = 15 and a = 4, the minimum number of primary photomasks is 4 and the number of multiplexed photomasks is 3.

[0081] (4) Assuming N = 20 and a = 6, the minimum number of primary masks is 4 and the number of multiplexed masks is 3.

[0082] Meanwhile, the number of graphic groups in each master mask can be designed according to requirements. For example, for N=20 and a=6, three master masks can each contain six graphic groups, and one master mask can contain two graphic groups; or, two master masks can each contain six graphic groups, and two master masks can each contain four graphic groups.

[0083] In some embodiments, at most A photoresist layers are present simultaneously during the fabrication of a semiconductor cell, and a main photomask is used to pattern one layer of photoresist; (A-1) multiplexed photomasks are used one-to-one to pattern (A-1) layers of photoresist; A is a positive integer greater than or equal to 2. In simple terms, in the embodiments of this disclosure, the fabrication of each semiconductor cell requires the combined use of a main photomask and some / all multiplexed photomasks.

[0084] It should be noted that photoresist, also known as photoresist, is a special chemical coating that can precisely transfer designed circuit patterns onto a semiconductor substrate through steps such as ultraviolet exposure, development, and etching. It acts as a medium for pattern transfer, ensuring that the tiny patterns and structures on the chip can be manufactured precisely as expected.

[0085] Photoresist can be divided into positive photoresist or negative photoresist. For positive photoresist, the photoresist in the area corresponding to the light-transmitting region of the photomask (exposed area) is dissolved, while the photoresist in the area corresponding to the non-light-transmitting region of the photomask (unexposed area) is retained, and the final semiconductor structure pattern is consistent with the photomask pattern. For negative photoresist, the photoresist in the area corresponding to the light-transmitting region of the photomask (exposed area) is retained, while the photoresist in the area corresponding to the non-light-transmitting region of the photomask (unexposed area) is dissolved, and the final semiconductor structure pattern is opposite to the photomask pattern.

[0086] The rules for choosing the value of A are related to the parity of N, as explained below:

[0087] (1) When N is odd: A is the result of a / 2 rounded up.

[0088] like Figure 4 In the case shown, a = 5, then A = 3. In this case, the main photomask can be used in combination with two multiplexed photomasks to prepare the corresponding semiconductor unit.

[0089] (2) When N is even: A = a / 2 + 1.

[0090] like Figure 1 In the case shown, if a = 4, then A = 3. In this case, the main photomask can be used in combination with a maximum of 2 multiplexed photomasks to prepare the corresponding semiconductor unit.

[0091] In some embodiments, see Figure 1 The main photomask is divided into a first region (a rectangular region in the upper left corner defined by two dashed lines), a second region (a rectangular region in the upper right corner defined by two dashed lines), a third region (a rectangular region in the lower left corner defined by two dashed lines), and a fourth region (a rectangular region in the lower right corner defined by two dashed lines). Each region contains at most one graphic group, and at least one region contains a graphic group.

[0092] The multiplexed photomask is also divided into four regions: the first region, the second region, the third region, and the fourth region.

[0093] For the first multiplexed photomask, the first and second regions as a whole are transparent areas, and the remaining regions are non-transparent areas; or, the first and second regions as a whole are non-transparent areas, and the remaining regions are transparent areas.

[0094] For the second multiplexed photomask, the first and third regions are entirely transparent, while the remaining regions are opaque; or, the second and third regions are entirely opaque, while the remaining regions are transparent.

[0095] It should be understood that the multiplexing mask and the main mask are the same size. Here, the first region of the multiplexing mask is the same size as the first region of the main mask, the second region of the multiplexing mask is the same size as the second region of the main mask, the third region of the multiplexing mask is the same size as the third region of the main mask, and the fourth region of the multiplexing mask is the same size as the fourth region of the main mask.

[0096] In particular, each area is not necessarily regular, and different areas can have different sizes.

[0097] In this embodiment, a photomask assembly is provided. The main photomask in the assembly has at least one pattern group. When the main photomask is used in conjunction with a partial / full multiplexed photomask, the selected area after the multiplexed photomask combination can cover only one pattern group, thereby allowing subsequent fabrication processes to be performed separately for that pattern group. Semiconductor units with different shape parameters can share a single main photomask, eliminating the need for separate photomasks for each type of semiconductor unit, thus reducing the number of photomasks and lowering costs.

[0098] In another embodiment of this disclosure, the aforementioned photomask assembly is used to fabricate resonators of different thicknesses in a filter.

[0099] With the development of communication technology, the requirements for filter components are becoming increasingly stringent. Filters allow signals within a specific frequency range to pass through while suppressing signals of other frequencies. The resonators in a filter produce a strong response at a specific frequency (resonant frequency) to select or generate signals of that specific frequency. Currently, for the filtering requirements of electronic devices, filters may include resonators of various thicknesses, each targeting different resonant frequencies, to achieve multi-band filtering. In addition, multi-thickness resonators offer advantages such as bandwidth control and performance optimization. For filters containing resonators of various thicknesses, the number of masks required in the manufacturing process is also larger, resulting in higher costs.

[0100] Please see Figure 7 An exemplary embodiment provides a schematic diagram of the structure of a resonator 10. For example... Figure 7 As shown, the resonator 10 includes a substrate 101, an acoustic mirror 102, a bottom electrode layer 103, a piezoelectric layer 104, a top electrode layer 105, and a frequency modulation layer or protective layer 106. In the same filter, resonators 10 of various thicknesses may exist. The thicknesses of the acoustic mirror 102, and / or the bottom electrode 103, and / or the piezoelectric layer 104, and / or the top electrode 105 in resonators 10 of different thicknesses are different, thus requiring more photomasks and resulting in higher costs.

[0101] Based on this, the photomask assembly provided in this embodiment is specifically used to form the bottom electrode layer 103 of different resonators; and / or, the photomask assembly is used to form the piezoelectric layer 104 of different resonators; and / or, the photomask assembly is used to form the top electrode layer 105 of different resonators; and / or, the photomask assembly is used to form the acoustic mirror 102 of different resonators.

[0102] In some embodiments, where the photomask assembly is used to fabricate resonators of different thicknesses in the filter, the photomask assembly further includes a device photomask (e.g., a lower electrode photomask or an upper electrode photomask) for forming the shape and electrical connections of each resonator.

[0103] In one example, if resonators of 12 different thicknesses need to be fabricated, 13 individual photomasks (including one device photomask) would be required if individual photomasks are used; however, if the photomask set provided in this disclosure is used, and each main photomask includes 4 pattern groups, 6 photomasks (3 main photomasks + 2 multiplexed photomasks + 1 device photomask) are sufficient. (See also...) Figure 1 .

[0104] In one example, if resonators of 17 different thicknesses need to be fabricated, 18 individual photomasks (including one device photomask) would be required if individual photomasks are used; however, if the photomask set provided in this disclosure is used, and each main photomask includes 5 pattern groups, 8 photomasks (4 main photomasks + 3 multiplexed photomasks + 1 device photomask) are sufficient. (See also...) Figure 4 .

[0105] In summary, assuming that the thickness of the harmonics in each filter has N possible values, where N is a positive integer greater than or equal to 4; each main photomask includes at most a pattern groups; the minimum number of multiplexed photomasks is the result of a / 2 rounded up; where a is a positive integer greater than or equal to 2; the minimum number of main photomasks is the result of N / a rounded up; plus one device photomask, the minimum number of photomasks in the photomask set is: N / a (rounded up) + a / 2 (rounded up) + 1;

[0106] When N is an odd number: the maximum number of photoresist layers that can exist simultaneously is A = a / 2 (rounded up);

[0107] When N is an even number: the maximum number of photoresist layers that can exist simultaneously is A = a / 2 + 1.

[0108] When using this photomask assembly for semiconductor fabrication, each semiconductor unit of thickness is formed by a main photomask plus some / all of the multiplexed photomasks. At the same time, there are multiple photoresist layers. The main photomask is used to pattern one layer of photoresist, and the multiplexed photomasks are used to pattern other photoresist layers. For details, please refer to the subsequent process description.

[0109] Thus, by using the photomask assembly provided in this embodiment to fabricate resonators of different thicknesses, the number of photomasks required is reduced, thereby lowering costs.

[0110] In another embodiment of this disclosure, a photomask assembly is used to fabricate through-silicon via (TSV) interconnect structures of different lengths, i.e., the aforementioned semiconductor unit is a TSV hole.

[0111] It should be noted that TSV is a vertical interconnect structure used in three-dimensional integrated circuits (3D ICs) and advanced packaging technologies. It achieves electrical connections between different chip layers by creating through-holes on a silicon wafer, thereby increasing integration density, shortening interconnect length, reducing power consumption, and improving performance. The length of the TSV (or the depth of the TSV hole) varies depending on the chips to be connected. Therefore, TSVs of different lengths can be fabricated using the aforementioned photomask assembly. For specific implementation methods, please refer to the aforementioned examples, which saves on the number of photomasks and reduces costs.

[0112] In yet another embodiment of this disclosure, please refer to Figure 8 This illustration shows a schematic flowchart of a semiconductor manufacturing method provided in an embodiment of this disclosure. Figure 8 As shown, the manufacturing method includes:

[0113] S31: Provide the material layer to be processed.

[0114] It should be noted that the material layer is located on one side of the substrate layer 101. The substrate layer can be a silicon substrate, germanium substrate, silicon germanide substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc. The specific composition of the material layer is not limited and is determined according to the actual application scenario. Figure 7 The bottom electrode layer 103, the piezoelectric layer 104, the top electrode layer 105, or the protective layer 106 can all be considered as material layers; or, Figure 9 The upper electrode 202 in the middle can also be regarded as a material layer.

[0115] S32: Using a main photomask and b selected multiplex photomasks, the material layer is patterned in the first way to obtain a semiconductor structure containing the first semiconductor unit.

[0116] Where b is a positive integer, and b is less than or equal to the total number of multiplexed masks in the mask set.

[0117] It should be noted that there may be multiple first semiconductor units, depending on the number of patterns in the corresponding pattern group. The photoresist layer can be either positive or negative photoresist, which needs to be determined based on the photomask design.

[0118] S33: The material layer is patterned using the same main photomask and b multiplex photomasks to obtain a semiconductor structure containing a first semiconductor unit and a second semiconductor unit.

[0119] The number of second semiconductor units may be multiple, depending on the number of patterns in the corresponding pattern group.

[0120] Thus, if the first semiconductor unit and the second semiconductor unit are convex structures, then the thickness (or length) of the first semiconductor unit and the second semiconductor unit is different; if the first semiconductor unit and the second semiconductor unit are concave structures, then the depth of the first semiconductor unit and the second semiconductor unit is different.

[0121] Here, the second patterning process does not change the first semiconductor cell; that is, the depth / thickness of the first semiconductor cell remains unchanged in the second patterning process.

[0122] In particular, step S33 is not necessarily a step that immediately follows S32. That is, other fabrication steps, such as fabricating other semiconductor cells, can be performed after step S33 before step S34 occurs.

[0123] In some embodiments, the aforementioned step S32 specifically includes:

[0124] S321: Deposit a first photoresist layer on the material layer and expose the first photoresist layer using the main photomask; continue to deposit b second photoresist layers, and obtain a first protective layer after exposure by b multiplex photomasks; wherein, after depositing the i-th second photoresist layer, expose the second photoresist layer using the i-th multiplex photomask.

[0125] Here, i ≤ b, and i is a positive integer.

[0126] It should be noted that the second photoresist layer is actually composed of multiple photoresist layers, and each time a second photoresist layer is deposited, a multiplexed photomask is used for exposure.

[0127] Please see Figure 9 The diagram shows a first photoresist layer 203, a first second photoresist layer 204, a second second photoresist layer 205, and a first protective layer 206.

[0128] S322: Based on the first protective layer, perform morphology control processing on the material layer, and after the morphology control processing, remove the first photoresist layer and all the second photoresist layers to obtain a semiconductor structure containing the first semiconductor unit.

[0129] Figure 9 The first semiconductor structure is shown.

[0130] In some embodiments, the aforementioned step S33 specifically includes:

[0131] S331: Deposit a third photoresist layer on the semiconductor structure and expose the third photoresist layer using the main photomask; continue to deposit b fourth photoresist layers, and obtain a second protective layer after exposure by b multiplex photomasks; wherein, after depositing the i-th fourth photoresist layer, the i-th multiplex photomask is used to expose the fourth photoresist layer.

[0132] It should be noted that the fourth photoresist layer is actually composed of multiple photoresist layers, and each time a fourth photoresist layer is deposited, a multiplexed photomask is used for exposure.

[0133] Please see Figure 10 The diagram shows a third photoresist layer 207, a first fourth photoresist layer 208, a second fourth photoresist layer 209, and a second protective layer 210.

[0134] S332: Based on the second protective layer, the material layer is subjected to morphology control processing, and after the morphology control processing, the third photoresist layer and the fourth photoresist layer are removed to obtain a semiconductor structure containing the first semiconductor unit and the second semiconductor unit.

[0135] Figure 10 The second semiconductor structure is shown.

[0136] It should be noted that morphology control treatment includes one or more of the following: etching treatment, material deposition treatment, material growth treatment, and thinning treatment. For example, the first morphology control treatment is etching treatment, and the second morphology control treatment is thinning treatment; or, both the first and second morphology control treatments are thinning treatments; or, both the first and second morphology control treatments are material deposition treatments.

[0137] Several specific examples are provided when this semiconductor unit is used to form a resonator.

[0138] In one example, using such Figure 1 The main photomask a, multiplexed photomask d1, and multiplexed photomask e1 shown form a first semiconductor unit and a second semiconductor unit. The interior of the pattern in the main photomask a is a transparent area, and the exterior is a non-transparent area. Please refer to... Figure 9 and Figure 10 The specific steps include:

[0139] S401: The upper electrode 202 is coated with a first photoresist layer 203 (positive photoresist);

[0140] for Figure 10 201 represents the film layer, or can be understood as... Figure 7 The piezoelectric layer in it.

[0141] S402: Expose using the master mask a;

[0142] S403: Deposit the first second photoresist layer 204 (positive photoresist);

[0143] S404: Expose using multiplexed mask d1;

[0144] S405: Deposit the second photoresist layer 205 (positive photoresist);

[0145] S406: Expose using multiplexed photomask e1 to thin the upper electrode 202;

[0146] S407: Remove the first photoresist layer 203, the first second photoresist layer 204 and the second second photoresist layer 205 to complete the first semiconductor unit with a thickness of 1;

[0147] S408: Deposited with a third photoresist layer 207 (positive photoresist);

[0148] S409: Expose using the master mask a;

[0149] S410: Deposit the first fourth photoresist layer 208 (negative photoresist);

[0150] S411: Expose using multiplexed mask d1;

[0151] S412: Deposit the second fourth photoresist layer 209 (positive photoresist);

[0152] s S413: Thinning of the upper electrode 202 after exposure using a multiplexed photomask e1;

[0153] S414: Remove the third photoresist layer 207, the first fourth photoresist layer 208 and the second fourth photoresist layer 209 to complete the second semiconductor unit with a thickness of 2;

[0154] The same multiplexed mask was used in the examples above, but this is not a limitation. See another example. Figure 4 The fabrication process utilizes a master mask f, a multiplexed mask j, a multiplexed mask k, and a multiplexed mask l. The specific steps include:

[0155] S601: Top electrode coating, first photoresist layer (positive photoresist) is deposited;

[0156] S602: Expose using the master mask f;

[0157] S603: Deposit the first second photoresist layer (positive photoresist);

[0158] S604: Exposure using multiplexed mask j;

[0159] S605: Deposit the second photoresist layer (positive photoresist);

[0160] S606: Exposure using a multiplexed mask k;

[0161] S607: The upper electrode is thinned, and in addition to the first photoresist layer and two second photoresist layers, a first semiconductor unit with a thickness of 1 is completed.

[0162] Here, the position of the first semiconductor unit corresponds to pattern group 3 in the main photomask f;

[0163] S608: Deposited with a third photoresist layer (positive photoresist);

[0164] S609: Exposure using the master photomask;

[0165] S610: Deposit the first fourth photoresist layer (positive photoresist);

[0166] S611: Exposure using a multiplexed mask k;

[0167] S612: Deposit the second fourth photoresist layer (positive photoresist);

[0168] S613: Exposure using a multiplexed mask l;

[0169] S614: Thinning process is performed on the upper electrode, and in addition to the third photoresist layer and two fourth photoresist layers, the second semiconductor unit with a thickness of 2 is completed.

[0170] Here, the position of the second semiconductor unit corresponds to the pattern group 5 in the main photomask f.

[0171] Thus, it can be seen from the above that the positive and negative properties of the photoresist layer are the same throughout the overall fabrication process. Combining the above examples, it can be seen that the positive and negative properties of the photoresist layer need to be determined according to the actual application scenario and photomask design. Furthermore, each thickness of semiconductor unit requires one main photomask + one multiplexed photomask + three layers of photoresist to be fabricated.

[0172] This disclosure also provides a resonator 70, fabricated using the aforementioned semiconductor manufacturing method. Specifically, the aforementioned semiconductor manufacturing method is only a part of the resonator's manufacturing process, not all of it.

[0173] This disclosure also provides a filter 80, please refer to [link to relevant documentation]. Figure 11 The filter 80 includes multiple resonators 70, and the multiple resonators 70 have different thicknesses; the multiple resonators 70 share a set of the aforementioned photomask assembly.

[0174] This disclosure also provides an electronic device 90, please refer to... Figure 12 The electronic device 90 includes the aforementioned filter 80. The electronic device 90 may be, but is not limited to, one of the following: a duplexer, a multiplexer, or multiple filters integrated on the same chip / substrate (common-die filter), such as an injection common-mode filter, a common-medium filter, etc.

[0175] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0176] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0177] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A photomask assembly, characterized in that, The photomask assembly includes at least one main photomask and at least one multiplex photomask; Each of the main photomasks includes at least one pattern group, and the number of pattern groups in at least one of the main photomasks is greater than or equal to 2; The multiplexed photomask includes a light-transmitting area and a non-light-transmitting area, and the multiplexed photomask itself or in combination forms a selected area; For any graphic group in each of the main photomasks, there exists a selected area that covers the graphic group but does not cover other graphic groups in the main photomask to which it belongs; The selected area refers to: The overlapping portion between the light-transmitting areas in all or part of the multiplexed photomask; Alternatively, the overlapping portions between the non-transparent areas in the photomask can be reused in whole or in part; Alternatively, the overlapping portion between the light-transmitting area in one part of the multiplexed photomask and the non-light-transmitting area in another part of the multiplexed photomask.

2. The photomask assembly according to claim 1, characterized in that, In any of the main photomasks, each pattern in the pattern group is used to fabricate a semiconductor unit; The semiconductor units corresponding to the patterns in the same pattern group have the same thickness, while the semiconductor units corresponding to the patterns in different pattern groups have different thicknesses. or, The semiconductor cells corresponding to the patterns in the same pattern group have the same depth, while the semiconductor cells corresponding to the patterns in different pattern groups have different depths.

3. The photomask assembly according to claim 1, characterized in that, The photomask assembly is used to fabricate semiconductor cells of N thicknesses and / or depths, where N is a positive integer greater than or equal to 4. Each of the master photomasks includes at most a pattern groups, and the minimum number of multiplexed photomasks is the result of a / 2 rounded up; where a is a positive integer greater than or equal to 2. The minimum number of main photomasks is the result of rounding up N / a.

4. The photomask assembly according to claim 1, characterized in that, During the fabrication of the semiconductor unit, at most A layers of photoresist are present simultaneously, and a main photomask is used to pattern one layer of photoresist; (A-1) multiplexed photomasks are used one-to-one to pattern (A-1) layers of photoresist; A is a positive integer greater than or equal to 2.

5. The photomask assembly according to claim 4, characterized in that, The photomask assembly is used to fabricate semiconductor cells of N thicknesses and / or depths, where N is a positive integer; If N is odd, then A = a / 2 rounded up. If N is even, then A = a / 2 + 1.

6. The photomask assembly according to claim 3, characterized in that, When a = 4 The main photomask is divided into a first region, a second region, a third region, and a fourth region, with at most one of the graphic groups distributed in each region, and at least one of the graphic groups distributed in at least one region. The multiplexed photomask is also divided into the first region, the second region, the third region, and the fourth region; For the first multiplexed photomask, the first region and the second region as a whole are the light-transmitting region, and the remaining regions are the non-light-transmitting region; or, the first region and the second region as a whole are the non-light-transmitting region, and the remaining regions are the light-transmitting region. For the second multiplexed photomask, the second region and the third region together serve as the light-transmitting area, and the remaining regions serve as the non-light-transmitting area; or, the second region and the third region together serve as the non-light-transmitting area, and the remaining regions serve as the light-transmitting area.

7. The photomask assembly according to any one of claims 1-6, characterized in that, The photomask assembly is used to fabricate resonators of different thicknesses in the filter; the photomask assembly is used to form the bottom electrode layer of different resonators; and / or, the photomask assembly is used to form the piezoelectric layer of different resonators; and / or, the photomask assembly is used to form the top electrode layer of different resonators.

8. The photomask assembly according to claim 7, characterized in that, When the photomask assembly is used to fabricate resonators of different thicknesses in a filter, The photomask assembly also includes a device photomask, which is used to form the shape and electrical connection of each of the resonators.

9. The photomask assembly according to any one of claims 1-8, characterized in that, The photomask assembly is used to fabricate silicon via connection structures of different depths.

10. A semiconductor manufacturing method, characterized in that, Applied to the photomask assembly according to any one of claims 1-9, the method comprises: Provide the material layer to be processed; The material layer is patterned using a main photomask and b selected multiplex photomasks to obtain a semiconductor structure containing a first semiconductor unit; b is a positive integer and b is less than or equal to the total number of multiplex photomasks in the photomask set. The material layer is subjected to a second patterning process using the same main photomask and b multiplex photomasks to obtain a semiconductor structure containing the first semiconductor unit and the second semiconductor unit; the second patterning process does not change the first semiconductor unit; The first semiconductor unit and the second semiconductor unit have different depths or thicknesses.

11. The semiconductor manufacturing method according to claim 10, characterized in that, The first patterning process of the material layer using the main photomask and b selected multiplexed photomasks includes: A first photoresist layer is deposited on the material layer, and the first photoresist layer is exposed using the main photomask; b second photoresist layers are then deposited, and the first protective layer is obtained after exposure using b multiplex photomasks; wherein, after depositing the i-th second photoresist layer, the second photoresist layer is exposed using the i-th multiplex photomask; i≤b, i is a positive integer; The material layer is subjected to morphology control based on the first protective layer, and the first photoresist layer and all second photoresist layers are removed after the morphology control process to obtain a semiconductor structure containing a first semiconductor unit.

12. The semiconductor manufacturing method according to claim 11, characterized in that, The second patterning process of the material layer using the same master photomask and b selected multiplex photomasks includes: A third photoresist layer is deposited on the semiconductor structure, and the third photoresist layer is exposed using the main photomask; b fourth photoresist layers are then deposited, and a second protective layer is obtained after exposure using b multiplex photomasks; wherein, after depositing the i-th fourth photoresist layer, the fourth photoresist layer is exposed using the i-th multiplex photomask. The material layer is subjected to morphology control based on the second protective layer, and the third and fourth photoresist layers are removed after the morphology control process to obtain a semiconductor structure containing the first semiconductor unit and the second semiconductor unit.

13. The semiconductor manufacturing method according to claim 12, characterized in that, The photoresist layer is either a positive photoresist layer or a negative photoresist layer; The morphology control process includes one or more of the following: etching, material deposition, and thinning.

14. A resonator, characterized in that, Prepared using the semiconductor manufacturing method as described in any one of claims 10-13.

15. A filter, characterized in that, It includes multiple resonators as described in claim 14, and the multiple resonators have different thicknesses; The plurality of resonators share a set of photomask assembly, and the photomask assembly is as described in any one of claims 1-9.

16. An electronic device, characterized in that, Includes the filter as described in claim 14.

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