Data acquisition control system, method and electronic device
Patent Information
- Application Number
- CN202510436034.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-08
- Publication Date
- 2026-10-16
AI Technical Summary
[0003]相关技术中提供的双冗余度的控制系统,若出现某个控制器故障或者失效的情况,会影响数据链路中数据的分发,从而影响系统的正常运行
[0018] By incorporating integrated circuits (such as FPGAs) into the data acquisition and control system, the integrated circuits can detect whether each controller has failed. When it is determined that one controller (i.e., the first controller) has failed, the integrated circuit can directly send the data acquisition and control information of the second controller to the data acquisition unit without re-initializing the data acquisition unit. This enables the control link of data acquisition to automatically and seamlessly switch to another controller when one controller in the dual-redundancy control system fails, ensuring that the data transmission of the data link is not affected.
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Figure CN122923601A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of intelligent device control, and more specifically, to a data acquisition and control system, method, and electronic device. Background Technology
[0002] In intelligent sensing devices (such as drones, robots, and smart cars), data acquisition is typically based on sensing sensors. For example, binocular cameras are used as sensing sensors to acquire depth images and other information, and the binocular cameras are required to synchronously trigger the acquisition of image data. In some applications with high robustness requirements, the device control system adopts a dual-redundancy backup design, which requires distributing data from two cameras simultaneously to two controllers. This achieves the goal of simultaneous reception of binocular camera data in both control systems, serving as a backup for each other. This presents challenges for the design of the circuit links.
[0003] In the dual-redundancy control system provided in related technologies, if a controller fails or malfunctions, it will affect the distribution of data in the data link, thereby affecting the normal operation of the system. Summary of the Invention
[0004] The purpose of this disclosure is to provide a data acquisition and control system, method, and electronic device.
[0005] To achieve the above objectives, this disclosure provides a data acquisition and control system, the system comprising: a first controller, a second controller, an integrated circuit, and a data acquisition unit; the integrated circuit is configured to send data acquisition control information sent by the first controller to the data acquisition unit, and, in the event of a failure of the first controller, send the data acquisition control information sent by the second controller to the data acquisition unit, so that the data acquisition unit performs data acquisition according to the data acquisition control information.
[0006] Optionally, the integrated circuit is configured to receive status data sent by the first controller and determine whether the first controller has failed based on the status data; and / or to receive status data sent by the second controller and determine whether the second controller has failed based on the status data.
[0007] Optionally, the first controller and the second controller are respectively connected to the data acquisition unit; The data acquisition unit is used to acquire data according to the data acquisition control information, and then send the acquired target data to the first controller and the second controller respectively.
[0008] Optionally, the integrated circuit is further configured to receive the data acquisition control information sent by the first controller and the second controller respectively.
[0009] Optionally, the system includes multiple data acquisition units, and the integrated circuit is further configured to send a specified control signal to each of the multiple data acquisition units according to the timing requirements of the multiple data acquisition units, wherein the specified control signal includes at least one of the following: Power control signal, reset signal, and synchronous trigger signal.
[0010] Optionally, the system further includes a signal enhancement device, through which the data acquisition unit is connected to the first controller and the second controller respectively; The signal enhancement device is used to enhance the signal quality of the target data signal output by the data acquisition unit, and send the enhanced target data signal to the first controller and the second controller. The target data signal is the signal corresponding to the target data acquired by the data acquisition unit.
[0011] Optionally, the integrated circuit includes a field-programmable gate array (FPGA).
[0012] Optionally, the data acquisition unit includes a binocular camera.
[0013] To achieve the above objectives, this disclosure provides a data acquisition method applied to a data acquisition control system, the system comprising: a first controller, a second controller, an integrated circuit, and a data acquisition unit; the method comprising: The integrated circuit transmits the data acquisition control information sent by the first controller to the data acquisition unit. In the event of a failure of the first controller, the integrated circuit transmits the data acquisition control information sent by the second controller to the data acquisition unit, so that the data acquisition unit performs data acquisition according to the data acquisition control information.
[0014] To achieve the above objectives, this disclosure provides an electronic device, including the data acquisition and control system described above.
[0015] Optionally, the electronic device may include a drone, a robot, or a vehicle.
[0016] To achieve the above objectives, this disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the data acquisition method described above.
[0017] To achieve the above objectives, this disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the data acquisition method described above.
[0018] By incorporating integrated circuits (such as FPGAs) into the data acquisition and control system, the integrated circuits can detect whether each controller has failed. When it is determined that one controller (i.e., the first controller) has failed, the integrated circuit can directly send the data acquisition and control information of the second controller to the data acquisition unit without re-initializing the data acquisition unit. This enables the control link of data acquisition to automatically and seamlessly switch to another controller when one controller in the dual-redundancy control system fails, ensuring that the data transmission of the data link is not affected.
[0019] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description
[0020] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a structural block diagram of a data acquisition and control system according to an exemplary embodiment.
[0021] Figure 2 It is based on Figure 1 The illustrated embodiment presents a structural block diagram of another data acquisition and control system.
[0022] Figure 3 It is based on Figure 1 The illustrated embodiment presents a structural block diagram of another data acquisition and control system.
[0023] Figure 4 This is a schematic diagram of the structure of a data acquisition and control system according to an exemplary embodiment.
[0024] Figure 5 This is a flowchart illustrating a data acquisition method according to an exemplary embodiment.
[0025] Figure 6 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation
[0026] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.
[0027] It should be noted that all actions involving the acquisition of signals, information, or data in this disclosure are carried out in compliance with the relevant data protection laws and policies of the country where the location is situated, and with authorization from the owner of the relevant device.
[0028] This disclosure is primarily applied to scenarios where intelligent sensing devices use a dual-redundancy control system for data acquisition. This dual-redundancy control system comprises two controllers. For example, devices such as drones and robots require the use of binocular cameras as sensing sensors to acquire depth images and other information, and the binocular cameras must be triggered synchronously to acquire image data. Data from both cameras needs to be simultaneously distributed to both controllers, achieving the goal of simultaneous reception and mutual backup of binocular camera data in both control systems.
[0029] In the dual-redundancy controller system provided by related technologies, when one controller fails, the other controller reinitializes the binocular camera, preventing seamless switching of the control link and affecting data distribution. Another related technology uses a SERDES scheme to serialize and then deserialize the data. However, the deserialization IC needs to support four MIPI data outputs, resulting in a high cost.
[0030] To address the aforementioned problems, this disclosure provides a data acquisition and control system, method, and electronic device. The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.
[0031] Figure 1 This is a structural block diagram of a data acquisition and control system according to an exemplary embodiment, such as... Figure 1 As shown, the system includes: The system comprises a first controller 101, a second controller 102, an integrated circuit 103, and a data acquisition unit 104; wherein the first controller 101, the second controller 102, and the data acquisition unit 104 are communicatively connected to the integrated circuit 103. In other words, the data acquisition and control system includes two controllers, making it a dual-redundancy control system. Furthermore, the data acquisition unit 104 may include one or more... Figure 1 Two of these data acquisition units 104 are shown as an example.
[0032] The integrated circuit 103 is used to send the data acquisition control information sent by the first controller 101 to each data acquisition unit 104, and when the failure of the first controller 101 is detected, to send the data acquisition control information sent by the second controller 102 to each data acquisition unit 104, so that the data acquisition unit 104 can perform data acquisition according to the data acquisition control information.
[0033] In one embodiment, the first controller 101 may include either of the two controllers in the control system. In another embodiment, the first controller 101 may include the controller with a higher preset control priority. For example, the first controller 101 may be a master controller with a higher preset control priority, and the second controller 102 may be an auxiliary controller with a lower preset control priority. In other words, the second controller 102 is the other controller that is different from the first controller 101. Furthermore, both the first controller 101 and the second controller 102 may include a System on Chip (SOC) controller.
[0034] Additionally, the integrated circuit 103 may include, for example, an FPGA (Field Programmable Gate Array). The data acquisition unit 104 may include a data acquisition sensor, for example, a binocular camera.
[0035] For example, in intelligent sensing devices such as drones and robots, binocular cameras can be used to simultaneously trigger the acquisition of depth image data. Furthermore, the depth image data acquired by the two cameras can be simultaneously distributed to two controllers, achieving the goal of simultaneous reception and mutual backup of binocular camera data in both controllers.
[0036] The data acquisition and control system disclosed herein may include a control link and a data link. The control link refers to the link through which the controller sends data acquisition control information to the data acquisition unit 104 to control the data acquisition unit 104 to perform data acquisition. The data link refers to the data transmission link through which the data acquisition unit 104 sends the acquired data to each controller.
[0037] The data acquisition control information may include sequence control information. During data acquisition, each controller can send the sequence control information to each data acquisition unit 104 via a control link (CFG), so that the data acquisition unit 104 can perform data acquisition according to the data acquisition control information.
[0038] Taking the data acquisition unit 104 as a camera as an example, the sequence control information may include initialization information (such as camera resolution settings, frame rate settings, etc.), sensor configuration parameters (such as exposure time, sensitivity settings, white balance settings, and image format settings, etc.), data output format settings, and data transmission control parameters, etc.
[0039] In this disclosure, an integrated circuit 103 is added to the data acquisition and control system. The first controller 101 and the second controller 102 can send their data acquisition control information to the integrated circuit 103 in the control link, respectively. In this way, the integrated circuit 103 can receive the data acquisition control information sent by the first controller 101 and the second controller 102, respectively. Then, the integrated circuit 103 can send the data acquisition control information sent by the first controller 101 to each data acquisition unit 104 according to a priority strategy or a random selection strategy.
[0040] Optionally, Figure 2 It is based on Figure 1 The illustrated embodiment shows another data acquisition and control system structural block diagram, as follows: Figure 2 As shown, the first controller 101 and the second controller 102 are respectively connected to the data acquisition unit 104. Thus, for each data acquisition unit 104, after acquiring data according to the data acquisition control information, the data acquisition unit 104 can send the acquired target data to the first controller 101 and the second controller 102 respectively, thereby backing up and storing the target data in the first controller 101 and the second controller 102. The target data may, for example, include MIPI data acquired by a binocular camera.
[0041] However, if the first controller 101 fails, the integrated circuit 103 will be unable to obtain the data acquisition control information from the first controller 101, which will inevitably affect the data acquisition process of the data acquisition unit 104, and thus affect the data distribution of the data link. To ensure that the subsequent data distribution of the data link is not affected when the first controller 101 fails, this disclosure can, based on the detection of the first controller 101 failure by the integrated circuit 103, send the data acquisition control information sent by the second controller 102 to each data acquisition unit 104, thereby achieving automatic switching of the control link of the data acquisition unit 104 between the two controllers. Since the delay of this switching process is typically in the nanosecond range, this delay is negligible, thus enabling the control link of the data acquisition unit to automatically and seamlessly switch to the second controller when the first controller fails, thereby ensuring that the target data distribution of the data link is not affected.
[0042] In one possible implementation of this disclosure, the integrated circuit 103 can receive status data sent by the first controller 101 and determine whether the first controller 101 has failed based on the status data sent by the first controller 101; and / or, receive status data sent by the second controller 102 and determine whether the second controller 102 has failed based on the status data sent by the second controller 102.
[0043] This status data could be, for example, heartbeat data.
[0044] For example, the integrated circuit 103 can receive heartbeat data from the first controller 101. If the first controller 101 is found to have lost its heartbeat, it indicates that the first controller 101 has failed. The integrated circuit 103 can also receive heartbeat data from the second controller 102. If the second controller 102 is found to have lost its heartbeat, it indicates that the second controller 102 has failed.
[0045] It is understood that, in the event that the second controller 102 is detected to be malfunctioning, this disclosure may send the data acquisition control information sent by the first controller 101 to the data acquisition unit 104, so that the data acquisition unit 104 may perform data acquisition according to the data acquisition control information.
[0046] In another possible embodiment of this disclosure, the data acquisition and control system may include a plurality of data acquisition units 104. The integrated circuit 103 may also be used to send a specified control signal to each data acquisition unit 104 according to the timing requirements of the plurality of data acquisition units 104. The specified control signal includes at least one of the following: a power control signal, a reset signal, and a synchronization trigger signal.
[0047] In one implementation, the specified control signal can be pre-written into the integrated circuit 103 based on the timing requirements of each data acquisition unit 104. In this way, during the data acquisition process, the integrated circuit 103 can output the power control signal, reset signal and synchronous trigger signal according to the timing required by the data acquisition unit 104.
[0048] Figure 3 It is based on Figure 1 The illustrated embodiment shows a structural block diagram of another data acquisition and control system, as follows: Figure 3 As shown, the system also includes a signal enhancement device 105, so that the data acquisition unit 104 can be connected to the first controller 101 and the second controller 102 respectively through the signal enhancement device 105. The signal enhancement device 105 can be used to enhance the signal quality of the target data signal output by the data acquisition unit 104, and send the enhanced target data signal to the first controller 101 and the second controller 102. The target data signal is the signal corresponding to the target data acquired by the data acquisition unit 104.
[0049] The signal enhancement device 105 may include, for example, a redriver signal enhancement device or a Retimer IC signal enhancement device.
[0050] In practical applications, since the target data acquired by the data acquisition unit 104 is directly distributed to two controllers at the same time, there will be signal quality problems. Therefore, this disclosure can add the signal enhancement device 105 to the data acquisition and control system. The signal enhancement device 105 can perform signal quality compensation (or "signal quality enhancement") on the target data signal output by the data acquisition unit 104.
[0051] Furthermore, each data acquisition unit 104 can be connected to one or more signal enhancement devices 105. For example, considering that the target data acquired by each data acquisition unit 104 needs to be distributed to two controllers for storage, this disclosure can connect two signal enhancement devices 105 to each data acquisition unit 104. In this way, the target data signal (carrying the target data) output by the data acquisition unit 104 can be enhanced in parallel by the two signal enhancement devices 105 and then sent to the respective connected controllers. Therefore, the signal enhancement device 105 can also serve as an isolation device between the first controller 101 and the second controller 102.
[0052] For example, Figure 4 This is a schematic diagram illustrating the structure of a data acquisition and control system according to an exemplary embodiment, such as... Figure 4 As shown, the integrated circuit 103 is an FPGA, the data acquisition unit 104 includes a left camera and a right camera, the first controller 101 is a SOC1, the second controller 102 is a SOC2, the signal enhancement device 105 is a redriver signal enhancement device, and each camera is connected to two redriver signal enhancement devices. CFG in the figure represents the control link.
[0053] like Figure 4As shown, the SOC1 and SOC2 controllers simultaneously transmit their sequence control information to the FPGA via the CFG control link. According to a priority strategy, the FPGA first copies the sequence control information from SOC1 into two identical sequence information streams, forwarding them to the left and right cameras of the dual-lens system respectively. In addition to distributing the sequence information from the SOC controllers, the FPGA also outputs sensor power control, reset, and synchronization trigger signals according to the timing requirements of the dual-lens cameras. The FPGA can also simultaneously receive heartbeat data from both SOC1 and SOC2. If SOC1 loses its heartbeat, indicating SOC1 failure (the FPGA will be unable to obtain normal sequence control information from SOC1), the FPGA automatically switches to obtaining sequence control information from SOC2 as the input source for sequence control and forwards the sequence control information obtained from SOC2 to the left and right cameras of the dual-lens system according to the original path. The dual-lens data link (MIPI data) remains unaffected. Similarly, if the first controller is SOC2, when the FPGA detects that SOC2 has lost its heartbeat, it indicates that SOC2 has failed (the FPGA will not be able to obtain normal sequence control information from SOC2). The FPGA automatically switches to obtaining sequence control information from SOC1 as the input source for sequence control, and forwards the sequence control information obtained from SOC1 to the left and right cameras of the dual-view camera according to the original path. The dual-view data link (MIPI data) is not affected.
[0054] For the data link used to transmit MIPI data: When the binoculars can output MIPI image data normally, directly distributing MIPI data to both SOCs simultaneously would cause signal quality issues. Therefore, a redriver signal enhancement device is added to compensate for signal quality and to isolate SOC1 and SOC2. Specifically, the left and right cameras of the binoculars each use two separate redriver signal enhancement devices to transmit MIPI data to SOC1 and SOC2. SOC1 and SOC2 can simultaneously receive data from the binocular cameras, and the latency during sequence switching (typically in the nanosecond range) is negligible. This allows the control link of the binocular cameras to automatically and seamlessly switch to another controller, ensuring that the MIPI data distribution of the camera data link is unaffected.
[0055] The above examples are merely illustrative and are not intended to limit the scope of this disclosure.
[0056] By incorporating an integrated circuit (such as an FPGA) into the data acquisition and control system, the integrated circuit can detect whether each controller has failed. When it is determined that one of the controllers (i.e., the first controller) has failed, the integrated circuit can directly send the data acquisition and control information of the second controller to the data acquisition unit without re-initializing the data acquisition unit. This enables the control link of data acquisition to automatically and seamlessly switch to another controller when one controller in the dual redundancy control system fails, ensuring that the data transmission of the data link is not affected.
[0057] Furthermore, this disclosure offers lower costs compared to the SERDES solution. It also utilizes an FPGA chip as the integrated circuit, allowing for flexible design, functional scalability, and easy upgrades and maintenance.
[0058] Figure 5 This is a flowchart illustrating a data acquisition method according to an exemplary embodiment, which can be applied to, for example... Figure 1 The data acquisition and control system shown includes: a first controller, a second controller, an integrated circuit, and a data acquisition unit; wherein the first controller, the second controller, and the data acquisition unit are each communicatively connected to the integrated circuit.
[0059] like Figure 5 As shown, the method includes the following steps: In step S501, the data acquisition control information sent by the first controller is sent to the data acquisition unit through the integrated circuit, and if the failure of the first controller is detected, the data acquisition control information sent by the second controller is sent to the data acquisition unit so that the data acquisition unit can perform data acquisition according to the data acquisition control information.
[0060] Optionally, the integrated circuit receives status data sent by the first controller and determines whether the first controller has failed based on the status data; and / or receives status data sent by the second controller and determines whether the second controller has failed based on the status data.
[0061] Optionally, the first controller and the second controller are respectively connected to the data acquisition unit; in this way, the data acquisition unit can acquire data according to the data acquisition control information and then send the acquired target data to the first controller and the second controller respectively.
[0062] Optionally, the integrated circuit can also receive data acquisition and control information sent by the first controller and the second controller respectively.
[0063] Optionally, the data acquisition and control system includes multiple data acquisition units, and the integrated circuit can also send a specified control signal to each data acquisition unit according to the timing requirements of the multiple data acquisition units. The specified control signal includes at least one of the following: a power control signal, a reset signal, and a synchronization trigger signal.
[0064] Optionally, the data acquisition and control system may further include a signal enhancement device, through which the data acquisition unit is connected to the first controller and the second controller respectively; thus, the signal enhancement device can be used to enhance the signal quality of the target data signal output by the data acquisition unit, and send the enhanced target data signal to the first controller and the second controller, wherein the target data signal is the signal corresponding to the target data acquired by the data acquisition unit.
[0065] Optionally, the integrated circuit includes a field-programmable gate array (FPGA).
[0066] Optionally, the data acquisition unit includes a binocular camera.
[0067] Regarding the methods in the above embodiments, the specific ways in which each part performs the operation have been described in detail in the embodiments of the relevant system, and will not be elaborated here.
[0068] Figure 6 This is a block diagram illustrating an electronic device according to an exemplary embodiment. The electronic device may include a drone, a robot, or a vehicle. Figure 6 As shown, the electronic device 600 may include a processor 601 and a memory 602. The electronic device 600 may also include one or more of a multimedia component 603, an input / output (I / O) interface 604, and a communication component 605.
[0069] The processor 601 controls the overall operation of the electronic device 600 to complete all or part of the steps in the data acquisition method described above. The memory 602 stores various types of data to support the operation of the electronic device 600. This data may include, for example, instructions for any application or method operating on the electronic device 600, and application-related data such as contact data, sent and received messages, pictures, audio, video, etc. The memory 602 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The multimedia component 603 may include a screen and audio components. The screen may be, for example, a touchscreen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in memory 602 or transmitted via communication component 605. The audio component also includes at least one speaker for outputting audio signals. I / O interface 604 provides an interface between processor 601 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual or physical buttons. Communication component 605 is used for wired or wireless communication between the electronic device 600 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, 4G, NB-IoT, eMTC, or other 5G technologies, or combinations thereof, is not limited here. Therefore, the corresponding communication component 605 may include: a Wi-Fi module, a Bluetooth module, an NFC module, etc.
[0070] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the data acquisition method described above.
[0071] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided, which, when executed by a processor, implement the steps of the data acquisition method described above. For example, the computer-readable storage medium may be the memory 602 including program instructions described above, which may be executed by the processor 601 of the electronic device 600 to complete the data acquisition method described above.
[0072] In another exemplary embodiment, a computer program product is also provided, which includes a computer program executable by a programmable device, the computer program having a code portion for performing the data acquisition method described above when executed by the programmable device.
[0073] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.
[0074] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.
[0075] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.
Claims
1. A data acquisition and control system, characterized in that, The system includes: a first controller, a second controller, an integrated circuit, and a data acquisition unit; the integrated circuit is used to send data acquisition control information sent by the first controller to the data acquisition unit, and, in the event of a failure of the first controller, send the data acquisition control information sent by the second controller to the data acquisition unit, so that the data acquisition unit performs data acquisition according to the data acquisition control information.
2. The system according to claim 1, characterized in that, The integrated circuit is configured to receive status data sent by the first controller and determine whether the first controller has failed based on the status data; and / or to receive status data sent by the second controller and determine whether the second controller has failed based on the status data.
3. The system according to claim 1, characterized in that, The first controller and the second controller are respectively connected to the data acquisition unit; The data acquisition unit is used to acquire data according to the data acquisition control information, and then send the acquired target data to the first controller and the second controller respectively.
4. The system according to claim 1, characterized in that, The integrated circuit is also used to receive the data acquisition control information sent by the first controller and the second controller respectively.
5. The system according to claim 1, characterized in that, The system includes multiple data acquisition units. The integrated circuit is further configured to send a specified control signal to each of the multiple data acquisition units according to the timing requirements of the multiple data acquisition units. The specified control signal includes at least one of the following: Power control signal, reset signal, and synchronous trigger signal.
6. The system according to claim 1, characterized in that, The system also includes a signal enhancement device, and the data acquisition unit is connected to the first controller and the second controller respectively through the signal enhancement device; The signal enhancement device is used to enhance the signal quality of the target data signal output by the data acquisition unit, and send the enhanced target data signal to the first controller and the second controller. The target data signal is the signal corresponding to the target data acquired by the data acquisition unit.
7. The system according to any one of claims 1-6, characterized in that, The integrated circuit includes a field-programmable gate array (FPGA).
8. The system according to any one of claims 1-6, characterized in that, The data acquisition unit includes a binocular camera.
9. A data acquisition method, characterized in that, An application is made in a data acquisition and control system, the system comprising: a first controller, a second controller, an integrated circuit, and a data acquisition unit; the method comprising: The integrated circuit transmits the data acquisition control information sent by the first controller to the data acquisition unit. In the event of a failure of the first controller, the integrated circuit transmits the data acquisition control information sent by the second controller to the data acquisition unit, so that the data acquisition unit performs data acquisition according to the data acquisition control information.
10. An electronic device, characterized in that, The data acquisition and control system includes any one of claims 1-8, wherein the electronic device includes a drone, a robot, or a vehicle.