Sem imaging multi-channel data real-time transmission system and method

Abstract

The application discloses a SEM imaging multi-channel data real-time transmission system and method, and belongs to the technical field of semiconductor detection equipment. The system comprises an FPGA master control board, which is used for collecting multi-channel SEM image data and packaging the data into a data stream containing channel numbers; and a PCIE transmission card, which is integrated with a data receiving and analyzing module, a double-queue FIFO cache module and a multi-channel DMA engine module. The analyzing module separates control information and payload data, and the double-queue FIFO respectively caches. The DMA engine carries data in parallel to the corresponding storage space of the host computer according to the channel number, and constitutes a three-stage pipeline architecture. Through the FPGA hardware pipeline architecture and the multi-channel independent DMA parallel transmission mechanism, the application solves the problems of high CPU occupation, data channel congestion and image display residual image in the existing gigabit network transmission, achieves stable, accurate and low-delay real-time transmission of multi-channel high-throughput data, and significantly improves the imaging efficiency and stability of the electron beam detection equipment.

Description

Technical Field

[0001] This invention relates to a real-time data transmission system and method for multi-channel SEM imaging, belonging to the field of semiconductor testing equipment technology. Background Technology

[0002] In the semiconductor manufacturing field, electron beam inspection equipment (such as scanning electron microscopes, SEM) is a core tool for wafer defect detection and critical dimension measurement. When scanning wafers or other samples, the equipment needs to acquire and display high-resolution topographic features of the target object in real time. With the continuous miniaturization of semiconductor process nodes, the requirements for detection resolution and field of view are increasing, leading to a geometrical increase in the amount of data generated per scan. Currently, the lower-level computer typically transmits the acquired image data directly to the upper-level computer via fiber optic cable using communication protocols such as 10 Gigabit Ethernet for display and processing. This transmission method based on a common network protocol is widely used for typical data volumes.

[0003] However, with the increase in the number of detector channels and the frequent switching of field of view and resolution, existing technologies have gradually revealed serious performance bottlenecks. 10 Gigabit Ethernet transmission relies on a complex data queue arbitration mechanism. In high-throughput scenarios, redundant arbitration mechanisms can lead to data channel congestion, making it impossible to guarantee parallel and real-time transmission of multi-channel data. Simultaneously, due to the processing overhead of the network protocol stack, the host computer CPU needs to consume significant resources for packet parsing and reassembly, resulting in excessive CPU utilization and affecting the overall real-time response capability of the system. Under high load, data transmission latency and jitter can also cause phenomena such as "frame errors," "slow image display," or image "ghosting" during image display on the host computer, severely impacting the accuracy and efficiency of detection. Therefore, how to achieve stable, accurate, and low-latency real-time transmission of multi-channel, high-throughput data has become a key technical challenge restricting the product deployment and performance improvement of electron beam metrology equipment. Summary of the Invention

[0004] To achieve stable, accurate, and low-latency real-time transmission of multi-channel, high-throughput data, and to improve the accuracy and efficiency of detection, this invention provides a real-time transmission system and method for multi-channel SEM imaging data. The technical solution is as follows: In a first aspect, the present invention provides a real-time data transmission system for multi-channel SEM imaging, comprising: The main control board, based on FPGA design, is used to acquire SEM image data from multiple detector channels and encapsulate the image data into a data stream containing channel numbers for transmission. The PCIe transmission card, based on FPGA design, is used to receive the data stream and transmit data with the host computer through the PCIe interface. The PCIe transmission card integrates a data receiving and parsing module, a dual-queue FIFO buffer module, and a multi-channel DMA engine module. The data receiving and parsing module is used to parse the data stream and separate channel control information and image payload data. The dual-queue FIFO buffer module includes a parallel image channel FIFO and an image payload FIFO. The image channel FIFO is used to buffer the channel control information, and the image payload FIFO is used to buffer the image payload data. The multi-channel DMA engine module is used to transfer the image payload data in parallel to the target storage space in the host computer memory corresponding to the channel number in the channel control information. The data receiving and parsing module, the dual-queue FIFO buffer module, and the multi-channel DMA engine module constitute a three-level pipeline architecture with deep decoupling between each level.

[0005] Optionally, during driver initialization, the host computer allocates M*N independent memory buffers for the N detector channels, where each detector channel has its own M memory buffers. The multi-channel DMA engine module calculates the address offset ADDR based on the real-time line number LINE_NUM of the image. OFFSET And according to the target address ADDR TARGET =ADDR BASE +ADDR OFFSET Write the image data to the corresponding memory buffer, where ADDR BASE Map the base address of the memory space for the current frame.

[0006] Optionally, the PCIe transmission card also integrates an interrupt management module, used to send an interrupt signal to the host computer when at least one of the following events occurs: (1) Frame header information was detected; (2) A memory buffer is filled with image data; (3) All channels of a frame of image have been transmitted. (4) Image transmission timeout or data error was detected.

[0007] Optionally, the PCIE transmission card also integrates an automatic error detection and clearing module for real-time monitoring of image data errors and image transmission timeouts; when an abnormality is detected, the interrupt management module notifies the host computer to discard the current frame data and reset in preparation for receiving the next frame of image data.

[0008] Optionally, the PCIe transmission card also integrates a PCIe TLP packet transmission module, which is used to package the data to be transmitted into PCIe transaction layer packets; wherein, the maximum effective payload of the PCIe transaction layer packet is set to the maximum value, and the internal data transmission is optimized to a back-to-back transmission mode.

[0009] Optionally, the channel control information includes the channel number CHANNEL_ID and the full channel transmission end flag ALL_CHANNEL_OVER.

[0010] Optionally, the PCIe transmission card is interconnected with the main control board via optical fiber and communicates using the AURORA interface protocol.

[0011] Optionally, the multi-channel DMA engine module also includes a state machine, which is used to schedule the target buffer for the next DMA transfer based on the transmission completion signal and bus occupancy status of each channel, ensuring that two buffers of any channel are not in a write state at the same time.

[0012] Secondly, the present invention provides a method for real-time transmission of multi-channel data in SEM imaging, applied to the system described in any of the preceding claims, the method comprising the following steps: The main control board acquires SEM image data from N detector channels and encapsulates it into a data stream containing the channel number CHANNEL_ID; The PCIE transmission card receives the data stream and separates the channel control information and image payload data through the data receiving and parsing module. The channel control information and image payload data are cached in the image channel FIFO and image payload FIFO, respectively. The multi-channel DMA engine module moves the image payload data in parallel to the target storage space in the host computer memory corresponding to the channel number CHANNEL_ID, according to the channel number CHANNEL_ID.

[0013] Optionally, the method further includes: During the initialization of the host computer driver, M*N independent memory buffers are allocated for N detector channels, with each detector channel having its own M memory buffers. The multi-channel DMA engine module calculates the address offset ADDR based on the real-time line number LINE_NUM of the image. OFFSET And according to the target address ADDR TARGET =ADDR BASE +ADDR OFFSET Write the image data to the corresponding memory buffer, where ADDR BASE Map the base address of the memory space for the current frame.

[0014] The beneficial effects of this invention are: This invention employs a three-stage pipeline architecture consisting of a data receiving and parsing module, a dual-queue FIFO buffer module, and a multi-channel DMA engine module. It utilizes a dual-queue FIFO to decouple the control flow from the data flow, minimizing transmission latency for image channel data and image payloads while maximizing data transmission bandwidth. This enables full-load pipeline transmission of images at any resolution and bandwidth, solving the data channel congestion problem caused by redundant queue arbitration mechanisms in existing 10 Gigabit Ethernet transmissions. This improves system throughput and reduces processing latency. Furthermore, the multi-channel DMA engine module moves image payload data in parallel to the corresponding target storage space based on the channel number (CHANNEL_ID), mitigating the risk of SEM image "ghosting" that may exist in traditional memory ping-pong operations. This achieves parallel memory movement of multi-channel image data and adaptive adaptation to resolution changes.

[0015] This invention solves the problem of excessive CPU usage of the host computer in the prior art by deeply decoupling the levels in the three-level pipeline architecture, allowing each level to run synchronously at different rates. It achieves full-bandwidth pipeline transmission at any resolution, reduces CPU overhead, and improves the overall real-time response capability of the system.

[0016] In one embodiment of the present invention, M*N independent memory buffers are allocated for N detector channels, and an address offset calculation and writing mechanism based on the real-time image line number LINE_NUM is adopted. This solves the read-write conflict and data overwriting problems caused by the sharing of memory resources for multi-channel data in the prior art, and achieves independent and orderly storage of multi-channel data, improving the stability of data transmission. In addition, the flexible memory space allocation simplifies the complexity of memory management and the ease of logic implementation.

[0017] In one embodiment of the present invention, by introducing an interrupt management module, interrupt signals are sent to the host computer at key nodes such as frame header detection, buffer filling, completion of whole frame transmission, and anomaly detection. This enables the host computer to accurately synchronize and control the transmission progress in real time, reduces CPU load, and ensures immediate response in the event of timeout or error, thereby improving the overall operating efficiency and reliability of the system.

[0018] In one embodiment of the present invention, the fault tolerance of the transmission system is improved and the robustness of the whole system is enhanced by introducing an automatic error detection and clearing module.

[0019] In one embodiment of the present invention, a state machine can be introduced to ensure the consistency of data transmitted concurrently through multiple channels and the stability of the system through the fine-grained control of the state machine. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a structural diagram of the SEM imaging multi-channel real-time data transmission system of the present invention.

[0022] Figure 2 This is a structural diagram of the multi-channel DMA engine module of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0024] Example 1: This embodiment provides a real-time multi-channel high-throughput data transmission system for SEM imaging. The system mainly consists of a main control board (CU) based on an FPGA design and a host computer PCIe transmission card based on an FPGA design. The main control board, acting as the acquisition and transmission end for raw image data, can organize N detector channels into data queues using channel numbers (CHANNEL_ID) and send them to the PCIe transmission card via a high-speed SERDES interface. The PCIe transmission card, acting as a data transmission middleware, is responsible for receiving data from the main control board and performing DMA data transfer with the host computer via the PCIe interface. When the host computer loads the driver, it reads the configuration information of the PCIe transmission card's BAR0 space and establishes a DMA memory address mapping relationship. The host computer is responsible for memory allocation, data reading, parsing, and display. The main control board and the PCIe transmission card are interconnected via optical fiber and use the AURORA interface protocol for high-speed communication.

[0025] In this embodiment, the host computer is deployed with a data receiving and parsing module, a dual-queue FIFO buffer module, a multi-channel DMA engine module, an interrupt management module, an automatic error detection and clearing module, and a PCIE TLP packet transmission module. The functions and collaborative workflows of each module are as follows.

[0026] The data receiving and parsing module is deployed inside the FPGA of the host computer's PCIe transmission card. It monitors in real time the SEM image frame information and image data streams from all channels sent by the main control board on the AXIS bus. The internal logic synchronizes the data to the same clock domain through an asynchronous FIFO, parses and obtains the frame header flag information, and retrieves the key information of the current frame, including: activated channel information ACTIVED_CHANNEL, image row number LINE_NUM, image column number COLUMN_NUM, channel number CHANNEL_ID, image payload FRAME_DATA, current row number CURRENT_LINE, and all-channel transmission end flag ALL_CHANNEL_OVER.

[0027] The dual-queue FIFO buffer module receives data streams from the data receiving and parsing module, decoupling the control flow from the data flow and forming a pipelined operation. This module consists of two independent parallel FIFO buffers: the image channel FIFO (CHANNEL QUEUE) and the image payload FIFO (PAYLOAD QUEUE). The image channel FIFO stores control information such as CHANNEL_ID and ALL_CHANNEL_OVER parsed from the frame header, providing a basis for subsequent data channel routing and status judgment. The image payload FIFO stores FRAME_DATA image pixel data, ensuring the continuity and integrity of the image data.

[0028] Two FIFO queues operate synchronously to ensure that channel control information and image payload data correspond strictly line-by-line. After receiving image data from all channels, the internal state machine waits for the ALL_CHANNEL_OVER field to be set before ending the reception of the current frame and waiting for the next frame.

[0029] The multi-channel DMA engine module is responsible for efficiently and in parallel transferring data from the image channel FIFO and image payload FIFO to the host computer memory.

[0030] During host computer driver initialization, M*N independent memory spaces are pre-allocated, where N is the number of detector channels and M is the number of buffers dedicated to each channel. The DMA engine simultaneously reads the "Image Channel FIFO" and the "Image Payload FIFO," obtains the channel number CHANNEL_ID from the Channel FIFO to determine the target channel, and then writes the image payload FRAME_DATA from the Payload FIFO to the memory address space corresponding to that channel.

[0031] During the transmission of one frame of image, the FPGA logic calculates the address offset ADDR based on the real-time image line number LINE_NUM. OFFSETWhen a special image scanning mode is launched in a SEM application, the DMA engine determines the target address ADDR. TARGET =ADDR BASE +ADDR OFFSET The target data corresponding to ACTIVED_CHANNEL is written to the memory space by mapping the intra-frame data address according to the real-time address offset, ADDR. BASE This indicates the base address of the memory space mapped to the current frame. The host application determines this based on CHANNEL_ID and ADDR. OFFSET The calculated index number is used to retrieve images from M memory spaces in real time, eliminating data waiting latency and enabling pipelined parallel operations for read and write. This method can resolve the anomaly that may occur in conventional ping-pong operations, where old address regions are overwritten before they are read, and greatly improves the flexibility of SEM image adjustments. A data flow diagram is shown below. Figure 2 As shown.

[0032] The state machine automatically determines the buffer to be written to in the next DMA transfer based on the current DMA channel transfer completion signal, whether the DMA transfer bus is occupied, and the current CHANNEL_ID of the DMA transfer. This ensures that the two buffers of any channel will not be in the write state at any time, thus avoiding data overwriting conflicts.

[0033] The interrupt management module only sends interrupt information to the host when transmitting image data. This mainly includes the following situations: (1) Detect the frame header information in the parsed image data stream, send an interrupt to the host, and notify the host to start a new image frame DMA transfer transaction; (2) When the transmitted image data fills a memory space, an interrupt is sent to the host. The host obtains the ACTIVED_CHANNEL and ADDR of the memory space by accessing the BAR0 space configuration information. OFFSET Information is used to switch address spaces; (3) Once the complete frame image data has been transmitted, ALL_CHANNEL_OVER is set and an interrupt is sent to the host, indicating that the transmission of the current frame has been completed; (4) If a timeout occurs due to excessively large transmission intervals between image pixels or between rows, or if a frame header representing the start of the next frame transmission is received before the image data length of the current frame is complete, an interrupt is sent to the host. The host obtains the information and processes the abnormal data.

[0034] The automatic error detection and clearing module handles image data errors and image transmission timeouts. Image data error flags include image channel error flags, frame error flags, and flags indicating that not all channels have been transmitted. Image transmission timeouts are monitored in real time by two counters: point timeout and line timeout. An image transmission timeout is triggered when the transmission interval between points within a line exceeds the time consumption and timeout redundancy corresponding to the current point's average parameters, or when the transmission interval between lines exceeds the time consumption and timeout redundancy corresponding to the current line's average parameters.

[0035] During image transmission, either image data errors or image transmission timeouts may occur. The interrupt management module will send an interrupt to the host. The host-side driver will then retrieve the current interrupt status and immediately discard the N channels of data received at that moment, ending the reception of this frame. Simultaneously, it will notify the upper-layer application to begin transmitting the next frame, preventing system flow blockage due to data anomalies. When a new image frame arrives, the interrupt status is cleared, and the next N channels of image data arriving at that moment are processed normally.

[0036] The PCIE TLP packet transmission module is responsible for packaging the data prepared by the DMA engine into PCIE Transaction Layer Packets (TLPs) for transmission. This module sets the Maximum Payload Size (MPS) to the maximum value, and the amount of data sent by the internal AXIS bus is also set to an integer multiple of MPS. This ensures that the burst length of the AXI bus transmission is aligned with MPS, and the internal logic is optimized for back-to-back transmission. Under the premise of sufficient hardware resources, it maximizes data slicing to minimize data transmission latency and fully utilizes pipeline transmission bandwidth and efficiency.

[0037] The overall system operation process is as follows: After system startup, the host computer driver first initializes the PCIe transmission card, allocating M*N independent buffers in the host memory and establishing DMA mapping, while simultaneously reading the BAR0 space configuration information to complete system presets. During data transmission, the main control board acquires SEM image data from N detector channels, encapsulates it into a data stream containing fields such as channel number (CHANNEL_ID), current line number (CURRENT_LINE), and image payload (FRAME_DATA), and sends it to the PCIe transmission card via fiber optic cable and the AURORA protocol. The PCIe transmission card's internal logic executes a three-stage pipelined processing: the first stage parses the frame header information in real time and separates the control flow from the data flow; the second stage writes the channel control information to the image channel FIFO and the image pixel data to the image payload FIFO, achieving data decoupling and caching; the third stage involves PCIe TLP data packet transport, where the multi-channel DMA engine locks the target channel based on the CHANNEL_ID and combines it with the real-time calculated address offset (ADDR). OFFSETThe data is moved in parallel to the corresponding memory space on the host machine. During this process, the interrupt management module sends interrupt signals to the host machine based on states such as frame start, buffer full, frame end, or transmission timeout, coordinating data reading and address switching. If the automatic error detection module detects data abnormalities or timeouts, it triggers an interrupt to notify the host machine to discard the current frame data and reset the state, ensuring that the system does not block. Finally, the host computer application reads the reconstructed image data from the memory space and displays the multi-dimensional morphology of the wafer in real time, completing a full high-throughput real-time transmission cycle.

[0038] Example 2: This embodiment provides a method for real-time transmission of multi-channel data in SEM imaging, applied to the system described in Embodiment 1, and includes the following steps: The main control board acquires SEM image data from N detector channels and encapsulates it into a data stream containing the channel number CHANNEL_ID; The PCIe transmission card receives the data stream and separates the channel control information and image payload data through the data receiving and parsing module. The channel control information and image payload data are cached in the image channel FIFO and image payload FIFO, respectively. The multi-channel DMA engine module moves the image payload data in parallel to the target storage space in the host computer memory corresponding to the channel number CHANNEL_ID, based on the channel number CHANNEL_ID.

[0039] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0040] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A real-time data transmission system for multi-channel SEM imaging, characterized in that, include: The main control board, based on FPGA design, is used to acquire SEM image data from multiple detector channels and encapsulate the image data into a data stream containing channel numbers for transmission. The PCIe transmission card, based on FPGA design, is used to receive the data stream and transmit data with the host computer through the PCIe interface. The PCIe transmission card integrates a data receiving and parsing module, a dual-queue FIFO buffer module, and a multi-channel DMA engine module. The data receiving and parsing module is used to parse the data stream and separate channel control information and image payload data. The dual-queue FIFO buffer module includes a parallel image channel FIFO and an image payload FIFO. The image channel FIFO is used to buffer the channel control information, and the image payload FIFO is used to buffer the image payload data. The multi-channel DMA engine module is used to transfer the image payload data in parallel to the target storage space in the host computer memory corresponding to the channel number according to the channel number in the channel control information. The data receiving and parsing module, the dual-queue FIFO buffer module, and the multi-channel DMA engine module constitute a three-level pipeline architecture with deep decoupling between each level.

2. The SEM imaging multi-channel data real-time transmission system according to claim 1, characterized in that, During driver initialization, the host computer allocates M*N independent memory buffers for N detector channels, with each detector channel having its own M memory buffers. The multi-channel DMA engine module calculates the address offset ADDR based on the real-time line number LINE_NUM of the image. OFFSET And according to the target address ADDR TARGET =ADDR BASE +ADDR OFFSET Write the image data to the corresponding memory buffer, where ADDR BASE Map the base address of the memory space for the current frame.

3. The SEM imaging multi-channel data real-time transmission system according to claim 1, characterized in that, The PCIe transmission card also integrates an interrupt management module, which is used to send an interrupt signal to the host computer when at least one of the following events occurs: (1) Frame header information was detected; (2) A memory buffer is filled with image data; (3) All channels of a frame of image have been transmitted. (4) Image transmission timeout or data error was detected.

4. The SEM imaging multi-channel data real-time transmission system according to claim 1, characterized in that, The PCIE transmission card also integrates an automatic error detection and clearing module, which is used to monitor image data errors and image transmission timeouts in real time. When an abnormality is detected, the interrupt management module notifies the host computer to discard the current frame data and reset in preparation for receiving the next frame image data.

5. The SEM imaging multi-channel data real-time transmission system according to claim 1, characterized in that, The PCIe transmission card also integrates a PCIe TLP packet transmission module, which is used to package the data to be transmitted into PCIe transaction layer packets; wherein, the maximum effective payload of the PCIe transaction layer packet is set to the maximum value, and the internal data transmission is optimized to a back-to-back transmission mode.

6. The SEM imaging multi-channel real-time data transmission system according to claim 1, characterized in that, The channel control information includes the channel number CHANNEL_ID and the full channel transmission end flag ALL_CHANNEL_OVER.

7. The SEM imaging multi-channel data real-time transmission system according to claim 1, characterized in that, The PCIe transmission card is interconnected with the main control board via optical fiber and communicates using the AURORA interface protocol.

8. The SEM imaging multi-channel data real-time transmission system according to claim 1, characterized in that, The multi-channel DMA engine module also includes a state machine, which is used to schedule the target buffer for the next DMA transfer based on the transmission completion signal and bus occupancy status of each channel, ensuring that two buffers of any channel are not in a write state at the same time.

9. A method for real-time transmission of multi-channel data in SEM imaging, characterized in that, Applied to the system as described in any one of claims 1 to 8, the method comprises the following steps: The main control board acquires SEM image data from N detector channels and encapsulates it into a data stream containing the channel number CHANNEL_ID; The PCIe transmission card receives the data stream and separates the channel control information and image payload data through the data receiving and parsing module. The channel control information and image payload data are cached in the image channel FIFO and image payload FIFO, respectively. The multi-channel DMA engine module moves the image payload data in parallel to the target storage space in the host computer memory corresponding to the channel number CHANNEL_ID, according to the channel number CHANNEL_ID.

10. The SEM imaging multi-channel data real-time transmission method according to claim 9, characterized in that, The method further includes: During the initialization of the host computer driver, M*N independent memory buffers are allocated for N detector channels, with each detector channel having its own M memory buffers. The multi-channel DMA engine module calculates the address offset ADDR based on the real-time line number LINE_NUM of the image. OFFSET And according to the target address ADDR TARGET =ADDR BASE +ADDR OFFSET Write the image data to the corresponding memory buffer, where ADDR BASE Map the base address of the memory space for the current frame.

Images