A multi-range modular electric control system for multi-stage cascaded amplification high-power ultrafast laser

Abstract

The application discloses a kind of multi-range modular electric control system for multi-stage cascade amplification high-power ultrafast laser, belong to laser electric control technical field, including host computer, FPGA master control board, STM32 control board, high-power pumping drive board, PD monitoring circuit board, pulse selector, optical shutter and seed pumping source, front stage and rear stage amplifier pumping source.Host computer is responsible for parameter issue, FPGA master control board cooperates with optical shutter and pulse selector to realize pulse selection, power regulation and optical path blocking;STM32 control board integrates drive and temperature control circuit, and carries out closed-loop control to seed and front stage pumping source;High-power pumping drive board is responsible for rear stage pumping source power drive;PD monitoring circuit board feedback mode-locked state.And establish the heartbeat monitoring between FPGA master control board and STM32 control board, when watchdog overflow caused by master control communication exception, STM32 independently maintains front-end pumping source controlled operation according to preset safety parameter.Realize the integration scheduling of multi-stage cascade laser and safety maintenance under abnormal state.

Description

Technical Field

[0001] This invention belongs to the field of laser electrical control technology, specifically relating to a multi-range modular electrical control system for multi-cascaded amplified high-power ultrafast lasers. Background Technology

[0002] With the increasing demand for precision laser processing in fields such as new energy and microelectronics, multi-cascaded ultrafast lasers have been widely used due to their superior performance. As the core of the laser system, the development of the electronic control system directly determines the performance ceiling and application breadth of laser technology. Driven by technological advancements and the demand for precision processing in various fields, electronic control systems are evolving towards higher precision, stronger integration, and greater intelligence, becoming a core driving force for the development of advanced manufacturing.

[0003] However, as laser systems evolve towards higher power, higher beam quality, more adjustable parameters, and multi-module integration, the advantages of cascaded ultrafast laser systems are becoming increasingly apparent. In such systems, it is often necessary to drive light sources with different ranges and be compatible with various laser modulation devices, placing higher demands on the multi-range driving capability, modular integration capability, and operational safety of the electrical control system. Especially in cascaded amplification structures, there are sequential coupling relationships between the light sources at each stage; any abnormality in the control link or scheduling process can easily affect the coordination between the driving and protection actions of each stage of the system.

[0004] In existing technologies, electronic control systems mostly adopt a discrete architecture, resulting in low system integration, weak inter-module coordination, and a lack of a unified monitoring and scheduling platform. This makes them unsuitable for the advanced laser processing requirements of multi-parameter collaborative control, real-time tuning of multiple modules, and reliable protection under abnormal conditions. Therefore, developing an integrated, platform-based, compact, intelligently controlled, and reliably operating laser electronic control system has significant research value and engineering implications. Summary of the Invention

[0005] To address the issues of low integration, weak inter-module collaboration, and lack of a unified monitoring and scheduling platform in existing discrete architectures, this invention provides a multi-range modular electrical control system for multi-cascaded high-power ultrafast lasers. This system enables centralized control, data fusion, and collaborative operation of the drive, temperature control, monitoring, and modulation modules within a unified electrical control platform, thereby improving system integration and response speed.

[0006] This invention provides a multi-range modular electronic control system for multi-cascaded high-power ultrafast lasers, comprising a host computer, an FPGA main control board, an STM32 control board, a high-power pump driver board, and seed pump sources, preamplifier pump sources, and power amplifier pump sources arranged along the optical path. The host computer is communicatively connected to the FPGA main control board; the FPGA main control board is communicatively connected to the STM32 control board and the high-power pump driver board respectively; the STM32 control board integrates a drive circuit and a temperature control circuit; the drive circuit is connected to the drive input terminals of the seed pump source and the preamplifier pump source; the temperature control circuit is connected to the temperature control component integrated inside the seed pump source and the temperature control module located on the preamplifier pump source respectively; the control output terminal of the FPGA main control board is connected to the control terminal of the high-power pump driver board; the power output terminal of the high-power pump driver board is connected to the power amplifier pump source. The FPGA main control board is configured to send heartbeat command frames to the STM32 control board at a preset period. The STM32 control board has a watchdog counter, which is configured to maintain the drive current output and temperature control of the seed pump source and the preamplifier pump source according to the internal preset safety parameters when the watchdog counter overflows due to the continuous failure to receive heartbeat command frames.

[0007] Through the above technical solution, the FPGA main control board serves as the unified system scheduling unit, the STM32 control board as the secondary control unit, and the high-power pump driver board as the high-power drive unit for the later stages. This enables the seed pump source, preamplifier pump source, and postamplifier pump source to be controlled in stages according to different ranges and control requirements. In particular, the STM32 control board directly undertakes the driving and temperature control closed loop of the seed pump source and preamplifier pump source. Even when the watchdog counter overflows due to the continuous absence of heartbeat command frames, it can still maintain the core light source at the front end in a controlled state according to the internally preset safety parameters, thereby reducing the risk of loss of control of the seed pump source or preamplifier pump source driving and temperature control due to the loss of main control commands.

[0008] Furthermore, the STM32 control board is configured to switch the control mode to the internal closed-loop control mode and enter the safety hold loop when the watchdog counter overflows. In the safety hold loop, the STM32 control board continuously refreshes the output of the drive circuit and the temperature control circuit to keep the seed pump source and the preamplifier pump source under control.

[0009] Through the above technical solutions, the STM32 control board can independently maintain the driving and temperature control of the seed pump source and the preamplifier pump source when it is unable to continuously receive the heartbeat command frame from the FPGA main control board, so that the core light source at the front end is kept in a preset safe working state, and the reliability of the system under abnormal conditions is improved.

[0010] Furthermore, the system also includes a PD monitoring circuit board, the input of which is optically coupled to the optical output of the seed pump source. The FPGA main control board is configured to capture the rising or falling edge of the pulse signal from the PD monitoring circuit board, calculate the period of adjacent pulses through a timer and convert it into a measured repetition frequency. When the error between the measured repetition frequency and the target repetition frequency is within a preset threshold range and multiple consecutive pulses meet the condition, the seed pump source is determined to be in a mode-locked state and the internal status flag is set to a high level.

[0011] Through the above technical solutions, the PD monitoring circuit board can convert the optical pulse signal of the seed pump source into an electrical pulse signal suitable for processing by the FPGA main control board. The FPGA main control board can obtain the measured repetition frequency based on adjacent pulse periods, thereby providing a monitoring basis for judging the mode-locking state of the seed pump source.

[0012] Furthermore, the FPGA main control board is also configured to set the internal status flag to a low level and trigger an alarm interrupt when the measured repetition frequency is detected to be out of tolerance or the pulse signal is lost.

[0013] Through the above technical solutions, the system can promptly generate an alarm state when the seed pump source experiences abnormal mode locking or pulse signal loss, providing triggering conditions for subsequent abnormal protection processes and improving the system's response capability to mode locking abnormalities.

[0014] Furthermore, the FPGA main control board is configured to enable the STM32 control board to power the seed pump source and perform temperature control; monitor the internal status flag bit, and after the internal status flag bit jumps to a high level, delay for a first preset time to enable the preamplifier pump source and perform temperature control; after receiving the status information sent by the STM32 control board through the communication connection indicating that the current fluctuation amplitude of the preamplifier pump source is within a preset threshold range, delay for a second preset time to enable the high-power pump driver board to power the postamplifier pump source.

[0015] Through the above technical solutions, the system enters the working state step by step in the order of seed pump source, preamplifier pump source and postamplifier pump source, so that the postamplifier pump source can be put into operation only after the front-end light source and the preamplifier state meet the conditions, which is conducive to the coordinated control of the multi-stage amplification system during startup.

[0016] Furthermore, the system also includes a pulse selector located on the optical path between the pump source of the preamplifier and the pump source of the postamplifier; the FPGA main control board is connected to the pulse selector and is configured to generate instruction frames containing frequency division, delay and pulse width information according to the parameters set by the host computer and send them to the pulse selector.

[0017] Through the above technical solutions, the FPGA main control board can centrally configure and coordinate the pulse selector, realize the modulation of parameters such as laser pulse frequency division, delay and pulse width, and improve the system's integration and control capabilities for external modulation devices.

[0018] Furthermore, the system also includes an optical shutter located on the output optical path after the pump source of the subsequent amplifier. The optical shutter has analog voltage pins and digital signal pins. The analog control terminal of the FPGA main control board is connected to the analog voltage pins, and the digital control terminal is connected to the digital signal pins. The FPGA main control board is configured to adjust the output power by outputting an analog voltage through the analog control terminal, and to output a signal through the digital control terminal to control the optical shutter to perform optical path blocking when an alarm interruption is received.

[0019] Through the above technical solutions, the FPGA main control board can link the control of the optical shutter with the overall working status of the laser, realize the adjustment of output power, and control the optical shutter to cut off the output optical path in abnormal conditions, thereby improving the safety of system operation.

[0020] Furthermore, the driving circuit includes an operational amplifier chip, a voltage divider circuit, and a sampling resistor; the non-inverting input terminal of the operational amplifier chip is connected to the voltage divider circuit, the inverting input terminal is connected to the sampling resistor, and the output terminal is connected to the control electrode of the driving MOSFET; the operational amplifier chip is configured to adjust the conduction level of the driving MOSFET by comparing the difference between the reference voltage and the feedback voltage.

[0021] Through the above technical solutions, the driving circuit can adjust the driving current based on the feedback voltage, thereby providing a stable and adjustable driving current output for the seed pump source and the preamplifier pump source.

[0022] Furthermore, the temperature control components integrated within the seed pump source and the temperature control module on the preamplifier pump source both include a thermoelectric cooler and a thermistor; the temperature control circuit includes a temperature control chip with a built-in analog-to-digital converter and an H-bridge drive circuit; the temperature control chip is configured to generate an adjustment command based on the error between the temperature fed back by the thermistor and the target temperature; the H-bridge drive circuit is configured to receive the adjustment command and output current to the thermoelectric cooler.

[0023] Through the above technical solutions, the temperature control circuit can control the heating or cooling of the semiconductor cooling chip based on the temperature feedback from the thermistor, thereby achieving closed-loop temperature control of the preamplifier pump source and seed pump source and improving the stability of the working state of the preamplifier pump source and seed pump source.

[0024] Furthermore, the driving circuit includes a first range driving channel and a second range driving channel. The first range driving channel is used to output a driving current of 0 to 800mA to the seed pump source, the second range driving channel is used to output a driving current of 0 to 10A to the pump source of the preamplifier, and the high-power pump driver board is used to output a driving current of 0 to 20A to the pump source of the postamplifier.

[0025] Through the above technical solutions, the FPGA main control board serves as the unified scheduling unit of the system, the STM32 control board serves as the secondary control unit, and the high-power pump driver board serves as the high-power drive unit of the later stage. This enables the seed pump source, the preamplifier pump source, and the postamplifier pump source to be controlled in stages according to different ranges and control requirements. It takes into account both low-noise precision drive and high-power fast response, and meets the differentiated requirements of multi-stage optical amplification systems for drive current.

[0026] Compared with the prior art, the present invention has at least the following beneficial effects: This invention establishes a hierarchical control architecture among the host computer, seed pump source, preamplifier pump source, and power amplifier pump source by setting up an FPGA main control board, an STM32 control board, and a high-power pump driver board. The FPGA main control board is used to uniformly schedule the STM32 control board and the high-power pump driver board. The STM32 control board is used to drive and temperature-control the seed pump source and the preamplifier pump source. The high-power pump driver board is used to power drive the power source of the power amplifier, thereby improving the integration and inter-module coordination capabilities of the multi-cascaded high-power ultrafast laser power control system. By integrating drive and temperature control circuits within the STM32 control board, the drive circuit is connected to the drive input terminals of the seed pump source and the preamplifier pump source, and the temperature control circuit is connected to the temperature control module located on the preamplifier pump source. This allows the STM32 control board to control the drive current output and temperature of the seed pump source and preamplifier pump source, meeting the drive and temperature control requirements of light sources with different ranges in a multi-cascaded amplification structure. The FPGA main control board sends heartbeat command frames to the STM32 control board at preset intervals, and a watchdog counter is set within the STM32 control board. This allows the STM32 control board to maintain the drive current output and temperature control of the seed pump source and preamplifier pump source according to internally preset safety parameters when the watchdog counter overflows due to consecutive failures to receive heartbeat command frames. This ensures that the seed pump source and preamplifier pump source remain under control when the main control command cannot be continuously issued, improving the abnormal maintenance capability of the core front-end light source and the reliability of system operation. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the invention. Other embodiments and many anticipated advantages of the embodiments will be readily recognized as they become better understood through reference to the following detailed description. Elements in the drawings are not necessarily to scale. The same reference numerals refer to corresponding similar parts.

[0028] Figure 1 This is a schematic block diagram of a multi-range modular electrical control system for multi-cascaded amplified high-power ultrafast lasers, according to an embodiment of the present invention.

[0029] Figure 2 This is a structural diagram of a multi-range modular electrical control system for a multi-cascaded amplified high-power ultrafast laser, according to an embodiment of the present invention.

[0030] Figure 3 This is a schematic block diagram of the STM32 control board and temperature control module in an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the drive circuit of the STM32 control board in an embodiment of the present invention.

[0032] Figure 5 This is a schematic diagram of the control signals for the high-power pump drive board in an embodiment of the present invention.

[0033] Figure 6 This is a schematic block diagram of the PD monitoring circuit board in an embodiment of the present invention.

[0034] Figure 7 This is a schematic block diagram of the pulse menu device in an embodiment of the present invention.

[0035] Figure 8 This is a schematic diagram of the laser output and digital and analog signals of the optical shutter in an embodiment of the present invention.

[0036] The meaning of each number in the diagram: 1: Host computer; 2: FPGA main control board; 3: STM32 control board; 3-1: Driver circuit; 3-2: Temperature control circuit; 3-3: Voltage divider circuit; 3-4: Operational amplifier chip; 3-5: Driver MOSFET; 3-6: Sampling resistor; 4: High-power pump driver board; 5: PD monitoring circuit board; 5-1: Transimpedance amplifier circuit; 5-2: Gain adjustable amplifier; 5-3: Filter; 5-4: ADC acquisition circuit; 6: Pulse selection... 6-1: Serial communication module; 6-2: Microcontroller main control module; 6-3: CPLD frequency divider module; 6-4: Delay pulse width adjustment module; 6-5: Signal power amplification module; 6-6: Acousto-optic modulator; 7: Optical shutter; 8: Semiconductor laser; 8-1: Seed pump source; 8-2: Preamplifier pump source; 8-3: Power amplifier pump source; 9: Temperature control module; 9-1: Thermistor; 9-2: Semiconductor cooling chip. Detailed Implementation

[0037] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0038] This invention provides a multi-range modular electronic control system for multi-cascaded high-power ultrafast lasers. This system is used for driving, temperature control, monitoring, and scheduling control of different range light sources in a multi-cascaded high-power ultrafast laser. The system adopts a hierarchical control architecture consisting of an FPGA main control board 2, an STM32 control board 3, and a high-power pump driver board 4. The FPGA main control board 2 is used to uniformly schedule the STM32 control board 3 and the high-power pump driver board 4. The STM32 control board 3 is used to drive and temperature control the seed pump source 8-1 and the preamplifier pump source 8-2. The high-power pump driver board 4 is used to power drive the post-amplifier pump source 8-3. The seed pump source 8-1 is a butterfly-shaped semiconductor laser, which integrates a thermistor and a thermoelectric cooler. The preamplifier pump source 8-2 is additionally equipped with a temperature control module 9, which includes a thermistor 9-1 and a thermoelectric cooler 9-2. The temperature control circuit 3-2 of the STM32 control board 3 is connected to the thermistor and semiconductor cooler integrated inside the seed pump source 8-1 and the temperature control module 9 on the preamplifier pump source 8-2, respectively, to control the temperature of the seed pump source 8-1 and the preamplifier pump source 8-2.

[0039] like Figure 1 and Figure 2As shown, the multi-range modular electronic control system of this embodiment includes a host computer 1, an FPGA main control board 2, an STM32 control board 3, a high-power pump driver board 4, a PD monitoring circuit board 5, a pulse selector 6, an optical shutter 7, a semiconductor laser 8, and a temperature control module 9. The semiconductor laser 8 includes a seed pump source 8-1, a preamplifier pump source 8-2, and a power amplifier pump source 8-3 arranged along the optical path. The temperature control module 9 includes a thermistor 9-1 and a thermoelectric cooler 9-2.

[0040] The host computer 1 communicates with the FPGA main control board 2. The host computer 1 displays the operable parameters and monitorable status of the electronic control system, and sends parameters such as the drive current value, temperature control value, output frequency, output power, and laser working mode of each channel to the FPGA main control board 2. The FPGA main control board 2 receives the data frame instructions sent by the host computer 1, and parses and distributes the data frame instructions.

[0041] The FPGA main control board 2 is connected to the STM32 control board 3 and the high-power pump drive board 4, and is also connected to the PD monitoring circuit board 5, the pulse selector 6 and the optical shutter 7 for communication or control.

[0042] Specifically, the FPGA main control board 2 sends the operating temperature and drive current settings of the seed pump source 8-1 and the preamplifier pump source 8-2 to the STM32 control board 3, outputs control signals to the high-power pump driver board 4 to control the postamplifier pump source 8-3, receives the mode-lock monitoring signal output by the PD monitoring circuit board 5, sends instruction frames containing frequency division, delay and pulse width information to the pulse selector 6, and outputs analog and digital signals to the optical shutter 7 to realize the switching of the laser's internal / gated working state.

[0043] The STM32 control board 3 is connected to the seed pump source 8-1, the preamplifier pump source 8-2, and the temperature control module 9. The STM32 control board 3 integrates a driver circuit 3-1 and a temperature control circuit 3-2. The driver circuit 3-1 is connected to the drive input terminals of both the seed pump source 8-1 and the preamplifier pump source 8-2, providing stable and adjustable drive currents to both. The temperature control circuit 3-2 is connected to the temperature control component integrated within the seed pump source 8-1 and the temperature control module 9 located on the preamplifier pump source 8-2, controlling the temperature of both sources. The power output terminal of the high-power pump driver board 4 is connected to the power amplifier pump source 8-3. The input terminal of the PD monitoring circuit board 5 is optically coupled to the optical output terminal of the seed pump source 8-1. Pulse selector 6 is located on the optical path between pump source 8-2 of the preamplifier and pump source 8-3 of the postamplifier. Optical shutter 7 is located on the output optical path after pump source 8-3 of the postamplifier.

[0044] Furthermore, the host computer 1 is developed based on Qt Creator and communicates with the FPGA main control board 2 via a UART serial port. The FPGA main control board 2 uses an EP4CE10, and the STM32 control board 3 uses an STM32F103RBT6. The FPGA main control board 2 communicates with the STM32 control board 3 and the pulse selector 6 via UART, and the FPGA main control board 2 communicates with the PD monitoring circuit board 5 via an SPI bus. The FPGA main control board 2 provides control voltage, enable signal, and square wave signal to the high-power pump driver board 4, and provides analog and digital signals to the optical shutter 7.

[0045] Furthermore, the drive circuit 3-1 of the STM32 control board 3 includes a first-range drive channel and a second-range drive channel. The first-range drive channel is used to output a stable and adjustable drive current of 0 to 800mA to the seed pump source 8-1, and the second-range drive channel is used to output a stable and adjustable drive current of 0 to 10A to the preamplifier pump source 8-2. The high-power pump drive board 4 is used to output a drive current of 0 to 20A to the postamplifier pump source 8-3. Thus, the system can adapt to the different range drive requirements of the seed pump source 8-1, the preamplifier pump source 8-2, and the postamplifier pump source 8-3 respectively.

[0046] In the two-level control architecture of FPGA main control board 2 and STM32 control board 3 constructed in this embodiment, an asymmetric task allocation strategy is adopted: STM32 control board 3 acts as an independent secondary controller, responsible for low-noise driving and closed-loop temperature control of the seed pump source 8-1 and the preamplifier pump source 8-2, which have extremely high stability requirements; while FPGA main control board 2, with its advantages of parallel processing and high-speed I / O, directly controls the high-power pump driver board 4 and coordinates the scheduling of fast modulation devices such as pulse selector 6 and optical shutter 7. This asymmetric architecture achieves a match between computing resources and the real-time requirements of devices, so that the low-noise driving and temperature closed-loop control of the front-end core light source are undertaken by STM32 control board 3, and the high-power driving and system-level scheduling of the subsequent stage are undertaken by FPGA main control board 2 and high-power pump driver board 4. Even if FPGA main control board 2 is unable to continuously issue real-time control commands due to electromagnetic interference, program abnormalities, or communication abnormalities, the front-end core light source can still be driven and temperature controlled by STM32 control board 3 according to the internally preset safety parameters.

[0047] Seed pump source 8-1 is used to generate high-quality, low-power laser output, i.e., seed light. After the seed light is incident on preamplifier pump source 8-2, stimulated emission occurs in the active gain medium of preamplifier pump source 8-2, resulting in the first coherent amplification of the optical signal energy and increasing the output power to a moderate level. The preamplified beam is then injected into postamplifier pump source 8-3 for a second power amplification, thereby achieving the high power output level required by the system. This multi-stage amplification structure overcomes the power bottleneck of single-stage amplification and helps maintain the beam quality of the final output light.

[0048] Furthermore, the pulse selector 6 is positioned in the optical path between the preamplifier pump source 8-2 and the postamplifier pump source 8-3, and is used to perform frequency division, delay, and pulse width modulation on the laser pulses before they enter the postamplifier pump source 8-3. The optical shutter 7 is positioned in the output optical path after the postamplifier pump source 8-3, and is used to adjust the power of the output laser or block the optical path.

[0049] Furthermore, the FPGA main control board 2 is configured to send heartbeat command frames to the STM32 control board 3 at preset intervals. The STM32 control board 3 has an internal watchdog counter. During normal operation, the FPGA main control board 2 sends heartbeat command frames to the STM32 control board 3 via the UART interface every fixed period (e.g., 100ms); the STM32 control board 3 resets the watchdog counter each time it receives a valid heartbeat command frame from the FPGA main control board 2.

[0050] When the STM32 control board 3 fails to receive heartbeat command frames for a continuous period of time (e.g., fails to receive a valid heartbeat for 500 ms), causing the watchdog counter to overflow, the STM32 control board 3 triggers its internal safety hold process.

[0051] When the internal safety hold procedure is triggered, STM32 control board 3 executes the following independent hold logic: 1. Lock the current driving current setting and temperature setting of the current seed pump source 8-1 and the preamplifier pump source 8-2; 2. Switch the control mode to internal closed-loop control mode, no longer relying on real-time control commands issued by FPGA main control board 2; 3. Enter the safety hold cycle and continuously refresh the output of the internal drive circuit 3-1 and temperature control circuit 3-2 to maintain the seed pump source 8-1 and the preamplifier pump source 8-2 operating stably near the current operating point.

[0052] During this process, the core seed pump source 8-1 and the preamplifier pump source 8-2 are kept under control by the STM32 control board 3, thereby reducing the risk of current drift, temperature drift or abnormal operation of the front-end light source due to loss of control commands.

[0053] like Figure 3 As shown, the temperature control circuit 3-2 is used for closed-loop temperature control of the seed pump source 8-1 and the preamplifier pump source 8-2. The temperature control module 9 includes a thermistor 9-1 and a thermoelectric cooler 9-2. The thermistor 9-1 is thermally coupled to the preamplifier pump source 8-2 and is used to collect the temperature information of the preamplifier pump source 8-2; the thermoelectric cooler 9-2 is used to cool or heat the preamplifier pump source 8-2 according to the direction and magnitude of the control current.

[0054] Furthermore, the temperature control components integrated within the seed pump source 8-1 include a thermistor and a thermoelectric cooler. The thermistor integrated within the seed pump source 8-1 is connected to the temperature acquisition terminal of the STM32 control board 3, and the thermoelectric cooler integrated within the seed pump source 8-1 is connected to the temperature control output terminal of the STM32 control board 3. The STM32 control board 3 acquires the temperature signal fed back by the thermistor through the temperature control circuit 3-2, and adjusts the drive current output to the thermoelectric cooler according to the error between the target temperature and the feedback temperature of the seed pump source 8-1, thereby achieving closed-loop temperature control of the seed pump source 8-1.

[0055] In this embodiment, the temperature control circuit 3-2 includes a temperature control chip (such as MAX1978) with a built-in analog-to-digital converter and an H-bridge driver circuit. The temperature control chip acquires the voltage values ​​of the thermistor integrated inside the seed pump source 8-1 and the thermistor 9-1 on the preamplifier pump source 8-2 in real time, and converts these voltage values ​​into actual temperature values. The temperature control chip generates adjustment commands based on the error between the temperature fed back by the corresponding thermistor and the target temperature. The H-bridge driver circuit receives the adjustment commands and outputs current to the corresponding thermoelectric cooler or thermoelectric cooler 9-2. By changing the direction and magnitude of the current output to the corresponding thermoelectric cooler or thermoelectric cooler 9-2, heating or cooling control of the seed pump source 8-1 and the preamplifier pump source 8-2 can be achieved. At the same time, the temperature control circuit 3-2 feeds back the real-time temperature status data to the STM32 control board 3 controller via the SPI interface to achieve fully automatic precision temperature closed-loop monitoring.

[0056] like Figure 4 As shown, the driving circuit 3-1 includes a voltage divider circuit 3-3, an operational amplifier chip 3-4, a driving MOSFET 3-5, and a sampling resistor 3-6. The non-inverting input of the operational amplifier chip 3-4 is connected to the voltage divider circuit 3-3, the inverting input is connected to the sampling resistor 3-6, and the output is connected to the control electrode of the driving MOSFET 3-5. The voltage divider circuit 3-3 is used to generate a reference voltage corresponding to the target driving current, and the sampling resistor 3-6 is used to acquire the feedback voltage corresponding to the actual driving current.

[0057] Operational amplifier chip 3-4 is configured to adjust the conduction level of driver MOSFET 3-5 by comparing the difference between the reference voltage and the feedback voltage. When the feedback voltage is lower than the reference voltage, operational amplifier chip 3-4 adjusts the conduction level of driver MOSFET 3-5 to increase its conduction level, thereby increasing the drive current; when the feedback voltage is higher than the reference voltage, operational amplifier chip 3-4 adjusts the conduction level of driver MOSFET 3-5 to decrease its conduction level, thereby reducing the drive current. Thus, driver circuit 3-1 can provide a stable and adjustable drive current output to seed pump source 8-1 and preamplifier pump source 8-2.

[0058] like Figure 5 As shown, the control terminal of the high-power pump driver board 4 is connected to the control output terminal of the FPGA main control board 2, and the power output terminal of the high-power pump driver board 4 is connected to the pump source 8-3 of the subsequent amplifier. The high-power pump driver board 4 is used to output a drive current of 0-20A to the pump source 8-3 of the subsequent amplifier.

[0059] Furthermore, the high-power pump driver board 4 uses the LT3763 as its core driver, receiving the enable signal EN, the square wave signal PWM, and the analog control voltage Vctrl output from the FPGA main control board 2. The enable signal EN controls the on / off state of the drive current of the high-power pump driver board 4, the analog control voltage Vctrl adjusts the drive current of the subsequent amplifier pump source 8-3, and the square wave signal PWM controls the operating mode of the subsequent amplifier pump source 8-3.

[0060] Specifically, when the enable signal EN is at an active level, the high-power pump driver board 4 outputs drive current; when the enable signal EN is at an inactive level, the high-power pump driver board 4 shuts off the drive current output. The magnitude of the drive current output by the high-power pump driver board 4 corresponds to the analog control voltage Vctrl. When the square wave signal PWM is connected to a 3.3V constant voltage signal, the subsequent amplifier pump source 8-3 is in continuous laser operation mode; when the square wave signal PWM is connected to an active PWM square wave, the subsequent amplifier pump source 8-3 enters pulse modulation mode according to the active PWM square wave.

[0061] The high-power pump driver board 4 also collects the actual drive current If of the subsequent amplifier pump source 8-3 in real time and feeds it back to the FPGA main control board 2. The FPGA main control board 2 determines whether there is an overcurrent abnormality in the subsequent amplifier pump source 8-3 based on the feedback current. When an overcurrent abnormality is detected, the FPGA main control board 2 can trigger an alarm interrupt and execute drive shutdown. Furthermore, the high-power pump driver board 4 also integrates overcurrent protection circuit, overvoltage protection circuit, and overtemperature protection circuit to provide protection when the subsequent amplifier pump source 8-3 experiences an abnormal drive state.

[0062] like Figure 6As shown, the PD monitoring circuit board 5 is used to monitor the mode-locking state of the seed pump source 8-1. The input terminal of the PD monitoring circuit board 5 is optically coupled to the optical output terminal of the seed pump source 8-1. The PD monitoring circuit board 5 converts the optical pulse signal output by the seed pump source 8-1 into an electrical pulse signal and inputs it to the pin of the FPGA main control board 2.

[0063] The PD monitoring circuit board 5 consists of a transimpedance amplifier circuit 5-1, a gain-adjustable amplifier 5-2, a filter 5-3, and an ADC acquisition circuit 5-4 connected in sequence. The transimpedance amplifier circuit 5-1 is used to convert the weak light signal output from the seed pump source 8-1 into an electrical signal and perform primary amplification; the gain-adjustable amplifier 5-2 is used to adjust the signal amplitude; the filter 5-3 is used to filter out noise and invalid frequency band signals; and the ADC acquisition circuit 5-4 is used to convert the conditioned signal into a digital pulse signal that can be acquired and processed by the FPGA main control board 2.

[0064] The FPGA main control board 2 internally incorporates mode-locking logic based on a hardware timer. Specifically, the FPGA main control board 2 can drive a 32-bit timer using an internal 50MHz clock. Whenever a rising or falling edge of a pulse signal from the PD monitoring circuit board 5 is detected, the FPGA main control board 2 latches the current timer count value and subtracts it from the count value corresponding to the previous rising or falling edge to obtain the clock cycle difference between adjacent pulses. The FPGA main control board 2 calculates the actual pulse period based on the clock cycle difference, thereby obtaining the measured repetition frequency.

[0065] The FPGA main control board 2 compares the measured repetition frequency with the target repetition frequency in the frequency setting register. If the error of N consecutive pulse cycles is within the preset threshold range, for example, within ±0.01%, the seed pump source 8-1 is determined to be in a stable mode-locked state, and the internal status flag lock_status is set to high level; if the measured repetition frequency exceeds the tolerance or the pulse signal is lost, the internal status flag lock_status is set to low level, and an alarm interrupt is immediately triggered to start the abnormal protection process.

[0066] During system startup, the FPGA main control board 2 first enables the STM32 control board 3 to power the seed pump source 8-1. Then, the FPGA main control board 2 determines whether the seed pump source 8-1 is in mode-locked state based on the electrical pulse signal input from the PD monitoring circuit board 5. When the internal status flag jumps high, the FPGA main control board 2 enables the preamplifier pump source 8-2 after a first preset time delay. After receiving status information from the STM32 control board via UART indicating that the current fluctuation amplitude of the preamplifier pump source 8-2 is within a preset threshold range, the FPGA main control board 2 enables the high-power pump driver board 4 after a second preset time delay, so that the high-power pump driver board 4 powers the postamplifier pump source 8-3. Thus, the system enters the working state step by step in the order of seed pump source 8-1, preamplifier pump source 8-2, and postamplifier pump source 8-3.

[0067] During system operation, when the FPGA main control board 2 detects that the internal status flag lock_status goes low, or detects that any drive current exceeds the safety threshold, or detects that any temperature control point exceeds the set range, the FPGA main control board 2 immediately executes the abnormal protection program and performs drive shutdown in the following order: shutting down the downstream amplifier pump source 8-3, shutting down the upstream amplifier pump source 8-2, and shutting down the seed pump source 8-1. The entire shutdown process is completed within milliseconds. Specifically, the FPGA main control board 2 first pulls down the enable signal EN to shut down the drive output of the high-power pump driver board 4 to the downstream amplifier pump source 8-3; then, the FPGA main control board 2 controls the STM32 control board 3 to shut down the upstream amplifier pump source 8-2 via UART instructions; finally, the FPGA main control board 2 controls the STM32 control board 3 to shut down the seed pump source 8-1 via UART instructions. By using this shutdown sequence, the system can prioritize taking the pump source 8-3 of the subsequent amplifier out of operation, thereby reducing the impact of abnormal optical path conditions on the subsequent high-power amplification link.

[0068] like Figure 7 As shown, pulse selector 6 is used to receive input laser pulses and perform frequency division, delay, and pulse width adjustment on the input laser pulses. In this embodiment, combined with... Figure 1 and Figure 2 The photoelectric physical layer structure shown includes a pulse selector 6 positioned in the optical path between the preamplifier pump source 8-2 and the postamplifier pump source 8-3. This selector modulates the laser pulses entering the postamplifier pump source 8-3. The pulse selector 6 comprises a serial communication module 6-1, a microcontroller main control module 6-2, a CPLD frequency divider module 6-3, a delay pulse width adjustment module 6-4, a signal power amplification module 6-5, and an acousto-optic modulator 6-6. The microcontroller main control module 6-2 is communicatively connected to the seed pump source 8-1 and receives synchronization signals from it.

[0069] The FPGA main control board 2 is communicatively connected to the pulse selector 6. Based on the parameters set by the host computer 1, the FPGA main control board 2 generates an instruction frame containing frequency division, delay, and pulse width information according to the instruction format specified by the pulse selector 6, and sends the instruction frame to the serial communication module 6-1 via the UART interface. The serial communication module 6-1 sends the instruction frame to the microcontroller main control module 6-2. After parsing the instruction frame, the microcontroller main control module 6-2 processes it in conjunction with the synchronization signal input from the seed pump source 8-1, sends the frequency division control parameters to the CPLD frequency division module 6-3, and sends the delay control parameters and pulse width control parameters to the delay pulse width adjustment module 6-4. The CPLD frequency division module 6-3 generates a frequency-divided pulse control signal based on the frequency division control parameters, and the delay pulse width adjustment module 6-4 adjusts the delay and pulse width of the pulse control signal based on the delay and pulse width control parameters. The adjusted signal is amplified by the signal power amplification module 6-5 and then output to the acousto-optic modulator 6-6. The final output drive signal controls the acousto-optic modulator 6-6 to process the input raw laser pulses, enabling the laser to selectively pass through according to the command rules and to be precisely timed.

[0070] Optical shutter 7 is located on the output optical path after the pump source 8-3 of the subsequent amplifier. Optical shutter 7 has an analog voltage input interface and a TTL digital signal input interface; the analog control terminal of the FPGA main control board 2 is connected to the analog voltage input interface of optical shutter 7, and the digital control terminal of the FPGA main control board 2 is connected to the TTL digital signal input interface of optical shutter 7.

[0071] In this embodiment, the FPGA main control board 2 integrates an analog control submodule and a digital control submodule. The analog control submodule generates a 0-5V analog control voltage through PWM plus RC filtering or an external DAC chip, and outputs the 0-5V analog control voltage to the analog voltage input interface of the optical shutter 7. When the host computer 1 sets the output power percentage to X%, the analog control submodule outputs an analog control voltage with an amplitude of (X / 100)×5V to achieve linear adjustment of the output laser power.

[0072] The digital control submodule generates TTL control signals and outputs them to the TTL digital signal input interface of the optical shutter 7. In internal mode, the digital control submodule outputs a constant TTL high level, keeping the optical shutter 7 in a normally open state. In gated mode, the digital control submodule receives high-frequency TTL pulse sequences provided by external users through the SMA interface, and outputs them to the TTL digital signal input interface of the optical shutter 7 after buffering and shaping to achieve gated modulation of the laser output.

[0073] like Figure 8As shown, when the digital signal is in the output-allowed state (high level), the optical shutter 7 adjusts the output laser power according to the amplitude of the analog signal; when the analog signal decreases, the output laser power decreases accordingly; when the digital signal switches to the off state (low level), the optical shutter 7 performs optical path blocking, and the output laser is turned off. Therefore, the FPGA main control board 2 can adjust the output laser power through the analog signal and control the optical shutter 7 to perform optical path conduction or optical path blocking through the digital signal. When the FPGA main control board 2 detects any of the abnormal states of mode lock failure, overcurrent abnormality, or overtemperature abnormality, the digital control submodule immediately outputs a TTL low level, cutting off the laser output through the optical shutter 7 within a nanosecond to microsecond time. Thus, the optical shutter 7 can be linked with the system alarm state to block the output optical path in abnormal states.

[0074] The working process of the multi-range modular electronic control system in this embodiment is as follows: After the system is powered on, the host computer 1 establishes a communication connection with the FPGA main control board 2 and sends initialization parameters to the FPGA main control board 2. After parsing the initialization parameters, the FPGA main control board 2 sends the driving and temperature control parameters of the seed pump source 8-1 and the preamplifier pump source 8-2 to the STM32 control board 3.

[0075] The FPGA main control board 2 initiates the heartbeat communication mechanism and sends heartbeat command frames to the STM32 control board 3 at preset intervals. After receiving a valid heartbeat command frame, the STM32 control board 3 resets its internal watchdog counter.

[0076] Subsequently, the FPGA main control board 2 enables the STM32 control board 3 to supply power to the seed pump source 8-1. The PD monitoring circuit board 5 collects the optical pulse signal output by the seed pump source 8-1 and converts it into an electrical pulse signal, which is then input to the FPGA main control board 2. The FPGA main control board 2 captures the rising or falling edge of the electrical pulse signal, calculates the period of adjacent pulses, and converts it into a measured repetition frequency, thereby determining whether the seed pump source 8-1 is in a mode-locked state.

[0077] When the seed pump source 8-1 is in mode-locked state and its internal status flag changes to a high level, the FPGA main control board 2 delays for a first preset time and enables the preamplifier pump source 8-2. The STM32 control board 3 outputs drive current to the preamplifier pump source 8-2 and performs closed-loop temperature control on the preamplifier pump source 8-2 through the temperature control circuit 3-2.

[0078] When the STM32 control board receives the status information sent via UART communication indicating that the current fluctuation amplitude of the preamplifier pump source 8-2 is within the preset threshold range, the FPGA main control board 2 delays for a second preset time and enables the high-power pump driver board 4, so that the high-power pump driver board 4 supplies power to the postamplifier pump source 8-3.

[0079] During normal system operation, the FPGA main control board 2 controls the pulse selector 6 to perform frequency division, delay, and pulse width adjustment according to the parameters set by the host computer 1, and controls the optical shutter 7 to adjust the output power or control the optical path on / off. When the FPGA main control board 2 detects a lockout, over-temperature, or over-current abnormality, the FPGA main control board 2 triggers an alarm interrupt and executes drive shutdown in the order of the downstream amplifier pump source 8-3, the upstream amplifier pump source 8-2, and the seed pump source 8-1, while simultaneously controlling the optical shutter 7 to block the optical path.

[0080] When the STM32 control board 3 fails to receive the heartbeat command frame sent by the FPGA main control board 2 for several consecutive times, causing the watchdog counter to overflow, the STM32 control board 3 locks the current drive current setting value and temperature setting value of the seed pump source 8-1 and the preamplifier pump source 8-2, and enters the internal safety holding loop, continuously refreshing the output of the drive circuit 3-1 and the temperature control circuit 3-2 to keep the seed pump source 8-1 and the preamplifier pump source 8-2 in a controlled state.

[0081] The specific embodiments of the present invention have been described above, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0082] In the description of this invention, it should be understood that the terms "upper," "lower," "inner," "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The simple fact that certain measures are recited in mutually different dependent claims does not indicate that combinations of these measures cannot be used for improvement. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A multi-range modular electronic control system for multi-cascaded high-power ultrafast lasers, characterized in that, The system includes a host computer, an FPGA main control board, an STM32 control board, a high-power pump driver board, and seed pump sources, preamplifier pump sources, and power amplifier pump sources arranged along the optical path. The host computer is communicatively connected to the FPGA main control board. The FPGA main control board is communicatively connected to both the STM32 control board and the high-power pump driver board. The STM32 control board integrates a drive circuit and a temperature control circuit. The drive circuit is connected to the drive input terminals of the seed pump source and the preamplifier pump source. The temperature control circuit is connected to the temperature control component integrated inside the seed pump source and the temperature control module located on the preamplifier pump source. The control output terminal of the FPGA main control board is connected to the control terminal of the high-power pump driver board. The power output terminal of the high-power pump driver board is connected to the power amplifier pump source. The FPGA main control board is configured to send heartbeat command frames to the STM32 control board at a preset period. The STM32 control board has a watchdog counter, which is configured to maintain the drive current output and temperature control of the seed pump source and the preamplifier pump source according to internally preset safety parameters when the watchdog counter overflows due to the continuous failure to receive the heartbeat command frame.

2. The multi-range modular electronic control system according to claim 1, characterized in that, The STM32 control board is configured to switch the control mode to internal closed-loop control mode and enter a safety hold loop when the watchdog counter overflows. In the safety hold loop, the STM32 control board continuously refreshes the output of the drive circuit and the temperature control circuit to maintain the seed pump source and the preamplifier pump source in a controlled state.

3. The multi-range modular electronic control system according to claim 1, characterized in that, The system also includes a PD monitoring circuit board, the input of which is optically coupled to the optical output of the seed pump source. The FPGA main control board is configured to capture the rising or falling edge of the pulse signal from the PD monitoring circuit board, calculate the period of adjacent pulses through a timer and convert it into a measured repetition frequency. When the error between the measured repetition frequency and the target repetition frequency is within a preset threshold range and multiple consecutive pulses meet the condition, the seed pump source is determined to be in a mode-locked state and the internal status flag is set to a high level.

4. The multi-range modular electronic control system according to claim 3, characterized in that, The FPGA main control board is also configured to set the internal status flag to a low level and trigger an alarm interrupt when the measured repetition frequency is detected to be out of tolerance or the pulse signal is lost.

5. The multi-range modular electronic control system according to claim 3, characterized in that, The FPGA main control board is configured to enable the STM32 control board to power the seed pump source and perform temperature control; monitor the internal status flag bit, and after the internal status flag bit jumps to the high level, delay for a first preset time to enable the preamplifier pump source and perform temperature control; after receiving status information sent by the STM32 control board through the communication connection indicating that the current fluctuation amplitude of the preamplifier pump source is within a preset threshold range, delay for a second preset time to enable the high-power pump driver board to power the power amplifier pump source.

6. The multi-range modular electronic control system according to claim 1, characterized in that, It also includes a pulse selector disposed on the optical path between the pump source of the preamplifier and the pump source of the postamplifier; the FPGA main control board is communicatively connected to the pulse selector and is configured to generate instruction frames containing frequency division, delay and pulse width information according to the parameters set by the host computer and send them to the pulse selector.

7. The multi-range modular electronic control system according to claim 1, characterized in that, It also includes an optical shutter located on the output optical path after the pump source of the post-amplifier, the optical shutter having an analog voltage pin and a digital signal pin; the analog control terminal of the FPGA main control board is connected to the analog voltage pin, and the digital control terminal is connected to the digital signal pin; the FPGA main control board is configured to output an analog voltage through the analog control terminal to adjust the output power, and to output a signal through the digital control terminal to control the optical shutter to perform optical path blocking when an alarm interruption is received.

8. The multi-range modular electronic control system according to claim 1, characterized in that, The driving circuit includes an operational amplifier chip, a voltage divider circuit, and a sampling resistor; the non-inverting input terminal of the operational amplifier chip is connected to the voltage divider circuit, the inverting input terminal is connected to the sampling resistor, and the output terminal is connected to the control electrode of the driving MOSFET; the operational amplifier chip is configured to adjust the conduction level of the driving MOSFET by comparing the difference between the reference voltage and the feedback voltage.

9. The multi-range modular electronic control system according to claim 1, characterized in that, The temperature control component integrated inside the seed pump source and the temperature control module on the preamplifier pump source both include a thermoelectric cooler and a thermistor; the temperature control circuit includes a temperature control chip with a built-in analog-to-digital converter and an H-bridge drive circuit; the temperature control chip is configured to generate an adjustment command based on the error between the temperature fed back by the thermistor and the target temperature; the H-bridge drive circuit is configured to receive the adjustment command and output current to the thermoelectric cooler.

10. The multi-range modular electronic control system according to claim 1, characterized in that, The driving circuit includes a first range driving channel and a second range driving channel. The first range driving channel is used to output a driving current of 0 to 800mA to the seed pump source, and the second range driving channel is used to output a driving current of 0 to 10A to the preamplifier pump source. The high-power pump drive board is used to output a driving current of 0 to 20A to the power amplifier pump source.

Images