High and low voltage enable circuit without bandgap reference
Patent Information
- Application Number
- CN202611366172.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-04
- Publication Date
- 2026-10-16
AI Technical Summary
但是此方案需要关机状态下产生基准电压的带隙基准源保持工作，虽然得到了准确的阈值但代价是更复杂的电路以及更大的关机电流，同时比较器只能接受低压输入，在高压系统中应用将会受限
[0018] The circuit structure proposed in this invention utilizes a built-in simple reference circuit (A1) to generate the comparison reference required for judgment, avoiding the dependence on bandgap references found in traditional enable circuits while possessing an accurate threshold. It also introduces a high-voltage protection module (A2) to protect the gates of NMOS transistors M3 and M4 after EN enters the high-voltage range, enabling the circuit to be directly applied in high-voltage systems. The comparison voltage is converted into a comparison current (A3) and then used for V... GS It generates a low-voltage source, avoiding the need for level conversion circuits and directly outputting low-voltage logic, thus providing convenience for circuit applications.
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Figure CN122924488A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic technology, specifically relating to integrated circuit technology. Background Technology
[0002] In most integrated circuit designs, the enable circuit is crucial for controlling the overall circuit's start and stop. Traditional enable circuits generally come in two forms. The first type is constructed using a Schmitt trigger, such as... Figure 1 As shown, M1, M2, M5, and M7 are low-voltage PMOS transistors, M3, M4, M6, and M8 are low-voltage NMOS transistors, EN is the input enable signal, ENB is the output, VCC is the low-voltage power supply voltage, and GND represents ground. This architecture achieves enable hysteresis by switching M5 and M6 between different states. The enable threshold of this structure is strongly correlated with the VTH of the MOS transistors; therefore, the enable threshold will vary significantly with process technology and temperature. Furthermore, the EN input is directly connected to the gate of the MOS transistors, so EN cannot be connected to a high voltage.
[0003] Another type is constructed using comparators, such as... Figure 2 As shown, M1, M2, M3, and M9 are low-voltage NMOS transistors, M4, M5, M6, M7, M8, M10, and M11 are low-voltage PMOS transistors, EN is the input enable signal, V_ref1 and V_vef2 are reference voltages, ENB is the output, VCC is the low-voltage power supply voltage, and GND represents ground. The comparator enable architecture operates on the principle of an open-loop operational amplifier. The EN input is connected to the non-inverting input of the op-amp, and the reference voltage is connected to the inverting input. When EN is lower than the reference voltage, the op-amp output is low; when EN is higher than the reference voltage, the op-amp output is high. Precise hysteresis is achieved by switching different reference voltages. However, this scheme requires the bandgap reference source that generates the reference voltage to remain operational while the system is off. Although an accurate threshold is obtained, the cost is more complex circuitry and a larger shutdown current. Furthermore, the comparator can only accept low-voltage inputs, which limits its application in high-voltage systems.
[0004] In summary, traditional enable circuits suffer from problems such as reliance on bandgap references, inaccurate threshold values, and inability to withstand high voltages. To address this issue, it is necessary to design an enable circuit that can withstand high voltages without requiring a bandgap reference. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a high and low voltage enable circuit that does not require a bandgap reference, can obtain an accurate enable threshold without a bandgap reference, and can work under both high and low voltage conditions.
[0006] The technical solution adopted by the present invention to solve the aforementioned technical problem is as follows:
[0007] A high / low voltage enable circuit that does not require a bandgap reference includes:
[0008] The high-voltage protection module has an enable signal EN connected to its first input terminal, an output terminal connected to the first input terminal of the voltage-to-current module, and a second input terminal connected to the second output terminal of the voltage-to-current module.
[0009] The voltage-to-current module has its input terminal connected to the first output terminal of the high-voltage protection module, its first output terminal connected to the first input terminal of the comparison output module, and its second output terminal connected to the second input terminal of the high-voltage protection module.
[0010] A simple reference current module has its first input terminal connected to the system voltage VIN, its second input terminal connected to the second output terminal of the comparison output module, its first output terminal connected to the second input terminal of the comparison output module, and its second output terminal connected to the third input terminal of the comparison output module.
[0011] The comparison output module has its first output terminal of the voltage-to-current module connected to its first input terminal, its first output terminal of the simple reference current module connected to its second input terminal, and its second output terminal of the simple reference current module connected to its third input terminal. The first output terminal of the comparison output module outputs the judgment logic ENB, and the second output terminal of the comparison output module is connected to the second input terminal of the simple reference current module.
[0012] The voltage-to-current conversion module and the comparison output module are connected via mirrored MOSFETs or directly via control lines.
[0013] The high-voltage protection module consists of a third resistor (R3), a fourth resistor (R4), a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), a fifth transistor (Q5), and a sixth transistor (Q6). The collector and base of the fifth transistor (Q5) are connected, and the collector of the fifth transistor (Q5) is connected to the enable signal terminal EN through the fourth resistor (R4). The emitter of the fifth transistor (Q5) is connected to the collector of the sixth transistor (Q6), and the base of the fifth transistor serves as the first output terminal of the high-voltage protection module, connected to the first input terminal of the voltage-to-current conversion module. The emitter of the sixth transistor (Q6) is grounded, and the base of the sixth transistor (Q6) is connected to the collector of the fourth transistor (Q4). Connections: The collector and base of the third transistor (Q3) are connected, the emitter of the third transistor (Q3) is grounded, and the base of the third transistor (Q3) is connected to the base of the fourth transistor (Q4); the collector of the first transistor (Q1) is connected to the collector of the third transistor (Q3), the emitter of the first transistor (Q1) is connected to the system voltage VIN through the third resistor (R3), and the base of the first transistor (Q1) is connected as the second input terminal of the high-voltage protection module and the second output terminal of the voltage-to-current module; the emitter of the second transistor (Q2) is connected to the system voltage VIN, the base of the second transistor (Q2) is connected to the base of the first transistor (Q1), and the collector of the second transistor (Q2) is connected to the collector of the fourth transistor (Q4).
[0014] The voltage-to-current conversion module consists of a first resistor R1, a second resistor R2, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, and a sixth MOSFET M6. The source of the first MOSFET M1 is connected to the system voltage VIN, and its gate is connected to its drain. The gate of the first MOSFET M1 is connected to the gate of the second MOSFET M2, and the source of the second MOSFET M2 is connected to the system voltage VIN through the second resistor R2. The drain of the third MOSFET M3 is connected to the drain of the first MOSFET M1, and its source is connected to... The first resistor R1 is grounded; the drain of the fourth MOSFET M4 is connected to the drain of the second MOSFET M2, the gate of the fourth MOSFET M4 is connected to the gate of the third MOSFET M3, and the source of the fourth MOSFET M4 is grounded through the first resistor R1; the source of the fifth MOSFET M5 is connected to the system voltage VIN, the gate of the fifth MOSFET M5 is connected to the gate of the second MOSFET M2, and the drain of the fifth MOSFET M5 is connected to the drain of the sixth MOSFET M6; the source of the sixth MOSFET M6 is grounded, and the drain of the sixth MOSFET M6 is connected to its gate; the gate of the sixth MOSFET M6 is connected to the first input terminal of the comparator output module.
[0015] The simple reference current generation module consists of a fifth resistor R5, a sixth resistor R6, a seventh transistor Q7, an eighth transistor Q8, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, a thirteenth MOSFET M13, and a fourteenth MOSFET M14. The emitters of the seventh transistor Q7 and the eighth transistor Q8 are connected to the system voltage VIN. The base and collector of the seventh transistor Q7 are connected to one end of the fifth resistor R5. The base of the eighth transistor Q8 is connected to the other end of the fifth resistor R5, and the collector of the eighth transistor Q8 is connected to the gate of the ninth MOSFET M9. One end of the sixth resistor R6 is connected to the system voltage VIN, and the other end is connected to the source of the ninth MOSFET M9. The drain of the ninth MOSFET M9... The drain of the 10th MOSFET M10 is connected to the drain of the 10th MOSFET M10, and the source of the 10th MOSFET M10 is grounded; the drain of the 7th MOSFET M7 is connected to one end of the 5th resistor R5, and the source of the 7th MOSFET M7 is grounded; the gates of the 7th MOSFET M7, the 8th MOSFET M8, the 10th MOSFET M10, the 11th MOSFET M11, and the 13th MOSFET M13 are connected to the gate of the 11th MOSFET M11; the source of the 11th MOSFET M11 is grounded, and the drain of the 11th MOSFET M11 is connected to the drain of the 12th MOSFET M12; the drain of the 13th MOSFET M13 is connected to the drain of the 12th MOSFET M12; the source of the 12th MOSFET M12 is connected to the system voltage VIN, and the gate and drain of the 12th MOSFET M12 are connected; the gate of the 12th MOSFET M12 is connected to the second input terminal of the comparator output module.
[0016] The comparison output module consists of the fifteenth MOSFET M15, the sixteenth MOSFET M16, the seventeenth MOSFET M17, the eighteenth MOSFET M18, the nineteenth MOSFET M19, the twentieth MOSFET M20, and the twenty-first MOSFET M21. The source of the fifteenth MOSFET M15 is connected to the system voltage VIN, and its gate and drain are connected. The source of the sixteenth MOSFET M16 is connected to the drain of the fifteenth MOSFET M15, its gate and drain are connected, and its drain is connected to the drain of the seventeenth MOSFET M17. The source of the seventeenth MOSFET M17 is grounded. The source of the eighteenth MOSFET M18 and the source of the twentieth MOSFET M20 are connected to the drain of the sixteenth MOSFET M16. The drain of the eighteenth MOSFET M18 is connected to the drain of the nineteenth MOSFET M19, and the source of the nineteenth MOSFET M19 is grounded. The gate of the twentieth MOSFET M20 is connected to the drain of the eighteenth MOSFET M18 and the drain of the nineteenth MOSFET M19. The source of the twenty-first MOSFET M21 is grounded. The gate of the twenty-first MOSFET M21 is connected to the gate of the twentieth MOSFET M20. The drain of the twenty-first MOSFET M21 and the drain of the twentieth MOSFET M20 are connected to the output terminal ENB of the comparator output module.
[0017] The beneficial effects of this invention are:
[0018] The circuit structure proposed in this invention utilizes a built-in simple reference circuit (A1) to generate the comparison reference required for judgment, avoiding the dependence on bandgap references found in traditional enable circuits while possessing an accurate threshold. It also introduces a high-voltage protection module (A2) to protect the gates of NMOS transistors M3 and M4 after EN enters the high-voltage range, enabling the circuit to be directly applied in high-voltage systems. The comparison voltage is converted into a comparison current (A3) and then used for V... GS It generates a low-voltage source, avoiding the need for level conversion circuits and directly outputting low-voltage logic, thus providing convenience for circuit applications. Attached Figure Description
[0019] Figure 1 This is a traditional Schmitt trigger circuit diagram;
[0020] Figure 2 This is the enable circuit diagram for a traditional comparator structure.
[0021] Figure 3 This is the circuit diagram of the present invention;
[0022] Figure 4 This is another circuit diagram of the present invention;
[0023] Figure 5 This is a transient simulation waveform diagram of the present invention;
[0024] Figure 6 The waveform diagram is a simulation diagram of the hysteresis characteristics of the present invention. Detailed Implementation
[0025] Example 1
[0026] This invention provides a high / low voltage enable circuit that does not require a bandgap reference, comprising:
[0027] The high-voltage protection module has an enable signal EN connected to its first input terminal, an output terminal connected to the first input terminal of the voltage-to-current module, and a second input terminal connected to the second output terminal of the voltage-to-current module.
[0028] The voltage-to-current module has its input terminal connected to the first output terminal of the high-voltage protection module, its first output terminal connected to the first input terminal of the comparison output module, and its second output terminal connected to the second input terminal of the high-voltage protection module.
[0029] A simple reference current module has its first input terminal connected to the system voltage VIN, its second input terminal connected to the second output terminal of the comparison output module, its first output terminal connected to the second input terminal of the comparison output module, and its second output terminal connected to the third input terminal of the comparison output module.
[0030] The comparison output module has its first output terminal of the voltage-to-current module connected to its first input terminal, its first output terminal of the simple reference current module connected to its second input terminal, and its second output terminal of the simple reference current module connected to its third input terminal. The first output terminal of the comparison output module outputs the judgment logic ENB, and the second output terminal of the comparison output module is connected to the second input terminal of the simple reference current module.
[0031] The voltage-to-current conversion module and the comparison output module are connected via mirrored MOSFETs or directly via control lines.
[0032] The high-voltage protection module consists of a third resistor (R3), a fourth resistor (R4), a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), a fifth transistor (Q5), and a sixth transistor (Q6). The collector and base of the fifth transistor (Q5) are connected, and the collector of the fifth transistor (Q5) is connected to the enable signal terminal EN through the fourth resistor (R4). The emitter of the fifth transistor (Q5) is connected to the collector of the sixth transistor (Q6), and the base of the fifth transistor serves as the first output terminal of the high-voltage protection module, connected to the first input terminal of the voltage-to-current conversion module. The emitter of the sixth transistor (Q6) is grounded, and the base of the sixth transistor (Q6) is connected to the collector of the fourth transistor (Q4). Electrode connections: The collector and base of the third transistor (Q3) are connected, the emitter of the third transistor (Q3) is grounded, and the base of the third transistor (Q3) is connected to the base of the fourth transistor (Q4); the collector of the first transistor (Q1) is connected to the collector of the third transistor (Q3), the emitter of the first transistor (Q1) is connected to the system voltage VIN through the third resistor (R3), and the base of the first transistor is connected to the second input terminal of the voltage-to-current module as the second output terminal of the high-voltage protection module; the emitter of the second transistor (Q2) is connected to the system voltage VIN, the base of the second transistor (Q2) is connected to the base of the first transistor (Q1), and the collector of the second transistor (Q2) is connected to the collector of the fourth transistor (Q4).
[0033] The voltage-to-current conversion module consists of a first resistor R1, a second resistor R2, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, and a sixth MOSFET M6. The source of the first MOSFET M1 is connected to the system voltage VIN, and its gate is connected to its drain. The gate of the first MOSFET M1 is connected to the gate of the second MOSFET M2, and the source of the second MOSFET M2 is connected to the system voltage VIN through the second resistor R2. The drain of the third MOSFET M3 is connected to the drain of the first MOSFET M1, and its source is connected to... The first resistor R1 is grounded; the drain of the fourth MOSFET M4 is connected to the drain of the second MOSFET M2, the gate of the fourth MOSFET M4 is connected to the gate of the third MOSFET M3, and the source of the fourth MOSFET M4 is grounded through the first resistor R1; the source of the fifth MOSFET M5 is connected to the system voltage VIN, the gate of the fifth MOSFET M5 is connected to the gate of the second MOSFET M2, and the drain of the fifth MOSFET M5 is connected to the drain of the sixth MOSFET M6; the source of the sixth MOSFET M6 is grounded, and the drain of the sixth MOSFET M6 is connected to its gate; the gate of the sixth MOSFET M6 is connected to the first input terminal of the comparator output module.
[0034] The simple reference current generation module consists of a fifth resistor R5, a sixth resistor R6, a seventh transistor Q7, an eighth transistor Q8, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, a thirteenth MOSFET M13, and a fourteenth MOSFET M14. The emitters of the seventh transistor Q7 and the eighth transistor Q8 are connected to the system voltage VIN. The base and collector of the seventh transistor Q7 are connected to one end of the fifth resistor R5. The base of the eighth transistor Q8 is connected to the other end of the fifth resistor R5, and the collector of the eighth transistor Q8 is connected to the gate of the ninth MOSFET M9. One end of the sixth resistor R6 is connected to the system voltage VIN, and the other end is connected to the source of the ninth MOSFET M9. The drain of the ninth MOSFET M9... The drain of the 10th MOSFET M10 is connected to the drain of the 10th MOSFET M10, and the source of the 10th MOSFET M10 is grounded; the drain of the 7th MOSFET M7 is connected to one end of the 5th resistor R5, and the source of the 7th MOSFET M7 is grounded; the gates of the 7th MOSFET M7, the 8th MOSFET M8, the 10th MOSFET M10, the 11th MOSFET M11, and the 13th MOSFET M13 are connected to the gate of the 11th MOSFET M11; the source of the 11th MOSFET M11 is grounded, and the drain of the 11th MOSFET M11 is connected to the drain of the 12th MOSFET M12; the drain of the 13th MOSFET M13 is connected to the drain of the 12th MOSFET M12; the source of the 12th MOSFET M12 is connected to the system voltage VIN, and the gate and drain of the 12th MOSFET M12 are connected; the gate of the 12th MOSFET M12 is connected to the second input terminal of the comparator output module.
[0035] The comparison output module consists of the fifteenth MOSFET M15, the sixteenth MOSFET M16, the seventeenth MOSFET M17, the eighteenth MOSFET M18, the nineteenth MOSFET M19, the twentieth MOSFET M20, and the twenty-first MOSFET M21. The source of the fifteenth MOSFET M15 is connected to the system voltage VIN, and its gate and drain are connected. The source of the sixteenth MOSFET M16 is connected to the drain of the fifteenth MOSFET M15, its gate and drain are connected, and its drain is connected to the drain of the seventeenth MOSFET M17. The source of the seventeenth MOSFET M17 is grounded. The source of the eighteenth MOSFET M18 and the source of the twentieth MOSFET M20 are connected to the drain of the sixteenth MOSFET M16. The drain of the eighteenth MOSFET M18 is connected to the drain of the nineteenth MOSFET M19, and the source of the nineteenth MOSFET M19 is grounded. The gate of the twentieth MOSFET M20 is connected to the drain of the eighteenth MOSFET M18 and the drain of the nineteenth MOSFET M19. The source of the twenty-first MOSFET M21 is grounded. The gate of the twenty-first MOSFET M21 is connected to the gate of the twentieth MOSFET M20. The drain of the twenty-first MOSFET M21 and the drain of the twentieth MOSFET M20 are connected to the output terminal ENB of the comparator output module.
[0036] A more detailed explanation of the principles of this invention:
[0037] In order to be compatible with high voltage and convert the judgment voltage into judgment current, this invention compares the current related to EN and the reference current through M18 and M19 after the input signal and outputs the judgment logic in the low voltage domain.
[0038] First is the current I related to EN. M19 The voltage input at pin EN is transmitted through resistors to the gate terminals of NMOS transistors M3 and M4. The total current flowing through M3 and M4 at this time is:
[0039] (1-1)
[0040] To ensure that the transistor sizes of M3 and M4 are kept consistent, it can be known that I M3 =I M4 Because I M1 =I M3 I M2 =I M4 Then we can get: (1-2)
[0041] Assuming the total transfer ratio of current mirrors M1, M5, M6, and M19 is 1:N, then we can know that:
[0042] (1-3)
[0043] Secondly, there is the generation of the reference current. When the system is powered on with input VIN, the base voltages of PNP transistors Q7 and Q8 fall across resistor R5. Assuming the emitter area ratio of transistors Q7 to Q8 is M:1, then:
[0044] (1-4)
[0045] Similarly, assuming the total transfer ratio of current mirrors M7, M11, M12, M13, and M18 is 1:B, then we can know that:
[0046] (1-5)
[0047] Furthermore, the low-voltage domain power supply voltage is from PMOS transistors M15 and M16 The specific value depends on the size ratio of M7 to M17, i.e., I. M15 The magnitude of the current and the dimensions (W / L) of the M15 and M16 transistors. 15 (W / L) 16 Its relationship with I M15 Proportional to (W / L) 15 (W / L) 16 Inversely proportional.
[0048] Reference current I M18 Dependent on VIN, then I after power-on M18 It exists when the device is powered off. M19 =0, at this time ENB is pulled low, corresponding to the power-off state. In the power-on state, EN starts rising from 0, and when EN exceeds the threshold values of NMOS transistors M3 and M4, I... M19 There is a current starting, and as EN rises further, I... M19 It will rise in sync with EN, until I M19 =I M18 Right now:
[0049] (1-6)
[0050] If EN rises further after reaching the inversion point of ENB, ENB will be pulled up, thus turning on the chip. Transforming equation (1-6) yields:
[0051] (1-7)
[0052] Due to V GS Depends on the threshold voltage V of the NMOS transistor TH It is inversely proportional to temperature, V T Thermal voltage is proportional to temperature, so the EN threshold with zero temperature coefficient at room temperature can be obtained by setting the circuit appropriately.
[0053] As EN increases further, since the ratio of PMOS transistors M1 to M2 is 1:4, therefore, in I... M1 I M2 During the initial increase, because the current is very small, the effect of R2 is not obvious. At this time, I M2 >I M1 As the current increases with EN, the current-limiting effect of R2 gradually becomes more prominent. M2 While increasing, move towards I M1 Approach, until I M2 =I M1 At this moment, the base voltage of transistor Q1 is at the critical state of reversal. When EN rises further, I... M2 M1 That is I M2 M4 The base voltage of transistor Q1 will be pulled from high to low, corresponding to the turning on of transistors Q1 and Q2. The emitter area ratio of transistors Q1 to Q2 and Q3 to Q4 is 1:1. Due to the presence of resistor R3, when Q1 and Q2 are turned on, Q3 and Q4 form a comparator that pulls the base of transistor Q6 high. At this time, R4, Q5, and Q6 form a current path from EN to ground. Subsequently, when EN rises further, the gate voltage VG_M3 / M4 of NMOS transistors M3 and M4 remains unchanged, and the voltage mainly falls on resistor R4, thereby achieving high-voltage protection and ensuring that EN can be directly connected to VIN in the high-voltage system for enabling. The corresponding high-voltage protection intervention threshold can be adjusted by changing the ratio of M1 and M2.
[0054] In the circuit, M9, M10, and R6 are used for biasing; M13 and M14 achieve hysteresis by changing the current mirror replication ratio.
[0055] The threshold voltage and gate voltage limiting characteristics of the NMOS transistor VG_M3 / M4 in a 20V high-voltage system are as follows: Figure 5 As shown, the hysteresis characteristics of EN are as follows: Figure 6 As shown.
[0056] Figure 3 The circuit shown is merely a preferred embodiment of the present invention, but the scope of protection of this patent is not limited thereto. Any modifications or changes made by those skilled in the art within the scope of the present invention, including alterations to the local structure of the circuit or other non-substantial substitutions or modifications, are within the scope of protection of this patent.
[0057] Example 2
[0058] like Figure 4 Embodiment 2 is another equivalent circuit, providing a high / low voltage enable circuit that does not require a bandgap reference, comprising:
[0059] The high-voltage protection module has an enable signal EN connected to its first input terminal, an output terminal connected to the first input terminal of the voltage-to-current module, and a second input terminal connected to the second output terminal of the voltage-to-current module.
[0060] The voltage-to-current module has its input terminal connected to the first output terminal of the high-voltage protection module, its first output terminal connected to the first input terminal of the comparison output module, and its second output terminal connected to the second input terminal of the high-voltage protection module.
[0061] A simple reference current module, whose first input terminal is connected to the system voltage VIN, and whose first output terminal is connected to the second input terminal of the comparison output module;
[0062] The comparison output module has its voltage-to-current module output connected to the first input of the comparison output module, and its simple reference current module first output connected to the second input of the comparison output module. The first output of the comparison output module outputs the judgment logic ENB.
[0063] The high-voltage protection module consists of a third resistor R30, a fourth resistor R40, a first transistor Q10, a fifth MOSFET N5, a sixth MOSFET N6, a seventh MOSFET N7, an eighth MOSFET N8, and a ninth MOSFET N9. The collector of the first transistor Q10 is connected to the enable signal EN input terminal through the fourth resistor R40. The base and collector of the first transistor Q10 are shorted. The emitter of the first transistor Q10 is connected to the collector of the ninth MOSFET N9. The source of the ninth MOSFET N9 is grounded. The gate of the ninth MOSFET N9 is connected to the collector of the sixth MOSFET N8. The drain of transistor N6 and the drain of transistor N8 are connected; the source of transistor N6 is grounded, the gate of transistor N6 is connected to the gate of transistor N5, the source of transistor N5 is grounded, the drain of transistor N5 is shorted to its gate, the drain of transistor N5 is connected to the drain of transistor N7, the source of transistor N7 is connected to the system voltage VIN through the third resistor R30, the gate of transistor N7 is connected to the gate of transistor N8, and the source of transistor N8 is connected to the system voltage VIN.
[0064] The voltage-to-current conversion module consists of a first resistor R10, a second resistor R20, a first MOSFET N1, a second MOSFET N2, a third MOSFET N3, and a fourth MOSFET N4. The source of the third MOSFET N3 is connected to the system voltage VIN through the first resistor R10. The source of the third MOSFET N3 is connected to the source of the fourth MOSFET N4. The gate of the third MOSFET N3 is connected to the gate of the fourth MOSFET N4. The drain of the third MOSFET N3 is connected to the drain of the first MOSFET N1. The gate and drain of the first MOSFET N1 are shorted together. The source of the first MOSFET N1 is grounded. The gate of the first MOSFET N1 is connected to the gate of the second MOSFET N2. The source of the second MOSFET N2 is grounded through the second resistor R20. The drain of the second MOSFET N2 is connected to the drain of the fourth MOSFET N4.
[0065] The simple reference current generation module consists of a fifth resistor R50, a sixth resistor R60, a second transistor Q20, a third transistor Q30, a tenth MOSFET N10, an eleventh MOSFET N11, a twelfth MOSFET N12, and a fourteenth MOSFET N14. The emitter of the second transistor Q20 is grounded, and its base and collector are shorted. The collector of the second transistor Q20 is connected to the drain of the tenth MOSFET N10 through the fifth resistor R50. The source of the tenth MOSFET N10 is connected to the system voltage VIN. The gate of the tenth MOSFET N10 is connected to the gate of the eleventh MOSFET N11 and the gate of the twelfth MOSFET N14. The gate of transistor N12 is connected to the system voltage VIN. The source of the eleventh MOSFET N1 and the source of the twelfth MOSFET N12 are connected to the system voltage VIN. The drain of the eleventh MOSFET N11 is connected to the collector of the third transistor Q30. The base of the third transistor Q30 is connected to the drain of the tenth MOSFET N10. The emitter of the third transistor Q30 is grounded. The gate and drain of the twelfth MOSFET N12 are shorted. The drain of the twelfth MOSFET N12 is connected to the drain of the fourteenth MOSFET N14. The gate of the fourteenth MOSFET N14 is connected to the collector of the third transistor Q30. The source of the fourteenth MOSFET N14 is grounded through the sixth resistor R60.
[0066] The comparison output module consists of thirteenth MOSFET N13, fifteenth MOSFET N15, sixteenth MOSFET N16, seventeenth MOSFET N17, eighteenth MOSFET N18, nineteenth MOSFET N19, twentieth MOSFET N20, twenty-first MOSFET N21, twenty-second MOSFET N22, twenty-third MOSFET N23, and twenty-fourth MOSFET N24. The source of thirteenth MOSFET N13 is connected to the system voltage VIN, and the gate of thirteenth MOSFET N13 is connected to the output terminal of the simple reference current module. The drain of N13 is connected to the drain of the fifteenth MOSFET N15; the gate and drain of the fifteenth MOSFET N15 are shorted, the source of the fifteenth MOSFET N15 is grounded, the gate of the fifteenth MOSFET N15 is connected to the gate of the sixteenth MOSFET N16, the source of the sixteenth MOSFET N16 is grounded, the drain of the sixteenth MOSFET N16 is connected to the drain of the seventeenth MOSFET N17, the gate and drain of the seventeenth MOSFET N17 are connected, the source of the seventeenth MOSFET N17 is connected to the drain of the eighteenth MOSFET N18, and the eighteenth MOSFET N18... The gate and drain of the 18th MOSFET N18 are shorted together, and the source of the 19th MOSFET N19 is connected to the system voltage VIN. The gate of the 19th MOSFET N19 is connected to the gate of the 16th MOSFET N16, and the source of the 19th MOSFET N19 is grounded. The gate of the 19th MOSFET N19 is connected to the gate of the 20th MOSFET N20, and the drain of the 19th MOSFET N19 is connected to the drain of the 20th MOSFET N20. The drain of the 20th MOSFET N20 is connected to the drain of the 21st MOSFET N21, and the source of the 22nd MOSFET N22 is connected to the drain of the 22nd MOSFET N23. The source of MOSFET N22 is connected to the drain of the seventeenth MOSFET N17. The drains of the twenty-second MOSFET N22 and the twenty-third MOSFET N23 are connected to the output terminal ENB of the comparator output module. The source of the twenty-third MOSFET N23 is grounded, and the gate of the twenty-third MOSFET N23 is connected to the gate of the first MOSFET N1. The drain of the twenty-fourth MOSFET N24 is connected to the source of the twentieth MOSFET N20. The drain of the twenty-fourth MOSFET N24 is grounded, and the gate of the twenty-fourth MOSFET N24 is connected to the output terminal ENB of the comparator output module.
[0067] Existing enable circuits based on MOSFET current comparison determine the enable level by comparing the currents of two MOSFETs, resulting in a simple circuit structure. However, this circuit lacks hysteresis. When the magnitudes of the two comparison currents are close, the internal intermediate node tends to maintain the power supply's intermediate level, causing the output enable signal to fall into a metastable state. When the input signal changes slowly, or when power supply noise or temperature drift is introduced into the circuit, the output enable signal is prone to jitter and false flips. Furthermore, in the metastable region, the subsequent inverter generates a continuous power-to-ground shoot-through current, increasing static power consumption. In addition, the circuit's decision threshold is significantly affected by MOSFET process variations, operating temperature, and supply voltage, resulting in poor consistency between chips and uncertainty in the output logic state at power-on, thus reducing the overall circuit reliability.
Claims
1. A high / low voltage enable circuit that does not require a bandgap reference, characterized in that: include: The high-voltage protection module has an enable signal EN connected to its first input terminal, an output terminal connected to the first input terminal of the voltage-to-current module, and a second input terminal connected to the second output terminal of the voltage-to-current module. The voltage-to-current module has its input terminal connected to the first output terminal of the high-voltage protection module, its first output terminal connected to the first input terminal of the comparison output module, and its second output terminal connected to the second input terminal of the high-voltage protection module. A simple reference current module has its first input terminal connected to the system voltage VIN, its second input terminal connected to the second output terminal of the comparison output module, its first output terminal connected to the second input terminal of the comparison output module, and its second output terminal connected to the third input terminal of the comparison output module. The comparison output module has its first output terminal of the voltage-to-current module connected to its first input terminal, its first output terminal of the simple reference current module connected to its second input terminal, and its second output terminal of the simple reference current module connected to its third input terminal. The first output terminal of the comparison output module outputs the judgment logic ENB, and the second output terminal of the comparison output module is connected to the second input terminal of the simple reference current module. The voltage-to-current conversion module and the comparison output module are connected via mirrored MOSFETs or directly via control lines.
2. The high and low voltage enable circuit without bandgap reference according to claim 1, characterized in that, The high-voltage protection module consists of a third resistor (R3), a fourth resistor (R4), a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), a fifth transistor (Q5), and a sixth transistor (Q6). The collector and base of the fifth transistor (Q5) are connected. The collector of the fifth transistor (Q5) is connected to the enable signal terminal EN through the fourth resistor (R4). The emitter of the fifth transistor (Q5) is connected to the collector of the sixth transistor (Q6). The base of the fifth transistor is connected to the first output terminal of the high-voltage protection module and the first input terminal of the voltage-to-current module. The emitter of the sixth transistor (Q6) is grounded, and the base of the sixth transistor (Q6) is connected to the collector of the fourth transistor (Q4). The collector and base of the third transistor (Q3) are connected, and the emitter of the third transistor (Q3) is grounded. 3) The base of the transistor is connected to the base of the fourth transistor (Q4); the collector of the first transistor (Q1) is connected to the collector of the third transistor (Q3), the emitter of the first transistor (Q1) is connected to the system voltage VIN through the third resistor (R3), and the base of the first transistor (Q1) is connected to the second output terminal of the voltage-to-current module as the second input terminal of the high voltage protection module; the emitter of the second transistor (Q2) is connected to the system voltage VIN, the base of the second transistor (Q2) is connected to the base of the first transistor (Q1), and the collector of the second transistor (Q2) is connected to the collector of the fourth transistor (Q4).
3. The high and low voltage enable circuit without bandgap reference according to claim 1, characterized in that, The voltage-to-current module consists of a first resistor (R1), a second resistor (R2), a first MOSFET (M1), a second MOSFET (M2), a third MOSFET (M3), a fourth MOSFET (M4), a fifth MOSFET (M5), and a sixth MOSFET (M6). The source of the first MOSFET (M1) is connected to the system voltage VIN, and its gate and drain are connected. The gate of the first MOSFET (M1) is connected to the gate of the second MOSFET (M2), and the source of the second MOSFET (M2) is connected to the system voltage VIN through the second resistor (R2). The drain of the third MOSFET (M3) is connected to the drain of the first MOSFET (M1), and its source is grounded through the first resistor (R1). The drain of the fourth MOSFET (M4) is connected to the drain of the second MOSFET (M2), and the fourth MOSFET... The gate of transistor (M4) is connected to the gate of the third MOSFET (M3), and the source of the fourth MOSFET (M4) is grounded through the first resistor (R1); the source of the fifth MOSFET (M5) is connected to the system voltage VIN, the gate of the fifth MOSFET (M5) is connected to the gate of the second MOSFET (M2), and the drain of the fifth MOSFET (M5) is connected to the drain of the sixth MOSFET (M6); the source of the sixth MOSFET (M6) is grounded, and the drain of the sixth MOSFET (M6) is connected to its gate; the gate of the sixth MOSFET (M6) is connected to the first input terminal of the comparator output module.
4. The high and low voltage enable circuit without bandgap reference according to claim 1, characterized in that, The simple reference current generation module consists of a fifth resistor (R5), a sixth resistor (R6), a seventh transistor (Q7), an eighth transistor (Q8), a seventh MOSFET (M7), an eighth MOSFET (M8), a ninth MOSFET (M9), a tenth MOSFET (M10), an eleventh MOSFET (M11), a twelfth MOSFET (M12), a thirteenth MOSFET (M13), and a fourteenth MOSFET (M14). The emitters of transistors Q7 and Q8 are connected to the system voltage VIN. The base and collector of transistor Q7 are connected to one end of resistor R5. The base of transistor Q8 is connected to the other end of resistor R5. The collector of transistor Q8 is connected to the gate of MOSFET M9. One end of resistor R6 is connected to the system voltage VIN, and the other end is connected to the source of MOSFET M9. The drain of MOSFET M9 is connected to the drain of MOSFET M10, and the source of MOSFET M10 is grounded. The drain of MOSFET M7 is connected to one end of resistor R5. The source of (M7) is grounded. The gates of the seventh MOSFET (M7), the eighth MOSFET (M8), the tenth MOSFET (M10), the eleventh MOSFET (M11), and the thirteenth MOSFET (M13) are connected. The source of the eleventh MOSFET (M11) is grounded. The drain of the eleventh MOSFET (M11) is connected to the drain of the twelfth MOSFET (M12). The drain of the thirteenth MOSFET (M13) is connected to the drain of the twelfth MOSFET (M12). The source of the twelfth MOSFET (M12) is connected to the system voltage VIN. The gate and drain of the twelfth MOSFET (M12) are connected. The gate of the twelfth MOSFET (M12) is connected to the second input terminal of the comparator output module.
5. The high and low voltage enable circuit without bandgap reference according to claim 1, characterized in that, The comparison output module consists of the fifteenth MOSFET (M15), the sixteenth MOSFET (M16), the seventeenth MOSFET (M17), the eighteenth MOSFET (M18), the nineteenth MOSFET (M19), the twentieth MOSFET (M20), and the twenty-first MOSFET (M21). The source of the fifteenth MOSFET (M15) is connected to the system voltage VIN, and its gate and drain are connected. The source of the sixteenth MOSFET (M16) is connected to the drain of the fifteenth MOSFET (M15), and its gate and drain are connected. The drain of the sixteenth MOSFET (M16) is connected to the drain of the seventeenth MOSFET (M17), and the source of the seventeenth MOSFET (M17) is grounded. The source of the eighteenth MOSFET (M18) and the source of the twentieth MOSFET (M20) are connected to the drain of the sixteenth MOSFET (M16). The drain of the eighteenth MOSFET (M18) is connected to the drain of the nineteenth MOSFET (M19), and the source of the nineteenth MOSFET (M19) is grounded. The gate of the twentieth MOSFET (M20) is connected to the drain of the eighteenth MOSFET (M18) and the drain of the nineteenth MOSFET (M19). The source of the twenty-first MOSFET (M21) is grounded, and the gate of the twenty-first MOSFET (M21) is connected to the gate of the twentieth MOSFET (M20). The drain of the twenty-first MOSFET (M21) and the drain of the twentieth MOSFET (M20) are connected to the output terminal ENB of the comparator output module.