Power compatibility method and device for re-timer chip

Abstract

The application provides a power supply compatible method and device of a Retimer chip. The method determines a target chip according to the configuration type of multiple chips, configures a common power supply module according to the target chip, determines the identification information corresponding to the target chip, determines the power supply timing control strategy corresponding to the target chip according to the identification information, and controls the common power supply module according to the power supply timing control strategy, so that the common power supply module supplies power to the target chip according to the power supply timing corresponding to the target chip.

Description

Technical Field

[0001] This application relates to the field of power technology, and in particular to a power compatibility method and apparatus for a Retimer chip. Background Technology

[0002] In existing PCIe Gen6 Retimer (PCI Express 6.0 Retimer) products, different manufacturers have not standardized the definition of the power pins for the Retimer (signal regenerator). Chips from different manufacturers vary in terms of power supply voltage, current requirements, power pin allocation, and power-on sequence. To meet the power supply requirements of different Retimer chips, existing solutions typically adopt the method of developing multiple versions of PCB (Printed Circuit Board) or readjusting the power supply circuit for adaptation, making it difficult for the same hardware platform to be compatible with multiple Retimer chips. Summary of the Invention

[0003] The purpose of this application is to provide a power compatibility method and apparatus for a Retimer chip.

[0004] The embodiments of this application adopt the following technical solution: a power compatibility method for a Retimer chip: The target chip is determined based on the configuration types of multiple chips; Configure the common power module according to the target chip; Determine the identification information corresponding to the target chip; The power timing control strategy corresponding to the target chip is determined based on the identification information; The common power module is controlled according to the power timing control strategy so that the common power module supplies power to the target chip according to the power timing corresponding to the target chip.

[0005] In some embodiments, the method further includes: Map the power pins of multiple chips to a preset common power module; The power supply capacity of the common power module is determined based on the power supply requirements of multiple chips; the power supply capacity of the common power module covers the current requirements of the power pin group of the target chip. Configure the output voltage of the common power module according to the power supply requirements of the target chip, so that the common power module outputs a power supply voltage corresponding to the target chip.

[0006] In some embodiments, different power supply groups in the common power supply module have different maximum output currents; and the maximum output current of the same power supply group in the common power supply module is not less than the maximum current requirement of the corresponding power pin group in the plurality of chips.

[0007] In some embodiments, configuring the common power module according to the target chip includes: Determine the target output voltage of the corresponding common power module based on the type of the target chip; By adjusting the resistor assembly state and / or resistor value in the feedback resistor network of the common power module, the common power module can output the target output voltage.

[0008] In some embodiments, configuring the common power module according to the target chip includes: Based on the current requirements of the power pin group corresponding to the target chip, configure the overcurrent protection parameters of the power group so that the overcurrent protection threshold of the power group matches the current requirements.

[0009] In some embodiments, determining the identification information corresponding to the target chip includes: The chip type identification circuit generates identification information corresponding to the target chip. The chip type identification circuit includes multiple identification configuration terminals, which are respectively connected to a first level terminal or a second level terminal through assembly resistors; By adjusting the assembly state of the assembly resistor, the plurality of identification configuration terminals form identification information that uniquely corresponds to the target chip.

[0010] In some embodiments, the chip type identification circuit includes a first identification configuration terminal, a second identification configuration terminal, and a third identification configuration terminal; Each identification configuration terminal is provided with a first resistor bit connected to the high-level terminal and / or a second resistor bit connected to the low-level terminal to form identification information with a three-bit identification signal. The identification information is used to characterize different types of chips.

[0011] In some embodiments, determining the power timing control strategy corresponding to the target chip based on the identification information includes: Based on the identification information, a target power timing control parameter is selected from multiple sets of power timing control parameters, and the enable state of multiple power groups in the common power module is controlled based on the target power timing control parameter.

[0012] In some embodiments, the target power supply timing control parameters include at least one of the following: The power-on sequence of each power supply group; The power-on time interval between two adjacent power supply groups; The sequence of power outages for each power supply group; The time interval between power outages between two adjacent power supply groups; The timing of the reset signal release for the target chip.

[0013] This application also provides a power compatibility device for a retimer chip, comprising: A common power supply module includes a first power supply group, a second power supply group, a third power supply group, and a fourth power supply group; multiple power supply pins of a target chip among multiple chips are respectively connected to the corresponding power supply groups in the first power supply group, the second power supply group, the third power supply group, and the fourth power supply group; The target chip determination module is configured to determine the target chip based on the configuration types of multiple chips. A configuration module configured to configure the common power supply module according to the target chip; An identification information determination module is configured to determine the identification information corresponding to the target chip; A power timing control strategy determination module is configured to determine a power timing control strategy corresponding to the target chip based on the identification information. The control module is configured to control the common power module according to the power timing control strategy, so that the common power module supplies power to the target chip according to the power timing corresponding to the target chip. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a flowchart illustrating the power compatibility method for the Retimer chip in this application.

[0016] Figure 2 This is a block diagram showing the compatibility design of the power supply group corresponding to the power supply pins in this application.

[0017] Figure 3 This is a timing requirement diagram for one of the Retimer chips in this application.

[0018] Figure 4 This is a timing requirement diagram for another Retimer chip in this application.

[0019] Figure 5This is a block diagram of the power compatibility device for the Retimer chip in this application.

[0020] Figure 6 This is a structural block diagram of the electronic device of this application. Detailed Implementation

[0021] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0022] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0023] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0024] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0025] It should also be understood that although this application has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this application.

[0026] The above and other aspects, features and advantages of this application will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0027] Specific embodiments of this application are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this application, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the application. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as the basis and representative basis for the claims to teach those skilled in the art to use this application in a variety of substantially any suitable detailed structures.

[0028] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in other embodiments,” all of which may refer to one or more of the same or different embodiments according to this application.

[0029] This application provides a power compatibility method for a retimer chip, which includes the following steps: Step S1: Determine the target chip based on the configuration type of multiple chips.

[0030] The chip is a retimer chip. The hardware platform supports compatible insertion of retimer chips from different manufacturers. Different manufacturers' retimer chips correspond to various configuration types. The power hardware pins of different configuration types of retimer chips are manufacturer-defined, and there are differences in power supply design between different manufacturers' retimer chips. Different manufacturers and different models of retimer chips have different fixed designs in their underlying power supply parameters, pin definitions, and timing specifications, corresponding to different configuration types. Retimer chips with completely identical power supply parameters, power pin assignments, and power timing parameters are classified into the same configuration type; any difference in any core parameter classifies them into different configuration types. During the hardware platform's power-on initialization phase, hardware detection, register reading, and pin level acquisition are used to match hardware characteristics and accurately identify the actual chip configuration type and corresponding target chip on the current hardware platform. For example, the first configuration type chip is model XC7K325T, whose configuration pin is fixed at a high level; the second configuration type chip is model RK3588, whose configuration pin is fixed at a floating level; and the third configuration type chip is model STM32H743, whose configuration pin is fixed at a low level. Different configuration type chips have unique device register parameters; for example, the register value for the first configuration type chip is 0x0001, the register value for the second configuration type chip is 0x0002, and the register value for the third configuration type chip is 0x0003. During the system power-on initialization phase, the actual chip model on the current hardware platform can be identified by acquiring pin levels and reading the chip's unique device register parameters. This allows for the selection of a valid working chip from multiple candidate chips, which is then designated as the target chip for power supply control, avoiding issues such as confusion in timing strategies among multiple chips and misconfiguration of power supplies. For example, during the system power-on initialization phase, if a high level is detected on the configuration pin and the register value is 0x0001, it is determined that the current chip is a first configuration type chip and is identified as the target chip; if a floating level is detected and the register value is 0x0002, it is determined that the second configuration type chip is the target chip; if a low level is detected and the register value is 0x0003, it is determined that the third configuration type chip is the target chip.

[0031] Through step S1, chip identification can be performed based on hardware physical characteristics to determine what kind of chip is currently being used, and the target chip can be identified (for example, the target chip is a first configuration type chip with model XC7K325T and register value 0x0001).

[0032] Step S2: Configure the common power module according to the target chip.

[0033] As shown in Table 1, the power supply requirements, such as operating voltage and rated current, vary for different types of Retimer chips. For example, Retimer chips from different manufacturers may require different power supply voltage ranges (such as 1.8V, 2.5V, or 3.3V).

[0034] Table 1: Power Requirements of Different Types of Retimer Chips

[0035] Different types of retimer chips have varying timing requirements. The common power module is a general-purpose configurable power supply unit without fixed output parameters. Once the target chip is determined, its output voltage values, output current limits, voltage regulation accuracy, enable modes, and overcurrent protection thresholds can be specifically configured based on the target chip's hardware specifications. This ensures that the common power module's hardware output capabilities match the target chip's rated power supply requirements, providing a hardware foundation for subsequent precise timing power supply.

[0036] That is, based on the target chip determined in step S1, the basic hardware parameters such as voltage, current, and overcurrent protection of the common power module are first adapted.

[0037] Step S3: Determine the identification information corresponding to the target chip.

[0038] To achieve accurate matching of power timing strategies, the system can preset a unique identifier for each type of chip configuration. This identifier can be understood as the binding code for the chip model, power supply parameters, and timing type, and serves as the index information for timing strategy retrieval.

[0039] After identifying the target chip, the identification information corresponding to the target chip is obtained by matching the chip model and configuration parameters. This information is then used to accurately retrieve the corresponding power timing control strategy, achieving a one-to-one correspondence between the chip and the timing strategy. This avoids the mixing of strategies and ensures accurate power supply to the target chip, precisely meeting its power supply requirements.

[0040] For example, a mapping table between chips and identification information can be pre-established, binding different configuration types of chips with unique identification information. This identification information contains the core attributes of the chip, providing a precise retrieval basis for subsequent timing strategy matching. For instance, the first configuration type chip (XC7K325T) corresponds to identification ID ID-01, the second configuration type chip corresponds to identification ID ID-02, and the third configuration type chip corresponds to identification ID ID-03. After determining that the target chip is the first configuration type chip of the XC7K325T model, based on the identified chip model and configuration parameters, the identification mapping table is searched to accurately extract the identification information corresponding to the target chip: identification ID-01, chip type can be high-speed programmable logic chip, power supply mode: multi-channel hierarchical power-on timing.

[0041] Step S3 determines the unique identification information ID of the target chip that has been identified in step S1, and binds a unique power supply, timing and other control strategies based on the ID.

[0042] If step S1 identifies the chip model, but there is no corresponding identifier ID in the mapping table, the chip model output in step S1 can be used as retrieval information to query the pre-stored mapping table. If no matching ID is found, the identifier matching is deemed abnormal. The configured power module parameters can be cleared, the default power safety threshold restored, and any timing strategies prohibited from being loaded to prevent timing strategy mismatch from burning out the chip. In this way, steps S1 and S3 can respectively ensure the accuracy of subsequent power timing control strategies based on hardware physical identifiers and software identifier information.

[0043] Step S4: Determine the power timing control strategy corresponding to the target chip based on the identification information.

[0044] Different chips have strict requirements for their power-on and power-off sequences. If the target chip is not powered on and off according to the power sequence control strategy corresponding to the target chip, it will lead to problems such as chip lock-up, core burn-out, and abnormal interface communication.

[0045] The system can pre-store multiple power timing control strategies, each bound to a unique chip identifier. Using the target chip's identifier, the system accurately determines the timing strategy uniquely corresponding to that target chip. Specifically, after determining the target chip's identifier in step S3, the system can select the power timing control strategy uniquely corresponding to the target chip's identifier from among multiple power timing control strategies. The power timing control strategy includes core parameters such as the target chip's power-on and power-off sequences.

[0046] Step S5: Control the common power module according to the power timing control strategy so that the common power module supplies power to the target chip according to the power timing corresponding to the target chip.

[0047] After configuring the parameters and matching the timing strategy of the common power module, the timing strategy can be converted into enable control signals, delay trigger signals, and voltage regulation feedback signals for the power module through the main timing control unit. This drives the common power module to operate, ensuring that it outputs voltage exactly according to the target chip's specific timing rules. In this way, multiple Retimer chips from different manufacturers can be supported on the same PCB platform, meeting the power supply parameter and timing requirements of different Retimer chips. Through chip type identification, dynamic power module configuration, precise matching of identification information, and invocation of specific timing strategies, adaptive timing power supply control of the common power module for multiple types of Retimer chips from different manufacturers is achieved. This eliminates the need for separate PCB design for different chips, significantly reducing hardware modification costs, while accurately matching the original power supply timing specifications of each chip.

[0048] In some embodiments, the method further includes: Map the power pins of multiple chips to a preset common power module.

[0049] Different configuration types of Retimer chips have different pin definitions and power supply parameters. By pre-setting pin mapping rules through hardware topology, the same type of power pins of multiple chips can be grouped and aggregated, and uniformly mapped and connected to the corresponding output channels of the same common power module. This enables the reuse of the output channels of the common power module and provides a hardware foundation for multi-chip compatible power supply.

[0050] Although the pin definitions and power supply parameters of retimer chips with different configurations vary, there are a large number of power pins with the same attributes and power supply domain. For example, referring to Table 2, the power supply voltages of the power pins of multiple chips are different. By obtaining the power supply parameters of all power pins of multiple chips and comparing the connection relationship between the power pins of multiple chips and the pins of the power supply module, and grouping the pins according to the degree of overlap of the power supply voltages of different chips, we can obtain 9 power pin groups. The number of power pins in the 9 power pin groups can be different. These 9 power pin groups can be mapped to a common power module, and the common power module outputs the power supply parameters through 9 output channels (POWER1~POWER9) corresponding to the 9 power pin groups (GROUP1~GROUP9). For example, through the above pin mapping design, the same type of power pins of multiple chips can reuse the corresponding output channels of the same common power module, realizing the unified reuse of power hardware resources.

[0051] Table 2 Pin definitions and power supply parameters for Retimer chips of different configuration types

[0052] This application embodiment uses a pre-defined unified pin mapping rule to group similar power pins of chips with different models and pin definitions into a fixed common power channel, instead of using the traditional discrete design of one chip with one set of power routing. Without making any changes to the hardware PCB topology, power routing, pin pads, or power circuit structure, it can be compatible with the power pin connection requirements of multiple heterogeneous chips, achieving uniqueness and universality of the hardware topology. This solves the problem of hardware modification and wiring redundancy required when using different chips on a PCB in traditional designs.

[0053] The power supply capacity of the common power module is determined based on the power supply requirements of multiple chips; the power supply capacity of the common power module covers the current requirements of the power pin group of the target chip.

[0054] The common power module is a general-purpose multiplexed power unit. Its power supply parameters, such as maximum output current and load capacity, need to be set in advance. Furthermore, it must meet the maximum power supply requirements of all compatible Retimer chips on the platform, ensuring that the power module will not experience issues such as insufficient load capacity, excessive voltage drop, or false triggering of overcurrent protection when any target chip is used. By using the rated current and peak current requirements of each power pin group of all compatible chips, the maximum current threshold of each power channel is determined. This determines the power supply capacity of each channel of the common power module, ensuring that the module's power supply capacity fully covers the upper limit of the current requirements of all target chips.

[0055] With the above configuration, the power supply capacity of each output channel of the common power module covers the peak current requirements of multiple compatible chips. Regardless of the target chip currently installed on the hardware platform, the common power module has sufficient load capacity, solving problems such as chip instability, restarts, and crashes caused by insufficient power supply margin, and achieving full compatibility coverage of power supply capabilities.

[0056] Configure the output voltage of the common power module according to the power supply requirements of the target chip, so that the common power module outputs a power supply voltage corresponding to the target chip.

[0057] Different configurations of target chips have different voltage specifications for their co-domain power pins, making fixed-voltage output common power modules unsuitable for multi-chip scenarios. This step dynamically and precisely configures the output voltage values ​​of each channel of the common power module based on the voltage specifications of the currently installed target chips. This ensures that the common power module outputs a rated supply voltage that perfectly matches the current target chip in real time. By achieving personalized voltage parameter adaptation based on power hardware reuse, it guarantees that different chips can obtain the standard operating voltage.

[0058] This dynamic configuration method can adapt the voltage of different chips simply by configuring parameters. It retains the hardware reuse advantages of common power supply modules while solving the adaptation problem of inconsistent voltage specifications among multiple chips. Addressing the issue of inconsistent voltage specifications within the same power domain for different chips, it dynamically switches the output voltage of each power supply by identifying the target chip type. Without modifying hardware, replacing power supply components, or adjusting wiring, it matches a dedicated rated supply voltage to different chips, solving the problem that fixed power supplies cannot adapt to the electrical specifications of multiple heterogeneous chip models.

[0059] In some embodiments, different power supply groups in the common power supply module have different maximum output currents; and the maximum output current of the same power supply group in the common power supply module is not less than the maximum current requirement of the corresponding power pin group in multiple chips.

[0060] Based on the differences in voltage and current of multiple retimer chips from different manufacturers, the common power supply module can be designed to include different power supply groups. For example, considering the differences in voltage and current of the retimer chips from the five manufacturers shown in Table 1, and combining Table 3 and... Figure 2 The common power module can be designed to include four different power groups (POL1, POL2, POL3 and LDO4). Table 3 shows the correspondence between the four power groups and five manufacturers.

[0061] Table 3: Power Supply Design Requirements

[0062] Different power supply groups correspond to different types of power pin groups on the chip. These different types of power pin groups inherently have different current consumption levels. Therefore, each power supply group is assigned its own independent maximum output current, rather than using the same current specification for all power supply groups. As shown in the table, the four power supply groups have different maximum output currents: POL1 has a maximum output current of 16.3A, POL2 has a maximum output current of 8.8A, POL3 has a maximum output current of 6A, and LDO4 has a maximum output current of 0.5A.

[0063] In a common power supply module, the maximum output current of the same power supply group should not be less than the maximum current requirement of the corresponding power pin group among multiple chips. That is, for each power supply group, the current parameters of the corresponding power pin groups of all chips corresponding to that power supply group are iterated to obtain the maximum operating current of that group of pins on each chip, and the maximum value is taken as the current design benchmark for that power supply group. For example, for five chips belonging to POL1, the maximum current requirements of the corresponding power pin groups of the five chips are 12.55A, 12.3A, 16.3A, 7.5A, and 12.8A respectively. Then, the maximum output current of POL1 should not be less than 16.3A. The maximum output current of POL1 can be 16.3A or increased from 16.3A (e.g., 17A or other current values ​​greater than 16.3A), as long as the maximum output current of the power supply group is not less than the maximum current requirement of the corresponding power pin group among multiple chips.

[0064] As shown in Table 3, the POL2, POL3, and LDO4 power supplies do not need to carry 16.3A current. Forcing all four power supplies to use 16.3A high-current power devices simply for the sake of uniform specifications would be problematic. High-current POL and LDO devices have drawbacks such as larger package size, higher unit cost, higher static power consumption, more complex loop compensation design, larger PCB copper width, and greater board area requirements. In particular, LDO4 only needs to meet a maximum load requirement of 0.5A; using a high-power linear regulator supporting 16.3A would result in significant hardware resource redundancy, significantly increased no-load losses, increased standby power consumption, and negatively impacted heat dissipation control of high-speed communication boards.

[0065] In this embodiment, for each power supply group, the maximum current of the channel is taken as the design upper limit of the power supply group based on the current requirements of the corresponding pin groups of all compatible Retimer chips in the same power supply group. The four power supplies are configured with different maximum output currents: POL1 is 16.3A, POL2 is 8.8A, POL3 is 6A, and LDO4 is 0.5A. On the one hand, the hardware load capacity fully covers the compatibility requirements: the maximum output current of each power supply is greater than or equal to the peak current of the corresponding pin groups of all manufacturers' Retimer chips. When any manufacturer's Retimer chip is used under full load and transient peak conditions, there will be no reliability problems such as insufficient power supply load, triggering of false overcurrent protection, or excessive output voltage drop, ensuring stable power-on operation of multiple Retimer models. On the other hand, it can also avoid the drawbacks of full-channel high-power redundancy design. Each power supply group selects power chips, power inductors, input and output capacitors, and PCB trace copper thickness according to the corresponding specifications. Under the premise of meeting electrical performance, it can reduce the device packaging, reduce material procurement costs, reduce PCB wiring area, reduce power circuit static power consumption and heat generation, simplify the difficulty of power loop stability debugging, and better meet the miniaturization and low power consumption design requirements of high-density server high-speed PCIe boards.

[0066] The maximum output current of this power supply group is set to be greater than or equal to this maximum value. This ensures that regardless of the manufacturer of the chips used in the hardware platform, the output capacity of the power supply group can meet the current requirements of the corresponding power pin group, avoiding insufficient load. Different power supply groups have independent values, eliminating the need to uniformly select specifications based on the maximum peak current of the entire system, thus achieving a match between power supply capacity and actual needs.

[0067] In some embodiments, configuring the common power module according to the target chip includes: Step S21: Determine the target output voltage of the corresponding common power module according to the type of the target chip.

[0068] For example, a mapping relationship between memory chip type and voltage can be established, as shown in Table 3. When the current target chip is identified as a type B chip, the power requirements of the B chip are retrieved: POL1 target output voltage 0.8V, POL2 target output voltage 1.5V, POL3 target output voltage 0.8V, and LDO4 target output voltage 1.8V.

[0069] Combined with Table 3 and Figure 2 The common power module contains four power banks used to supply power to the POWER1~POWER9 power channels corresponding to different types of target chips.

[0070] Different chip configurations have different output voltage requirements for the same POL (Point of Load) power supply, as shown in Table 3. For example, for a POL1 power supply, chip requirements are as follows: Manufacturer A requires 0.75V, Manufacturer B requires 0.8V, Manufacturer C requires 0.7V, Manufacturer M requires 0.75V, and Manufacturer S requires 0.75V. For a POL2 power supply, chip requirements are as follows: Manufacturer A requires 1.35V, Manufacturer B requires 1.5V, Manufacturer C requires 1.2V, Manufacturer M requires 0.75V, and Manufacturer S requires 0.75V. If the POL power supply uses a fixed feedback resistor, a single PCB hardware can only output a single voltage, which cannot adapt to the voltage requirements of multiple chips. If all voltage regulation is achieved using digital registers, the reliability of the power chip's digital interface and firmware is highly dependent. If the firmware malfunctions, output voltage errors will occur, causing the chip to burn out.

[0071] Step S22: Adjust the resistor assembly state and / or resistor value in the feedback resistor network of the common power module to make the common power module output the target output voltage.

[0072] This embodiment employs resistor adjustment within a feedback resistor network to achieve the target output voltage from the common power module. For example, each POL and LDO power supply feedback pin of the common power module is configured with an independent feedback resistor network. The feedback resistor network includes upper and lower voltage divider resistors. Multiple optional resistor pads are set on the lower voltage divider resistor branch. These optional resistor pads can be assembled or not assembled. By selecting to assemble or not assemble the optional resistors, the equivalent voltage divider resistance value of the feedback network is changed. A control switch corresponding to the resistor can also be set. Even after assembling the optional resistors, the control switch can be used to control whether the corresponding resistor with the feedback resistor network participates in the adjustment. Alternatively, the resistance value can be adjusted by directly replacing the resistor components.

[0073] For example, the assembly state of the resistors in the feedback resistor network of the common power supply module can be adjusted to enable the common power supply module to output the target output voltage. Each resistor in the feedback network has a pre-selected fixed resistance value; the resistance value itself is not changed, only whether a surface-mount resistor is mounted on the resistor pad is adjusted, i.e., the assembly state is adjusted. The feedback network has multiple selectable pull-down resistor branches: Rb1=1kΩ, Rb2=3kΩ, with fixed resistance values. Different target voltage outputs are achieved simply by switching between the mounted / unmounted assembly states of the resistors, thus changing the equivalent pull-down resistance.

[0074] For example, the target output voltage can be achieved by simply adjusting the resistance values ​​in the feedback resistor network of the common power supply module. Resistors are mounted on all reserved resistor pads in the feedback resistor network, and the assembly state remains unchanged. Only the resistance values ​​of the surface-mount resistors on the pads are changed to adjust the voltage division ratio. The upper resistor Rtop is always mounted (the assembly state remains fixed), and only the resistance value of the pull-down resistor Rbot is changed.

[0075] For example, by adjusting the resistor assembly state and resistance value in the feedback resistor network of the common power supply module, the common power supply module can output the target output voltage. This involves selecting some resistor pads for mounting / leaving them unmounted (adjusting the assembly state) and simultaneously using different resistance values ​​for the assembled resistors. These two methods work together to achieve the target voltage configuration, adapting to a wider range of output voltages. For instance, the feedback resistor network might include two optional branches, R1 and R2. Chip A is installed: R1 (2kΩ resistance) is installed, and R2 is left unused; Equipped with extended model chip B (target output voltage 0.9V): Simultaneously fitted with resistor R1 (2kΩ) and resistor R3 (4.3kΩ) to achieve voltage divider regulation. This combination offers greater configuration flexibility and is compatible with more retimer chips of different voltage specifications.

[0076] For example, if the target chip is identified as a type B chip, and the target output voltage of POL2 is 1.5V, then a resistor corresponding to this target output voltage can be soldered and assembled to make the output voltage of POL2 1.5V, matching the power supply voltage requirements of the type B chip.

[0077] In this embodiment, the POL1, POL3, and LDO4 of the common power supply module all employ the same feedback resistor network voltage regulation logic. Taking POL1 as an example, for different types of chips (A / B / C / M / S), corresponding to different target output voltages in the ranges of 0.7V, 0.75V, and 0.8V, the corresponding target voltage is output by adjusting the resistor assembly state or resistance value of the feedback resistor network of POL1. Similarly, LDO4 uses its own feedback resistor network to achieve the switching between 1.2V and 1.8V voltages required by different chips.

[0078] (Refer to the attached diagram) Figure 2 After POL1, POL2, POL3, and LDO4 output, they are connected to the power supply channels of POWER1 to POWER9 via different selector resistors (A / B / C / M / S selector paths) to provide the power supply voltage adapted to the target chip, thus meeting the power supply requirements of each power pin group of the currently assembled target chip.

[0079] This application embodiment utilizes a single PCB hardware platform, allowing adaptation to various chips with different voltage requirements simply by adjusting resistor assembly settings or replacing resistor components. This eliminates the need for multiple PCB versions, reducing hardware development costs. Voltage regulation is achieved through hardware resistor voltage division, not entirely reliant on the power chip's digital interface and firmware, thus avoiding voltage configuration errors caused by firmware malfunctions and improving power system reliability. Through a shared power supply architecture with multiple POLs and LDOs, each power supply is independently configured with a feedback resistor network, allowing for independent voltage adjustment of each power supply to meet the diverse multi-domain power supply needs of different chips.

[0080] In some embodiments, configuring the common power module according to the target chip includes: Based on the current requirements of the power pin group corresponding to the target chip, configure the overcurrent protection parameters of the power group so that the overcurrent protection threshold of the power group matches the current requirements.

[0081] Different types of target chips have different operating current requirements for the same power pin group. The overcurrent protection parameters of the power supply group can be configured according to the current requirements of the corresponding power pin group of the target chip. The overcurrent protection threshold of the power supply group needs to be compatible with the current requirements of the target chip's power pin group: the threshold needs to be higher than the chip's maximum normal operating current, with a reasonable safety margin, and must not exceed the maximum current that the power supply path hardware can withstand. After configuration, the power supply group collects the output current in real time; when the output current exceeds the overcurrent protection threshold, the overcurrent protection unit triggers protection, cutting off the power output of that path to achieve fault protection.

[0082] The overcurrent protection threshold is fixed to the maximum design value of the hardware. If the threshold is set too high, the overcurrent protection will not be triggered in time when the chip has a short circuit fault, which may easily burn out the chip and the power supply link. If the threshold is set according to the low current chip, the normal operating current will trigger false protection when a high current chip is installed, and the system will abnormally power down and reset.

[0083] In some embodiments, determining the identification information corresponding to the target chip includes: Step S31: Generate identification information corresponding to the target chip through the chip type identification circuit.

[0084] For example, a circuit board compatible with different chips can be configured with a chip type identification circuit. The chip type identification circuit can generate identification information corresponding to the target chip. The common power module can then perform adaptation operations such as voltage configuration, overcurrent protection configuration, and power timing control based on this identification information.

[0085] Step S32, the chip type identification circuit includes multiple identification configuration terminals, which are respectively connected to a first level terminal or a second level terminal through assembly resistors.

[0086] For example, a chip type identification circuit may include N identification configuration terminals, each with two optional pads. One pad can be connected to a first level terminal via a mounting resistor, and the other pad can be connected to a second level terminal via a mounting resistor. The first and second level terminals can be understood as two reference potentials with a potential difference. For example, the first level terminal can be a high level (VCC), and the second level terminal can be a ground level (GND); or the first level terminal can correspond to 1.8V, and the second level terminal to 1.0V; or the first level terminal can be a reference voltage of 0.6V, and the second level terminal to 0V, etc. These are merely examples of the first and second level terminals and do not constitute a limitation on the scope of the claims.

[0087] Step S33: By adjusting the assembly state of the assembly resistor, the plurality of identification configuration terminals form identification information that uniquely corresponds to the target chip.

[0088] The voltage level of each identification configuration terminal is determined by the assembly state of the mounting resistor: when a mounting resistor is installed between the identification configuration terminal and the first voltage level terminal, the identification configuration terminal outputs a high level; when a mounting resistor is installed between the identification configuration terminal and the second voltage level terminal, the identification configuration terminal outputs a low level. Only one mounting resistor is installed on the same identification configuration terminal at a time to avoid voltage level conflicts. By adjusting the assembly / disassembly states of the mounting resistors corresponding to multiple identification configuration terminals, the voltage levels output by multiple identification configuration terminals are combined to form a binary code, which is the unique identification information corresponding to the target chip.

[0089] Some solutions use software programming to record chip type identification information. However, software-based identification information is prone to firmware upgrade errors and storage media damage, leading to incorrect identification readings and consequently, power module misconfiguration and chip burnout. Other solutions use dedicated encoding chips, which increases the number of components, PCB area, and material costs. This embodiment generates hardware identification information entirely based on the on-board resistor assembly status, requiring no software programming or additional encoding chips. The identification is permanently embedded in the hardware, ensuring high reliability.

[0090] In some embodiments, the chip type identification circuit includes a first identification configuration terminal, a second identification configuration terminal, and a third identification configuration terminal.

[0091] Each identification configuration terminal is provided with a first resistor bit connected to the high-level terminal and / or a second resistor bit connected to the low-level terminal to form identification information with a three-bit identification signal. The identification information is used to characterize different types of chips.

[0092] The first, second, and third identifier configuration terminals are each equipped with a first resistor bit connected to a high-level terminal and a second resistor bit connected to a low-level terminal. For example, the first and second resistor bits may be pre-installed resistor pads on the PCB, allowing for the selective installation of mounting resistors, preferably 0Ω resistors. The high-level terminal is the board system's high-level VCC, and the low-level terminal is the board ground GND.

[0093] For any given identifier configuration terminal, when a resistor is installed in the first resistor bit and the second resistor bit is left empty, the identifier configuration terminal is pulled up to a high level, representing "1"; when a resistor is installed in the second resistor bit and the first resistor bit is left empty, the identifier configuration terminal is pulled down to a low level, representing "0". Resistors are not allowed to be installed in both the first and second resistor bits of the same identifier configuration terminal simultaneously to avoid direct connection between the high and low level terminals via resistors, which would cause power loss. Referring to Table 4, ID0 is the most significant bit (LSB) and ID2 is the least significant bit (LSB). The encoding string is written in a fixed order: ID0, ID1, ID2. The reading rule can be to collect the three levels in parallel, reading ID0 first, then ID1, and finally ID2, sequentially as characters in the binary string from left to right, avoiding table lookup errors caused by reversed bit order. Alternatively, the three levels corresponding to ID0, ID1, and ID2 can be collected sequentially, and then sequentially as characters in the binary string from left to right, for example, ID0=1, ID1=0, ID2=0, with the encoding string written as 100. By selectively assembling resistors at the first and second resistor bits of the first, second, and third identification configuration terminals, a three-bit identification signal can be generated. These three-bit identification signals combine to form binary-coded identification information, resulting in various encoding states. Different binary codes correspond to different manufacturers or models of Retimer chips. For example, the identification information formed by the three-bit identification signal combination is "000," corresponding to manufacturer A; "001," corresponding to manufacturer B; "010," corresponding to manufacturer C; "011," corresponding to manufacturer M; and "100," corresponding to manufacturer S. Identification information "101" and "110" can be reserved as extended codes for future compatibility with new manufacturers or models of Retimer chips. For example, when hardware iterations require compatibility with the sixth and seventh Retimer chips, the chip power supply parameters and timing strategies are directly entered into the internal mapping table of the control unit and bound to the identification information "101" and "110". No PCB modifications are needed; only the firmware parameter table and the corresponding resistor assembly list are updated to achieve hardware platform expansion. The identification information "111" is defined as an illegal NA code, belonging to an unassigned reserved code, and is not bound to any Retimer chip.

[0094] If the parsed code is 111 (NA illegal code), or if the level sampling is abnormal (e.g., the level is between high and low thresholds, making it impossible to determine logic 0 / 1), the identification is considered a failure. In the event of identification failure, the power-on operation of each power supply group of the common power module can be prohibited, the common power module remains in a shut-off output state, and an alarm signal can be output to report to the upper management unit. This protection strategy avoids the use of undefined power supply parameters and power mismatch under illegal coding, thus eliminating the risk of abnormal power supply burning out the Retimer chip.

[0095] This application uses a three-bit code to form identification information, which can cover the above five types (A / B / C / M / S) of in-use Retimer chips. Two of the remaining three sets of codes (101 and 110) are used for subsequent chip model expansion, and one set (111) is used as an NA illegal protection code. It only occupies three control unit GPIO pins, with two resistor pads configured for each channel. Compared with more bit-bit solutions, it can reduce GPIO resource occupation, reduce the number of PCB pads, and balance compatibility with hardware cost and wiring area. At the same time, it reserves illegal codes for fault protection to realize a safe power-off mechanism when abnormalities are identified. However, two-bit identification information can only provide four independent codes (00, 01, 10, 11), which cannot cover more than four Retimer chips and cannot meet the differentiation requirements of existing five manufacturers' Retimers.

[0096] Table 4: Retimer ID Allocation

[0097] In some embodiments, determining the power timing control strategy corresponding to the target chip based on the identification information includes: Based on the identification information, a target power timing control parameter is selected from multiple sets of power timing control parameters, and the enable state of multiple power groups in the common power module is controlled based on the target power timing control parameter.

[0098] For example, multiple sets of power timing control parameters can be pre-stored, each set corresponding one-to-one with a specific Retimer chip. Each set of power timing control parameters includes the power-on sequence, power-on delay, power-off sequence, power-off delay, and power enable logic for each power group within the common power module. Different manufacturers and models of Retimer chips have different power-on and power-off timing requirements. For example, some Retimer chips require the core power supply to power on first, followed by the I / O power supply after a set interval; some Retimer chips require the I / O power supply to power on first, followed by the core power supply. The delay time between power-on cycles also varies among different chip models. If the power-on / power-off sequence is disordered or the delay does not meet the specifications, it can cause the Retimer chip to lock up, malfunction, or even be damaged.

[0099] For example, power timing control parameters can be pre-stored in the register space of the power module itself. The control unit only transmits the identifier index, and the power module internally performs table lookups and timing execution. This makes the main control logic more lightweight, allowing the power module to autonomously manage timing. Of course, power timing control parameters can also be stored in other locations or on other media.

[0100] Using chip identification information as the index key, a complete set of power timing control parameter structures is mapped. For example, the timing parameter structure may include a power-on sequence list, an array of power-on time intervals between adjacent power supplies, a power-off sequence list, an array of power-off time intervals between adjacent power supplies, and the delay of the reset signal release relative to power-on. After obtaining the target power timing control parameters from the table but before executing the power-on timing, a parameter validity verification step is added to avoid illegal timing configurations caused by storage media damage, abnormal parameter burning, or index matching errors. For example, in index validity verification, if the identification information is the illegal code 111, the index is directly determined to be illegal, and power-on is prohibited.

[0101] The power timing control strategy corresponding to the target chip is determined based on the identification information. Specifically, this may include: selecting target power timing control parameters from multiple pre-stored sets of power timing control parameters based on the identification information read by the hardware. The identification information serves as an index, directly pointing to a unique set of target power timing control parameters. The target power timing control parameters define the enable trigger time, channel turn-on sequence, channel turn-off sequence, and time interval between adjacent power channels for each power group. The target power timing control parameters are parsed, and enable control signals are sequentially output to each power group within the common power module to control the corresponding power group to power on or off. For example, each power group has an independent enable control port that receives the enable signal output by the control unit; a high level enables the corresponding power group to power on, and a low level enables the corresponding power group to power off.

[0102] When the Retimer chip on the board is replaced, the identification information output by the chip type identification circuit changes accordingly. The control unit automatically switches to select another set of power timing control parameters and outputs different enable control timings. Without modifying the hardware PCB, it can adapt to the different power-on and power-off timing specifications of different Retimer chips.

[0103] In some embodiments, the target power supply timing control parameters include at least one of the following: The power-on sequence of each power supply group; The power-on time interval between two adjacent power supply groups; The sequence of power outages for each power supply group; The time interval between power outages between two adjacent power supply groups; The timing of the reset signal release for the target chip.

[0104] Besides differences in the power-on and power-off sequence and intervals of power channels, different manufacturers and models of Retimer chips also have requirements regarding the timing of the reset signal release. For example, the chip reset signal must be released only after the output voltage of the relevant power supply group has stabilized; if the reset is released too early, before the power supply has stabilized, it will cause Retimer chip initialization failure, abnormal register configuration, and link training failure. If the reset is released too late, it will lengthen the overall system startup time. The embodiments of this application can solve the problem that using fixed timing parameters cannot adapt to the different requirements of reset release timing for multiple Retimer chips, and is prone to product malfunctions.

[0105] It should be noted that the above five types of parameters are independent, configurable individually, and can be combined arbitrarily. They do not need to be configured simultaneously; any one or more types of parameters can be effective independently to form a complete, executable, and safe power timing control strategy. There is no limitation that all parameters must be present for the system to function. A global default safe timing strategy can be pre-stored. This default baseline is a universal safe power-on and power-off logic compatible with all Retimer chips, ensuring basic power supply safety. When the target chip's corresponding power timing control parameters include a certain type of custom parameter, the custom parameter is used to override the default strategy for that dimension. When the target chip does not configure a certain type of parameter, the system automatically uses the global default strategy to complete it, enabling single-parameter, multi-parameter, and full-parameter combinations to independently form legal and executable timing control schemes. For example, the target power timing control parameters only configure the reset signal release time, without defining the power-on sequence, power-on interval, power-off parameters, etc. Some Retimer chip models do not have particularly stringent requirements for the power-on sequence, power-on interval, and power-off sequence; they can work stably using the platform's default general timing. However, the timing of the reset release is critical. Resetting too early will lead to power instability and chip initialization failure; resetting too late will lengthen the overall system startup delay. For this type of chip, this solution supports configuring only the fifth type of parameter (the reset signal release time of the target chip), while leaving the other four types of parameters as default. The executable strategy logic is that after the control unit is powered on, all power groups are powered on according to the system's default safe power-on sequence and default power-on interval. After power-on, the default reset release time is no longer used; instead, the reset signal is pulled high only after a delay according to the reset signal release time defined in the target parameters to complete chip initialization. For example, for a certain Retimer chip model with the identification information 101, its target power timing control parameters are only configured so that the reset signal release time is 20ms after all power supplies have stabilized. The system automatically retains the default power-on sequence, default power-on interval, and default power-down logic, with only the reset timing being precisely replaced with custom parameters, forming a complete and executable timing strategy that meets the chip's specific reset constraints. This mode only requires configuring a single-dimensional parameter to solve the problem of reset timing mismatch for a specific chip.

[0106] For example, combining Figure 3 The power-on sequence of the Retimer chip shown is DVDD (POL1) → AVDD (POL2) → VDDIO (POL3). The reset signal needs to be released after the power is established, which is a delay of ≥10ms after the power is fully stable. The total delay from power-on to reset is ≥100ms. The power-off sequence is VDDIO (POL3) → AVDD (POL2) → DVDD (POL1), with an interval of ≥1ms between adjacent power-offs. Figure 4The Retimer chip shown has a power-on sequence of VDDIO (POL3) → VDD (POL1) → AVDD (POL2), with adjacent power supply intervals greater than 1ms and less than 10ms during power-on. The power-off sequence is AVDD (POL2) → VDD (POL1) → VDDIO (POL3), with adjacent power supply intervals less than 1ms during power-off. The reset signal is released after AVDD stabilizes. LDO4 serves as the REFCLK reference clock and auxiliary logic power supply; LDO enable is synchronized with the first power supply; LDO power-off is synchronized with the last power supply. The reset signal PGOOD_RST_N is a global power domain reset; PERST# is a dedicated PCIe reset. If the platform uses a fixed set of timing parameters and directly applies them to multiple Retimer chips, the power-on sequence may be reversed, the intervals may not meet specifications, and the reset may be released too early or too late, causing abnormal chip operation.

[0107] For manufacturer A, the timing table between POL1, POL2, POL3, LDO4 and the reset signal is as follows:

[0108] For manufacturer B, the timing table between POL1, POL2, POL3, LDO4 and the reset signal is as follows:

[0109] For manufacturer C, the timing table between POL1, POL2, POL3, LDO4 and the reset signal is as follows:

[0110] For manufacturer M, the timing table between POL1, POL2, POL3, LDO4 and the reset signal is as follows:

[0111] For manufacturer S, the timing table between POL1, POL2, POL3, LDO4 and the reset signal is as follows:

[0112] Furthermore, although exemplary embodiments have been described herein, their scope includes any and all embodiments based on this application that have equivalent elements, modifications, omissions, combinations (e.g., schemes involving intersections of various embodiments), adaptations, or alterations. Features or elements in the claims will be interpreted broadly based on the language used in the claims and are not limited to the examples described in this specification or during the implementation of this application, and such examples will be interpreted as non-exclusive.

[0113] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more of them) can be used in combination with each other. Other embodiments can be used by those skilled in the art when reading the above description. Furthermore, in the above detailed description, various features may be grouped together to simplify the application. This should not be construed as an intention that a disclosed feature not claimed is necessary for any claim. Rather, the subject matter of the application may be less than all the features of a particular disclosed embodiment. Thus, the claims are incorporated herein by reference as examples or embodiments, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated as being able to be combined with each other in various combinations or arrangements. The scope of this application should be determined by reference to the appended claims and the full scope of their equivalents.

[0114] Combination Figure 5 This application also provides a power compatibility device for a Retimer chip. The power compatibility device includes a common power module, a target chip determination module, a configuration module, an identification information determination module, a power timing control strategy determination module, and a control module.

[0115] Combination Figure 2 The common power supply module includes: a first power supply group, a second power supply group, a third power supply group, and a fourth power supply group.

[0116] Multiple power supply pins of the target chip among the multiple chips are respectively connected to the corresponding power supply groups in the first power supply group, the second power supply group, the third power supply group and the fourth power supply group.

[0117] The target chip determination module is configured to identify the target chip based on the configuration types of multiple chips. The hardware platform supports compatible interfacing of Retimer chips from different manufacturers. These Retimer chips correspond to various configuration types, and the hardware pinouts for each configuration type are manufacturer-defined. Furthermore, the power supply designs of Retimer chips from different manufacturers differ.

[0118] During the system power-on initialization phase, the actual chip model on the current hardware platform can be identified by acquiring pin levels (such as the power supply pins and function pins of the Retimer chip). The acquired pin level signals are used as input signals for the target chip determination module to select the working chip from a variety of candidate chips and determine it as the target chip for this power supply control. The identification result signal is output, which includes the configuration type and chip model information of the Retimer chip actually installed on the current board, avoiding the problems of confusion in timing strategies of multiple chips and misconfiguration of power supply.

[0119] The signal acquisition terminals of the target chip determination module can be connected to respectively Figure 2 The Retimer chip power supply pins corresponding to each output of the common power module POWER1~POWER9 will output the target chip identification result to the configuration module and the identification information determination module.

[0120] The configuration module configures the common power supply module according to the target chip. Different types of retimer chips have different power supply requirements, such as operating voltage and rated current. For example, retimer chips from different manufacturers may require different supply voltage ranges (e.g., 1.8V, 2.5V, or 3.3V). Different types of retimer chips also have different timing requirements. The common power supply module is a general-purpose configurable power unit without fixed output parameters. After determining the target chip, power configuration commands (output voltage configuration parameters, overcurrent protection parameters, and voltage regulation accuracy parameters) can be output based on the target chip's hardware specifications (e.g., rated voltage of each power domain, maximum load current, and overcurrent protection threshold). This allows for targeted configuration of the common power supply module's output voltage values, output current limits, voltage regulation accuracy, enable mode, and overcurrent protection threshold, ensuring that the common power supply module's hardware output capabilities match the target chip's rated power supply requirements, providing a hardware foundation for subsequent precise timing power supply.

[0121] The configuration module can be used with Figure 2 A communication link is established between the common power supply module consisting of POL1, POL2, POL3, and LDO. The configuration module issues configuration commands to adjust the output voltage corresponding to the POL feedback resistor network assembly and the overcurrent protection threshold of each power supply group, so that the power supply capacity of POL and LDO matches the current requirements of each power supply pin group of the target chip, completing the hardware parameter adaptation of the common power supply module. After configuration, a ready signal is output to the identification information confirmation module.

[0122] The identification information determination module is configured to determine the identification information corresponding to the target chip. To achieve accurate matching of power timing strategies, the system can preset unique identification information for each configuration type of chip. This identification information can be understood as a binding code for the chip's model, power supply parameters, and timing type, serving as an index for timing strategy retrieval. The identification information determination module can output retrieval identification information (e.g., a three-bit binary hardware code).

[0123] After identifying the target chip, the identification information corresponding to the target chip is obtained by matching the chip model and configuration parameters. This information is then used to accurately retrieve the corresponding power timing control strategy, achieving a one-to-one correspondence between the chip and the timing strategy. This avoids the mixing of strategies and ensures accurate power supply to the target chip, precisely meeting its power supply requirements.

[0124] The identification information determination module receives the target chip model and completes the encoding matching; on the other hand, it can be connected to an onboard chip type identification circuit to collect the hardware code generated by resistor assembly as identification information; the identification information determination module outputs the generated unique identification information to the power timing control strategy determination module.

[0125] The power timing control strategy determination module is configured to determine the power timing control strategy corresponding to the target chip based on the identification information output by the identification information determination module, and output a set of target power timing control parameters. Different chips have strict specifications for their power-on and power-off sequences. Failure to follow the power timing control strategy corresponding to the target chip during power-on and power-off can lead to problems such as chip lock-up, core burn-out, and abnormal interface communication.

[0126] The system can pre-store multiple power timing control strategies, each bound to a unique chip identifier. Using the target chip's identifier, the system accurately determines the timing strategy uniquely corresponding to that target chip. Specifically, after determining the target chip's identifier in step S3, the system can select the power timing control strategy uniquely corresponding to the target chip's identifier from among multiple power timing control strategies. The power timing control strategy includes core parameters such as the target chip's power-on and power-off sequences.

[0127] The power timing control strategy determination module can be built-in or connected to an external non-volatile storage medium to pre-store multiple sets of timing parameter mapping tables; it can retrieve the exclusive timing strategy by looking up the table using the identification information as the retrieval key and send the complete timing parameters to the control module.

[0128] The control module is configured to control the common power supply module according to the power timing control strategy, so that the common power supply module supplies power to the target chip according to the power timing corresponding to the target chip. The target power timing control parameters output by the power timing control strategy determination module are used as input to the control module. After completing the configuration of the common power supply module parameters and timing strategy matching, the timing strategy can be converted into enable control signals, delay trigger signals, voltage regulation feedback signals, etc., of the power supply module through the main timing control unit. That is, the control module outputs multiple independent power enable control signals, delay trigger signals, reset control signals, etc., to drive the common power supply module to work, so that the common power supply module outputs voltage completely according to the target chip's specific timing rules. In this way, multiple Retimer chips from different manufacturers can be supported on the same PCB platform, while meeting the power supply parameter requirements and power timing requirements of different Retimer chips. Through chip type identification, dynamic configuration of the power supply module, accurate matching of identification information, and invocation of specific timing strategies, adaptive timing power supply control of the common power supply module for multiple types of Retimer chips from different manufacturers is achieved. There is no need to design separate PCBs for different chips, which greatly reduces the cost of hardware modification, while accurately matching the original power supply timing specifications of each chip manufacturer.

[0129] The control modules can be connected separately. Figure 2 The enable control pins of POL1, POL2, POL3, and LDO control the power-on and power-off actions of each power channel from POWER1 to POWER9; at the same time, they output a reset signal to the reset pin of the Retimer chip.

[0130] The control module outputs enable signals sequentially according to timing parameters: controlling the POL and LDO to turn on / off in a specified order and inserting set time intervals; releasing a reset signal at the designated time; and finally... Figure 2 The Power CONN supplies power to the POL via the first circuit and to the LDO via the second circuit. The POL and LDO output power to POWER1~POWER9 according to the timing sequence, providing timing-matched power supply to the target Retimer chip.

[0131] In some embodiments, combined with Figure 2The first, second, and third power supply groups are connected to the target power supply via a first circuit, while the fourth power supply group is connected via a second circuit. The first and second circuits have different power supply conditions, such as different input voltage levels and / or different rated input currents. For example, the first, second, and third power supply groups are all POL (Point-of-Load Converter) power supplies, with the first power supply group corresponding to POL1, the second to POL2, and the third to POL3; the fourth power supply group is an LDO (Low-Dropout Regulator) power supply. A gating assembly circuit is set between the four power supply groups and POWER1 to POWER9 as a gating branch. The first and second circuits have different power supply conditions, such as different input voltage levels and different maximum input current capacities; the two power supplies are independent, supplying power to the POL and LDO respectively. POL1, POL2, and POL3 receive input power from P12V_RT via the first circuit; the LDO receives input power from P3V3_AUX via the second circuit. Among them, P12V_RT, rated at 2A, serves as the input power supply for the first circuit, providing input voltage for the three POL load point power supplies: POL1, POL2, and POL3; P3V3_AUX, rated at 1A, serves as the input power supply for the second circuit, providing input voltage for the LDO low-dropout linear regulator. For example... Figure 2 The POL1, POL2, and POL3 shown are point-of-load DC-DC switching converters, which require high input voltages and support multiple variable output voltages. POL1 supports output of 0.8V / 0.75V / 0.7V, with a maximum output current of 16.3A, and is connected to POWER1 via a selector switch. POL2 supports output of 1.5V / 0.75V / 1.2V / 1.35V, with a maximum output current of 8.8A, and is connected to POWER2 via a selector switch. POL3 supports output of 0.8V / 1.2V, with a maximum output current of 6A, and can be connected to POWER3, POWER4, POWER5, POWER6, and POWER7.

[0132] The three POLs require a 12V power input, resulting in a large overall load current. The P12V_RT branch can be selected, which is rated at 2A and can provide sufficient input power for multiple POLs, supplying power to the Retimer chip core and the analog high-current power rail.

[0133] The fourth power supply group uses an LDO (Low Dropout Linear Regulator) that supports outputs of 1.8V / 1.2V and a maximum output current of 0.5A. It is connected to POWER8 and POWER9 via selectable connections. It is primarily used in noise-sensitive, low-current circuits, such as reference clocks, reset circuits, and I / O auxiliary power supplies. The LDO does not require a 12V high-voltage input; a 3.3V auxiliary power supply P3V3_AUX is sufficient. This branch is rated at 1A, meeting the low-power input requirements of the LDO.

[0134] If an overcurrent or short-circuit fault occurs in the POL load, only the P12V_RT branch will be pulled low, without affecting the P3V3_AUX branch. The auxiliary power supply branch containing the LDO can continue to operate, and some auxiliary circuits can still remain operational, facilitating fault reporting and status monitoring, and preventing the entire power supply from failing simultaneously. Furthermore, the three POLs have a large total output power, allocated to a 2A rated 12V input branch; the LDO has a mere 0.5A output, configured with a 1A rated 3.3V auxiliary branch. Both branches have current limits configured according to the load power, preventing branch overload.

[0135] Taking POL3 and LDO4 as examples, multiple branches are drawn from the same POL / LDO's regulated output node. Each branch is connected in series with an independent selector resistor and then connected to a POWER channel. The output voltage of the same power supply group is unique, and all POWER channels with selector resistors connected share the voltage and current capacity of that power rail. The total load current cannot exceed the rated maximum output current of the POL / LDO (the DESIGN row in Table 3 represents the rated capacity reserved according to the maximum requirements of all manufacturers). For example, POL3 has a rated current of 6A and can simultaneously power multiple channels from POWER3 to POWER7, with the sum of the currents of the multiple channels ≤ 6A. LDO4 has a rated current of 0.5A and can simultaneously power POWER8 and POWER9, with the total current of the two channels ≤ 0.5A. Different manufacturers' Retimer chips reuse different channels for their power pins, and the channel to be enabled can be selected by soldering or not soldering selector resistors. Channels without soldered resistors are electrically disconnected and do not participate in power supply.

[0136] If two power rails with different voltages are directly short-circuited, the high-voltage rail will backflow current into the low-voltage rail (reverse current flow), causing damage to the voltage regulator chip, power supply short circuit, and abnormal chip power-on. This embodiment achieves isolation by using a gate resistor and single-point soldering for each branch. A single mounting resistor is uniquely configured between each POWER channel and the POL / LDO; multiple power supply resistor pads can be connected to the same POWER channel. Figure 2Each POWER channel has multi-colored branch lines above it, representing multiple selectable resistor pads. Only one select resistor can be soldered onto any given POWER channel; the remaining resistors remain unmounted. If only one resistor is soldered onto the same channel: this channel is only connected to one power rail, and the other power rail branches are physically disconnected, eliminating any paths between different voltage rails. Furthermore, the resistor itself provides current limiting and isolation; even in the event of an assembly error, the series resistor can limit reverse current, preventing power supply components from burning out. For example, if POWER4 is connected to both POL2 and POL3 pads, manufacturer C's solution only solders the resistor on the POL3 side, leaving the POL2 side unsoldered. POWER4 is only connected to the POL3 power rail, electrically isolated from POL2, preventing reverse current between different voltage rails.

[0137] For the branch assembly rules of different manufacturers, referring to Tables 1 and 3, the POL output voltage is configured for the five types of manufacturers (A / B / C / M / S), and the assembly status of each selector resistor is defined: assembling the selector resistor means the branch is conducting and connected to the corresponding POL / LDO; not assembling means the branch is disconnected. Taking manufacturer A as an example, POL1: 0.75V / 12.55A, solder the resistor between POL1 and POWER1; POL2: 1.35V / 2.84A, solder the resistor between POL2 and POWER2; POL3: 1.2V / 1.89A, solder the POWER branch resistor corresponding to POL3; LDO4: 1.2V / 0.03A, solder the resistor corresponding to LDO4 and POWER8 / POWER9; all other selector resistors across power supply groups are not assembled, and the branch is disconnected.

[0138] Combination Figure 6 This application also provides an electronic device, including a memory and a processor, wherein the memory stores an executable program and the processor is configured to execute: determining a target chip based on the configuration type of a plurality of chips; Configure the common power module according to the target chip; Determine the identification information corresponding to the target chip; The power timing control strategy corresponding to the target chip is determined based on the identification information; The common power module is controlled according to the power timing control strategy so that the common power module supplies power to the target chip according to the power timing corresponding to the target chip.

[0139] The foregoing has described in detail several embodiments of this application, but this application is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications based on the concept of this application, and all such variations and modifications should fall within the scope of protection claimed in this application.

Claims

1. A power compatibility method for a retimer chip: The target chip is determined based on the configuration type of multiple chips; Configure the common power module according to the target chip; Determine the identification information corresponding to the target chip; The power timing control strategy corresponding to the target chip is determined based on the identification information; The common power module is controlled according to the power timing control strategy so that the common power module supplies power to the target chip according to the power timing corresponding to the target chip.

2. The method according to claim 1, further comprising: Map the power pins of multiple chips to a preset common power module; The power supply capacity of the common power module is determined based on the power supply requirements of multiple chips. The power supply capacity of the common power module covers the current requirements of the power pin group of the target chip; Configure the output voltage of the common power module according to the power supply requirements of the target chip, so that the common power module outputs a power supply voltage corresponding to the target chip.

3. The method according to claim 1, The common power supply module contains different power supply groups with different maximum output currents; and the maximum output current of the same power supply group in the common power supply module is not less than the maximum current requirement of the corresponding power pin group in the plurality of chips.

4. The method according to claim 1, wherein configuring the common power module according to the target chip includes: Determine the target output voltage of the corresponding common power module based on the type of the target chip; By adjusting the resistor assembly state and / or resistor value in the feedback resistor network of the common power module, the common power module can output the target output voltage.

5. The method according to claim 3, wherein configuring the common power module according to the target chip includes: Based on the current requirements of the power pin group corresponding to the target chip, configure the overcurrent protection parameters of the power group so that the overcurrent protection threshold of the power group matches the current requirements.

6. The method according to claim 1, wherein determining the identification information corresponding to the target chip includes: The chip type identification circuit generates identification information corresponding to the target chip. The chip type identification circuit includes multiple identification configuration terminals, which are respectively connected to a first level terminal or a second level terminal through assembly resistors; By adjusting the assembly state of the assembly resistor, the plurality of identification configuration terminals form identification information that uniquely corresponds to the target chip.

7. The method according to claim 6, wherein the chip type identification circuit includes a first identification configuration terminal, a second identification configuration terminal, and a third identification configuration terminal; Each identification configuration terminal is provided with a first resistor bit connected to the high-level terminal and / or a second resistor bit connected to the low-level terminal to form identification information with a three-bit identification signal. The identification information is used to characterize different types of chips.

8. The method according to claim 1, wherein determining the power timing control strategy corresponding to the target chip based on the identification information includes: Based on the identification information, a target power timing control parameter is selected from multiple sets of power timing control parameters, and the enable state of multiple power groups in the common power module is controlled based on the target power timing control parameter.

9. The method according to claim 8, wherein the target power supply timing control parameters include at least one of the following: The power-on sequence of each power supply group; The power-on time interval between two adjacent power supply groups; The sequence of power outages for each power supply group; The time interval between power outages between two adjacent power supply groups; The timing of the reset signal release for the target chip.

10. A power compatibility device for a retimer chip, comprising: A common power supply module, which includes a first power supply group, a second power supply group, a third power supply group and a fourth power supply group; Multiple power supply pins of the target chip among the multiple chips are respectively connected to the corresponding power supply groups in the first power supply group, the second power supply group, the third power supply group and the fourth power supply group; The target chip determination module is configured to determine the target chip based on the configuration types of multiple chips. A configuration module configured to configure the common power supply module according to the target chip; An identification information determination module is configured to determine the identification information corresponding to the target chip; A power timing control strategy determination module is configured to determine a power timing control strategy corresponding to the target chip based on the identification information. The control module is configured to control the common power module according to the power timing control strategy, so that the common power module supplies power to the target chip according to the power timing corresponding to the target chip.

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