Display module and display device

Abstract

The present disclosure provides a display module and a display device. The display module comprises a touch display panel. For each frame of picture, at least one touch sensing period is inserted in a picture display period of the touch display panel. The touch display panel is configured to make the potential of the gate signal line corresponding to the non-stop pit row and the gate signal line corresponding to the non-stop pit row approximately equal in the touch sensing period. The embodiment of the present disclosure can keep the potential consistency of the gate signal line corresponding to the non-stop pit row and the non-stop pit row in the touch sensing period, thereby reducing the display touch coupling crosstalk noise in the touch display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display module and a display device. Background Technology

[0002] Currently, Touch and Display Driver Integration (TDDI) technology is gradually becoming the mainstream technology for touch display products. To improve the touch reporting rate by decoupling the touch sampling rate from the display refresh rate, touch scanning can employ intra-frame touch mode, also known as Long-H horizontal stop mode. However, intra-frame touch mode suffers from display-touch coupling crosstalk noise, and as display resolution increases, the algorithm cannot compensate for this noise, leading to significant yield losses. Summary of the Invention

[0003] To address at least one of the aforementioned problems, a first aspect of this disclosure provides a display module including a touch display panel, wherein for each frame, at least one touch sensing period is inserted into the frame display cycle of the touch display panel. The touch display panel is configured such that, during the touch sensing period, the potentials of the gate signal lines corresponding to the stopped rows and the gate signal lines corresponding to the non-stop rows are approximately equal.

[0004] Optionally, the display module further includes a display driver chip electrically connected to the touch display panel, and a first resistor, wherein a first end of the first resistor is electrically connected to the modulation voltage terminal of the display driver chip, and a second end is electrically connected to the low voltage power supply signal terminal of the display driver chip.

[0005] Optionally, the display module includes: a first capacitor and a first resistor connected in series, wherein the second end of the first resistor is electrically connected to a low-voltage power supply signal terminal via the first capacitor, or the first end of the first resistor is electrically connected to a modulation voltage terminal via the first capacitor.

[0006] Optionally, the display module further includes a display driver chip electrically connected to the touch display panel. The display driver chip includes a resistor module electrically connected between its low-voltage power supply signal terminal and modulation voltage terminal. The resistor module includes a first matching unit and a second matching unit. The first matching unit includes multiple first resistance modulation branches connected in parallel between the input and output terminals of the first matching unit; the second matching unit includes multiple second resistance modulation branches connected in parallel between the input and output terminals of the first matching unit. The first resistance modulation branch includes a first selector switch and a second resistor connected in series, and the second selector resistance modulation branch includes a second selector switch and a third resistor connected in series.

[0007] Optionally, at least a portion of the third resistors have a resistance value less than that of the second resistor, the resistance values ​​of the third resistors are different, and the resistance values ​​of the second resistors are different.

[0008] Optionally, the touch display panel includes: at least one set of gate driving circuits, the gate driving circuits including a plurality of cascaded shift register circuits, the output of the shift register circuits being electrically connected to a gate signal line, and the shift register circuits including: The input sub-circuit is electrically connected to the input terminal and the pull-up node of the shift register circuit, and is configured to transmit the signal at the input terminal to the pull-up node based on the input control signal; The pull-up sub-circuit is electrically connected to the clock signal terminal, the output terminal of the shift register circuit, and the pull-up node, and is configured to electrically connect the clock signal terminal to the output terminal based on the potential of the pull-up node; The first control sub-circuit is electrically connected to the output terminal of the shift register circuit, the first power signal terminal and the first control terminal, and is configured to electrically connect the output terminal to the first power signal terminal based on the signal of the first control terminal being at an effective level. The signal at the first control terminal is at an active level during the touch sensing period and at an inactive level during the screen display period.

[0009] Optionally, the shift register circuit further includes: a reset sub-circuit, electrically connected to the first reset control terminal, the pull-up node, and the first power supply signal terminal, configured to electrically connect the pull-up node and the first power supply signal terminal based on the signal of the first reset control terminal, wherein the signal of the first control terminal includes an effective level period between the period when the signal of the first reset control terminal is at an effective level and the period when the signal of the input control terminal of the first-stage shift register circuit is at an effective level.

[0010] Optionally, the first control sub-circuit includes a first transistor, the first electrode of which is electrically connected to the output terminal of the shift register circuit, the second electrode of which is electrically connected to the first power supply signal terminal, and the control electrode of which is electrically connected to the first control terminal.

[0011] Optionally, the touch display panel includes: at least one set of gate driving circuits, the gate driving circuits including a plurality of cascaded shift register circuits, the output of the shift register circuits being electrically connected to a gate signal line, and the shift register circuits including: The input sub-circuit is electrically connected to the input terminal and the pull-up node of the shift register circuit, and is configured to transmit the signal at the input terminal to the pull-up node based on the input control signal; The pull-up sub-circuit is electrically connected to the clock signal terminal, the output terminal of the shift register circuit, and the pull-up node, and is configured to electrically connect the clock signal terminal to the output terminal based on the potential of the pull-up node; The second control sub-circuit is electrically connected to the output terminal, clock signal terminal, and second control terminal of the shift register circuit. It is configured to electrically connect the output terminal and the clock signal terminal based on the signal of the second control terminal being at an effective level. The signal of the second control terminal is at an effective level during the touch sensing period and at an ineffective level during the screen display period.

[0012] Optionally, the second control sub-circuit includes a second transistor, the first electrode of which is electrically connected to the clock signal terminal, the second electrode of which is electrically connected to the output terminal of the shift register circuit, and the control electrode of which is electrically connected to the second control terminal.

[0013] A second aspect of this disclosure provides a display device including the display module described above.

[0014] The beneficial effects of this disclosure are as follows: This disclosure addresses existing problems by providing a display module and display device. A touch display panel is incorporated, which inserts at least one touch sensing period into each frame's display cycle. During this touch sensing period, the potentials of the gate signal lines corresponding to the stopped rows and the gate signal lines corresponding to the non-stopped rows are approximately equal. This ensures that the voltage fluctuation amplitudes on the gate signal lines of the stopped and non-stopped rows are also approximately consistent within the intra-frame touch sensing period. This reduces or even eliminates display touch coupling crosstalk noise, improving product yield. Furthermore, the embodiments of this disclosure do not require algorithm compensation, are applicable to high-resolution products, and have broad application prospects. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic circuit diagram of a shift register circuit, a related technology, is shown. Figure 2 Showing based on Figure 1 The timing diagram of the relevant ports of the shift register circuit in the schematic diagram shown is for the stop row and non-stop row. Figure 3 This diagram illustrates the in-plane capacitance distribution in a touch display panel. Figure 4 The diagram shows numerical values ​​of touch baseline, raw touch data, and V-noise in the relevant technologies. Figure 5 This diagram illustrates a display module according to an embodiment of the present disclosure; Figure 6This is a schematic diagram of a display module according to another embodiment of the present disclosure; Figure 7 Show Figure 6 A schematic diagram of the resistor module in the display module of the illustrated embodiment; Figure 8 A schematic diagram of a shift register circuit in a display module according to another embodiment of the present disclosure is shown; Figure 9 A schematic circuit diagram of a shift register circuit in a display module according to an embodiment of the present disclosure is shown. Figure 10 A schematic timing diagram of a key port in a shift register circuit in a display module according to an embodiment of the present disclosure is shown; Figure 11 A schematic circuit diagram of a shift register circuit in a display module according to another embodiment of the present disclosure is shown. Detailed Implementation

[0017] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0018] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising," "including," etc., mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms "connected," "linked," etc., are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Furthermore, in this disclosure, an electrical connection can be a direct connection or a connection of transistors separated by a certain conducting element.

[0019] Currently, embedded touch display panels based on TDDI technology and gate drive circuit architecture, when using the Long-H mode to achieve a high touch reporting rate, suffer from display touch coupling crosstalk noise, also known as V-noise, caused by the physical characteristics of the gate drive circuit and the parasitic capacitance coupling of the gate touch.

[0020] Figure 1The diagram shows a schematic of a first-stage shift register circuit of an exemplary gate driving circuit. The output terminals of each stage of the shift register circuit of the gate driving circuit are connected to the gate signal lines respectively, and are used to scan the pixel rows corresponding to each gate signal line line by line when the shift register circuit shifts and outputs. Figure 2 Show Figure 1 The diagram shows the timing of key ports of the shift register circuit and some ports of the gate drive circuit formed by the shift register circuit during a portion of a frame image display period. The t2 period includes a touch sensing period. For Long-H mode, touch sensing (TP Sensing) periods are evenly inserted within the display period using a stop-and-go method. Combined with... Figure 1 and Figure 2 As shown, during the touch sensing period in Long-H mode, the display driver chip switches its operating mode, stopping the display drive of the data signal terminal (Source) and the gate drive circuit. To maintain consistency with the touch drive signal used to drive the touch emission electrode, the signals connected to all signal lines of the gate drive circuit become pulse signals identical to the touch drive signal. The amplitude of this pulse signal is low, for example... Figure 2 The signal terminals VDDO, STV, and CLK are shown. Of course, although not shown, other signal terminals VDDE and VGL are also low-level pulse signals of this amplitude, and the data signal lines also become low-level pulse signals. During the touch sensing period, the display scan pauses midway (commonly known as a "pause"). The pixels scanned and driven by the gate signal line of the shift register circuit that should have output a valid signal during this period are called paused rows, and the other rows are called non-pause rows. For example... Figure 2 As shown, a stopped row can include a row entering the stopped row and a row exiting the stopped row, while a non-stopped row is a normal display scan row. The pull-up node PU of the shift register circuit corresponding to the stopped row is high, while the pull-up node PU and the active pull-down node PD1 or PD2 of the shift register circuit corresponding to the non-stopped row are set low. Because the pull-up node PU of the stopped row is high, the transistor M3 is turned on during the touch sensing period in the pull-up node PU of the shift register circuit corresponding to the core stopped position. The voltage fluctuation corresponding to the touch drive signal charges the output terminal OUT and the corresponding gate signal line through the transistor M3. However, since the pull-up node PU and the active pull-down node PD1 or PD2 of the non-stopped row are at a low potential (low power supply signal terminal VGL), the output terminal OUT of the shift register circuit corresponding to the non-stopped row maintains the same low potential as the low power supply signal terminal VGL in its original coupled state. Therefore, there is a difference in potential between the output terminals and corresponding gate signal lines of the shift register circuits of the stopped and non-stopped rows.

[0021] like Figure 3The diagram shown illustrates the parasitic capacitance within the display area of ​​the touch panel. During the touch sensing period, the voltages of the data signal line Data(n) and the common electrode Vcom are the same pulse signals as the touch drive signal; the only influencing variable is the voltage of each gate signal line. Correspondingly, when there is a difference in the potential at the output of the shift register circuit for the stopped and non-stop rows, the parasitic capacitance Cgc between the gate and the touch electrode differs. It should be noted that... Figure 3 An example of a common electrode being reused as a touch electrode is shown. In addition, when the touch electrode is disposed in an independent electrode film layer, the parasitic capacitance between the gate and the touch electrode also has the above-mentioned differences, which will not be elaborated here.

[0022] like Figure 4 As shown, this diagram illustrates the numerical values ​​of the touch sensing signals within the nth frame of a touch display panel, obtained by using one touch sampling channel on each of the left and right screens. According to the noise calculation principle, noise Diff(n) = Rawdata(n) - Baseline, where Rawdata(n) represents the original touch sensing signal sampled by the touch chip, and Baseline represents the touch baseline value when there is no touch. The final noise level is determined by the difference between the two. Figure 4 As shown, for the same touch baseline value, when the display refresh rate and touch reporting rate are the same, the position of the touch scan and the display stop point are always aligned in a fixed manner. That is, the stop point position appears in the same row in each acquired raw touch data (see...). Figure 4 The raw touch data (frame n, located in the upper center) has a fixed deviation. This fixed deviation is synchronously incorporated into the touch baseline value. After the difference between the two, the fixed deviation is canceled out, resulting in very low noise and no observable V-noise (see...). Figure 4 The noise in the nth frame at the upper center position). When the display refresh rate is lower than the touch reporting rate, for example, a display refresh rate of 60Hz and a touch reporting rate of 120Hz, two complete scans of raw touch data need to be completed within the duration of one frame. Due to the misalignment between the touch cycle and the display frame cycle, the relative position of the stopping position and the touch scan will have two combinations (i.e., it may appear as follows). Figure 4 If two types of raw touch data (top and bottom positions) are used, the final noise will also exhibit two patterns, meaning the deviations cancel each other out (see...). Figure 4 Noise in the nth frame at the upper-middle position) and residual amplification of bias (see Figure 4(Noise in the nth frame at the lower center). The stop position does not match the touch baseline value. After subtraction, the difference between the corresponding positions of the stop position is significantly larger, resulting in two V-shaped noise bands on the front of the panel, which is V-noise exceeding the standard. Essentially, the stop position and touch scan are no longer fixedly aligned under different frequencies. The baseline cannot stably offset the fixed deviation of the original touch data (Rawdata), ultimately leaving visible noise. It should be noted that this situation not only occurs in panels where the display refresh rate is lower than the reporting rate, but also in variable frequency display panels where the refresh rate varies with the display mode. Therefore, as long as there is a difference in frequency between the display refresh rate and the reporting rate, the V-noise exceeding the standard problem will occur.

[0023] The current industry practice is to use algorithmic compensation in the touch driver chip. This involves batch collecting V-noise values ​​from the panels, calculating a fixed compensation amount (also known as the cook value, usually the statistical average), and subtracting this value from the raw touch data at the corresponding location to offset V-noise. However, as panel pixel density (PPI) increases, the number of gate signal lines and the number of clock signal lines (CLK) in the driving gate circuit increase, leading to a continuous increase in the voltage fluctuation amplitude at the gate and a continuous rise in the absolute value of V-noise, reaching the upper limit of the algorithmic compensation capability. Simultaneously, process fluctuations during mass production (such as film thickness and linewidth deviations causing inconsistent parasitic capacitance (Cgc) between the gate and touch electrode, and discrete transistor characteristics in shift registers) result in differences in the amplitude and location of V-noise for each display panel. A uniform cook value cannot cover all panels, ultimately leading to a significant decrease in product yield.

[0024] Therefore, there is an urgent need to provide a display solution that can overcome the aforementioned problems of high display touch coupling crosstalk noise and yield loss caused by the super-algorithm compensation limit under high pixel density.

[0025] In view of this, the present disclosure provides a display module, including a touch display panel, wherein for each frame of the image, at least one touch sensing period is inserted into the image display cycle of the touch display panel; The touch display panel is configured such that, during the touch sensing period, the potentials of the gate signal lines corresponding to the stopped rows and the gate signal lines corresponding to the non-stop rows are approximately equal.

[0026] In this embodiment, the provided touch display panel inserts at least one touch sensing period into the display cycle of each frame. The touch display panel is configured such that during the touch sensing period, the potentials of the gate signal lines corresponding to the stop row and the gate signal lines corresponding to the non-stop row are approximately equal. As a result, the voltage fluctuation amplitudes on the gate signal lines of the stop row and the non-stop row are also approximately the same during the touch sensing period within the frame. This can reduce or even eliminate display touch coupling crosstalk noise and improve product yield. In addition, the embodiments of this disclosure do not require algorithm compensation and are applicable to high-resolution products.

[0027] The specific structure and function of the display module of this disclosure embodiment are described below with reference to the accompanying drawings and specific embodiments.

[0028] Reference Figure 5 As shown, the display module includes a touch display panel 1, a display driver chip 11 electrically connected to the touch display panel 1, and a first resistor R1. In embodiments of this disclosure, the touch display panel 1 refers to a display panel with touch functionality, such as a TDDI display panel. The first end of the first resistor R1 is electrically connected to the modulation voltage terminal VMOD of the display driver chip 11, and the second end is electrically connected to the low-voltage power supply signal terminal VGLO of the display driver chip 11. The low-voltage power supply signal terminal VGLO is a voltage output pin in the display driver chip 11 used to generate and output the low-level power supply signal terminal VGL used in the gate drive circuit. The modulation voltage terminal VMOD, also known as the gate modulation voltage pin, is used to output a low-level pulse signal consistent with the touch drive signal during the touch sensing period and to output a low-level DC reference signal, such as 0V or other low-level amplitude common voltage, during the non-touch sensing period.

[0029] Specifically, the touch display panel 1 includes a display area AA and a non-display area NA disposed around the display area AA. The display driver chip 11 can be disposed in the non-display area NA. The display module may also include a printed circuit board 2 and a flexible circuit board 3. The printed circuit board 2 can be electrically connected to the touch display panel 1 via the flexible circuit board 3. For example, one end of the flexible circuit board 3 is electrically connected to the touch display panel 1, and the other end is electrically connected to the printed circuit board 2. A first resistor R1 can be disposed on the printed circuit board 2. It should be noted that when the layout and wiring space of the touch display panel 2 is not considered, the first resistor R1 can also be disposed on the touch display panel.

[0030] By connecting a first resistor R1 in series between the modulation voltage terminal VMOD and the low-voltage power supply signal terminal VGLO, the rising and falling edges of the touch drive signal waveform used for touch sensing are made closer to those of the signal waveform on the gate signal line. This ensures that the potentials of the gate signal lines corresponding to the stopped rows and the corresponding non-stop rows are approximately equal during the touch sensing period. With this setting, even if the display refresh rate and the touch reporting rate differ in Long-H mode, no significant V-noise will occur between the gate signal lines of the stopped and non-stop rows during the touch sensing period, improving product yield.

[0031] It is worth mentioning that the inventors, through experiments, verified that the effect produced by different values ​​of the first resistor R1 varies for different touch display panels. Specifically, Table 1 shows the V-noise values ​​obtained by verifying two touch display panels, 1# and 2#, with the same design parameters, using different values ​​of the first resistor R1. As can be seen from Table 1, the data corresponding to rows Y4, Y8...Y52 correspond to the touch sensing data sampled by different columns of touch sensing electrodes of the touch driver chip when the first resistor R1 has different values. The "max" row represents the maximum value of the V-noise value for each column of the first resistor R1. As can be seen from the table, even touch display panels with the same design parameters have different actual physical parameters, resulting in different V-noise values ​​obtained by the same value of the first resistor R1. This proves that the effect produced by different values ​​of the first resistor R1 varies for different touch display panels.

[0032] It is particularly important to note, as shown in Table 1, that setting the first resistor R1 significantly reduces V-noise in the touch display panel. Furthermore, within a certain resistance range, increasing the value of the first resistor R1 further enhances the V-noise reduction effect. However, there is an optimal matching resistance value. For the touch display panel in this example, when the first resistor R1 is 51Ω, the maximum V-noise value can be reduced by 60% to 80% compared to not setting the first resistor R1. In other words, the first resistor R1 with the optimal matching resistance value can be adjusted during the manufacturing process for different touch display panels to achieve the best V-noise reduction effect within the given architecture.

[0033] Specifically, from a process perspective, a resistor pad can be set during the layout of the printed circuit board, and the optimal configuration for each panel can be adjusted by hardware soldering a first resistor R1 with different resistance values ​​during the module manufacturing process.

[0034] Table 1

[0035] For example, refer to Figure 5As shown, the display module includes a first capacitor C1 and a first resistor R1 connected in series. A first terminal of the first resistor R1 is electrically connected to the modulation voltage terminal VMOD of the display driver chip 11, and a second terminal of the first resistor R1 is electrically connected to the low-voltage power supply signal terminal VGLO via the first capacitor C1. In another example, although not shown, the display module includes a first capacitor C1 and a first resistor R1 connected in series. A first terminal of the first resistor R1 is electrically connected to the low-voltage power supply signal terminal VGLO of the display driver chip 11, and a second terminal of the first resistor R1 is electrically connected to the modulation voltage terminal VMOD via the first capacitor C1.

[0036] This is because, currently, in order to ensure that the signals at each stage of the gate drive circuit synchronously sense the touch drive signal for synchronous output, a first capacitor C1 is typically connected in series between the modulation voltage terminal VMOD and the low-voltage power supply signal terminal VGLO of the display driver chip 11. By connecting the first resistor R1 in series with the first capacitor C1 between the modulation voltage terminal VMOD and the low-voltage power supply signal terminal VGLO, the aforementioned noise reduction function can be directly achieved in the capacitive sensing path of the touch drive signal, thereby simplifying the layout and wiring space.

[0037] In another alternative embodiment, the matching resistor can be integrated within the display driver chip, enabling adjustable resistor matching levels. (See also...) Figure 6 As shown, the display module includes a display driver chip 11 electrically connected to the touch display panel 1. The display driver chip 11 includes a resistor module 11-1 electrically connected between its low-voltage power supply signal terminal VGLO and its modulation voltage terminal VMOD.

[0038] Similarly, the low-voltage power supply signal terminal VGLO is a voltage output pin in the display driver chip 11 used to generate and output the low-level power supply signal terminal VGL used in the gate drive circuit. The modulation voltage terminal VMOD, also known as the gate modulation voltage pin, is used to output a low-level pulse signal consistent with the touch drive signal during the touch sensing period, and to output a low-level DC reference signal, such as 0V or other low-level amplitude common voltage, during the non-touch sensing period.

[0039] Specifically, refer to Figure 7As shown, resistor module 11-1 includes a first matching unit 111 and a second matching unit 121. The first matching unit 111 includes multiple first resistance modulation branches 111_1, 111_2, 111_3, ..., 111_N connected in parallel between its input and output terminals. The second matching unit 121 includes multiple second resistance modulation branches 111_1, 111_2, 111_3, ..., 111_M connected in parallel between its input and output terminals. Wherein, N and M are integers greater than or equal to 1. The first resistance modulation branch 111_n includes a first selection switch K1 and a second resistor R2 connected in series, and the second selection resistance modulation branch 121_m includes a second selection switch K2 and a third resistor R3 connected in series. Here, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M. It should be noted that the second resistors R2 are not intended to be resistors with the same resistance value, nor are the third resistors R3 intended to be resistors with the same resistance value; rather, they are used only to represent multiple different branch structures.

[0040] It should be understood that by controlling the on / off schemes of multiple first selection switches K1 and multiple second selection switches K2, the resistance value of the equivalent resistance connected in series between the low-voltage power supply signal terminal VGLO and the modulation voltage terminal VMOD can be changed.

[0041] Through the above settings, the multiple first resistance modulation branches 111_1, 111_2, 111_3, ... 111_N within the first matching unit 111 provide the first range of matching resistors, and the multiple second resistance modulation branches 111_1, 111_2, 111_3, ... 111_M within the second matching unit 121 provide the second range of matching resistors. Therefore, compared to connecting discrete devices in series on the peripheral circuitry of the display driver chip 11, during the subsequent optimal matching and debugging phase of the display module, only the on / off states of multiple first selection switches K1 and multiple second selection switches K2 need to be changed to obtain multiple resistance debugging schemes. This eliminates the need for repeated hardware soldering and desoldering during the optimal matching and debugging phase, improving debugging convenience.

[0042] Furthermore, it should be noted that even touch display panels from the same batch with the same design parameters may have different final parameters due to variations in actual manufacturing processes. These variations can lead to different optimal matching resistor values ​​for individual touch display panels, which discrete components struggle to achieve. By providing the aforementioned resistor module 11-1, the shortcomings of discrete components can be significantly improved, providing multi-level fine modulation and achieving an optimized V-noise reduction scheme for the aforementioned architecture in response to process variations.

[0043] Optionally, at least a portion of the third resistors R3 have a resistance value less than that of the second resistor R2, and the resistance values ​​of the multiple third resistors R3 are different, as are the resistance values ​​of the multiple second resistors R2. For example, the difference between any two second resistors R2 can be on the order of 10Ω or 100Ω, and the difference between any two third resistors R3 can be on the order of 1Ω or 0.1Ω. Furthermore, the second resistors R2 may include 0Ω resistors, and the third resistors R3 may include 0Ω resistors.

[0044] This configuration allows for coarse adjustment levels using the first matching unit 111 and fine adjustment levels using the second matching unit 121. This provides an optimal matching resistor level suitable for different touch display panels.

[0045] In some alternative embodiments, the difference between this embodiment and the embodiment described above is that, through structural improvements to the shift register circuit in the gate drive circuit, the potentials of the gate signal lines corresponding to the stop row and the gate signal lines corresponding to the non-stop row are made equal during the touch sensing period.

[0046] Specifically, the touch display panel of the display module includes at least one set of gate driving circuits. Each gate driving circuit includes multiple cascaded shift register circuits, and the output terminal G_Out of the shift register circuit is electrically connected to a gate signal line. (Refer to...) Figure 8 As shown, the shift register circuit includes: an input sub-circuit 10, a pull-up sub-circuit 20, and a first control sub-circuit 30.

[0047] The input sub-circuit 10 is electrically connected to the input terminal Input and the pull-up node PU of the shift register circuit, and is configured to transmit the signal of the input terminal Input to the pull-up node PU based on the input control signal; the pull-up sub-circuit 20 is electrically connected to the clock signal terminal CLK, the output terminal G_Out of the shift register circuit, and the pull-up node PU, and is configured to connect the signal of the clock signal terminal CLK to the output terminal G_Out based on the potential of the pull-up node PU; the first control sub-circuit 30 is electrically connected to the output terminal G_Out of the shift register circuit, the first power signal terminal VGL, and the first control terminal Cr1, and is configured to connect the output terminal G_Out to the first power signal terminal VGL based on the signal of the first control terminal Cr1 being at an effective level. The signal of the first control terminal Cr1 is at an effective level during the touch sensing period and at an ineffective level during the screen display period.

[0048] By providing the first control sub-circuit 30 and the signal provided by the first control terminal Cr1 being at an effective level during the touch sensing period in Long-H mode and at an ineffective level during the screen display cycle, it is possible to ensure that, regardless of the location of the stoppage during the touch sensing period, the output terminal G_Out of the shift register circuit connected to the gate signal line of the stoppage row has a path to the first power signal terminal VGL under the control of the first control terminal Cr1. This ensures that the potential of the gate signal line of the corresponding stoppage row and the gate signal line of the corresponding non-stoppage row are equal, i.e., both are pulled low to the potential of the first power signal terminal VGL. Therefore, regardless of whether the display refresh rate and the reporting rate are the same, the problem of increased V-noise caused by the potential difference of the gate signal lines of the stoppage row and the non-stoppage row can be avoided, thereby improving product yield.

[0049] For example, refer to Figure 8 As shown, the first control unit 30 includes a first transistor T1. The first electrode of the first transistor T1 is electrically connected to the output terminal G_Out of the shift register circuit, the second electrode is electrically connected to the first power supply signal terminal VGL, and the control electrode is electrically connected to the first control terminal T1. When the first control terminal Cr1 receives a valid signal, for example, in this example, the first transistor T1 is an N-type transistor with a high valid level, the first transistor T1 is turned on, thereby electrically connecting the output terminal G_Out of the shift register circuit to the first power supply signal terminal VGL.

[0050] Optionally, refer to Figure 8 As shown, the input sub-circuit 10 includes a second transistor T2. The first terminal and the control terminal of the second transistor T2 are electrically connected to the input terminal Input of the shift register circuit, and the second terminal is electrically connected to the pull-up node PU. It can be understood that in this example, the input control signal is the signal at the input terminal Input. When the input terminal Input is at an active level, the input terminal Input is electrically connected to the pull-up node PU. It should also be understood that this disclosure is not intended to limit the specific connection method of the input sub-circuit 10. The control terminal of the second transistor T2 can also receive independent control signals, which will not be elaborated upon herein.

[0051] The pull-up circuit 20 includes a third transistor T3 and a third capacitor C3. The first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, the second electrode is electrically connected to the output terminal G_Out of the shift register circuit, and the control electrode is electrically connected to the pull-up node PU. The first electrode of the third capacitor C3 is electrically connected to the pull-up node PU, and the second electrode is electrically connected to the output terminal G_Out. When the potential of the pull-up node PU is high and raised to a level sufficient to turn on the third transistor T3 under the bootstrap effect of the third capacitor C3, the clock signal terminal CLK is electrically connected to the output terminal G_Out.

[0052] Optionally, refer to Figure 9As shown, the shift register circuit also includes a reset sub-circuit 40, which is electrically connected to a first reset control terminal RST, a pull-up node PU, and a first power supply signal terminal VGL. It is configured to electrically connect the pull-up node PU to the first power supply signal terminal VGL based on the signal from the first reset control terminal RST. For example, the reset sub-circuit 40 includes a fourth transistor T4. The first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, the second electrode is electrically connected to the first power supply signal terminal VGL, and the control electrode is electrically connected to the first reset control terminal RST. When the first reset control terminal RST is active, the fourth transistor T4 is turned on, electrically connecting the pull-up node PU to the first power supply signal terminal VGL to reset the pull-up node PU.

[0053] Reference Figure 10 As shown, Figure 10 Show Figure 9 The timing diagram of the key ports in the circuit schematic shown is shown, where STV1 represents... Figure 9 The input terminal Input of the gate drive circuit of the shift register circuit shown is connected to the initial signal line. RST represents the signal connected to the first reset control terminal RST, and Cr1 represents the signal connected to the first control terminal Cr1.

[0054] As can be seen, in the embodiments of this disclosure, the reset sub-circuit 40 is a global reset circuit. It is set to a high level before each effective level represented by the initial signal line being high, so as to perform a global reset on all shift register circuits. When the initial signal line is connected to a high level, the display cycle of one frame begins.

[0055] In addition, from Figure 10 As can be seen, multiple touch sensing periods represented by TP are inserted into each frame display cycle. During these periods, the first control terminal Cr1 receives an effective level signal, thereby setting the output terminal G_Out of each register circuit to the same potential without discrimination. This ensures that the potential of the gate signal line is consistent regardless of the location of the stopped row, thus avoiding the problem of increased V-noise caused by the potential difference between the gate signal lines of the stopped and non-stop rows and improving product yield.

[0056] It is worth mentioning that, referring to Figure 10 In the embodiment shown, the signal of the first control terminal Cr1 includes an effective level period between the effective level period of the signal of the first reset control terminal RST and the effective level period of the signal of the initial signal of the input control terminal of the first stage shift register circuit, i.e., the initial signal line STV1.

[0057] With this setting, the first control sub-circuit 20 can reuse the transistor used in the existing structure for global reset of the output terminal G_OUT, and reuse the period before the input control terminal of the first-stage shift register circuit is at an effective level as the touch sensing period and the global reuse function for the output terminal G_Out. Thus, the functions of the present disclosure embodiment can be achieved with almost no change to the overall layout of the existing gate drive circuit, that is, a minimalist design can be achieved with almost no change to the existing structure.

[0058] In another alternative embodiment, refer to Figure 11 As shown, this embodiment is similar to the one described above. Figure 8 and Figure 9 The difference between the embodiments is that the shift register circuit includes a second control sub-circuit 50, which is electrically connected to the output terminal G_Out, the clock signal terminal CLK, and the second control terminal Cr2 of the shift register circuit. It is configured to electrically connect the output terminal to the clock signal terminal CLK based on the signal of the second control terminal Cr2 being at an effective level. The signal of the second control terminal Cr2 is at an effective level during the touch sensing period and at an ineffective level during the screen display period.

[0059] Specifically, the second control sub-circuit 50 includes a second transistor T2', the first electrode of the second transistor T2' is electrically connected to the clock signal terminal CLK, the second electrode is electrically connected to the output terminal G_Out of the shift register circuit, and the control electrode is electrically connected to the second control terminal Cr2.

[0060] This design establishes a second control sub-circuit 50 between the output G_Out of the shift register circuit and the clock signal line CLK. The signal provided by the second control terminal Cr2 is active during the touch sensing period in Long-H mode and inactive during the screen display cycle. This ensures that regardless of the location of the stop signal line during the touch sensing period, the output G_Out of the shift register circuit connected to the stop signal line maintains a path to the clock signal line CLK under the control of the second control terminal Cr2. This achieves equal potential between the gate signal lines of the stop signal line and the non-stop signal line, meaning both are pulled low to the first power supply signal line VGL. Therefore, regardless of whether the display refresh rate and reporting rate are the same, the V-noise increase caused by the potential difference between the gate signal lines of the stop signal line and the non-stop signal line can be avoided, improving product yield.

[0061] For example, the timing of the second control terminal Cr2 can be consistent with that shown in Figure 10, because the signal of the second control terminal Cr2 is used to pull the output terminal G_Out high, thus still requiring a global reset circuit electrically connected to the output terminal G_Out. Of course, because there is an independent global reset circuit, the effective level period of the second control terminal Cr2 before the initial signal line STV1 is active is not necessary. When this period exists, it is not intended to reset the output terminal G_Out, but rather to utilize the blank period Tb outside the screen display cycle to add a touch sensing period, thereby improving time utilization.

[0062] For example, refer to Figure 11 As shown, the shift register circuit may further include a second reset sub-circuit 60, which may include a fifth transistor T5. The first electrode of the fifth transistor T5 is electrically connected to the output terminal G_Out of the shift register circuit, the second electrode is electrically connected to the first power supply signal terminal VGL, and the control electrode is electrically connected to the first reset control terminal RST, so as to reset the output terminal G_Out of the shift register circuit.

[0063] It should also be noted that the above Figure 9 and Figure 11 The circuit schematic in the diagram omits the specific structure of the noise reduction unit controlled by the first pull-down node PD1 and the second pull-down node PD2 by using short dashed boxes. Those skilled in the art should understand that the actual shift register circuit may also include multiple noise reduction sub-circuits controlled by the first pull-down node PD1 and / or the second pull-down node PD2 to ensure the stable operation of the shift register circuit. This will not be elaborated further here.

[0064] Based on the same inventive concept, embodiments of this disclosure also provide a display device, including the display module described in the above embodiments.

[0065] In this embodiment, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, in-vehicle display, digital photo frame, or navigator. By using the above display module, the problem of excessive V-noise when the refresh rate and reporting rate are inconsistent in Long-H mode in the display product with integrated touch and display architecture can be effectively improved, thereby increasing product yield, enhancing user experience, and having broad application prospects.

[0066] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A display module, characterized in that, Including a touch display panel, for each frame of the image, at least one touch sensing period is inserted into the image display cycle of the touch display panel. The touch display panel is configured such that during the touch sensing period, the potentials of the gate signal lines corresponding to the stopped rows and the gate signal lines corresponding to the non-stopped rows are approximately equal.

2. The display module according to claim 1, characterized in that, It also includes a display driver chip electrically connected to the touch display panel, and a first resistor. The first end of the first resistor is electrically connected to the modulation voltage terminal of the display driver chip, and the second end is electrically connected to the low voltage power supply signal terminal of the display driver chip.

3. The display module according to claim 2, characterized in that, include: The first capacitor and the first resistor are connected in series. The second terminal of the first resistor is electrically connected to the low-voltage power supply signal terminal via the first capacitor, or The first end of the first resistor is electrically connected to the modulation voltage terminal via the first capacitor.

4. The display module according to claim 1, characterized in that, It also includes a display driver chip electrically connected to the touch display panel, the display driver chip including a resistor module electrically connected between its low-voltage power supply signal terminal and modulation voltage terminal. The resistor module includes: a first matching unit and a second matching unit. The first matching unit includes multiple first resistance modulation branches connected in parallel between the input and output terminals of the first matching unit, and the second matching unit includes multiple second resistance modulation branches connected in parallel between the input and output terminals of the first matching unit. The first resistance modulation branch includes a first selector switch and a second resistor connected in series, and the second selector resistance modulation branch includes a second selector switch and a third resistor connected in series.

5. The display module according to claim 4, characterized in that, At least a portion of the third resistors have a resistance value less than that of the second resistor. The resistance values ​​of the multiple third resistors are different, and the resistance values ​​of the multiple second resistors are also different.

6. The display module according to claim 1, characterized in that, The touch display panel includes at least one set of gate driving circuits, each gate driving circuit including a plurality of cascaded shift register circuits, the output of which is electrically connected to a gate signal line. The shift register circuit includes: An input sub-circuit, electrically connected to the input terminal and pull-up node of the shift register circuit, is configured to transmit the signal from the input terminal to the pull-up node based on the input control signal. A pull-up circuit, electrically connected to the clock signal terminal, the output terminal of the shift register circuit, and the pull-up node, is configured to electrically connect the signal from the clock signal terminal to the output terminal based on the potential of the pull-up node. A first control sub-circuit is electrically connected to the output terminal, the first power supply signal terminal, and the first control terminal of the shift register circuit, and is configured to electrically connect the output terminal to the first power supply signal terminal based on the signal level of the first control terminal being valid. The signal from the first control terminal is at an active level during the touch sensing period and at an inactive level during the screen display period.

7. The display module according to claim 6, characterized in that, The shift register circuit also includes: A reset sub-circuit, electrically connected to a first reset control terminal, the pull-up node, and the first power signal terminal, is configured to electrically connect the pull-up node and the first power signal terminal based on the signal from the first reset control terminal. The signal at the first control terminal includes an effective level period between the period when the signal at the first reset control terminal is at an effective level and the period when the signal at the input control terminal of the first-stage shift register circuit is at an effective level.

8. The display module according to claim 6, characterized in that, The first control sub-circuit includes a first transistor, the first electrode of the first transistor is electrically connected to the output terminal of the shift register circuit, the second electrode is electrically connected to the first power signal terminal, and the control electrode is electrically connected to the first control terminal.

9. The display module according to claim 1, characterized in that, The touch display panel includes at least one set of gate driving circuits, each gate driving circuit including a plurality of cascaded shift register circuits, the output of which is electrically connected to a gate signal line. The shift register circuit includes: An input sub-circuit, electrically connected to the input terminal and pull-up node of the shift register circuit, is configured to transmit the signal from the input terminal to the pull-up node based on the input control signal. A pull-up circuit, electrically connected to the clock signal terminal, the output terminal of the shift register circuit, and the pull-up node, is configured to electrically connect the signal from the clock signal terminal to the output terminal based on the potential of the pull-up node. The second control sub-circuit is electrically connected to the output terminal of the shift register circuit, the clock signal terminal, and the second control terminal, and is configured to electrically connect the output terminal and the clock signal terminal based on the signal level of the second control terminal being valid. The signal of the second control terminal is at an active level during the touch sensing period and at an inactive level during the screen display period.

10. The display module according to claim 9, characterized in that, The second control sub-circuit includes a second transistor, the first electrode of which is electrically connected to the clock signal terminal, the second electrode of which is electrically connected to the output terminal of the shift register circuit, and the control electrode of which is electrically connected to the second control terminal.

11. A display device, characterized in that, Includes the display module as described in claims 1-10.

Images