FPGA-based BiSS-C signal asynchronous acquisition method

Abstract

The application provides a BiSS-C signal asynchronous acquisition method based on FPGA, and the falling edge of a SLO signal returned by a slave machine based on a BiSS-C protocol is used as an asynchronous acquisition trigger reference; a plurality of sampling points are obtained by continuously sampling the SLO signal by using an oversampling clock in a data bit transmission period; and a continuous half of the sampling points located in a middle region are selected to form a data decision window, so as to avoid metastable state regions at both ends of the signal; the levels of the sampling points in the data decision window are counted, and the output level of the data bit is determined by a majority voting mechanism; and the method does not need to measure channel line delays in advance, can adapt to transmission delays of different channels, and can suppress narrow pulse noise and signal edge jitter.

Description

Technical Field

[0001] This invention relates to the field of high-speed serial communication and multi-channel synchronous data acquisition technology, and in particular to an FPGA-based asynchronous acquisition method for BiSS-C signals, which can be used in absolute encoders, laser interferometer signal processing boards and other high-precision sensing devices using BiSS-C interfaces. Background Technology

[0002] In applications such as ultra-precision equipment manufacturing, robot motion control, and precision measurement, it is often necessary to acquire data from multiple displacement measurement channels. To meet the needs of equipment control and status monitoring, the acquisition system should have high data transmission rates, channel synchronization, and anti-interference capabilities.

[0003] BiSS-C (Bidirectional Serial Synchronous Continuous) is a bidirectional serial synchronous continuous communication protocol with features such as high transmission rate, low hardware implementation cost, and support for CRC check. Therefore, it is widely used in high-precision sensing devices such as absolute encoders and laser interferometer phase boards.

[0004] Existing BiSS-C data acquisition solutions can be broadly categorized into three types. The first type is dedicated decoding chip solutions. These solutions offer stable timing and are easy to develop, but their high specialization and cost make them difficult to adapt to multi-channel integration requirements. The second type utilizes software decoding solutions based on serial processors (such as DSPs and MCUs), typically employing SPI interfaces or GPIOs to simulate timing for data reading. However, limited by the serial architecture of the processor, this solution has a low upper limit on single-channel transmission rate; in multi-channel scenarios, polling is required, compromising real-time performance. The third type is FPGA-based hardware decoding solutions. FPGA decoding offers significant advantages in parallel processing capabilities and transmission rates, but most existing designs rely on slave devices returning data at the rising edge of the MA clock, neglecting line delays introduced by transmission cables and level conversions. This can lead to sampling points deviating from the valid data window, resulting in acquisition errors.

[0005] To address line delay issues, existing compensation schemes typically measure the delay value first and then adjust the transmission clock phase. This method requires introducing a line delay measurement step. Once the line delay fluctuates, data acquisition errors may occur within the current communication cycle. Summary of the Invention

[0006] This invention aims to provide an FPGA-based asynchronous acquisition method for BiSS-C signals to address the problem of inconsistent transmission delays across channels during multi-channel BiSS-C acquisition, which causes fixed sampling points to deviate from the valid data window and thus lead to data acquisition errors. This method uses the falling edge of the SLO signal's response as the asynchronous sampling start reference for each channel, performing multi-point sampling and majority voting within the stable interval of the data bits, thereby eliminating the need to pre-measure line delays before communication.

[0007] To achieve the above objectives, the FPGA-based asynchronous acquisition method for BiSS-C signals includes the following steps:

[0008] Step S1: The FPGA outputs the MA clock to the BiSS-C slave device and receives the SLO signal;

[0009] Step S2: Asynchronous sampling trigger reference establishment. Based on the characteristics that the data bit duration is equal to the MA clock period and the slave response time is an integer multiple of the MA clock period, the falling edge of the SLO signal is used as the asynchronous sampling trigger reference;

[0010] Step S3: Starting from the time corresponding to the asynchronous sampling start reference, the SLO signal is continuously sampled using the FPGA system clock in each data bit transmission cycle to obtain m sampling points;

[0011]

[0012] in, For FPGA system clock frequency, The MA clock frequency of the BiSS-C host. This indicates the floor function.

[0013] Furthermore, to ensure sufficient sampling points within each data bit transmission cycle, the asynchronous acquisition uses an FPGA system clock with a frequency not less than 10 times the MA clock frequency.

[0014] Step S4: Determine the boundaries of the data decision window. To avoid the metastable regions at both ends of the data bits, select n sampling points located in the central region out of m sampling points, where... Using the above n sampling points as the data decision window, its left and right boundary indices are... , The calculation formula is:

[0015]

[0016] Step S5: Majority Voting Decision Output. A majority vote is performed on the n sampling points within the data decision window, and the logic level representing the majority is output as the decision for the corresponding data bit. The majority vote decision output... It can be represented as:

[0017]

[0018] in Indicates the first data decision window The logic level of each sampling point This indicates the rounding up operation.

[0019] Furthermore, for the acquisition of BiSS-C data from multiple channels, each channel determines its own falling edge of the SLO response as the asynchronous sampling start reference and independently executes steps S1 to S5 to complete the asynchronous acquisition of multi-channel BiSS-C signals.

[0020] The beneficial effects of this invention are:

[0021] (1) Each channel uses its own SLO response falling edge as the asynchronous sampling start reference, which can adapt to different line delays and delay fluctuations of each channel without the need to measure the line delay in advance;

[0022] (2) The data decision window avoids the transition areas at both ends of the data bits. Majority voting can reduce the probability of misjudgment caused by narrow pulse interference and signal edge jitter.

[0023] (3) FPGA can perform sampling, decision-making and BiSS-C protocol parsing on multiple channels in parallel, improving the real-time performance and synchronization of multi-channel acquisition. Attached Figure Description

[0024] The accompanying drawings are used to provide a further understanding of the technical solutions of this application or the prior art, and constitute a part of the specification. The drawings illustrating embodiments of this application, together with the embodiments of this application, are used to explain the technical solutions of this application, but do not constitute a limitation on the technical solutions of this application.

[0025] Figure 1 This is a flowchart illustrating an embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of the architecture of a multi-channel BiSS-C signal acquisition system according to an embodiment of the present invention.

[0027] Figure 3 This is a schematic diagram of the BiSS-C transmission frame structure according to an embodiment of the present invention.

[0028] Figure 4This is a schematic diagram of the asynchronous oversampling and majority voting timing of the BiSS-C protocol ACK bit SLO signal in an embodiment of the present invention.

[0029] Figure 5 This is a waveform diagram of the dual-channel BiSS-C signal acquired by a logic analyzer in an embodiment of the present invention. Detailed Implementation

[0030] The present invention will be further illustrated below with reference to specific embodiments.

[0031] Figure 1 This is a flowchart illustrating the asynchronous acquisition method provided in an embodiment of the present invention. The asynchronous acquisition method includes steps S1 to S5 executed sequentially, namely, MA clock output and SLO signal reception, asynchronous sampling start reference determination, continuous data bit sampling, data decision window construction, and majority voting output.

[0032] Figure 2 This is a schematic diagram of the overall architecture of a multi-channel BiSS-C data acquisition system provided in an embodiment of the present invention. The system includes a laser interferometer signal processing board 100 acting as a BiSS-C slave, a signal acquisition board 200 equipped with six RS-485 transceivers 211-216, an FPGA evaluation board 300 acting as a BiSS-C master, and a host computer 400. The FPGA evaluation board 300 includes clock generation modules 311-316, asynchronous acquisition modules 321-326, BiSS-C state machines 331-336, a multi-channel barrier synchronization module 340, and a communication interface 350. The FPGA uses a Xilinx Kintex-7 series XC7K325T-FFG676 chip, and the system clock frequency (…). The clock frequency is 100 MHz, MA clock frequency ( The frequency is 10 MHz. The interface supports up to 6 channels of BiSS-C slave devices for access and synchronous transmission. For ease of testing and verification, the following explanation is based on actual test results of a dual-channel BiSS-C slave device.

[0033] Figure 3This is a schematic diagram of the BiSS-C transmission frame structure according to an embodiment of the present invention. The master device continuously outputs a MA clock, and the slave device sequentially feeds back the ACK, START, CDS, DATA, ERROR, WARN, CRC, and TIMEOUT fields via the SLO signal. The ACK phase lasts for N MA clock cycles, where N is determined by the slave device's response delay. In this embodiment, the DATA field is 36 bits long, the ERROR and WARN fields are both 1 bit long, and the CRC field is 6 bits long. The asynchronous acquisition module makes a decision on each data bit and generates a corresponding SLO_VOTE signal; the BiSS-C state machine parses each field based on the SLO_VOTE signal and outputs a channel validity flag and channel data after the CRC check passes. The lengths of the DATA and CRC fields can be adjusted according to the slave device configuration.

[0034] Figure 4 This is a schematic diagram of the asynchronous oversampling and majority voting timing of the BiSS-C protocol ACK bit SLO signal in an embodiment of the present invention. When a falling edge of the SLO signal is detected, the asynchronous acquisition module uses this falling edge as the asynchronous sampling start reference for the corresponding channel, and continuously samples the SLO signal according to the system clock in each subsequent data bit transmission cycle.

[0035] The total number of sampling points m corresponding to each data bit, and the number of sampling points n within the decision window, are calculated as follows:

[0036]

[0037] The decision window is set in the middle area of ​​a single data bit. If the index of each sample point is counted starting from 0, then the left boundary of the decision window is... and right boundary They are respectively:

[0038]

[0039] In this embodiment, , , , Therefore, among the 10 sampling points of each data bit, the 5 sampling points with indices 2 to 6 constitute the decision window and participate in the majority vote. The asynchronous acquisition module counts the number of sampling results of logic "0" and logic "1" within the data decision window, and determines the logic level with the larger number of samples as the decision result for that data bit.

[0040] Figure 5This is a waveform diagram of the dual-channel BiSS-C signal acquired by a logic analyzer in an embodiment of the present invention. The SLO signals of CH1 and CH2 have different return timings. Each channel uses the falling edge of its respective SLO signal's response as the asynchronous sampling start reference and outputs CH1_SLO_VOTE and CH2_SLO_VOTE signals. After data decision window processing and majority voting, the BiSS-C state machine completes the reception of the DATA and CRC fields and returns to the IDLE state after communication ends. When expanded to six channels, each channel is configured with an independent asynchronous acquisition module and BiSS-C state machine, and the sampling timing is determined based on the falling edge of the SLO response for that channel. After all enabled channels have completed valid reception, the multi-channel barrier synchronization module submits the data from each channel to the communication interface to ensure that the data read by the host computer belongs to the same acquisition batch.

[0041] Those skilled in the art can make equivalent substitutions or modifications to the system clock frequency, sampling window length, number of channels, communication interface type, and state machine implementation method without departing from the concept of the present invention; all such substitutions or modifications should fall within the scope of protection claimed by the present invention.

Claims

1. An asynchronous acquisition method for BiSS-C signals based on FPGA, characterized in that, Includes the following steps: Step S1: The FPGA outputs the MA clock to the BiSS-C slave device and receives the SLO signal returned by the BiSS-C slave device; Step S2: During the receiving phase of the current communication cycle, detect the falling edge in the SLO signal corresponding to the slave device acknowledge bit, and determine the falling edge as the asynchronous sampling start reference for the corresponding acquisition channel; Step S3: Starting from the time corresponding to the asynchronous sampling start reference, the SLO signal is continuously sampled using the FPGA system clock in each data bit transmission cycle, and m sampling points are obtained for each data bit; Step S4: Select n consecutive sampling points from the m sampling points to form a data decision window; the n sampling points are located in the middle region of the m sampling points to avoid the metastable regions at the beginning and end of the data bits. The left and right boundaries of the data decision window are respectively... and ; Step S5: Perform a majority vote on the n sampling points within the data decision window, and use the logic level that accounts for the majority as the decision output for the corresponding data bit.

2. The asynchronous acquisition method for BiSS-C signals according to claim 1, characterized in that... The values ​​of m and n are determined by the following formula: in, For FPGA system clock frequency, The MA clock frequency of the BiSS-C host. This indicates the floor function.

3. The asynchronous acquisition method for BiSS-C signals according to claim 1, characterized in that, The left and right boundary indexes of the data decision window , Determined by the following formula:

4. The asynchronous acquisition method for BiSS-C signals according to claim 1, characterized in that, The majority vote decision output It can be represented as: in, The logic level of the k-th sampling point within the data decision window. This indicates the rounding up operation.

5. The asynchronous acquisition method for BiSS-C signals according to claim 1, characterized in that, The asynchronous acquisition uses an FPGA system clock with a frequency no less than 10 times the MA clock frequency.

6. The asynchronous acquisition method for BiSS-C signals according to claim 1, characterized in that, The asynchronous sampling start reference is determined by the falling edge of the SLO signal itself, rather than by the MA clock edge; the data decision window is aligned with the actual return timing of the corresponding channel, without the need to pre-measure the line delay of the corresponding channel.

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