An elastically expandable distributed data tiered shared storage system

Abstract

The application relates to the technical field of distributed big data storage, and discloses an elastically expanded distributed data hierarchical shared storage system, which comprises a high-speed storage hierarchical module, a large-capacity storage hierarchical module, an asynchronous data flow control module and a concurrent access conflict scheduling module. The asynchronous data flow control module reconstructs addressing into a nearby reading mode when a data channel is congested. The concurrent access conflict scheduling module cuts an access time axis into discrete time sequence slices during capacity expansion, and controls discrete order injection of rewriting requests through a high-precision time management module. The application is coupled through hierarchical storage and topological evolution, saves the lock manager overhead, eliminates the collision between write-down elimination and topological rebalancing, maintains parallel throughput during elastic expansion, reduces addressing delay and shortens convergence time.

Description

Technical Field

[0001] This invention belongs to the field of distributed big data storage technology, and in particular relates to a scalable distributed hierarchical shared storage system. Background Technology

[0002] In current large-scale distributed hierarchical data physical shared storage technology grid architecture, multi-tenant concurrent access and dynamic node expansion constitute the resident control conditions. The industry's common design solution is to deploy a hierarchical storage architecture, using the upper-layer high-speed cache storage medium to carry high-frequency shared access flow. When a node initiates normal data reading or multi-source rewriting, the cache logic layer completes the interception and version update of high-frequency data blocks locally according to the preset hit strategy. The consistency topology structure of the lower capacity layer runs independently to maintain the convergence of the global routing chain. Although this design simplifies the internal logic complexity of a single storage level, it implicitly depends on the static or long-term stable data access heat distribution state and lacks the dynamic perception capability of transient routing changes caused by complex external shared conditions.

[0003] The aforementioned limitations not only exist in the deployment of hierarchical storage architectures at the hardware level, but also in the dynamic coordination of related storage control methods at the software logic level. For example, Chinese invention patent application CN119739340A discloses a distributed all-flash storage data writing method, device, and medium that avoids hardware partitioning overhead by reusing erasure coding data blocks as replica cache blocks. However, this technical solution relies on smooth data channels and a stable topology, which is mismatched with the complex dynamic scenarios of elastic scaling of physical nodes and high-concurrency rewriting. When cluster expansion causes the transfer of ownership of underlying hash slots, this technology lacks adaptive and self-defense logic to deal with transient channel congestion, resulting in overlap between write eviction streams and topology rebalancing streams. Collisions occur when multiple tenants concurrently rewrite resident conflicting data blocks. Static mapping mechanisms cannot achieve micro-level temporal isolation, which can easily lead to memory bus deadlock and impair parallel throughput performance. When a distributed storage system undergoes elastic expansion or capacity reduction of physical nodes, the physical slots of the underlying hash ring undergo large-scale ownership transfer and trigger cross-node data block migration. If concurrent shared nodes initiate variable-length and non-continuous multi-source rewrites, the cache layer may trigger data block eviction and write-down due to frequent data heat fluctuations or insufficient available capacity. This writes the data block to the underlying physical area where slot migration is occurring, causing the capacity layer's expansion data migration traffic and the cache layer's eviction data write-down traffic to overlap and collide in the limited distributed network channel.

[0004] Therefore, the technical problem to be solved by this invention is how to construct a dual-loop control mechanism that enables dynamic control of cache lifecycle and deep interlocking of the underlying storage topology state machine, while abandoning centralized metadata services, so as to smoothly offset the network bandwidth contention caused by dynamic node expansion and the memory bus lock-up caused by multi-tenant high-concurrency rewriting, thereby improving the rebalancing convergence speed of elastic data while ensuring the timeliness of routing addressing. Summary of the Invention

[0005] This invention aims to solve the problems of read / write competition caused by the decoupling of the hierarchical storage lifecycle from the underlying hash topology mechanism and memory bus deadlock caused by high-concurrency rewrites during multi-tenant concurrent expansion.

[0006] In this technical solution, a scalable distributed hierarchical shared storage system is provided, comprising:

[0007] The high-speed storage tiering module and the large-capacity storage tiering module exchange information through a bidirectional data transmission channel;

[0008] The asynchronous data flow control module is interlocked with the data interfaces of the high-speed storage tiering module and the large-capacity storage tiering module, respectively.

[0009] The concurrent access conflict scheduling module is deployed in the high-speed storage tiered module via logical addressing paths;

[0010] The process of managing multi-tenant concurrent access and dynamic node scaling includes the following steps:

[0011] Step S101: The asynchronous data flow control module monitors the local data I / O channel congestion rate in the high-speed storage tiering module;

[0012] Step S102: When the local data I / O channel congestion rate reaches the preset congestion threshold, the asynchronous data flow control module suspends the node status heartbeat broadcast update logic, reconstructs the data addressing decision into a nearest-neighbor reading mode based on local static historical snapshots, and uses the consistency vector clock to align the logical version number of the multi-tenant.

[0013] In step S103, when a multi-tenant initiates a concurrent rewrite request to the resident conflicting data block in the high-speed flash memory table during dynamic node expansion, the concurrent access conflict scheduling module extracts the multi-tenant identity code from the concurrent rewrite request and assembles the corresponding tenant identity vector. The continuous access time axis is discretized into discrete time-series fragments through a hash mapping algorithm, and the concurrent rewrite request is controlled by the high-precision time management module to be distributed and injected in a discrete order according to the fragmentation period of the discrete time-series fragments.

[0014] Preferably, the asynchronous data flow control module calculates the real-time fluctuation gradient of the local data I / O channel congestion rate; when the real-time fluctuation gradient falls below 0.8 and lasts for 10 seconds, the asynchronous data flow control module releases the nearest read mode, reactivates the node status heartbeat broadcast update logic, and uses a two-phase commit protocol to batch synchronize the changed routing data cached locally in the high-speed storage tier module to the large-capacity storage tier module.

[0015] Preferably, the concurrent access conflict scheduling module counts the frequency of write operations to the same physical memory address within a historical 50ms period; when the write operation frequency exceeds the conflict threshold, the concurrent access conflict scheduling module initiates the discretization of the continuous access time axis, dividing the continuous access time axis into discrete time-series segments with a time span of 2ms to 10ms.

[0016] Preferably, the high-speed storage tiered module includes multiple decentralized distributed storage units constructed from solid-state flash memory media. Each decentralized distributed storage unit integrates a local data addressing state machine. The local data addressing state machine is used to manage the storage lifecycle of data blocks locally and independently completes distributed routing addressing between each decentralized distributed storage unit through a bidirectional routing feedback channel.

[0017] Preferably, during the preparation phase of the two-phase commit protocol, the asynchronous data flow control module sends a data pre-write instruction to the target capacity storage unit within the large-capacity storage tier module; after receiving the ready response from all target capacity storage units, the asynchronous data flow control module enters the commit phase of the two-phase commit protocol and sends a confirmation commit instruction to all target capacity storage units, synchronously updating the locally cached changed routing data to global routing table entries.

[0018] Preferably, when the local data I / O channel congestion rate is lower than a preset congestion threshold, the asynchronous data flow control module periodically samples the storage topology map of the large-capacity storage tiered module and overwrites the latest topology mapping data table in the local cache of the high-speed storage tiered module to generate a local static historical cross-sectional snapshot.

[0019] Preferably, the concurrent access conflict scheduling module is signal-connected to the high-precision time management module; in step 103, the concurrent access conflict scheduling module controls the injection time interval of concurrent rewrite requests through the counting pulse of the high-precision time management module, and allocates the arrival time nodes of concurrent rewrite requests of different tenants at the time sequence level.

[0020] Preferably, in step S103, the concurrent access conflict scheduling module includes the following sub-steps when discretizing the continuous access time axis: step S1031, extracting the multi-tenant identity code from the concurrent rewrite request; step S1032, assembling the corresponding tenant identifier vector based on the multi-tenant identity code as the calculation input of the hash mapping algorithm.

[0021] Preferably, during dynamic node expansion, when the migration path of the underlying data slot in the large-capacity storage tiered module is blocked, the logical version number in the high-speed flash memory entry triggers high-frequency alternation. The concurrent access conflict scheduling module will discretely distribute the concurrent rewrite requests to discrete time-series shards and limit the update rate of the logical version number to within the preset physical cache bandwidth threshold.

[0022] Compared with existing technologies, the flexible scalability distributed hierarchical shared storage system of the present invention has the following advantages:

[0023] 1. In distributed hierarchical shared storage, by deploying a cache logical ring composed of high-performance storage nodes and a capacity storage logical ring composed of large-capacity storage nodes, data routing and hierarchical decisions are pushed down to the local logical units of each physical node. The storage nodes use the data block access time interval sequence collected by the local hardware timer to calculate the average access time interval. This adaptive transformation directly drives the hierarchical migration of data between the two rings and the consistent hash routing addressing, eliminating the need for centralized global metadata lookup and eliminating serialization lock contention caused by the deepening of the metadata addressing tree when the system is elastically expanded. This allows the average addressing latency of the system to break free from the nonlinear constraints of the node expansion scale. Even with a wide topology change from 128 nodes to 2048 nodes, the addressing latency of data blocks is still stabilized in the range of 12μs to 15μs, and the fluctuation range is limited to within 5%, maintaining the high-speed convergence of storage routing addressing.

[0024] 2. By adjusting the consistent hash mapping rules using the access popularity decay operator of data blocks, the migration probability of the hash region where high-hot data blocks reside is reduced during capacity ring expansion. Combined with the interval partitioning instructions fed back to the cache logic ring in place when physical nodes are elastically added, the eviction pointer of the corresponding cache segment is dynamically locked. Data writing to the cache segment is prohibited before the underlying capacity rebalancing is completed, interrupting the cache failure chain caused by topology migration. This prevents the blind writing of conventional hot and cold tiered eviction and the read / write competition induced by the underlying hash slot migration at the storage boundary. It also eliminates the overlap and collision of expansion data migration traffic and cache write traffic in the distributed network, reducing the migration probability of high-hot data blocks during expansion by more than 85%. Under 50,000 shared access requests per second, the network bandwidth occupation of cross-level data migration is controlled within 4.5%, shortening the rebalancing time of capacity ring topology convergence.

[0025] 3. Configure an asynchronous flow control gating device inside the storage node. It periodically reads the ring receive queue register in the local network adapter to obtain the NIC queuing delay change rate. In the local topology jitter environment where the change rate exceeds the threshold of 1.5 for three consecutive collection cycles, the cache logic ring automatically disconnects the weight modification loop of the capacity storage logic ring. The routing decision is adjusted to the nearest read mode based on the static local historical copy. The topology version of the multi-tenant is aligned with the consistency vector clock until the NIC queuing delay change rate falls below 0.8 and lasts for 10 seconds. Then, the accumulated routing changes are batch synchronized to the capacity storage logic ring through the two-phase commit protocol. The transient network dissipation that causes large-scale routing failure is transformed into version control of the local static section. Without incurring communication costs, the pseudo-expansion and topology drift caused by transient network partitioning are offset, ensuring the continuity of the basic fault tolerance control of the storage node. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the composition structure of the elastically scalable distributed hierarchical shared storage system of the present invention;

[0027] Figure 2 This is a channel congestion handling decision diagram for the elastically scalable distributed data hierarchical shared storage system of this invention. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0029] A scalable, distributed, hierarchical, shared data storage system, comprising:

[0030] The high-speed storage tiering module and the large-capacity storage tiering module exchange information through a bidirectional data transmission channel;

[0031] The asynchronous data flow control module is interlocked with the data interfaces of the high-speed storage tiering module and the large-capacity storage tiering module, respectively.

[0032] The concurrent access conflict scheduling module is deployed in the high-speed storage tiered module via logical addressing paths;

[0033] The process of managing multi-tenant concurrent access and dynamic node scaling includes the following steps:

[0034] Step S101: The asynchronous data flow control module monitors the local data I / O channel congestion rate in the high-speed storage tiering module;

[0035] Step S102: When the local data I / O channel congestion rate reaches the preset congestion threshold, the asynchronous data flow control module suspends the node status heartbeat broadcast update logic, reconstructs the data addressing decision into a nearest-neighbor reading mode based on local static historical snapshots, and uses the consistency vector clock to align the logical version number of the multi-tenant.

[0036] In step S103, when a multi-tenant initiates a concurrent rewrite request to the resident conflicting data block in the high-speed flash memory table during dynamic node expansion, the concurrent access conflict scheduling module extracts the multi-tenant identity code from the concurrent rewrite request and assembles the corresponding tenant identity vector. The continuous access time axis is discretized into discrete time-series fragments through a hash mapping algorithm, and the concurrent rewrite request is controlled by the high-precision time management module to be distributed and injected in a discrete order according to the fragmentation period of the discrete time-series fragments.

[0037] Preferably, the asynchronous data flow control module calculates the real-time fluctuation gradient of the local data I / O channel congestion rate; when the real-time fluctuation gradient falls below 0.8 and lasts for 10 seconds, the asynchronous data flow control module releases the nearest read mode, reactivates the node status heartbeat broadcast update logic, and uses a two-phase commit protocol to batch synchronize the changed routing data cached locally in the high-speed storage tier module to the large-capacity storage tier module.

[0038] Preferably, the concurrent access conflict scheduling module counts the frequency of write operations to the same physical memory address within a historical 50ms period; when the write operation frequency exceeds the conflict threshold, the concurrent access conflict scheduling module initiates the discretization of the continuous access time axis, dividing the continuous access time axis into discrete time-series segments with a time span of 2ms to 10ms.

[0039] Preferably, the high-speed storage tiered module includes multiple decentralized distributed storage units constructed from solid-state flash memory media. Each decentralized distributed storage unit integrates a local data addressing state machine. The local data addressing state machine is used to manage the storage lifecycle of data blocks locally and independently completes distributed routing addressing between each decentralized distributed storage unit through a bidirectional routing feedback channel.

[0040] Preferably, during the preparation phase of the two-phase commit protocol, the asynchronous data flow control module sends a data pre-write instruction to the target capacity storage unit within the large-capacity storage tier module; after receiving the ready response from all target capacity storage units, the asynchronous data flow control module enters the commit phase of the two-phase commit protocol and sends a confirmation commit instruction to all target capacity storage units, synchronously updating the locally cached changed routing data to global routing table entries.

[0041] Preferably, when the local data I / O channel congestion rate is lower than a preset congestion threshold, the asynchronous data flow control module periodically samples the storage topology map of the large-capacity storage tiered module and overwrites the latest topology mapping data table in the local cache of the high-speed storage tiered module to generate a local static historical cross-sectional snapshot.

[0042] Preferably, the concurrent access conflict scheduling module is signal-connected to the high-precision time management module; in step 103, the concurrent access conflict scheduling module controls the injection time interval of concurrent rewrite requests through the counting pulse of the high-precision time management module, and allocates the arrival time nodes of concurrent rewrite requests of different tenants at the time sequence level.

[0043] Preferably, in step S103, the concurrent access conflict scheduling module includes the following sub-steps when discretizing the continuous access time axis: step S1031, extracting the multi-tenant identity code from the concurrent rewrite request; step S1032, assembling the corresponding tenant identifier vector based on the multi-tenant identity code as the calculation input of the hash mapping algorithm.

[0044] Preferably, during dynamic node expansion, when the migration path of the underlying data slot in the large-capacity storage tiered module is blocked, the logical version number in the high-speed flash memory entry triggers high-frequency alternation. The concurrent access conflict scheduling module will discretely distribute the concurrent rewrite requests to discrete time-series shards and limit the update rate of the logical version number to within the preset physical cache bandwidth threshold.

[0045] Example 1: In a distributed big data storage grid environment that continuously processes multi-tenant variable-length and non-continuous concurrent shared access requests, when the underlying storage node cluster dynamically expands or shrinks due to business load, the conventional hierarchical storage architecture is logically disconnected from the cold and hot data eviction mechanism of the cache layer and the consistent hash topology rebalancing of the capacity layer. This causes cache nodes to write eviction data blocks to the physical capacity storage area where hash slot ownership is being transferred when available space is exhausted or data hotness decays. This induces high-frequency read and write ownership contention and path blocking at the hierarchical storage boundary, causing the underlying expansion and migration traffic and the cache layer write traffic to viciously compete for the limited network interface bandwidth in the distributed network, resulting in degraded addressing latency and a multiplied extension of the topology convergence period.

[0046] To resolve conflicts at the boundaries of tiered storage, this invention calls the local control unit configured within each high-speed storage tiered module node, and directly reads hardware registers through a local hardware timer to obtain the access time interval sequence of data blocks within the local node. It also automatically calculates the average access interval of the data block over the past 100 accesses. This allows for the measurement of average access time entirely through physical nodes, without relying on external centralized metadata services or external statistical metrics. Adaptive transformations are used to drive data routing and hierarchical migration between the two rings.

[0047] Storage nodes in the high-speed storage tiering module call local logical computing units based on the average access time interval. Calculate the access heat decay operator for data blocks The calculation equation is expressed as: ,in, To access the heat decay operator, It is a constant attenuation factor, which is a dimensionless constant with a fixed value of 0.05. The average access time interval of the current data block over the past 100 accesses is used as the access frequency decay operator when concurrent shared access causes a certain data block to be accessed less frequently. Exceeding the preset threshold for triggering a change in the rating At this time, the high-speed storage tiered module node currently carrying the data block forcibly modifies the weight of the mapped virtual node corresponding to the data block in the large-capacity storage tiered module. This reduces the truncation range of the virtual node on the consistent hash ring, decreasing the probability of physical migration of the hash region where the high-frequency data block is located during subsequent large-capacity storage tiered module topology expansion. Specifically, reducing the truncation range of the virtual node on the hash ring means applying the popularity decay operator as a weight multiplier to the hash value step range of the virtual node in the hash routing logic. This blocks subsequent new write requests from flowing into the shrinking range at the source. On this basis, in order to offset the impact of the truncation range shrinkage on the ownership transfer of existing high-frequency data blocks, the current high-speed storage... While modifying the large-capacity weights, the local control unit of the hierarchical module node directly transcribes and solidifies the hash key values ​​of the currently hit high-frequency data blocks into the high-speed static mapping table entries of the local cache, and sends a code-level residency declaration containing the globally unique identifier of the data block to the large-capacity storage hierarchical module in situ. After receiving the residency declaration, each underlying storage unit in the large-capacity storage hierarchical module forcibly removes the data block corresponding to the specific residency declaration from the slot migration list of physical relocation when performing slot rebalancing and reorganization caused by horizontal expansion of the node, and forcibly maintains its existing underlying physical node allocation ownership unchanged, thereby protecting the local static stability of the existing data through the shrinkage of the hash ring logical interval.

[0048] When the high-capacity storage tiering module detects the elastic addition of a new physical storage node, the local storage node calculates a discrete interval partitioning instruction based on the load factor announced by the newly added physical storage node. This instruction is then fed back to the high-speed storage tiering module in place, dynamically locking the eviction pointer of the corresponding cache segment. Data writing to this cache segment is prohibited until the high-capacity storage tiering module's rebalancing is complete, thus breaking the cache invalidation chain caused by expansion migration. Local logical residency in the upper-layer cache space is used to exchange for lock-free parallel flow during the convergence of the lower-layer capacity ring topology. In actual execution, the specific algorithm for the interval partitioning instruction is as follows: Each adjacent node in the high-capacity storage tiering module calculates a discrete interval partitioning instruction based on the hardware capacity load factor announced by the newly added physical node. The value is a real number between zero and one. The expected coverage ratio of hash slots to be reclaimed from the existing hash ring is calculated, thereby generating an integer data pair containing the start and end boundary values ​​of the migrated slots. This data pair is then assembled into an interval partitioning instruction. After receiving this instruction through the bidirectional data transmission channel, the data interface of the high-speed storage tiering module parses the data pair using its internally integrated local data addressing state machine, extracting the range of slots currently in the rebalancing and relocation state. Then, the local data addressing state machine directly searches the cache area, locks all local cache data segments whose current routing mapping relationship falls within the slot range, and forcibly rewrites the eviction flag in the memory control block of these data segments to the Boolean value True, indicating that they are locked. By suspending the write eviction scheduling of these specific cache segments in the LRU eviction chain, a complete write abort defense closed loop is constructed.

[0049] To address the congestion in topology communication caused by extremely high concurrency shared access and underlying capacity expansion, each physical storage node invokes its internally configured asynchronous flow control module to periodically read the ring receive queue register in the local network adapter to obtain the current queuing latency change rate of the network card. When the network card queuing latency change rate When the congestion rate exceeds the set threshold of 1.5 for three consecutive sampling cycles, it indicates that the local topology channel is congested. At this time, the asynchronous flow control module initiates adaptive degradation control, forcibly suspends the node status heartbeat broadcast update logic, cuts off the weight modification loop of the high-speed storage tiering module to the large-capacity storage tiering module, reconstructs the data addressing decision to a nearest-neighbor read mode based on local static historical snapshots, and uses a consistent vector clock to align the logical version numbers of multi-tenants. When the asynchronous data flow control module monitors the local data I / O channel congestion rate, it periodically reads the ring receive queue register of the local network adapter in the high-speed storage tiering module to obtain the network card queuing delay change rate as the local data I / O channel congestion rate. It then uses the value of the current sampling cycle and the historical sampling values, and applies the formula... Calculate the real-time fluctuation gradient of the local data I / O channel congestion rate, where, The dimensionless scalar damping value represents the real-time fluctuating gradient and characterizes the evolution trend of channel congestion. This represents the rate of change in network interface card (NIC) queuing delay, read from the circular receive queue register during the current acquisition period. The network card queuing delay change rate is stored in the previous collection period. When the network card queuing delay change rate exceeds the set threshold for three consecutive collection periods, the node status heartbeat broadcast update logic is suspended, and the data addressing decision is reconstructed into a nearest-neighbor reading mode based on the local static historical cross-sectional snapshot.

[0050] During the continuous operation of adaptive degradation control, the asynchronous flow control module continuously calculates the rate of change of network interface card queuing delay. The real-time fluctuation gradient until the network card queuing delay change rate. After the value drops below 0.8 and remains below 0.8 for 10 seconds, the asynchronous flow control module releases the nearest read mode, resumes the weight modification loop, and reactivates the node status heartbeat broadcast update logic. It then uses a two-phase commit protocol to batch synchronize the accumulated routing change data cached locally in the high-speed storage tiering module to the large-capacity storage tiering module to update the global routing table entries.

[0051] When multiple tenants initiate high-frequency concurrent rewrite requests to resident conflicting data blocks in the high-speed flash memory table during dynamic node expansion, the concurrent access conflict scheduling module located within the high-speed storage tiering module counts the frequency of write operations to the same physical memory address within a historical 50ms period. When this frequency exceeds the conflict threshold, the concurrent access conflict scheduling module initiates discretization of the continuous access timeline, extracts the multi-tenant identity code from the concurrent rewrite requests, assembles the corresponding tenant identity vector, and uses a hash mapping algorithm to discretize the continuous physical access timeline into discrete time-series fragments with a time span of 2ms to 10ms, enabling heterogeneous multi-tenants to share access requests. The forced mapping is scattered across different discrete time-series slices. Furthermore, the multi-tenant identity code is a unique integer value assigned to each access tenant by the system. The concurrent access conflict scheduling module allocates an independent vector storage space in memory, using the extracted integer value code as the first vector component. Simultaneously, it calls the system management unit to extract the access priority level pre-registered in the configuration file for that tenant, with values ​​ranging from 1 to 5, as the second component. This is then combined with the historical write request frequency count of that tenant within the current sampling period, as calculated by the bus monitoring unit, as the third component. This assembles a three-dimensional attribute feature vector representing the comprehensive behavioral characteristics of the multi-tenant. ,in, To convert the identity code component to an unsigned integer, For the integer components representing priority, The scalar counting component represents the request frequency; the assembled three-dimensional attribute feature vector serves as the direct input for subsequent multivariate calculations of the hash mapping algorithm, and the hash clustering collisions caused by a single identity code are avoided by increasing the parameter dimension.

[0052] When the concurrent access conflict scheduling module adjusts the time slice width, the system control unit collects parameters through the built-in hardware counter register and bus monitoring unit. It uses the forced invalidation frequency of flash memory cache lines read by the bus monitoring unit within a fixed time window of fifty milliseconds, and simultaneously measures the duty cycle value of the memory bus busy signal within the time window, using a formula... Calculate the current conflict sensitivity level, where, It is a dimensionless scalar processing index that represents the degree of conflict sensitivity and the intensity of row lock contention on the bus. To force the invalidation frequency of cache lines generated by the hardware counter register within a fixed time window, The bus monitoring unit collects the memory bus busy signal duration duty cycle within the same window, defining its value as a real number between zero and one. The system control unit then compares the conflict sensitivity level with preset low-risk and high-risk thresholds, adjusting the corresponding time slice width based on the comparison results. When the concurrent access conflict scheduling module discretizes the continuous access time axis into discrete time slices, it extracts the tenant identification code from multi-tenant concurrent rewrite requests and combines it to generate a tenant identification vector. A hash algorithm is used to convert the tenant identification vector into an unsigned integer hash value. Combined with the time slice width value determined based on the real-time memory bus conflict probability, the modulo of the unsigned integer hash value with the time slice width value and the system master clock cycle is calculated using the formula... The time-series slot index for queuing scheduling is calculated, where, It is a time-series slot index and represents a non-negative integer slot number. This is an unsigned integer hash value calculated from the tenant identifier vector. The time slice width is the ratio of the time slice width to the system master clock cycle. After calculating the time slot index, the high-precision time management module allocates hardware interrupt trigger signals according to the time slot index, and controls the concurrent rewrite requests to be injected sequentially on the physical time axis.

[0053] In the event of cross-shard conflicts within the same discrete time-series shard, the concurrent access conflict scheduling module calculates the step-delay waiting time of low-priority requests within the shard in real time based on the remaining available bandwidth of the current storage bus. It then triggers a hardware high-precision timer interrupt via a counting pulse from the high-precision time management module to control the discrete sequential injection of the access flow. At the time-series level, it allocates the arrival nodes of concurrent rewrite requests from different tenants, thereby achieving time-series decoupling of the request flow and limiting the update rate of the logical version number. This completely avoids the deadlock risk of local memory bus row locks and eliminates the path blocking overhead of the global distributed lock manager.

[0054] Under the joint operation of the decentralized dual-ring collaborative control mechanism, by abandoning centralized metadata services and severing the write conflict chain at the hierarchical storage boundary, the distributed routing overhead of the system no longer grows exponentially with the expansion of physical nodes. During the wide topology change process of the storage system from 128 physical nodes to 2048, the average addressing latency of data blocks remains stable within the range of 12μs to 15μs, and the fluctuation range of addressing latency is limited to within 5%. At the same time, under the extreme condition of high-concurrency shared access intensity reaching 50,000 requests per second, the physical network bandwidth occupation caused by cross-level data migration is reduced from 42% of the traditional architecture to within 4.5%. The rebalancing time of the topology convergence of large-capacity storage hierarchical modules is shortened, and the automatic coordination of the evolution of distributed hierarchical storage boundary and consistent hash topology is realized. This demonstrates a distributed storage system construction method that uses the local logical residency of the upper-layer high-speed storage medium to adaptively offset the cost of the underlying physical data migration.

[0055] Example 2: In a distributed big data storage physical cluster containing tiered storage media and supporting horizontal scaling, the test platform continuously inputs variable-length and non-continuous mixed read / write data streams into a distributed mesh composed of high-speed storage tiering modules and large-capacity storage tiering modules through a storage traffic generation unit. The physical node scale of the storage cluster includes 128, 1088, and 2048 physical nodes. The input data stream is superimposed with random physical input / output latency spikes caused by multi-source concurrent requests. The time shard width in the high-speed storage tiering module is selected based on the addressing latency of the high-speed flash memory chip and the high-concurrency write conflict density of multi-tenant applications. The system is constrained by the time slice width. Too small a time slice width increases the frequency of timing splitting hardware interrupts triggered by the high-speed storage tiering module, thereby increasing the processor's kernel context switching overhead. On the other hand, too wide a time slice width reduces the dilution efficiency of concurrent write requests on the time axis, resulting in a physical constraint between bus overhead and write conflict suppression rate. To address this, the system control unit adjusts the time slice width based on the real-time conflict probability of the physical memory bus. When the conflict probability increases from 1.2% to 8.5%, the time slice width setting is monotonically reduced from 10ms to 2ms. Under normal stable operating conditions, the time slice width is adjusted to 6ms to generate the initial input / output baseline.

[0056] Under continuous data input conditions, the high-speed storage tiering module collects the corresponding shared access characteristics. The unprocessed raw data stream exhibits time delay hysteresis on the high-speed flash bus, with its local input / output queuing delay fluctuating non-linearly between 42.5ms and 118.3ms. At this time, the control unit in the high-speed storage tiering module continuously reads the access time interval sequence of the same data block in the local node over the past 100 accesses. And calculate the average access time interval. The testing process included multiple control groups. The present invention's sample group comprised a high-speed storage tiering module, a large-capacity storage tiering module, an asynchronous data flow control module, and a concurrent access conflict scheduling module. Control group one omitted the asynchronous data flow control module, control group two omitted the concurrent access conflict scheduling module, control group three had a time slice width of 1.2ms, and control group four had a time slice width of 12.6ms. Simultaneously, three intensity gradients were constructed by varying the total number of concurrent threads for shared access requests: 10,000 requests per second, 30,000 requests per second, and 50,000 requests per second. Under the gradient of 10,000 requests per second, the present invention's sample group measured an average addressing latency of 12.3μs, while the average addressing latencies of control groups one and two were 14.1μs and 1μs, respectively. At 3.8 μs, when the request intensity increased to 50,000 shared access requests per second, the average addressing latency of Control Group 1 increased to 165.4 μs due to the lack of local channel congestion-related read reconstruction logic, leading to increased network card queuing latency. Control Group 2, lacking decoupling of write conflicts via discrete-time fragmentation mapping, resulted in local flash memory table entry locking, causing processor utilization to reach 98.2%, thus increasing the average addressing latency to 142.1 μs. In contrast, the sample of this invention, when the physical node size was expanded from 128 and 1088 to 2048, showed average addressing latency of 12.2 μs, 13.4 μs, and 14.8 μs respectively, with fluctuations within 4.2%. This was achieved by calculating the average access time interval. Adjust the hash weight of the mapping nodes to block read / write contention at the hierarchical storage boundary.

[0057] Regarding the boundary characteristics of time slice width, when the time slice width of control group three is shortened to 1.2ms and below the lower limit of 2ms, the frequency of timing slicing hardware interrupts triggered by the high-speed storage tiering module increases. This results in the bus interrupt response processing time occupying 46.7% of the processor core's computation cycle, and the resulting management overhead exceeds its diversion benefit for access conflicts, leading to an increase in average addressing latency. Conversely, when the time slice width of control group four is increased to 12.6ms and above the upper limit of 10ms, the excessively wide time window causes multiple concurrent rewrite requests to overlap within the same discrete time slice. This makes it impossible to isolate rewrite actions in time, triggering a cascading deadlock of the memory bus row locks, which reduces the local data throughput of the physical cluster. The non-linear decrease in volume indicates that the numerical range of 2ms to 10ms constitutes a working window for balancing computational loss and write conflict suppression rate. Furthermore, during the topology convergence phase caused by the elastic expansion of distributed nodes leading to hash slot migration in the large-capacity storage tiered module, the large-capacity storage tiered module feeds back the interval partitioning instruction to the high-speed storage tiered module in situ to lock the eviction pointer. Under the shared access condition of 50,000 requests per second, the physical network bandwidth occupancy caused by cross-level data migration is reduced from 41.6% under the tiered storage architecture to 4.3%. The topology rebalancing time of the large-capacity storage tiered module is shortened by 86.5%, restoring the addressing routing under the constraints of physical storage network bandwidth and physical node processing computing power to a convergent state.

[0058] Example 3: In a distributed big data storage grid with a large capacity of storage nodes ranging from 128 to 2048, multi-tenant concurrent shared rewrite requests for the same high-speed flash memory entry physical address generate high-frequency interleaving conflicts, causing row lock bouncing and consistency collisions on the local memory bus of the storage nodes. To reduce the resulting computational power loss and bus path congestion, the concurrent access conflict scheduling module within the high-speed storage tiering module initiates a parameter calibration process to establish a quantization basis for the discretization of the continuous access time axis. Based on the hardware failure cycle of the cache consistency protocol and the bus duty cycle, the concurrent access conflict scheduling module defines the conflict sensitivity level as the product of the forced invalidation frequency of the flash chip cache line within a unit detection cycle and the duration of the flash memory entry memory bus busy signal. Conflict sensitivity level It is a dimensionless scalar used to characterize the intensity of local bus row lock contention, turning concurrent conflicts into physically measurable variables of the storage architecture.

[0059] The concurrent access conflict scheduling module determines the time slice width through its built-in hardware counter register and bus monitoring unit. In the first timing sequence, the local control unit reads the cache line forced invalidation frequency recorded in the hardware counter register in a fixed time window of 50ms, and simultaneously retrieves the bus busy signal duty cycle collected by the bus monitoring unit. The product of the two is used as the raw input parameter to calculate the current conflict sensitivity level. In the second time sequence, the concurrent access conflict scheduling module will determine the current conflict sensitivity level. Compared with the fixed low-risk threshold of 1.5 and high-risk threshold of 6.0, the calibration characteristic values ​​of the distributed grid under no-load and full-load conditions are compared between the low-risk threshold and the high-risk threshold. In the third time series, a step-wise adaptive adjustment is performed based on the comparison results, if the current conflict sensitivity level is... If the output time slice width is less than or equal to 1.5, then the output time slice width is... Locked for 10ms, if the current conflict sensitivity level is... If the value is greater than or equal to 6.0, then the output time slice width is... The lock time is 2ms, while the current conflict sensitivity level is... When the value is between 1.5 and 6.0, the concurrent access conflict scheduling module uses an equation to divide the time slice width. Converted to conflict sensitivity level A monotonically decreasing mapping value that increases and decreases linearly, time slice width The calculation formula is as follows: ,in, The width of the output time slice. For the current conflict sensitivity level, a constant of 10 represents the maximum fragment width baseline, a constant of 1.78 represents the narrowing slope factor, and a constant of 1.5 represents the low-risk judgment baseline. The constant coefficients in the control thresholds, monitoring time windows, and fragment width calculation formulas mentioned above are all based on performance boundary experiments of the distributed storage system under typical overload conditions. Specifically, the historical write operation monitoring window is set to 50ms because this window time precisely covers 3 to 5 cycles of the local memory bus row lock cascading collision hard retry cycle. This ensures the sample validity of the write frequency statistics; the low-risk threshold of 1.5 and the high-risk threshold of 6.0 correspond to the physical inflection points of bus row lock deterioration from conflict-free to linear growth and from linear growth to exponential lockout, respectively. The constant 10 in the formula represents the maximum fragment width baseline under the risk-free bus state, while the variable width slope factor of 1.78 is the theoretical extreme value derived from the difference of 8ms between the maximum fragment width of 10ms and the overload physical lower limit width of 2ms, divided by the difference between the high and low risk thresholds (6.0-1.5=4.5). ), thereby ensuring that when the level of conflict sensitivity is high When the physical full load limit of 6.0 is reached, the calculated time slice width can be accurately closed-loop converged to 2ms, achieving mathematical self-consistency between data logic and the underlying hardware physical damping state.

[0060] When the storage system faces a light-load condition with multiple tenants concurrent shared access and a conflict sensitivity level When the value is kept at 1.5, the time slice width of the system output is adjusted according to the adaptive adjustment mechanism. At 10ms, multi-tenant write control instructions are scattered across time-axis slices, keeping the processor's kernel context switching overhead at a normal level of 0.5%, reducing the processor's computational load. However, as the total number of threads making concurrent write requests increases, the frequency of forced invalidation of flash memory cache lines and the duration of the memory bus busy signal increase within a unit detection cycle, thus increasing the conflict sensitivity level. When the overload condition reaches 6.0, the concurrent access conflict scheduling module will divide the time slice width. Adjusted to 2ms, interleaved conflicting write requests are time-isolated within discrete time-series shards. The counting pulse of the high-precision time management module triggers a hardware timer interrupt, delaying low-priority access flows on demand. This aligns conflicting requests at the 2ms shard boundary, reducing the probability of cascading deadlocks of memory bus row locks from 38.5% under the hierarchical storage architecture to 0.0%. When dealing with overload conditions of 50,000 requests per second, the distributed high-capacity storage nodes maintain the addressing parallel throughput of the distributed grid through the local logical residency of the top-level cache space. This allows the high-capacity storage hierarchical module to control the average addressing latency of data blocks within the range of 12μs to 15μs during the topology evolution process of elastically expanding the physical node scale from 128 to 2048.

[0061] Example 4: In field deployment scenarios involving the horizontal expansion of new physical nodes or the updating of storage media, addressing misjudgments can easily arise due to physical differences in bus bandwidth and flash controller latency between different storage hardware. Before the data interface interlock between the high-speed storage tiering module and the large-capacity storage tiering module is enabled, the system control unit calls the pre-calibration loop to control the allocation module to continuously inject a write request stream of 1024 data blocks into the storage node to be calibrated. Under no-load conditions, the initial duty cycle of the local memory bus busy signal is read, and the initial invalid frequency of the cache line is obtained synchronously through a hardware timer. The initial result of the product of the initial duty cycle and the initial invalid frequency is used as the environmental calibration factor and stored in the non-volatile storage unit of the node.

[0062] The concurrent access conflict scheduling module calls the environment calibration factor stored in the non-volatile memory cell to calculate an adaptive correction value for the low-risk threshold to align with the physical boundaries of heterogeneous memory chips. The formula for calculating the adaptive correction value is as follows: ,in, The adaptively corrected low-risk threshold is in the form of a dimensionless control variable, and 1.5 is the initial discrimination scalar. The dimensionless conversion coefficients generated for the environmental calibration factor conversion, combined with the new physical node and the adaptively corrected low-risk threshold, By adding a consistent hashing topology ring, the concurrent access conflict scheduling module will adjust the current conflict sensitivity level. With the adaptively adjusted low-risk threshold By comparing and adjusting the time slice width, controlling the timing injection sequence of multi-tenant concurrent shared rewriting, the average addressing latency of shared data blocks is stabilized within the range of 12μs to 15μs during the topology expansion of the large-capacity storage tiered module.

[0063] Example 5: The current distributed big data storage system is deployed in a distributed storage environment that includes heterogeneous flash memory arrays and whose node scale has been vertically expanded from 128 to 2048 nodes. To address the issue of static control parameter mismatch caused by manufacturing residuals in the bus cycles of different controller batches, the system control unit runs a pre-initialization cycle before enabling the data interface interlock between the high-speed storage tiering module and the large-capacity storage tiering module. This involves injecting pseudo-random traffic of 50,000 shared write requests into the local cache nodes to measure hardware throughput under write conflict conditions. To convert the local hardware-level collision loss during the memory bus arbitration phase into system-level quantitative control, the system calculates the ratio of the number of clock cycles during which the row lock is suspended to the total number of system clock cycles, based on clock distribution principles, to determine the bus arbitration loss operator. Bus arbitration loss operator The calculation formula is as follows: ,in, For bus arbitration loss operator, The number of clock cycles the row lock pending state has been monitored by the master clock cycle counter. The total number of master clock cycles is used to calculate the current bus arbitration attenuation operator when the master clock cycle counter detects that the row lock has been suspended for 85 consecutive clock cycles and the total system cycle count reaches 1000 clock cycles. The value is 0.085, thereby eliminating timing lag caused by hardware specification deviations.

[0064] The concurrent access conflict scheduling module substitutes the current calculation results into the hierarchical control matrix, controlling the sequential injection of high-concurrency rewrite instructions within discrete time-series segments ranging from 2ms to 10ms. This ensures that the interval partitioning instructions generated by the high-capacity storage hierarchical module when detecting topology changes meet the mass transfer latency requirements of different batches of flash memory chips. Test results show that under test conditions of 50,000 shared access requests per second and the underlying node cluster undergoing slot rebalancing, controlling multi-tenant write requests through the correction parameters generated by the pre-calibration loop reduces the network card queuing latency variation rate. The average addressing latency of shared data blocks is kept within the convergence range of 12.4μs to 14.9μs in the heterogeneous physical storage grid. The physical network bandwidth occupancy caused by cross-level data migration is controlled within the specification of 4.3%. The distributed hierarchical storage boundary control logic is used to achieve in-situ physical alignment of the underlying hardware heterogeneous nonlinear fluctuations.

[0065] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit of this application and the scope of protection of this invention, and all of these forms are within the protection scope of this application.

Claims

1. A scalable, distributed, hierarchical, shared data storage system, characterized in that: The system includes: The high-speed storage tiering module and the large-capacity storage tiering module exchange information through a bidirectional data transmission channel; The asynchronous data flow control module is interlocked with the data interfaces of the high-speed storage tiering module and the large-capacity storage tiering module, respectively. The concurrent access conflict scheduling module is deployed in the high-speed storage tiered module via logical addressing paths; The process of managing multi-tenant concurrent access and dynamic node scaling includes the following steps: Step S101: The asynchronous data flow control module monitors the local data I / O channel congestion rate in the high-speed storage tiering module; Step S102: When the local data I / O channel congestion rate reaches the preset congestion threshold, the asynchronous data flow control module suspends the node status heartbeat broadcast update logic, reconstructs the data addressing decision into a nearest-neighbor reading mode based on local static historical snapshots, and uses the consistency vector clock to align the logical version number of the multi-tenant. In step S103, when a multi-tenant initiates a concurrent rewrite request to the resident conflicting data block in the high-speed flash memory table during dynamic node expansion, the concurrent access conflict scheduling module extracts the multi-tenant identity code from the concurrent rewrite request and assembles the corresponding tenant identity vector. The continuous access time axis is discretized into discrete time-series fragments through a hash mapping algorithm, and the concurrent rewrite request is controlled by the high-precision time management module to be distributed and injected in a discrete order according to the fragmentation period of the discrete time-series fragments.

2. The elastically scalable distributed hierarchical shared storage system according to claim 1, characterized in that, The asynchronous data flow control module calculates the real-time fluctuation gradient of the local data I / O channel congestion rate. When the real-time fluctuation gradient falls below 0.8 and lasts for 10 seconds, the asynchronous data flow control module releases the nearest read mode, reactivates the node status heartbeat broadcast update logic, and uses a two-phase commit protocol to batch synchronize the changed routing data cached locally in the high-speed storage tiering module to the large-capacity storage tiering module.

3. The elastically scalable distributed hierarchical shared storage system according to claim 1, characterized in that, The concurrent access conflict scheduling module counts the frequency of write operations to the same physical memory address within a historical 50ms period. When the write operation frequency exceeds the conflict threshold, the concurrent access conflict scheduling module initiates the discretization of the continuous access time axis, dividing the continuous access time axis into discrete time-series segments with a time span of 2ms to 10ms.

4. The elastically scalable distributed hierarchical shared storage system according to claim 1, characterized in that, The high-speed storage tiered module includes multiple decentralized distributed storage units constructed from solid-state flash memory media, and each decentralized distributed storage unit integrates a local data addressing state machine. The local data addressing state machine is used to manage the storage lifecycle of data blocks locally and independently completes distributed routing addressing between each decentralized distributed storage unit through a bidirectional routing feedback channel.

5. A scalable distributed hierarchical shared storage system for data according to claim 2, characterized in that, During the preparation phase of the two-phase commit protocol, the asynchronous data flow control module sends a data pre-write instruction to the target capacity storage unit within the large-capacity storage tier module. After receiving ready responses from all target capacity storage units, the asynchronous data flow control module enters the commit phase of the two-phase commit protocol and sends a confirmation commit instruction to all target capacity storage units, synchronously updating the locally cached changed routing data to global routing table entries.

6. The elastically scalable distributed hierarchical shared storage system according to claim 1, characterized in that, When the local data I / O channel congestion rate is lower than the preset congestion threshold, the asynchronous data flow control module periodically samples the storage topology map of the large-capacity storage tiered module and overwrites the latest topology mapping data table in the local cache of the high-speed storage tiered module to generate a local static historical cross-sectional snapshot.

7. A scalable distributed hierarchical shared storage system for data according to claim 1, characterized in that, The concurrent access conflict scheduling module is signal-connected to the high-precision time management module; in step 103, the concurrent access conflict scheduling module controls the injection time interval of concurrent rewrite requests through the counting pulse of the high-precision time management module, and allocates the arrival time nodes of concurrent rewrite requests of different tenants at the time sequence level.

8. A scalable distributed hierarchical shared storage system for data according to claim 1, characterized in that, In step S103, the concurrent access conflict scheduling module includes the following sub-steps when discretizing the continuous access time axis: Step S1031, extract the multi-tenant identity code from the concurrent rewrite request; Step S1032, assemble the corresponding tenant identifier vector based on the multi-tenant identity code, and use it as the calculation input of the hash mapping algorithm.

9. A scalable distributed hierarchical shared storage system for data according to claim 1, characterized in that, During dynamic node expansion, when the migration path of the underlying data slot in the large-capacity storage tiered module is blocked, the logical version number in the high-speed flash memory table is triggered to alternate frequently. The concurrent access conflict scheduling module will discretely distribute the concurrent rewrite requests to discrete time-series shards and limit the update rate of the logical version number to within the preset physical cache bandwidth threshold.

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